OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [sh/] [psub.s] - Blame information for rev 842

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
# sh testcase for psub
2
# mach:  shdsp
3
# as(shdsp):    -defsym sim_cpu=1 -dsp
4
 
5
        .include "testutils.inc"
6
 
7
        start
8
        set_grs_a5a5
9
        lds     r0, a0
10
        pcopy   a0, a1
11
        lds     r0, x0
12
        lds     r0, x1
13
        lds     r0, y0
14
        lds     r0, y1
15
        pcopy   x0, m0
16
        pcopy   y1, m1
17
 
18
psub_sx_sy:
19
        # 0xa5a5a5a5 minus 0xa5a5a5a5 equals zero
20
        psub    x0, y0, a0
21
        assert_sreg     0, a0
22
 
23
psub_sy_sx:
24
        # 100 - 25 = 75
25
        mov     #100, r0
26
        mov     #25, r1
27
        lds     r0, y1
28
        lds     r1, x1
29
        psub    y1, x1, a0
30
        assert_sreg     75, a0
31
 
32
dct_psub:
33
        # 100 - 25 = 75
34
        set_dcfalse
35
        dct     psub    y1, x1, a1
36
        assert_sreg2    0xa5a5a5a5, a1
37
        set_dctrue
38
        dct     psub    y1, x1, a1
39
        assert_sreg2    75, a1
40
 
41
dcf_psub:
42
        # 25 - 100 = -75
43
        set_dctrue
44
        dcf     psub    x1, y1, m1
45
        assert_sreg2    0xa5a5a5a5, m1
46
        set_dcfalse
47
        dcf     psub    x1, y1, m1
48
        assert_sreg2    -75, m1
49
 
50
psub_pmuls:
51
        # 25 - 100 = -75, and 2 x 2 = 8 (yes, eight, not four)
52
        mov     #2, r0
53
        shll16  r0
54
        lds     r0, x0
55
        lds     r0, y0
56
        psub    x1, y1, a1      pmuls   x0, y0, a0
57
        assert_sreg     8, a0
58
        assert_sreg2    -75, a1
59
 
60
        set_greg        0xa5a5a5a5, r0
61
        set_greg        0xa5a5a5a5, r1
62
        test_grs_a5a5
63
        pass
64
        exit 0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.