OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [sh/] [shll16.s] - Blame information for rev 816

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn 
# sh testcase for shll16
2 
# mach: all
3 
# as(sh):       -defsym sim_cpu=0
4 
# as(shdsp):    -defsym sim_cpu=1 -dsp
5 
 
6 
        .include "testutils.inc"
7 
 
8 
        start
9 
 
10 
shll16:
11 
        set_grs_a5a5
12 
        mov #0x18, r1
13 
        shll16 r1
14 
        assertreg 0x180000, r1
15 
        shll16 r1
16 
        assertreg 0, r1
17 
 
18 
        # another:
19 
        mov #1, r1
20 
        shll16 r1
21 
        mov #1, r7
22 
        shll r7
23 
        shll r7
24 
        shll r7
25 
        shll r7
26 
        shll r7
27 
        shll r7
28 
        shll r7
29 
        shll r7
30 
        shll r7
31 
        shll r7
32 
        shll r7
33 
        shll r7
34 
        shll r7
35 
        shll r7
36 
        shll r7
37 
        shll r7
38 
        cmp/eq r1, r7
39 
        bt   okay
40 
        fail
41 
okay:
42 
        set_greg 0xa5a5a5a5, r1
43 
        set_greg 0xa5a5a5a5, r7
44 
        test_grs_a5a5
45 
        pass
46 
        exit 0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.