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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [sh/] [shlr.s] - Blame information for rev 816

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Line No. Rev Author Line
1 227 jeremybenn
# sh testcase for shlr
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# mach: all
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# as(sh):       -defsym sim_cpu=0
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# as(shdsp):    -defsym sim_cpu=1 -dsp
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        .include "testutils.inc"
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        start
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shlr:
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        set_grs_a5a5
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        mov #0, r0
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        or #192, r0
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        shlr r0
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        assertreg0 96
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        shlr r0
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        assertreg0 48
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        shlr r0
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        assertreg0 24
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        shlr r0
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        assertreg0 12
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        shlr r0
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        assertreg0 6
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        shlr r0
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        assertreg0 3
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        # Make sure a bit is shifted into T.
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        shlr r0
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        bf wrong
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        assertreg0 1
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        # Ditto.
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        shlr r0
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        bf wrong
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        assertreg0 0
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        set_greg 0xa5a5a5a5, r0
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        test_grs_a5a5
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        pass
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        exit 0
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wrong:
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        fail

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