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jeremybenn |
/*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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/************************************************************************
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*
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* defBF532.h
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*
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* Copyright (C) 2008 Analog Devices, Inc.
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*
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************************************************************************/
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/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
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#ifndef _DEF_BF532_H
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#define _DEF_BF532_H
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#if !defined(__ADSPLPBLACKFIN__)
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#warning defBF532.h should only be included for 532 compatible chips
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#endif
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/* include all Core registers and bit definitions */
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#include <def_LPBlackfin.h>
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#ifdef _MISRA_RULES
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#pragma diag(push)
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#pragma diag(suppress:misra_rule_19_7)
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#endif /* _MISRA_RULES */
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/*********************************************************************************** */
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/* System MMR Register Map */
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/*********************************************************************************** */
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/*// Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
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#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
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#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
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#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
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#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
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#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
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#define CHIPID 0xFFC00014 /* Chip ID Register */
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| 50 |
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/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
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#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
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#define SYSCR 0xFFC00104 /* System Configuration registe */
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#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
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#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
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#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
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#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
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#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
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#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
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#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
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| 61 |
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| 62 |
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/*// Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
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#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
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#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
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#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
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| 68 |
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/*// Real Time Clock (0xFFC00300 - 0xFFC003FF) */
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#define RTC_STAT 0xFFC00300 /* RTC Status Register */
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#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
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#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
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#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
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#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
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#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
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#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
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| 78 |
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/* UART Controller (0xFFC00400 - 0xFFC004FF) */
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#define UART_THR 0xFFC00400 /* Transmit Holding register */
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| 80 |
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#define UART_RBR 0xFFC00400 /* Receive Buffer register */
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#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
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#define UART_IER 0xFFC00404 /* Interrupt Enable Register */
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#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
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#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */
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#define UART_LCR 0xFFC0040C /* Line Control Register */
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#define UART_MCR 0xFFC00410 /* Modem Control Register */
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#define UART_LSR 0xFFC00414 /* Line Status Register */
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/*#define UART_MSR 0xFFC00418 // Modem Status Register //(UNUSED in ADSP-BF532) */
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#define UART_SCR 0xFFC0041C /* SCR Scratch Register */
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#define UART_GCTL 0xFFC00424 /* Global Control Register */
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/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
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#define SPI_CTL 0xFFC00500 /* SPI Control Register */
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#define SPI_FLG 0xFFC00504 /* SPI Flag register */
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#define SPI_STAT 0xFFC00508 /* SPI Status register */
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#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
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#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
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#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
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#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
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| 102 |
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/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
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#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
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#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
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#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
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#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
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#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
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#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
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#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
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#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
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| 114 |
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#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
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#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
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#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
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#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
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#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
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#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
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#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
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| 123 |
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| 124 |
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/*// General Purpose IO (0xFFC00700 - 0xFFC007FF) */
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#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
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#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
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#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
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#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
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#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
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#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
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#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
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#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
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#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
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#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
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#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
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#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
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#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
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#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
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#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
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#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
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#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
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/*// SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
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#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
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#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
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#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
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#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
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#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
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#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
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#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
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#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
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#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
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#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
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#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
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#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
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#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
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#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
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#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
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#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
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#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
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#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
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#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
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#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
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#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
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#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
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/*// SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
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#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
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#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
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#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
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#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
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#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
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#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
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#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
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#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
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| 178 |
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#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
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| 179 |
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#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
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| 180 |
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#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
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| 181 |
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#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
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| 182 |
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#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
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#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
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#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
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#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
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#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
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#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
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#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
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#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
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#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
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#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
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| 192 |
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| 193 |
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| 194 |
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/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
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/* Asynchronous Memory Controller */
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#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
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#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
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| 198 |
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#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
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| 199 |
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| 200 |
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/* SDRAM Controller */
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| 201 |
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#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
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| 202 |
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#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
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| 203 |
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#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
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| 204 |
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#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
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| 205 |
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| 206 |
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| 207 |
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/* DMA Traffic controls */
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| 208 |
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#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
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| 209 |
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#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
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| 210 |
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| 211 |
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/* Alternate deprecated register names (below) provided for backwards code compatibility */
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| 212 |
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#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
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| 213 |
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#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
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| 214 |
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| 215 |
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| 216 |
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/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
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| 217 |
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#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
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| 218 |
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#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
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| 219 |
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#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
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| 220 |
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#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
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| 221 |
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#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
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| 222 |
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#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
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| 223 |
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#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
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| 224 |
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#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
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| 225 |
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#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
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| 226 |
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#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
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| 227 |
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#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
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| 228 |
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#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
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| 229 |
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#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
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| 230 |
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| 231 |
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#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
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| 232 |
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#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
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| 233 |
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#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
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| 234 |
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#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
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| 235 |
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#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
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| 236 |
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#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
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| 237 |
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#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
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| 238 |
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#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
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| 239 |
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#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
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| 240 |
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#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
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| 241 |
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#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
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| 242 |
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#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
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| 243 |
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#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
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| 244 |
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| 245 |
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#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
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| 246 |
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#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
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| 247 |
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#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
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| 248 |
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#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
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| 249 |
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#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
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| 250 |
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#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
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| 251 |
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#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
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| 252 |
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#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
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| 253 |
|
|
#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
|
| 254 |
|
|
#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
|
| 255 |
|
|
#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
|
| 256 |
|
|
#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
|
| 257 |
|
|
#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
|
| 258 |
|
|
|
| 259 |
|
|
#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
|
| 260 |
|
|
#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
|
| 261 |
|
|
#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
|
| 262 |
|
|
#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
|
| 263 |
|
|
#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
|
| 264 |
|
|
#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
|
| 265 |
|
|
#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
|
| 266 |
|
|
#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
|
| 267 |
|
|
#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
|
| 268 |
|
|
#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
|
| 269 |
|
|
#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
|
| 270 |
|
|
#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
|
| 271 |
|
|
#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
|
| 272 |
|
|
|
| 273 |
|
|
#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
|
| 274 |
|
|
#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
|
| 275 |
|
|
#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
|
| 276 |
|
|
#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
|
| 277 |
|
|
#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
|
| 278 |
|
|
#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
|
| 279 |
|
|
#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
|
| 280 |
|
|
#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
|
| 281 |
|
|
#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
|
| 282 |
|
|
#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
|
| 283 |
|
|
#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
|
| 284 |
|
|
#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
|
| 285 |
|
|
#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
|
| 286 |
|
|
|
| 287 |
|
|
#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
|
| 288 |
|
|
#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
|
| 289 |
|
|
#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
|
| 290 |
|
|
#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
|
| 291 |
|
|
#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
|
| 292 |
|
|
#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
|
| 293 |
|
|
#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
|
| 294 |
|
|
#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
|
| 295 |
|
|
#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
|
| 296 |
|
|
#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
|
| 297 |
|
|
#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
|
| 298 |
|
|
#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
|
| 299 |
|
|
#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
|
| 300 |
|
|
|
| 301 |
|
|
#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
|
| 302 |
|
|
#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
|
| 303 |
|
|
#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
|
| 304 |
|
|
#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
|
| 305 |
|
|
#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
|
| 306 |
|
|
#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
|
| 307 |
|
|
#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
|
| 308 |
|
|
#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
|
| 309 |
|
|
#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
|
| 310 |
|
|
#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
|
| 311 |
|
|
#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
|
| 312 |
|
|
#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
|
| 313 |
|
|
#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
|
| 314 |
|
|
|
| 315 |
|
|
#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
|
| 316 |
|
|
#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
|
| 317 |
|
|
#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
|
| 318 |
|
|
#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
|
| 319 |
|
|
#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
|
| 320 |
|
|
#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
|
| 321 |
|
|
#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
|
| 322 |
|
|
#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
|
| 323 |
|
|
#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
|
| 324 |
|
|
#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
|
| 325 |
|
|
#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
|
| 326 |
|
|
#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
|
| 327 |
|
|
#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
|
| 328 |
|
|
|
| 329 |
|
|
#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
|
| 330 |
|
|
#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
|
| 331 |
|
|
#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */
|
| 332 |
|
|
#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */
|
| 333 |
|
|
#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */
|
| 334 |
|
|
#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */
|
| 335 |
|
|
#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */
|
| 336 |
|
|
#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
|
| 337 |
|
|
#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */
|
| 338 |
|
|
#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */
|
| 339 |
|
|
#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */
|
| 340 |
|
|
#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
|
| 341 |
|
|
#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */
|
| 342 |
|
|
|
| 343 |
|
|
#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */
|
| 344 |
|
|
#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
|
| 345 |
|
|
#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */
|
| 346 |
|
|
#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */
|
| 347 |
|
|
#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */
|
| 348 |
|
|
#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */
|
| 349 |
|
|
#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */
|
| 350 |
|
|
#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
|
| 351 |
|
|
#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */
|
| 352 |
|
|
#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */
|
| 353 |
|
|
#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */
|
| 354 |
|
|
#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
|
| 355 |
|
|
#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */
|
| 356 |
|
|
|
| 357 |
|
|
#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */
|
| 358 |
|
|
#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
|
| 359 |
|
|
#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */
|
| 360 |
|
|
#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */
|
| 361 |
|
|
#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */
|
| 362 |
|
|
#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */
|
| 363 |
|
|
#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */
|
| 364 |
|
|
#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
|
| 365 |
|
|
#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */
|
| 366 |
|
|
#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */
|
| 367 |
|
|
#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */
|
| 368 |
|
|
#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
|
| 369 |
|
|
#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */
|
| 370 |
|
|
|
| 371 |
|
|
#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */
|
| 372 |
|
|
#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
|
| 373 |
|
|
#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */
|
| 374 |
|
|
#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */
|
| 375 |
|
|
#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */
|
| 376 |
|
|
#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */
|
| 377 |
|
|
#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */
|
| 378 |
|
|
#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
|
| 379 |
|
|
#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */
|
| 380 |
|
|
#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */
|
| 381 |
|
|
#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */
|
| 382 |
|
|
#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */
|
| 383 |
|
|
#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */
|
| 384 |
|
|
|
| 385 |
|
|
|
| 386 |
|
|
/*// Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
|
| 387 |
|
|
#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
|
| 388 |
|
|
#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
|
| 389 |
|
|
#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
|
| 390 |
|
|
#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
|
| 391 |
|
|
#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
|
| 392 |
|
|
|
| 393 |
|
|
/*********************************************************************************** */
|
| 394 |
|
|
/* System MMR Register Bits */
|
| 395 |
|
|
/******************************************************************************* */
|
| 396 |
|
|
|
| 397 |
|
|
/* ********************* PLL AND RESET MASKS ************************ */
|
| 398 |
|
|
/*// PLL_CTL Masks */
|
| 399 |
|
|
#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
|
| 400 |
|
|
#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
|
| 401 |
|
|
#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
|
| 402 |
|
|
#define PLL_OFF 0x0002 /* Shut off PLL clocks */
|
| 403 |
|
|
#define STOPCK_OFF 0x0008 /* Core clock off */
|
| 404 |
|
|
#define STOPCK 0x0008 /* Core Clock Off */
|
| 405 |
|
|
#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
|
| 406 |
|
|
|
| 407 |
|
|
#if !defined(__ADSPBF538__)
|
| 408 |
|
|
/* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */
|
| 409 |
|
|
# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
|
| 410 |
|
|
# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
|
| 411 |
|
|
#endif
|
| 412 |
|
|
|
| 413 |
|
|
#define BYPASS 0x0100 /* Bypass the PLL */
|
| 414 |
|
|
/* PLL_CTL Macros */
|
| 415 |
|
|
#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
|
| 416 |
|
|
|
| 417 |
|
|
/* PLL_DIV Masks */
|
| 418 |
|
|
#define SSEL 0x000F /* System Select */
|
| 419 |
|
|
#define CSEL 0x0030 /* Core Select */
|
| 420 |
|
|
|
| 421 |
|
|
#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
|
| 422 |
|
|
|
| 423 |
|
|
#define CCLK_DIV1 0x0000 /* CCLK = VCO / 1 */
|
| 424 |
|
|
#define CCLK_DIV2 0x0010 /* CCLK = VCO / 2 */
|
| 425 |
|
|
#define CCLK_DIV4 0x0020 /* CCLK = VCO / 4 */
|
| 426 |
|
|
#define CCLK_DIV8 0x0030 /* CCLK = VCO / 8 */
|
| 427 |
|
|
/* PLL_DIV Macros */
|
| 428 |
|
|
#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
|
| 429 |
|
|
|
| 430 |
|
|
/* PLL_STAT Masks */
|
| 431 |
|
|
#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
|
| 432 |
|
|
#define FULL_ON 0x0002 /* Processor In Full On Mode */
|
| 433 |
|
|
#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
|
| 434 |
|
|
#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
|
| 435 |
|
|
|
| 436 |
|
|
/* VR_CTL Masks */
|
| 437 |
|
|
#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
|
| 438 |
|
|
#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
|
| 439 |
|
|
#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
|
| 440 |
|
|
#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
|
| 441 |
|
|
#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
|
| 442 |
|
|
|
| 443 |
|
|
#define GAIN 0x000C /* Voltage Level Gain */
|
| 444 |
|
|
#define GAIN_5 0x0000 /* GAIN = 5 */
|
| 445 |
|
|
#define GAIN_10 0x0004 /* GAIN = 10 */
|
| 446 |
|
|
#define GAIN_20 0x0008 /* GAIN = 20 */
|
| 447 |
|
|
#define GAIN_50 0x000C /* GAIN = 50 */
|
| 448 |
|
|
|
| 449 |
|
|
#define VLEV 0x00F0 /* Internal Voltage Level - Only Program Values Within Specifications */
|
| 450 |
|
|
#define VLEV_085 0x0060 /* VLEV = 0.85 V (See Datasheet for Regulator Tolerance) */
|
| 451 |
|
|
#define VLEV_090 0x0070 /* VLEV = 0.90 V (See Datasheet for Regulator Tolerance) */
|
| 452 |
|
|
#define VLEV_095 0x0080 /* VLEV = 0.95 V (See Datasheet for Regulator Tolerance) */
|
| 453 |
|
|
#define VLEV_100 0x0090 /* VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */
|
| 454 |
|
|
#define VLEV_105 0x00A0 /* VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */
|
| 455 |
|
|
#define VLEV_110 0x00B0 /* VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */
|
| 456 |
|
|
#define VLEV_115 0x00C0 /* VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */
|
| 457 |
|
|
#define VLEV_120 0x00D0 /* VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */
|
| 458 |
|
|
#define VLEV_125 0x00E0 /* VLEV = 1.25 V (See Datasheet for Regulator Tolerance) */
|
| 459 |
|
|
#define VLEV_130 0x00F0 /* VLEV = 1.30 V (See Datasheet for Regulator Tolerance) */
|
| 460 |
|
|
|
| 461 |
|
|
#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
|
| 462 |
|
|
#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
|
| 463 |
|
|
|
| 464 |
|
|
/* SWRST Mask */
|
| 465 |
|
|
#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
|
| 466 |
|
|
#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
|
| 467 |
|
|
#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
|
| 468 |
|
|
#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
|
| 469 |
|
|
#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
|
| 470 |
|
|
|
| 471 |
|
|
/* SYSCR Masks */
|
| 472 |
|
|
#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
|
| 473 |
|
|
#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
|
| 474 |
|
|
|
| 475 |
|
|
|
| 476 |
|
|
/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
|
| 477 |
|
|
|
| 478 |
|
|
/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
|
| 479 |
|
|
#define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */
|
| 480 |
|
|
#define DMA_ERR_IRQ 0x00000002 /* DMA Controller Error Interrupt Request */
|
| 481 |
|
|
#define PPI_ERR_IRQ 0x00000004 /* PPI Error Interrupt Request */
|
| 482 |
|
|
#define SPORT0_ERR_IRQ 0x00000008 /* SPORT0 Error Interrupt Request */
|
| 483 |
|
|
#define SPORT1_ERR_IRQ 0x00000010 /* SPORT1 Error Interrupt Request */
|
| 484 |
|
|
#define SPI_ERR_IRQ 0x00000020 /* SPI Error Interrupt Request */
|
| 485 |
|
|
#define UART_ERR_IRQ 0x00000040 /* UART Error Interrupt Request */
|
| 486 |
|
|
#define RTC_IRQ 0x00000080 /* Real-Time Clock Interrupt Request */
|
| 487 |
|
|
#define DMA0_IRQ 0x00000100 /* DMA Channel 0 (PPI) Interrupt Request */
|
| 488 |
|
|
#define DMA1_IRQ 0x00000200 /* DMA Channel 1 (SPORT0 RX) Interrupt Request */
|
| 489 |
|
|
#define DMA2_IRQ 0x00000400 /* DMA Channel 2 (SPORT0 TX) Interrupt Request */
|
| 490 |
|
|
#define DMA3_IRQ 0x00000800 /* DMA Channel 3 (SPORT1 RX) Interrupt Request */
|
| 491 |
|
|
#define DMA4_IRQ 0x00001000 /* DMA Channel 4 (SPORT1 TX) Interrupt Request */
|
| 492 |
|
|
#define DMA5_IRQ 0x00002000 /* DMA Channel 5 (SPI) Interrupt Request */
|
| 493 |
|
|
#define DMA6_IRQ 0x00004000 /* DMA Channel 6 (UART RX) Interrupt Request */
|
| 494 |
|
|
#define DMA7_IRQ 0x00008000 /* DMA Channel 7 (UART TX) Interrupt Request */
|
| 495 |
|
|
#define TIMER0_IRQ 0x00010000 /* Timer 0 Interrupt Request */
|
| 496 |
|
|
#define TIMER1_IRQ 0x00020000 /* Timer 1 Interrupt Request */
|
| 497 |
|
|
#define TIMER2_IRQ 0x00040000 /* Timer 2 Interrupt Request */
|
| 498 |
|
|
#define PFA_IRQ 0x00080000 /* Programmable Flag Interrupt Request A */
|
| 499 |
|
|
#define PFB_IRQ 0x00100000 /* Programmable Flag Interrupt Request B */
|
| 500 |
|
|
#define MDMA0_IRQ 0x00200000 /* MemDMA Stream 0 Interrupt Request */
|
| 501 |
|
|
#define MDMA1_IRQ 0x00400000 /* MemDMA Stream 1 Interrupt Request */
|
| 502 |
|
|
#define WDOG_IRQ 0x00800000 /* Software Watchdog Timer Interrupt Request */
|
| 503 |
|
|
|
| 504 |
|
|
|
| 505 |
|
|
/* SIC_IAR0 Macros */
|
| 506 |
|
|
#define P0_IVG(x) (((x)-7)&0xF) /* Peripheral #0 assigned IVG #x */
|
| 507 |
|
|
#define P1_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #1 assigned IVG #x */
|
| 508 |
|
|
#define P2_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #2 assigned IVG #x */
|
| 509 |
|
|
#define P3_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #3 assigned IVG #x */
|
| 510 |
|
|
#define P4_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #4 assigned IVG #x */
|
| 511 |
|
|
#define P5_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #5 assigned IVG #x */
|
| 512 |
|
|
#define P6_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #6 assigned IVG #x */
|
| 513 |
|
|
#define P7_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #7 assigned IVG #x */
|
| 514 |
|
|
|
| 515 |
|
|
/* SIC_IAR1 Macros */
|
| 516 |
|
|
#define P8_IVG(x) (((x)-7)&0xF) /* Peripheral #8 assigned IVG #x */
|
| 517 |
|
|
#define P9_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #9 assigned IVG #x */
|
| 518 |
|
|
#define P10_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #10 assigned IVG #x */
|
| 519 |
|
|
#define P11_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #11 assigned IVG #x */
|
| 520 |
|
|
#define P12_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #12 assigned IVG #x */
|
| 521 |
|
|
#define P13_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #13 assigned IVG #x */
|
| 522 |
|
|
#define P14_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #14 assigned IVG #x */
|
| 523 |
|
|
#define P15_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #15 assigned IVG #x */
|
| 524 |
|
|
|
| 525 |
|
|
/* SIC_IAR2 Macros */
|
| 526 |
|
|
#define P16_IVG(x) (((x)-7)&0xF) /* Peripheral #16 assigned IVG #x */
|
| 527 |
|
|
#define P17_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #17 assigned IVG #x */
|
| 528 |
|
|
#define P18_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #18 assigned IVG #x */
|
| 529 |
|
|
#define P19_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #19 assigned IVG #x */
|
| 530 |
|
|
#define P20_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #20 assigned IVG #x */
|
| 531 |
|
|
#define P21_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #21 assigned IVG #x */
|
| 532 |
|
|
#define P22_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #22 assigned IVG #x */
|
| 533 |
|
|
#define P23_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #23 assigned IVG #x */
|
| 534 |
|
|
|
| 535 |
|
|
/* SIC_IARx Macros */
|
| 536 |
|
|
#define PX_IVG_CLR(x) (0xFFFFFFFF ^ (0xF << (((x)%8)*4))) /* Clear IVG Select for Peripheral #x */
|
| 537 |
|
|
/* Usage: *pSIC_IAR1 &= PX_IVG_CLR(11); // Clears IVG Level of Peripheral #11 */
|
| 538 |
|
|
#define PX_IVG(x,y) ((((y)-7)&0xF) << (((x)%8)*4)) /* Set IVG Select to #y for Peripheral #x */
|
| 539 |
|
|
/* Usage: *pSIC_IAR1 |= PX_IVG(11, 8); // Sets Peripheral #11 to IVG8 */
|
| 540 |
|
|
|
| 541 |
|
|
/* SIC_IMASK Masks */
|
| 542 |
|
|
#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
|
| 543 |
|
|
#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
|
| 544 |
|
|
#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
|
| 545 |
|
|
#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
|
| 546 |
|
|
|
| 547 |
|
|
/* SIC_IWR Masks */
|
| 548 |
|
|
#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
|
| 549 |
|
|
#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
|
| 550 |
|
|
#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
|
| 551 |
|
|
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
|
| 552 |
|
|
|
| 553 |
|
|
|
| 554 |
|
|
/* ********* WATCHDOG TIMER MASKS ******************** */
|
| 555 |
|
|
|
| 556 |
|
|
/* Watchdog Timer WDOG_CTL Register Masks */
|
| 557 |
|
|
|
| 558 |
|
|
#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
|
| 559 |
|
|
#define WDEV_RESET 0x0000 /* generate reset event on roll over */
|
| 560 |
|
|
#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
|
| 561 |
|
|
#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
|
| 562 |
|
|
#define WDEV_NONE 0x0006 /* no event on roll over */
|
| 563 |
|
|
#define WDEN 0x0FF0 /* enable watchdog */
|
| 564 |
|
|
#define WDDIS 0x0AD0 /* disable watchdog */
|
| 565 |
|
|
#define WDRO 0x8000 /* watchdog rolled over latch */
|
| 566 |
|
|
|
| 567 |
|
|
/* depreciated WDOG_CTL Register Masks for legacy code */
|
| 568 |
|
|
#define ICTL WDEV
|
| 569 |
|
|
#define ENABLE_RESET WDEV_RESET
|
| 570 |
|
|
#define WDOG_RESET WDEV_RESET
|
| 571 |
|
|
#define ENABLE_NMI WDEV_NMI
|
| 572 |
|
|
#define WDOG_NMI WDEV_NMI
|
| 573 |
|
|
#define ENABLE_GPI WDEV_GPI
|
| 574 |
|
|
#define WDOG_GPI WDEV_GPI
|
| 575 |
|
|
#define DISABLE_EVT WDEV_NONE
|
| 576 |
|
|
#define WDOG_NONE WDEV_NONE
|
| 577 |
|
|
|
| 578 |
|
|
#define TMR_EN WDEN
|
| 579 |
|
|
#define WDOG_DISABLE WDDIS
|
| 580 |
|
|
#define TRO WDRO
|
| 581 |
|
|
|
| 582 |
|
|
#define ICTL_P0 0x01
|
| 583 |
|
|
#define ICTL_P1 0x02
|
| 584 |
|
|
#define TRO_P 0x0F
|
| 585 |
|
|
|
| 586 |
|
|
|
| 587 |
|
|
/* *************** REAL TIME CLOCK MASKS **************************/
|
| 588 |
|
|
/* RTC_STAT and RTC_ALARM register */
|
| 589 |
|
|
#define RTSEC 0x0000003F /* Real-Time Clock Seconds */
|
| 590 |
|
|
#define RTMIN 0x00000FC0 /* Real-Time Clock Minutes */
|
| 591 |
|
|
#define RTHR 0x0001F000 /* Real-Time Clock Hours */
|
| 592 |
|
|
#define RTDAY 0xFFFE0000 /* Real-Time Clock Days */
|
| 593 |
|
|
|
| 594 |
|
|
/* RTC_ICTL register */
|
| 595 |
|
|
#define SWIE 0x0001 /* Stopwatch Interrupt Enable */
|
| 596 |
|
|
#define AIE 0x0002 /* Alarm Interrupt Enable */
|
| 597 |
|
|
#define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */
|
| 598 |
|
|
#define MIE 0x0008 /* Minutes Interrupt Enable */
|
| 599 |
|
|
#define HIE 0x0010 /* Hours Interrupt Enable */
|
| 600 |
|
|
#define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */
|
| 601 |
|
|
#define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
|
| 602 |
|
|
#define WCIE 0x8000 /* Write Complete Interrupt Enable */
|
| 603 |
|
|
|
| 604 |
|
|
/* RTC_ISTAT register */
|
| 605 |
|
|
#define SWEF 0x0001 /* Stopwatch Event Flag */
|
| 606 |
|
|
#define AEF 0x0002 /* Alarm Event Flag */
|
| 607 |
|
|
#define SEF 0x0004 /* Seconds (1 Hz) Event Flag */
|
| 608 |
|
|
#define MEF 0x0008 /* Minutes Event Flag */
|
| 609 |
|
|
#define HEF 0x0010 /* Hours Event Flag */
|
| 610 |
|
|
#define DEF 0x0020 /* 24 Hours (Days) Event Flag */
|
| 611 |
|
|
#define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */
|
| 612 |
|
|
#define WPS 0x4000 /* Write Pending Status (RO) */
|
| 613 |
|
|
#define WCOM 0x8000 /* Write Complete */
|
| 614 |
|
|
|
| 615 |
|
|
/*// RTC_FAST Mask (RTC_PREN Mask) */
|
| 616 |
|
|
#define ENABLE_PRESCALE 0x00000001 /* Enable prescaler so RTC runs at 1 Hz */
|
| 617 |
|
|
#define PREN 0x00000001
|
| 618 |
|
|
/* ** Must be set after power-up for proper operation of RTC */
|
| 619 |
|
|
|
| 620 |
|
|
/* RTC_ALARM Macro z=day y=hr x=min w=sec */
|
| 621 |
|
|
#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
|
| 622 |
|
|
|
| 623 |
|
|
/* Deprecated RTC_STAT and RTC_ALARM Masks */
|
| 624 |
|
|
#define RTC_SEC RTSEC /* Real-Time Clock Seconds */
|
| 625 |
|
|
#define RTC_MIN RTMIN /* Real-Time Clock Minutes */
|
| 626 |
|
|
#define RTC_HR RTHR /* Real-Time Clock Hours */
|
| 627 |
|
|
#define RTC_DAY RTDAY /* Real-Time Clock Days */
|
| 628 |
|
|
|
| 629 |
|
|
/* Deprecated RTC_ICTL/RTC_ISTAT Masks */
|
| 630 |
|
|
#define STOPWATCH SWIE /* Stopwatch Interrupt Enable */
|
| 631 |
|
|
#define ALARM AIE /* Alarm Interrupt Enable */
|
| 632 |
|
|
#define SECOND SIE /* Seconds (1 Hz) Interrupt Enable */
|
| 633 |
|
|
#define MINUTE MIE /* Minutes Interrupt Enable */
|
| 634 |
|
|
#define HOUR HIE /* Hours Interrupt Enable */
|
| 635 |
|
|
#define DAY DIE /* 24 Hours (Days) Interrupt Enable */
|
| 636 |
|
|
#define DAY_ALARM DAIE /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
|
| 637 |
|
|
#define WRITE_COMPLETE WCIE /* Write Complete Interrupt Enable */
|
| 638 |
|
|
|
| 639 |
|
|
|
| 640 |
|
|
/* ***************************** UART CONTROLLER MASKS ********************** */
|
| 641 |
|
|
/* UART_LCR Register */
|
| 642 |
|
|
|
| 643 |
|
|
#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
|
| 644 |
|
|
#define STB 0x04 /* Stop Bits */
|
| 645 |
|
|
#define PEN 0x08 /* Parity Enable */
|
| 646 |
|
|
#define EPS 0x10 /* Even Parity Select */
|
| 647 |
|
|
#define STP 0x20 /* Stick Parity */
|
| 648 |
|
|
#define SB 0x40 /* Set Break */
|
| 649 |
|
|
#define DLAB 0x80 /* Divisor Latch Access */
|
| 650 |
|
|
|
| 651 |
|
|
#define DLAB_P 0x07
|
| 652 |
|
|
#define SB_P 0x06
|
| 653 |
|
|
#define STP_P 0x05
|
| 654 |
|
|
#define EPS_P 0x04
|
| 655 |
|
|
#define PEN_P 0x03
|
| 656 |
|
|
#define STB_P 0x02
|
| 657 |
|
|
#define WLS_P1 0x01
|
| 658 |
|
|
#define WLS_P0 0x00
|
| 659 |
|
|
|
| 660 |
|
|
/* UART_MCR Register */
|
| 661 |
|
|
#define LOOP_ENA 0x10 /* Loopback Mode Enable */
|
| 662 |
|
|
#define LOOP_ENA_P 0x04
|
| 663 |
|
|
/* Deprecated UARTx_MCR Mask */
|
| 664 |
|
|
|
| 665 |
|
|
/* UART_LSR Register */
|
| 666 |
|
|
#define DR 0x01 /* Data Ready */
|
| 667 |
|
|
#define OE 0x02 /* Overrun Error */
|
| 668 |
|
|
#define PE 0x04 /* Parity Error */
|
| 669 |
|
|
#define FE 0x08 /* Framing Error */
|
| 670 |
|
|
#define BI 0x10 /* Break Interrupt */
|
| 671 |
|
|
#define THRE 0x20 /* THR Empty */
|
| 672 |
|
|
#define TEMT 0x40 /* TSR and UART_THR Empty */
|
| 673 |
|
|
|
| 674 |
|
|
#define TEMP_P 0x06
|
| 675 |
|
|
#define THRE_P 0x05
|
| 676 |
|
|
#define BI_P 0x04
|
| 677 |
|
|
#define FE_P 0x03
|
| 678 |
|
|
#define PE_P 0x02
|
| 679 |
|
|
#define OE_P 0x01
|
| 680 |
|
|
#define DR_P 0x00
|
| 681 |
|
|
|
| 682 |
|
|
/* UART_IER Register */
|
| 683 |
|
|
#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
|
| 684 |
|
|
#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
|
| 685 |
|
|
#define ELSI 0x04 /* Enable RX Status Interrupt */
|
| 686 |
|
|
|
| 687 |
|
|
#define ELSI_P 0x02
|
| 688 |
|
|
#define ETBEI_P 0x01
|
| 689 |
|
|
#define ERBFI_P 0x00
|
| 690 |
|
|
|
| 691 |
|
|
/* UART_IIR Register */
|
| 692 |
|
|
#define STATUS(x) (((x) << 1) & 0x06)
|
| 693 |
|
|
#define NINT 0x01
|
| 694 |
|
|
#define STATUS_P1 0x02
|
| 695 |
|
|
#define STATUS_P0 0x01
|
| 696 |
|
|
#define NINT_P 0x00
|
| 697 |
|
|
|
| 698 |
|
|
/* UART_GCTL Register */
|
| 699 |
|
|
#define UCEN 0x01 /* Enable UARTx Clocks */
|
| 700 |
|
|
#define IREN 0x02 /* Enable IrDA Mode */
|
| 701 |
|
|
#define TPOLC 0x04 /* IrDA TX Polarity Change */
|
| 702 |
|
|
#define RPOLC 0x08 /* IrDA RX Polarity Change */
|
| 703 |
|
|
#define FPE 0x10 /* Force Parity Error On Transmit */
|
| 704 |
|
|
#define FFE 0x20 /* Force Framing Error On Transmit */
|
| 705 |
|
|
|
| 706 |
|
|
#define FFE_P 0x05
|
| 707 |
|
|
#define FPE_P 0x04
|
| 708 |
|
|
#define RPOLC_P 0x03
|
| 709 |
|
|
#define TPOLC_P 0x02
|
| 710 |
|
|
#define IREN_P 0x01
|
| 711 |
|
|
#define UCEN_P 0x00
|
| 712 |
|
|
|
| 713 |
|
|
|
| 714 |
|
|
/* ********** SERIAL PORT MASKS ********************** */
|
| 715 |
|
|
/* SPORTx_TCR1 Masks */
|
| 716 |
|
|
#define TSPEN 0x0001 /* TX enable */
|
| 717 |
|
|
#define ITCLK 0x0002 /* Internal TX Clock Select */
|
| 718 |
|
|
#define TDTYPE 0x000C /* TX Data Formatting Select */
|
| 719 |
|
|
#define DTYPE_NORM 0x0000 /* Data Format Normal */
|
| 720 |
|
|
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
|
| 721 |
|
|
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
|
| 722 |
|
|
#define TLSBIT 0x0010 /* TX Bit Order */
|
| 723 |
|
|
#define ITFS 0x0200 /* Internal TX Frame Sync Select */
|
| 724 |
|
|
#define TFSR 0x0400 /* TX Frame Sync Required Select */
|
| 725 |
|
|
#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
|
| 726 |
|
|
#define LTFS 0x1000 /* Low TX Frame Sync Select */
|
| 727 |
|
|
#define LATFS 0x2000 /* Late TX Frame Sync Select */
|
| 728 |
|
|
#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
|
| 729 |
|
|
/* SPORTx_RCR1 Deprecated Masks */
|
| 730 |
|
|
#define TULAW DTYPE_ULAW /* Compand Using u-Law */
|
| 731 |
|
|
#define TALAW DTYPE_ALAW /* Compand Using A-Law */
|
| 732 |
|
|
|
| 733 |
|
|
/* SPORTx_TCR2 Masks */
|
| 734 |
|
|
#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
|
| 735 |
|
|
defined(__ADSPBF533__)
|
| 736 |
|
|
# define SLEN 0x001F
|
| 737 |
|
|
#else
|
| 738 |
|
|
# define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
|
| 739 |
|
|
#endif
|
| 740 |
|
|
#define TXSE 0x0100 /*TX Secondary Enable */
|
| 741 |
|
|
#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
|
| 742 |
|
|
#define TRFST 0x0400 /*TX Right-First Data Order */
|
| 743 |
|
|
|
| 744 |
|
|
/* SPORTx_RCR1 Masks */
|
| 745 |
|
|
#define RSPEN 0x0001 /* RX enable */
|
| 746 |
|
|
#define IRCLK 0x0002 /* Internal RX Clock Select */
|
| 747 |
|
|
#define RDTYPE 0x000C /* RX Data Formatting Select */
|
| 748 |
|
|
#define DTYPE_NORM 0x0000 /* no companding */
|
| 749 |
|
|
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
|
| 750 |
|
|
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
|
| 751 |
|
|
#define RLSBIT 0x0010 /* RX Bit Order */
|
| 752 |
|
|
#define IRFS 0x0200 /* Internal RX Frame Sync Select */
|
| 753 |
|
|
#define RFSR 0x0400 /* RX Frame Sync Required Select */
|
| 754 |
|
|
#define LRFS 0x1000 /* Low RX Frame Sync Select */
|
| 755 |
|
|
#define LARFS 0x2000 /* Late RX Frame Sync Select */
|
| 756 |
|
|
#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
|
| 757 |
|
|
/* SPORTx_RCR1 Deprecated Masks */
|
| 758 |
|
|
#define RULAW DTYPE_ULAW /* Compand Using u-Law */
|
| 759 |
|
|
#define RALAW DTYPE_ALAW /* Compand Using A-Law */
|
| 760 |
|
|
|
| 761 |
|
|
/* SPORTx_RCR2 Masks */
|
| 762 |
|
|
/* SLEN defined above */
|
| 763 |
|
|
#define RXSE 0x0100 /*RX Secondary Enable */
|
| 764 |
|
|
#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
|
| 765 |
|
|
#define RRFST 0x0400 /*Right-First Data Order */
|
| 766 |
|
|
|
| 767 |
|
|
/*SPORTx_STAT Masks */
|
| 768 |
|
|
#define RXNE 0x0001 /*RX FIFO Not Empty Status */
|
| 769 |
|
|
#define RUVF 0x0002 /*RX Underflow Status */
|
| 770 |
|
|
#define ROVF 0x0004 /*RX Overflow Status */
|
| 771 |
|
|
#define TXF 0x0008 /*TX FIFO Full Status */
|
| 772 |
|
|
#define TUVF 0x0010 /*TX Underflow Status */
|
| 773 |
|
|
#define TOVF 0x0020 /*TX Overflow Status */
|
| 774 |
|
|
#define TXHRE 0x0040 /*TX Hold Register Empty */
|
| 775 |
|
|
|
| 776 |
|
|
/*SPORTx_MCMC1 Masks */
|
| 777 |
|
|
#define WSIZE 0x0000F000 /*Multichannel Window Size Field */
|
| 778 |
|
|
#define WOFF 0x000003FF /*Multichannel Window Offset Field */
|
| 779 |
|
|
/* SPORTx_MCMC1 Macros */
|
| 780 |
|
|
#define SET_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
|
| 781 |
|
|
/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
|
| 782 |
|
|
#define SET_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
|
| 783 |
|
|
|
| 784 |
|
|
/*SPORTx_MCMC2 Masks */
|
| 785 |
|
|
#define MCCRM 0x0003 /*Multichannel Clock Recovery Mode */
|
| 786 |
|
|
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
|
| 787 |
|
|
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
|
| 788 |
|
|
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
|
| 789 |
|
|
#define MCDTXPE 0x0004 /*Multichannel DMA Transmit Packing */
|
| 790 |
|
|
#define MCDRXPE 0x0008 /*Multichannel DMA Receive Packing */
|
| 791 |
|
|
#define MCMEN 0x0010 /*Multichannel Frame Mode Enable */
|
| 792 |
|
|
#define FSDR 0x0080 /*Multichannel Frame Sync to Data Relationship */
|
| 793 |
|
|
#define MFD 0xF000 /*Multichannel Frame Delay */
|
| 794 |
|
|
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
|
| 795 |
|
|
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
|
| 796 |
|
|
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
|
| 797 |
|
|
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
|
| 798 |
|
|
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
|
| 799 |
|
|
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
|
| 800 |
|
|
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
|
| 801 |
|
|
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
|
| 802 |
|
|
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
|
| 803 |
|
|
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
|
| 804 |
|
|
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
|
| 805 |
|
|
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
|
| 806 |
|
|
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
|
| 807 |
|
|
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
|
| 808 |
|
|
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
|
| 809 |
|
|
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
|
| 810 |
|
|
|
| 811 |
|
|
|
| 812 |
|
|
/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
|
| 813 |
|
|
/*// PPI_CONTROL Masks */
|
| 814 |
|
|
#define PORT_EN 0x0001 /* PPI Port Enable */
|
| 815 |
|
|
#define PORT_DIR 0x0002 /* PPI Port Direction */
|
| 816 |
|
|
#define XFR_TYPE 0x000C /* PPI Transfer Type */
|
| 817 |
|
|
#define PORT_CFG 0x0030 /* PPI Port Configuration */
|
| 818 |
|
|
#define FLD_SEL 0x0040 /* PPI Active Field Select */
|
| 819 |
|
|
#define PACK_EN 0x0080 /* PPI Packing Mode */
|
| 820 |
|
|
/* previous versions of defBF532.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
|
| 821 |
|
|
#define ALT_TIMING 0x0100 /* Enable Alternate PPI Timing (0.5 Silicon And Beyond) */
|
| 822 |
|
|
#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
|
| 823 |
|
|
#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
|
| 824 |
|
|
#define DLENGTH 0x3800 /* PPI Data Length */
|
| 825 |
|
|
#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
|
| 826 |
|
|
#define DLEN_10 0x0800 /* Data Length = 10 Bits */
|
| 827 |
|
|
#define DLEN_11 0x1000 /* Data Length = 11 Bits */
|
| 828 |
|
|
#define DLEN_12 0x1800 /* Data Length = 12 Bits */
|
| 829 |
|
|
#define DLEN_13 0x2000 /* Data Length = 13 Bits */
|
| 830 |
|
|
#define DLEN_14 0x2800 /* Data Length = 14 Bits */
|
| 831 |
|
|
#define DLEN_15 0x3000 /* Data Length = 15 Bits */
|
| 832 |
|
|
#define DLEN_16 0x3800 /* Data Length = 16 Bits */
|
| 833 |
|
|
#define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
|
| 834 |
|
|
#define POL 0xC000 /* PPI Signal Polarities */
|
| 835 |
|
|
#define POLC 0x4000 /* PPI Clock Polarity */
|
| 836 |
|
|
#define POLS 0x8000 /* PPI Frame Sync Polarity */
|
| 837 |
|
|
|
| 838 |
|
|
|
| 839 |
|
|
/*// PPI_STATUS Masks */
|
| 840 |
|
|
#define FLD 0x0400 /* Field Indicator */
|
| 841 |
|
|
#define FT_ERR 0x0800 /* Frame Track Error */
|
| 842 |
|
|
#define OVR 0x1000 /* FIFO Overflow Error */
|
| 843 |
|
|
#define UNDR 0x2000 /* FIFO Underrun Error */
|
| 844 |
|
|
#define ERR_DET 0x4000 /* Error Detected Indicator */
|
| 845 |
|
|
#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
|
| 846 |
|
|
|
| 847 |
|
|
|
| 848 |
|
|
/* ********** DMA CONTROLLER MASKS ***********************/
|
| 849 |
|
|
/*//DMAx_CONFIG, MDMA_yy_CONFIG Masks */
|
| 850 |
|
|
#define DMAEN 0x0001 /* Channel Enable */
|
| 851 |
|
|
#define WNR 0x0002 /* Channel Direction (W/R*) */
|
| 852 |
|
|
#define WDSIZE_8 0x0000 /* Word Size 8 bits */
|
| 853 |
|
|
#define WDSIZE_16 0x0004 /* Word Size 16 bits */
|
| 854 |
|
|
#define WDSIZE_32 0x0008 /* Word Size 32 bits */
|
| 855 |
|
|
#define DMA2D 0x0010 /* 2D/1D* Mode */
|
| 856 |
|
|
#define RESTART 0x0020 /* Restart */
|
| 857 |
|
|
#define DI_SEL 0x0040 /* Data Interrupt Select */
|
| 858 |
|
|
#define DI_EN 0x0080 /* Data Interrupt Enable */
|
| 859 |
|
|
#define NDSIZE 0x0900 /* Next Descriptor Size */
|
| 860 |
|
|
#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
|
| 861 |
|
|
#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
|
| 862 |
|
|
#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
|
| 863 |
|
|
#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
|
| 864 |
|
|
#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
|
| 865 |
|
|
#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
|
| 866 |
|
|
#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
|
| 867 |
|
|
#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
|
| 868 |
|
|
#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
|
| 869 |
|
|
#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
|
| 870 |
|
|
#define FLOW 0x7000 /* Flow Control */
|
| 871 |
|
|
#define FLOW_STOP 0x0000 /* Stop Mode */
|
| 872 |
|
|
#define FLOW_AUTO 0x1000 /* Autobuffer Mode */
|
| 873 |
|
|
#define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */
|
| 874 |
|
|
#define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
|
| 875 |
|
|
#define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
|
| 876 |
|
|
|
| 877 |
|
|
#define DMAEN_P 0x0 /* Channel Enable */
|
| 878 |
|
|
#define WNR_P 0x1 /* Channel Direction (W/R*) */
|
| 879 |
|
|
#define DMA2D_P 0x4 /* 2D/1D* Mode */
|
| 880 |
|
|
#define RESTART_P 0x5 /* Restart */
|
| 881 |
|
|
#define DI_SEL_P 0x6 /* Data Interrupt Select */
|
| 882 |
|
|
#define DI_EN_P 0x7 /* Data Interrupt Enable */
|
| 883 |
|
|
|
| 884 |
|
|
/*//DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
|
| 885 |
|
|
#define DMA_DONE 0x0001 /* DMA Done Indicator */
|
| 886 |
|
|
#define DMA_ERR 0x0002 /* DMA Error Indicator */
|
| 887 |
|
|
#define DFETCH 0x0004 /* Descriptor Fetch Indicator */
|
| 888 |
|
|
#define DMA_RUN 0x0008 /* DMA Running Indicator */
|
| 889 |
|
|
|
| 890 |
|
|
#define DMA_DONE_P 0x0 /* DMA Done Indicator */
|
| 891 |
|
|
#define DMA_ERR_P 0x1 /* DMA Error Indicator */
|
| 892 |
|
|
#define DFETCH_P 0x2 /* Descriptor Fetch Indicator */
|
| 893 |
|
|
#define DMA_RUN_P 0x3 /* DMA Running Indicator */
|
| 894 |
|
|
|
| 895 |
|
|
/*//DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
|
| 896 |
|
|
|
| 897 |
|
|
#define CTYPE 0x0040 /* DMA Channel Type Indicator */
|
| 898 |
|
|
#define CTYPE_P 0x6 /* DMA Channel Type Indicator BIT POSITION */
|
| 899 |
|
|
#define PCAP8 0x0080 /* DMA 8-bit Operation Indicator */
|
| 900 |
|
|
#define PCAP16 0x0100 /* DMA 16-bit Operation Indicator */
|
| 901 |
|
|
#define PCAP32 0x0200 /* DMA 32-bit Operation Indicator */
|
| 902 |
|
|
#define PCAPWR 0x0400 /* DMA Write Operation Indicator */
|
| 903 |
|
|
#define PCAPRD 0x0800 /* DMA Read Operation Indicator */
|
| 904 |
|
|
#define PMAP 0xF000 /* DMA Peripheral Map Field */
|
| 905 |
|
|
|
| 906 |
|
|
#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
|
| 907 |
|
|
#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
|
| 908 |
|
|
#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
|
| 909 |
|
|
#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
|
| 910 |
|
|
#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
|
| 911 |
|
|
#define PMAP_SPI 0x5000 /* PMAP SPI DMA */
|
| 912 |
|
|
#define PMAP_UARTRX 0x6000 /* PMAP UART Receive DMA */
|
| 913 |
|
|
#define PMAP_UARTTX 0x7000 /* PMAP UART Transmit DMA */
|
| 914 |
|
|
|
| 915 |
|
|
|
| 916 |
|
|
/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
|
| 917 |
|
|
/* PWM Timer bit definitions */
|
| 918 |
|
|
/* TIMER_ENABLE Register */
|
| 919 |
|
|
#define TIMEN0 0x0001 /* Enable Timer 0 */
|
| 920 |
|
|
#define TIMEN1 0x0002 /* Enable Timer 1 */
|
| 921 |
|
|
#define TIMEN2 0x0004 /* Enable Timer 2 */
|
| 922 |
|
|
|
| 923 |
|
|
#define TIMEN0_P 0x00
|
| 924 |
|
|
#define TIMEN1_P 0x01
|
| 925 |
|
|
#define TIMEN2_P 0x02
|
| 926 |
|
|
|
| 927 |
|
|
/* TIMER_DISABLE Register */
|
| 928 |
|
|
#define TIMDIS0 0x0001 /* Disable Timer 0 */
|
| 929 |
|
|
#define TIMDIS1 0x0002 /* Disable Timer 1 */
|
| 930 |
|
|
#define TIMDIS2 0x0004 /* Disable Timer 2 */
|
| 931 |
|
|
|
| 932 |
|
|
#define TIMDIS0_P 0x00
|
| 933 |
|
|
#define TIMDIS1_P 0x01
|
| 934 |
|
|
#define TIMDIS2_P 0x02
|
| 935 |
|
|
|
| 936 |
|
|
/* TIMER_STATUS Register */
|
| 937 |
|
|
#define TIMIL0 0x0001 /* Timer 0 Interrupt */
|
| 938 |
|
|
#define TIMIL1 0x0002 /* Timer 1 Interrupt */
|
| 939 |
|
|
#define TIMIL2 0x0004 /* Timer 2 Interrupt */
|
| 940 |
|
|
#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
|
| 941 |
|
|
#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
|
| 942 |
|
|
#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
|
| 943 |
|
|
#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
|
| 944 |
|
|
#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
|
| 945 |
|
|
#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
|
| 946 |
|
|
|
| 947 |
|
|
#define TIMIL0_P 0x00
|
| 948 |
|
|
#define TIMIL1_P 0x01
|
| 949 |
|
|
#define TIMIL2_P 0x02
|
| 950 |
|
|
#define TOVF_ERR0_P 0x04
|
| 951 |
|
|
#define TOVF_ERR1_P 0x05
|
| 952 |
|
|
#define TOVF_ERR2_P 0x06
|
| 953 |
|
|
#define TRUN0_P 0x0C
|
| 954 |
|
|
#define TRUN1_P 0x0D
|
| 955 |
|
|
#define TRUN2_P 0x0E
|
| 956 |
|
|
|
| 957 |
|
|
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
|
| 958 |
|
|
#define TOVL_ERR0 TOVF_ERR0
|
| 959 |
|
|
#define TOVL_ERR1 TOVF_ERR1
|
| 960 |
|
|
#define TOVL_ERR2 TOVF_ERR2
|
| 961 |
|
|
#define TOVL_ERR0_P TOVF_ERR0_P
|
| 962 |
|
|
#define TOVL_ERR1_P TOVF_ERR1_P
|
| 963 |
|
|
#define TOVL_ERR2_P TOVF_ERR2_P
|
| 964 |
|
|
|
| 965 |
|
|
/* TIMERx_CONFIG Registers */
|
| 966 |
|
|
#define PWM_OUT 0x0001
|
| 967 |
|
|
#define WDTH_CAP 0x0002
|
| 968 |
|
|
#define EXT_CLK 0x0003
|
| 969 |
|
|
#define PULSE_HI 0x0004
|
| 970 |
|
|
#define PERIOD_CNT 0x0008
|
| 971 |
|
|
#define IRQ_ENA 0x0010
|
| 972 |
|
|
#define TIN_SEL 0x0020
|
| 973 |
|
|
#define OUT_DIS 0x0040
|
| 974 |
|
|
#define CLK_SEL 0x0080
|
| 975 |
|
|
#define TOGGLE_HI 0x0100
|
| 976 |
|
|
#define EMU_RUN 0x0200
|
| 977 |
|
|
#define ERR_TYP(x) (((x) & 0x03) << 14)
|
| 978 |
|
|
|
| 979 |
|
|
#define TMODE_P0 0x00
|
| 980 |
|
|
#define TMODE_P1 0x01
|
| 981 |
|
|
#define PULSE_HI_P 0x02
|
| 982 |
|
|
#define PERIOD_CNT_P 0x03
|
| 983 |
|
|
#define IRQ_ENA_P 0x04
|
| 984 |
|
|
#define TIN_SEL_P 0x05
|
| 985 |
|
|
#define OUT_DIS_P 0x06
|
| 986 |
|
|
#define CLK_SEL_P 0x07
|
| 987 |
|
|
#define TOGGLE_HI_P 0x08
|
| 988 |
|
|
#define EMU_RUN_P 0x09
|
| 989 |
|
|
#define ERR_TYP_P0 0x0E
|
| 990 |
|
|
#define ERR_TYP_P1 0x0F
|
| 991 |
|
|
|
| 992 |
|
|
|
| 993 |
|
|
/*/ ****************** GENERAL-PURPOSE I/O ********************* */
|
| 994 |
|
|
/* Port F (Previously Flag I/O_ Masks */
|
| 995 |
|
|
#define PF0 0x0001
|
| 996 |
|
|
#define PF1 0x0002
|
| 997 |
|
|
#define PF2 0x0004
|
| 998 |
|
|
#define PF3 0x0008
|
| 999 |
|
|
#define PF4 0x0010
|
| 1000 |
|
|
#define PF5 0x0020
|
| 1001 |
|
|
#define PF6 0x0040
|
| 1002 |
|
|
#define PF7 0x0080
|
| 1003 |
|
|
#define PF8 0x0100
|
| 1004 |
|
|
#define PF9 0x0200
|
| 1005 |
|
|
#define PF10 0x0400
|
| 1006 |
|
|
#define PF11 0x0800
|
| 1007 |
|
|
#define PF12 0x1000
|
| 1008 |
|
|
#define PF13 0x2000
|
| 1009 |
|
|
#define PF14 0x4000
|
| 1010 |
|
|
#define PF15 0x8000
|
| 1011 |
|
|
|
| 1012 |
|
|
/* PORT F BIT POSITIONS */
|
| 1013 |
|
|
#define PF0_P 0x0
|
| 1014 |
|
|
#define PF1_P 0x1
|
| 1015 |
|
|
#define PF2_P 0x2
|
| 1016 |
|
|
#define PF3_P 0x3
|
| 1017 |
|
|
#define PF4_P 0x4
|
| 1018 |
|
|
#define PF5_P 0x5
|
| 1019 |
|
|
#define PF6_P 0x6
|
| 1020 |
|
|
#define PF7_P 0x7
|
| 1021 |
|
|
#define PF8_P 0x8
|
| 1022 |
|
|
#define PF9_P 0x9
|
| 1023 |
|
|
#define PF10_P 0xA
|
| 1024 |
|
|
#define PF11_P 0xB
|
| 1025 |
|
|
#define PF12_P 0xC
|
| 1026 |
|
|
#define PF13_P 0xD
|
| 1027 |
|
|
#define PF14_P 0xE
|
| 1028 |
|
|
#define PF15_P 0xF
|
| 1029 |
|
|
|
| 1030 |
|
|
|
| 1031 |
|
|
/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
|
| 1032 |
|
|
/* SPI_CTL Masks */
|
| 1033 |
|
|
#define TIMOD 0x0003 /* Transfer Initiate Mode */
|
| 1034 |
|
|
#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
|
| 1035 |
|
|
#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
|
| 1036 |
|
|
#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
|
| 1037 |
|
|
#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
|
| 1038 |
|
|
#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
|
| 1039 |
|
|
#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
|
| 1040 |
|
|
#define PSSE 0x0010 /* Slave-Select Input Enable */
|
| 1041 |
|
|
#define EMISO 0x0020 /* Enable MISO As Output */
|
| 1042 |
|
|
#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
|
| 1043 |
|
|
#define LSBF 0x0200 /* LSB First */
|
| 1044 |
|
|
#define CPHA 0x0400 /* Clock Phase */
|
| 1045 |
|
|
#define CPOL 0x0800 /* Clock Polarity */
|
| 1046 |
|
|
#define MSTR 0x1000 /* Master/Slave* */
|
| 1047 |
|
|
#define WOM 0x2000 /* Write Open Drain Master */
|
| 1048 |
|
|
#define SPE 0x4000 /* SPI Enable */
|
| 1049 |
|
|
|
| 1050 |
|
|
/* SPI_FLG Masks */
|
| 1051 |
|
|
#define FLS1 0x0002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
|
| 1052 |
|
|
#define FLS2 0x0004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
|
| 1053 |
|
|
#define FLS3 0x0008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
|
| 1054 |
|
|
#define FLS4 0x0010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
|
| 1055 |
|
|
#define FLS5 0x0020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
|
| 1056 |
|
|
#define FLS6 0x0040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
|
| 1057 |
|
|
#define FLS7 0x0080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
|
| 1058 |
|
|
|
| 1059 |
|
|
#define FLG1 0x0200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
|
| 1060 |
|
|
#define FLG2 0x0400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
|
| 1061 |
|
|
#define FLG3 0x0800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
|
| 1062 |
|
|
#define FLG4 0x1000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
|
| 1063 |
|
|
#define FLG5 0x2000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
|
| 1064 |
|
|
#define FLG6 0x4000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
|
| 1065 |
|
|
#define FLG7 0x8000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
|
| 1066 |
|
|
|
| 1067 |
|
|
/* SPI_FLG Bit Positions */
|
| 1068 |
|
|
#define FLS1_P 0x0001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
|
| 1069 |
|
|
#define FLS2_P 0x0002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
|
| 1070 |
|
|
#define FLS3_P 0x0003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
|
| 1071 |
|
|
#define FLS4_P 0x0004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
|
| 1072 |
|
|
#define FLS5_P 0x0005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
|
| 1073 |
|
|
#define FLS6_P 0x0006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
|
| 1074 |
|
|
#define FLS7_P 0x0007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
|
| 1075 |
|
|
#define FLG1_P 0x0009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
|
| 1076 |
|
|
#define FLG2_P 0x000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
|
| 1077 |
|
|
#define FLG3_P 0x000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
|
| 1078 |
|
|
#define FLG4_P 0x000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
|
| 1079 |
|
|
#define FLG5_P 0x000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
|
| 1080 |
|
|
#define FLG6_P 0x000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
|
| 1081 |
|
|
#define FLG7_P 0x000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
|
| 1082 |
|
|
|
| 1083 |
|
|
/* SPI_STAT Masks */
|
| 1084 |
|
|
#define SPIF 0x0001 /* Set (=1) when SPI single-word transfer complete */
|
| 1085 |
|
|
#define MODF 0x0002 /* Set (=1) in a master device when some other device tries to become master */
|
| 1086 |
|
|
#define TXE 0x0004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
|
| 1087 |
|
|
#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
|
| 1088 |
|
|
#define RBSY 0x0010 /* Set (=1) when data is received with RDBR full */
|
| 1089 |
|
|
#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
|
| 1090 |
|
|
#define TXCOL 0x0040 /* When set (=1), corrupt data may have been transmitted */
|
| 1091 |
|
|
|
| 1092 |
|
|
/* SPIx_FLG Masks */
|
| 1093 |
|
|
#define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */
|
| 1094 |
|
|
#define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */
|
| 1095 |
|
|
#define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */
|
| 1096 |
|
|
#define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */
|
| 1097 |
|
|
#define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */
|
| 1098 |
|
|
#define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */
|
| 1099 |
|
|
#define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */
|
| 1100 |
|
|
|
| 1101 |
|
|
|
| 1102 |
|
|
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
|
| 1103 |
|
|
/* EBIU_AMGCTL Masks */
|
| 1104 |
|
|
#define AMCKEN 0x0001 /* Enable CLKOUT */
|
| 1105 |
|
|
#define AMBEN_NONE 0x0000 /* All Banks Disabled */
|
| 1106 |
|
|
#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */
|
| 1107 |
|
|
#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */
|
| 1108 |
|
|
#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
|
| 1109 |
|
|
#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
|
| 1110 |
|
|
#define CDPRIO 0x0100 /* DMA has priority over core for for external accesses */
|
| 1111 |
|
|
|
| 1112 |
|
|
/* EBIU_AMGCTL Bit Positions */
|
| 1113 |
|
|
#define AMCKEN_P 0x0000 /* Enable CLKOUT */
|
| 1114 |
|
|
#define AMBEN_P0 0x0001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
|
| 1115 |
|
|
#define AMBEN_P1 0x0002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
|
| 1116 |
|
|
#define AMBEN_P2 0x0003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
|
| 1117 |
|
|
|
| 1118 |
|
|
/* EBIU_AMBCTL0 Masks */
|
| 1119 |
|
|
#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
|
| 1120 |
|
|
#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
|
| 1121 |
|
|
#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
|
| 1122 |
|
|
#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
|
| 1123 |
|
|
#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
|
| 1124 |
|
|
#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
|
| 1125 |
|
|
#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
|
| 1126 |
|
|
#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
|
| 1127 |
|
|
#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
|
| 1128 |
|
|
#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
|
| 1129 |
|
|
#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
|
| 1130 |
|
|
#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
|
| 1131 |
|
|
#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
|
| 1132 |
|
|
#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
|
| 1133 |
|
|
#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
|
| 1134 |
|
|
#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
|
| 1135 |
|
|
#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
|
| 1136 |
|
|
#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
|
| 1137 |
|
|
#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
|
| 1138 |
|
|
#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
|
| 1139 |
|
|
#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
|
| 1140 |
|
|
#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
|
| 1141 |
|
|
#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
|
| 1142 |
|
|
#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
|
| 1143 |
|
|
#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
|
| 1144 |
|
|
#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
|
| 1145 |
|
|
#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
|
| 1146 |
|
|
#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
|
| 1147 |
|
|
#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
|
| 1148 |
|
|
#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
|
| 1149 |
|
|
#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
|
| 1150 |
|
|
#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
|
| 1151 |
|
|
#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
|
| 1152 |
|
|
#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
|
| 1153 |
|
|
#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
|
| 1154 |
|
|
#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
|
| 1155 |
|
|
#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
|
| 1156 |
|
|
#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
|
| 1157 |
|
|
#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
|
| 1158 |
|
|
#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
|
| 1159 |
|
|
#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
|
| 1160 |
|
|
#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
|
| 1161 |
|
|
#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
|
| 1162 |
|
|
#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
|
| 1163 |
|
|
#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
|
| 1164 |
|
|
#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
|
| 1165 |
|
|
#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
|
| 1166 |
|
|
#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
|
| 1167 |
|
|
#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
|
| 1168 |
|
|
#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
|
| 1169 |
|
|
#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
|
| 1170 |
|
|
#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
|
| 1171 |
|
|
#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
|
| 1172 |
|
|
#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
|
| 1173 |
|
|
#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
|
| 1174 |
|
|
#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
|
| 1175 |
|
|
#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
|
| 1176 |
|
|
#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
|
| 1177 |
|
|
#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
|
| 1178 |
|
|
#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
|
| 1179 |
|
|
#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
|
| 1180 |
|
|
#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
|
| 1181 |
|
|
#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
|
| 1182 |
|
|
#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
|
| 1183 |
|
|
#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
|
| 1184 |
|
|
#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
|
| 1185 |
|
|
#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
|
| 1186 |
|
|
#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
|
| 1187 |
|
|
#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
|
| 1188 |
|
|
#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
|
| 1189 |
|
|
#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
|
| 1190 |
|
|
#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
|
| 1191 |
|
|
#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
|
| 1192 |
|
|
#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
|
| 1193 |
|
|
#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
|
| 1194 |
|
|
#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
|
| 1195 |
|
|
#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
|
| 1196 |
|
|
#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
|
| 1197 |
|
|
#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
|
| 1198 |
|
|
#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
|
| 1199 |
|
|
#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
|
| 1200 |
|
|
#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
|
| 1201 |
|
|
#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
|
| 1202 |
|
|
#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
|
| 1203 |
|
|
#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
|
| 1204 |
|
|
#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
|
| 1205 |
|
|
#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
|
| 1206 |
|
|
#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
|
| 1207 |
|
|
|
| 1208 |
|
|
/* EBIU_AMBCTL1 Masks */
|
| 1209 |
|
|
#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
|
| 1210 |
|
|
#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
|
| 1211 |
|
|
#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
|
| 1212 |
|
|
#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
|
| 1213 |
|
|
#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
|
| 1214 |
|
|
#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
|
| 1215 |
|
|
#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
|
| 1216 |
|
|
#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
|
| 1217 |
|
|
#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
|
| 1218 |
|
|
#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
|
| 1219 |
|
|
#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
|
| 1220 |
|
|
#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
|
| 1221 |
|
|
#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
|
| 1222 |
|
|
#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
|
| 1223 |
|
|
#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
|
| 1224 |
|
|
#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
|
| 1225 |
|
|
#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
|
| 1226 |
|
|
#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
|
| 1227 |
|
|
#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
|
| 1228 |
|
|
#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
|
| 1229 |
|
|
#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
|
| 1230 |
|
|
#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
|
| 1231 |
|
|
#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
|
| 1232 |
|
|
#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
|
| 1233 |
|
|
#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
|
| 1234 |
|
|
#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
|
| 1235 |
|
|
#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
|
| 1236 |
|
|
#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
|
| 1237 |
|
|
#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
|
| 1238 |
|
|
#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
|
| 1239 |
|
|
#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
|
| 1240 |
|
|
#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
|
| 1241 |
|
|
#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
|
| 1242 |
|
|
#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
|
| 1243 |
|
|
#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
|
| 1244 |
|
|
#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
|
| 1245 |
|
|
#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
|
| 1246 |
|
|
#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
|
| 1247 |
|
|
#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
|
| 1248 |
|
|
#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
|
| 1249 |
|
|
#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
|
| 1250 |
|
|
#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
|
| 1251 |
|
|
#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
|
| 1252 |
|
|
#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
|
| 1253 |
|
|
#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
|
| 1254 |
|
|
#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
|
| 1255 |
|
|
#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
|
| 1256 |
|
|
#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
|
| 1257 |
|
|
#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
|
| 1258 |
|
|
#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
|
| 1259 |
|
|
#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
|
| 1260 |
|
|
#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
|
| 1261 |
|
|
#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
|
| 1262 |
|
|
#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
|
| 1263 |
|
|
#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
|
| 1264 |
|
|
#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
|
| 1265 |
|
|
#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
|
| 1266 |
|
|
#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
|
| 1267 |
|
|
#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
|
| 1268 |
|
|
#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
|
| 1269 |
|
|
#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
|
| 1270 |
|
|
#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
|
| 1271 |
|
|
#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
|
| 1272 |
|
|
#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
|
| 1273 |
|
|
#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
|
| 1274 |
|
|
#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
|
| 1275 |
|
|
#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
|
| 1276 |
|
|
#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
|
| 1277 |
|
|
#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
|
| 1278 |
|
|
#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
|
| 1279 |
|
|
#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
|
| 1280 |
|
|
#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
|
| 1281 |
|
|
#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
|
| 1282 |
|
|
#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
|
| 1283 |
|
|
#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
|
| 1284 |
|
|
#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
|
| 1285 |
|
|
#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
|
| 1286 |
|
|
#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
|
| 1287 |
|
|
#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
|
| 1288 |
|
|
#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
|
| 1289 |
|
|
#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
|
| 1290 |
|
|
#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
|
| 1291 |
|
|
#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
|
| 1292 |
|
|
#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
|
| 1293 |
|
|
#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
|
| 1294 |
|
|
#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
|
| 1295 |
|
|
#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
|
| 1296 |
|
|
#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
|
| 1297 |
|
|
|
| 1298 |
|
|
/* ********************** SDRAM CONTROLLER MASKS *************************** */
|
| 1299 |
|
|
/* EBIU_SDGCTL Masks */
|
| 1300 |
|
|
#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
|
| 1301 |
|
|
#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
|
| 1302 |
|
|
#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
|
| 1303 |
|
|
#define PFE 0x00000010 /* Enable SDRAM prefetch */
|
| 1304 |
|
|
#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
|
| 1305 |
|
|
#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
|
| 1306 |
|
|
#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
|
| 1307 |
|
|
#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
|
| 1308 |
|
|
#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
|
| 1309 |
|
|
#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
|
| 1310 |
|
|
#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
|
| 1311 |
|
|
#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
|
| 1312 |
|
|
#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
|
| 1313 |
|
|
#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
|
| 1314 |
|
|
#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
|
| 1315 |
|
|
#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
|
| 1316 |
|
|
#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
|
| 1317 |
|
|
#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
|
| 1318 |
|
|
#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
|
| 1319 |
|
|
#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
|
| 1320 |
|
|
#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
|
| 1321 |
|
|
#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
|
| 1322 |
|
|
#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
|
| 1323 |
|
|
#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
|
| 1324 |
|
|
#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
|
| 1325 |
|
|
#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
|
| 1326 |
|
|
#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
|
| 1327 |
|
|
#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
|
| 1328 |
|
|
#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
|
| 1329 |
|
|
#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
|
| 1330 |
|
|
#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
|
| 1331 |
|
|
#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
|
| 1332 |
|
|
#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
|
| 1333 |
|
|
#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
|
| 1334 |
|
|
#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
|
| 1335 |
|
|
#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
|
| 1336 |
|
|
#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
|
| 1337 |
|
|
#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
|
| 1338 |
|
|
#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
|
| 1339 |
|
|
#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
|
| 1340 |
|
|
#define PUPSD 0x00200000 /*Power-up start delay */
|
| 1341 |
|
|
#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
|
| 1342 |
|
|
#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
|
| 1343 |
|
|
#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
|
| 1344 |
|
|
#define EBUFE 0x02000000 /* Enable external buffering timing */
|
| 1345 |
|
|
#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
|
| 1346 |
|
|
#define EMREN 0x10000000 /* Extended mode register enable */
|
| 1347 |
|
|
#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
|
| 1348 |
|
|
#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
|
| 1349 |
|
|
|
| 1350 |
|
|
/* EBIU_SDBCTL Masks */
|
| 1351 |
|
|
#define EBE 0x00000001 /* Enable SDRAM external bank */
|
| 1352 |
|
|
#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
|
| 1353 |
|
|
#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
|
| 1354 |
|
|
#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
|
| 1355 |
|
|
#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
|
| 1356 |
|
|
#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
|
| 1357 |
|
|
#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
|
| 1358 |
|
|
#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
|
| 1359 |
|
|
#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
|
| 1360 |
|
|
|
| 1361 |
|
|
/* EBIU_SDSTAT Masks */
|
| 1362 |
|
|
#define SDCI 0x00000001 /* SDRAM controller is idle */
|
| 1363 |
|
|
#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
|
| 1364 |
|
|
#define SDPUA 0x00000004 /* SDRAM power up active */
|
| 1365 |
|
|
#define SDRS 0x00000008 /* SDRAM is in reset state */
|
| 1366 |
|
|
#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
|
| 1367 |
|
|
#define BGSTAT 0x00000020 /* Bus granted */
|
| 1368 |
|
|
|
| 1369 |
|
|
#ifdef _MISRA_RULES
|
| 1370 |
|
|
#pragma diag(pop)
|
| 1371 |
|
|
#endif /* _MISRA_RULES */
|
| 1372 |
|
|
|
| 1373 |
|
|
#endif /* _DEF_BF532_H */
|
