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jeremybenn |
/*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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/************************************************************************
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*
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* anomaly_macros_rtl.h : $Revision: 1.1 $
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*
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* Copyright (C) 2008 Analog Devices, Inc.
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*
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* This file defines macros used within the run-time libraries to enable
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* certain anomaly workarounds for the appropriate chips and silicon
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* revisions. Certain macros are defined for silicon-revision none - this
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* is to ensure behaviour is unchanged from libraries supplied with
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* earlier tools versions, where a small number of anomaly workarounds
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* were applied in all library flavours. __FORCE_LEGACY_WORKAROUNDS__
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* is defined in this case.
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*
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* This file defines macros for a subset of all anomalies that may impact
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* the run-time libraries.
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*
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************************************************************************/
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#if !defined(__SILICON_REVISION__)
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#define __FORCE_LEGACY_WORKAROUNDS__
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#endif
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/* 05-00-0096 - PREFETCH, FLUSH, and FLUSHINV must be followed by a CSYNC
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**
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** ADSP-BF531/2/3 - revs 0.0-0.1,
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** ADSP-BF561 - revs 0.0-0.1 (not supported in VDSP++ 4.0)
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**
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*/
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#define WA_05000096 \
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((defined(__ADSPBF531__) || \
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defined(__ADSPBF532__) || \
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defined(__ADSPBF533__) || \
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defined(__ADSPBF561__)) && \
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((defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x1)) || \
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defined(__FORCE_LEGACY_WORKAROUNDS__)))
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/* 05-00-0109 - Reserved bits in SYSCFG register not set at power on
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**
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** ADSP-BF531/2/3 - revs 0.0-0.2 (fixed 0.3)
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** ADSP-BF561 - revs 0.0-0.2 (fixed 0.3. 0.0, 0.1 not supported in VDSP++ 4.0)
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**
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** Changes to start code.
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*/
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#define WA_05000109 \
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((defined(__ADSPBF531__) || \
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defined(__ADSPBF532__) || \
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defined(__ADSPBF533__) || \
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defined(__ADSPBF561__)) && \
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((defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
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defined(__FORCE_LEGACY_WORKAROUNDS__)))
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/* 05-00-0123 - DTEST_COMMAND initiated memory access may be incorrect if
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** data cache or DMA is active.
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**
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** ADSP-BF531/2/3 - revs 0.1-0.2 (fixed 0.3)
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** ADSP-BF561 - revs 0.0-0.2 (0.0 and 0.1 not supported in VDSP++ 4.0)
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*/
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#define WA_05000123 \
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((defined(__ADSPBF531__) || \
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defined(__ADSPBF532__) || \
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defined(__ADSPBF533__) || \
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defined(__ADSPBF561__)) && \
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((defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
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defined(__FORCE_LEGACY_WORKAROUNDS__)))
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/* 05-00-0125 - Erroneous exception when enabling cache
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**
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** ADSP-BF531/2/3 - revs 0.1-0.2 (fixed 0.3)
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** ADSP-BF561 - revs 0.0-0.2 (0.0 and 0.1 not supported in VDSP++ 4.0)
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**
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*/
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#define WA_05000125 \
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((defined(__ADSPBF531__) || \
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defined(__ADSPBF532__) || \
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defined(__ADSPBF533__) || \
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defined(__ADSPBF561__)) && \
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((defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
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defined(__FORCE_LEGACY_WORKAROUNDS__)))
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/* 05-00-0137 - DMEM_CONTROL<12> is not set on Reset
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**
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** ADSP-BF531/2/3 - revs 0.0-0.2 (fixed 0.3)
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**
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** Changes to start code.
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**
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*/
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#define WA_05000137 \
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((defined(__ADSPBF531__) || \
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defined(__ADSPBF532__) || \
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defined(__ADSPBF533__)) && \
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((defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
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defined(__FORCE_LEGACY_WORKAROUNDS__)))
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/* 05-00-0158 - "Boot fails when data cache enabled: Data from a Data Cache
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** fill can be corrupted after or during instruction DMA if certain core
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** stalls exist"
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**
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** Impacted:
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** BF533/3/1 : 0.0-0.4 (fixed 0.5)
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**
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** The workaround we have only works for si-revisions >= 0.3. No workaround for
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** ealier revisions.
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*/
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#define WA_05000158 \
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((defined(__ADSPBF531__) || \
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defined(__ADSPBF532__) || \
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defined(__ADSPBF533__)) && \
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((defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ == 0xffff || \
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(__SILICON_REVISION__ >= 0x3 && \
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__SILICON_REVISION__ < 0x5))) || \
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defined(__FORCE_LEGACY_WORKAROUNDS__)))
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/* 05-00-0204 - "Incorrect data read with write-through cache and
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** allocate cache lines on reads only mode.
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**
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** This problem is cache related with high speed clocks. It apparently does
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** not impact BF531 and BF532 because they cannot run at high enough clock
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** to cause the anomaly. We build libs for BF532 though so that means we will
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** need to do the workaround for BF532 and BF531 also.
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**
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** Also the 0.3 to 0.4 revision is not an inflexion for libs BF532 and BF561.
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** This means a RT check may be required to avoid doing the WA for 0.4.
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**
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** Impacted:
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** BF533 - 0.0-0.3 (fixed 0.4)
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** BF534 - 0.0 (fixed 0.1)
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** BF536 - 0.0 (fixed 0.1)
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** BF537 - 0.0 (fixed 0.1)
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** BF538 - 0.0 (fixed 0.1)
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** BF539 - 0.0 (fixed 0.1)
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** BF561 - 0.0-0.3 (fixed 0.4)
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*/
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#if defined(__ADI_LIB_BUILD__)
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# define __BUILDBF53123 1 /* building one single library for BF531/2/3 */
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#else
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# define __BUILDBF53123 0
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#endif
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#define WA_05000204 \
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((((__BUILDBF53123==1 && \
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(defined(__ADSPBF531__) || defined(__ADSPBF532__))) || \
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(defined(__ADSPBF533__) || defined(__ADSPBF561__))) && \
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(defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x3))) || \
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((defined(__ADSPBF534__) || defined(__ADSPBF536__) || \
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defined(__ADSPBF537__) || defined(__ADSPBF538__) || \
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defined(__ADSPBF539__)) && \
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(defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ == 0x0))))
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#if ((defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
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defined(__ADSPBF533__) || defined(__ADSPBF561__)) && \
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(defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ == 0x3)))
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/* check at RT for 0.4 revs when doing 204 workaround */
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# define WA_05000204_CHECK_AVOID_FOR_REV <=3
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#elif ((defined(__ADSPBF534__) || defined(__ADSPBF536__) || \
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defined(__ADSPBF537__) || defined(__ADSPBF538__) || \
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defined(__ADSPBF539__)) && \
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(defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ == 0x0)))
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/* check at RT for 0.4 revs when doing 204 workaround */
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# define WA_05000204_CHECK_AVOID_FOR_REV <1
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#else
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/* do not check at RT for 0.4 revs when doing 204 workaround */
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#endif
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/* 05-00-0258 - "Instruction Cache is corrupted when bit 9 and 12 of
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* the ICPLB Data registers differ"
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*
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| 198 |
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* When bit 9 and bit 12 of the ICPLB Data MMR differ, the cache may
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* not update properly. For example, for a particular cache line,
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| 200 |
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* the cache tag may be valid while the contents of that cache line
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| 201 |
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* are not present in the cache.
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*
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* Impacted:
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*
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| 205 |
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* BF531/2/3 - 0.0-0.4 (fixed 0.5)
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* BF534/6/7/8/9 - 0.0-0.2 (fixed 0.3)
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| 207 |
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* BF561 - 0.0-0.4 (fixed 0.5)
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| 208 |
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* BF535/AD6532/AD6900 - all revs
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*/
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| 211 |
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#define WA_05000258 \
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defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ == 0xffff || \
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| 214 |
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!defined(__ADSPLPBLACKFIN__) || \
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((defined(__ADSPBF531__) || \
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defined(__ADSPBF532__) || \
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| 217 |
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defined(__ADSPBF533__)) && \
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| 218 |
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(__SILICON_REVISION__ <= 0x4)) || \
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| 219 |
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((defined(__ADSPBF534__) || \
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| 220 |
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defined(__ADSPBF536__) || \
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| 221 |
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defined(__ADSPBF537__) || \
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defined(__ADSPBF538__) || \
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defined(__ADSPBF539__)) && \
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| 224 |
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(__SILICON_REVISION__ <= 0x2)) || \
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| 225 |
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((defined(__ADSPBF561__)) && \
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| 226 |
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(__SILICON_REVISION__ <= 0x4)) || \
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| 227 |
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((defined(__ADSPBF561__)) && \
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| 228 |
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(__SILICON_REVISION__ < 0x1)))
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| 229 |
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| 230 |
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/* 05-00-0259 - "Non-deterministic ICPLB descriptors delivered to
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* hardware". Whenever ICPLBs are disabled via an MMR write, immediately
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| 232 |
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* follow this write with a CSYNC, and locate the MMR write and CSYNC
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| 233 |
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* within the same aligned 64 bit word.
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| 234 |
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*
|
| 235 |
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* This problem impacts all revisions of Blackfins.
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| 236 |
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*/
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| 237 |
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| 238 |
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#define WA_05000259 \
|
| 239 |
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(defined(__ADSPBLACKFIN__) && defined(__SILICON_REVISION__))
|
| 240 |
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| 241 |
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| 242 |
|
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/* 05-00-0261 - "DCPLB_FAULT_ADDR MMR may be corrupted".
|
| 243 |
|
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* The DCPLB_FAULT_ADDR MMR may contain the fault address of a
|
| 244 |
|
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* aborted memory access which generated both a protection exception
|
| 245 |
|
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* and a stall.
|
| 246 |
|
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*
|
| 247 |
|
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* We work around this by initially ignoring a DCPLB miss exception
|
| 248 |
|
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* on the assumption that the faulting address might be invalid.
|
| 249 |
|
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* We return without servicing. The exception will be raised
|
| 250 |
|
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* again when the faulting instruction is re-executed. The fault
|
| 251 |
|
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* address is correct this time round so the miss exception can
|
| 252 |
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* be serviced as normal. The only complication is we have to
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| 253 |
|
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* ensure that we are about to service the same miss rather than
|
| 254 |
|
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* a miss raised within a higher-priority interrupt handler, where
|
| 255 |
|
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* the fault address could again be invalid. We therefore record
|
| 256 |
|
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* the last seen RETX and only service an exception when RETX and
|
| 257 |
|
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* the last seen RETX are equal.
|
| 258 |
|
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*
|
| 259 |
|
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* This problem impacts:
|
| 260 |
|
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* BF531/2/3 - rev 0.0-0.4 (fixed 0.5)
|
| 261 |
|
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* BF534/6/7/8/9 - rev 0.0-0.2 (fixed 0.3)
|
| 262 |
|
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* BF561 - rev 0.0-0.4 (fixed 0.5)
|
| 263 |
|
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*
|
| 264 |
|
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*/
|
| 265 |
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| 266 |
|
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#define WA_05000261 \
|
| 267 |
|
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defined(__SILICON_REVISION__) && \
|
| 268 |
|
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(__SILICON_REVISION__ == 0xffff || \
|
| 269 |
|
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((defined(__ADSPBF531__) || \
|
| 270 |
|
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defined(__ADSPBF532__) || \
|
| 271 |
|
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defined(__ADSPBF533__)) && \
|
| 272 |
|
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(__SILICON_REVISION__ <= 0x4)) || \
|
| 273 |
|
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((defined(__ADSPBF534__) || \
|
| 274 |
|
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defined(__ADSPBF536__) || \
|
| 275 |
|
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defined(__ADSPBF537__) || \
|
| 276 |
|
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defined(__ADSPBF538__) || \
|
| 277 |
|
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defined(__ADSPBF539__)) && \
|
| 278 |
|
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(__SILICON_REVISION__ <= 0x2)) || \
|
| 279 |
|
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((defined(__ADSPBF561__)) && \
|
| 280 |
|
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(__SILICON_REVISION__ <= 0x4)) || \
|
| 281 |
|
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((defined(__ADSPBF561__)) && \
|
| 282 |
|
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(__SILICON_REVISION__ < 0x1)))
|
| 283 |
|
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|
| 284 |
|
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/* 05-00-0229 - "SPI Slave Boot Mode Modifies Registers".
|
| 285 |
|
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* When the SPI slave boot completes, the final DMA IRQ is cleared
|
| 286 |
|
|
* but the DMA5_CONFIG and SPI_CTL registers are not reset to their
|
| 287 |
|
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* default states.
|
| 288 |
|
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*
|
| 289 |
|
|
* We work around this by resetting the registers to their default
|
| 290 |
|
|
* values at the beginning of the CRT. The only issue would be when
|
| 291 |
|
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* users boot from flash and make use of the DMA or serial port.
|
| 292 |
|
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* In this case, users would need to modify the CRT.
|
| 293 |
|
|
*
|
| 294 |
|
|
* This problem impacts all revisions of ADSP-BF531/2/3/8/9
|
| 295 |
|
|
*/
|
| 296 |
|
|
|
| 297 |
|
|
#define WA_05000229 \
|
| 298 |
|
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(defined(__ADSPBLACKFIN__) && defined (__SILICON_REVISION__) && \
|
| 299 |
|
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(defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
|
| 300 |
|
|
defined(__ADSPBF533__) || defined(__ADSPBF538__) || \
|
| 301 |
|
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defined(__ADSPBF539__)))
|
| 302 |
|
|
|
| 303 |
|
|
/* 05-00-0283 - "A system MMR write is stalled indefinitely when killed in a
|
| 304 |
|
|
* particular stage".
|
| 305 |
|
|
*
|
| 306 |
|
|
* Where an interrupt occurs killing a stalled system MMR write, and the ISR
|
| 307 |
|
|
* executes an SSYNC, execution execution may stall indefinitely".
|
| 308 |
|
|
*
|
| 309 |
|
|
* The workaround is to execute a mispredicted jump over a dummy MMR read,
|
| 310 |
|
|
* thus killing the read. Also to avoid a system MMR write in two slots
|
| 311 |
|
|
* after a not predicted conditional jump.
|
| 312 |
|
|
*
|
| 313 |
|
|
* This problem impacts:
|
| 314 |
|
|
* BF531/2/3 - all revs
|
| 315 |
|
|
* BF534/6/7/8/9 - all revs
|
| 316 |
|
|
* BF561/6 - all revs
|
| 317 |
|
|
*/
|
| 318 |
|
|
|
| 319 |
|
|
#define WA_05000283 \
|
| 320 |
|
|
defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__)
|
| 321 |
|
|
|
| 322 |
|
|
|
