OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [newlib-1.17.0/] [libgloss/] [m68k/] [cf-isv.S] - Blame information for rev 816

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 148 jeremybenn
/* The interrupt table.
2
 *
3
 * Copyright (c) 2006 CodeSourcery Inc
4
 *
5
 * The authors hereby grant permission to use, copy, modify, distribute,
6
 * and license this software and its documentation for any purpose, provided
7
 * that existing copyright notices are retained in all copies and that this
8
 * notice is included verbatim in any distributions. No written agreement,
9
 * license, or royalty fee is required for any of the authorized uses.
10
 * Modifications to this software may be copyrighted by their authors
11
 * and need not follow the licensing terms described here, provided that
12
 * the new terms are clearly indicated on the first page of each file where
13
 * they apply.
14
 */
15
 
16
        .macro SLOT,n,prefix=,suffix=
17
        .long __\prefix\n\suffix
18
        .endm
19
 
20
        .macro ISR n
21
        SLOT \n,interrupt,
22
        .endm
23
 
24
        .macro TRAP n
25
        SLOT \n,trap,
26
        .endm
27
 
28
        .macro FP n
29
        SLOT \n,fp_,
30
        .endm
31
 
32
        .macro UNIMP_OPCODE n
33
        SLOT \n,unimplemented_,_opcode
34
        .endm
35
 
36
        .macro BREAKPOINT_DEBUG n
37
        SLOT \n,,_breakpoint_debug_interrupt
38
        .endm
39
 
40
        .section .interrupt_vector,"a"
41
 
42
        .globl __interrupt_vector
43
__interrupt_vector:
44
 
45
        .long __stack                           /* 0 */
46
        .long __reset                           /* 1 */
47
        .long __access_error                    /* 2 */
48
        .long __address_error                   /* 3 */
49
        .long __illegal_instruction             /* 4 */
50
        .long __divide_by_zero                  /* 5 */
51
        ISR 6
52
        ISR 7
53
        .long __privilege_violation             /* 8 */
54
        .long __trace                           /* 9 */
55
        UNIMP_OPCODE line_a                     /* 10 */
56
        UNIMP_OPCODE line_f                     /* 11 */
57
        BREAKPOINT_DEBUG non_pc                 /* 12 */
58
        BREAKPOINT_DEBUG pc                     /* 13 */
59
        .long __format_error                    /* 14 */
60
        .irp N,15,16,17,18,19,20,21,22,23
61
        ISR \N                                  /* [15,24) */
62
        .endr
63
        .long __spurious_interrupt              /* 24 */
64
        .irp N,25,26,27,28,29,30,31
65
        ISR \N                                  /* [25,32) */
66
        .endr
67
        .irp N,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
68
        TRAP \N                                 /* [32,48) */
69
        .endr
70
        FP branch_unordered                     /* 48 */
71
        FP inexact_result                       /* 49 */
72
        FP divide_by_zero                       /* 50 */
73
        FP underflow                            /* 51 */
74
        FP operand_error                        /* 52 */
75
        FP overflow                             /* 53 */
76
        FP input_not_a_number                   /* 54 */
77
        FP input_denormalized_number            /* 55 */
78
        .irp N,56,57,58,59,60
79
        ISR \N                                  /* [56,61) */
80
        .endr
81
        .long __unsupported_instruction         /* 61 */
82
        .irp N,62,63
83
        ISR \N                                  /* [62,64) */
84
        .endr
85
        .irp N,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79
86
        ISR \N                  /* [64,80) */
87
        .endr
88
        .irp N,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95
89
        ISR \N                  /* [80,96) */
90
        .endr
91
        .irp N,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111
92
        ISR \N                  /* [96,112) */
93
        .endr
94
        .irp N,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127
95
        ISR \N                  /* [112,128) */
96
        .endr
97
        .irp N,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143
98
        ISR \N                  /* [128,144) */
99
        .endr
100
        .irp N,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159
101
        ISR \N                  /* [144,160) */
102
        .endr
103
        .irp N,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175
104
        ISR \N                  /* [160,176) */
105
        .endr
106
        .irp N,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191
107
        ISR \N                  /* [176,192) */
108
        .endr
109
        .irp N,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207
110
        ISR \N                  /* [192,208) */
111
        .endr
112
        .irp N,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223
113
        ISR \N                  /* [208,224) */
114
        .endr
115
        .irp N,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239
116
        ISR \N                  /* [224,240) */
117
        .endr
118
        .irp N,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255
119
        ISR \N                  /* [240,256) */
120
        .endr

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.