OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [newlib-1.17.0/] [libgloss/] [m68k/] [mc68681reg.h] - Blame information for rev 816

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 148 jeremybenn
/* mc68681reg.h -- Motorola mc68681 DUART register offsets.
2
 * Copyright (c) 1995 Cygnus Support
3
 *
4
 * The authors hereby grant permission to use, copy, modify, distribute,
5
 * and license this software and its documentation for any purpose, provided
6
 * that existing copyright notices are retained in all copies and that this
7
 * notice is included verbatim in any distributions. No written agreement,
8
 * license, or royalty fee is required for any of the authorized uses.
9
 * Modifications to this software may be copyrighted by their authors
10
 * and need not follow the licensing terms described here, provided that
11
 * the new terms are clearly indicated on the first page of each file where
12
 * they apply.
13
 */
14
 
15
#define DUART_MR1A      0x00            /* Mode Register A */
16
#define DUART_MR1A      0x00            /* Mode Register A */
17
#define DUART_SRA       0x01            /* Status Register A */
18
#define DUART_CSRA      0x01            /* Clock-Select Register A */
19
#define DUART_CRA       0x02            /* Command Register A */
20
#define DUART_RBA       0x03            /* Receive Buffer A */
21
#define DUART_TBA       0x03            /* Transmit Buffer A */
22
#define DUART_IPCR      0x04            /* Input Port Change Register */
23
#define DUART_ACR       0x04            /* Auxiliary Control Register */
24
#define DUART_ISR       0x05            /* Interrupt Status Register */
25
#define DUART_IMR       0x05            /* Interrupt Mask Register */
26
#define DUART_CUR       0x06            /* Counter Mode: current MSB */
27
#define DUART_CTUR      0x06            /* Counter/Timer upper reg */
28
#define DUART_CLR       0x07            /* Counter Mode: current LSB */
29
#define DUART_CTLR      0x07            /* Counter/Timer lower reg */
30
#define DUART_MR1B      0x08            /* Mode Register B */
31
#define DUART_MR2B      0x08            /* Mode Register B */
32
#define DUART_SRB       0x09            /* Status Register B */
33
#define DUART_CSRB      0x09            /* Clock-Select Register B */
34
#define DUART_CRB       0x0A            /* Command Register B */
35
#define DUART_RBB       0x0B            /* Receive Buffer B */
36
#define DUART_TBB       0x0B            /* Transmit Buffer A */
37
#define DUART_IVR       0x0C            /* Interrupt Vector Register */
38
#define DUART_IP        0x0D            /* Input Port */
39
#define DUART_OPCR      0x0D            /* Output Port Configuration Reg. */
40
#define DUART_STRTCC    0x0E            /* Start-Counter command */
41
#define DUART_OPRSET    0x0E            /* Output Port Reg, SET bits */
42
#define DUART_STOPCC    0x0F            /* Stop-Counter command */
43
#define DUART_OPRRST    0x0F            /* Output Port Reg, ReSeT bits */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.