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1 148 jeremybenn
/*
2
 * interrupt_vectors.s -- the interrupt handler jump table.
3
 *
4
 *
5
 * There are a total of 32 interrupt vector possible, however, only
6
 *   11 of those are currently used (the others are reserved). The
7
 *   order of vectors is as follows:
8
 *
9
 *     1. Boot Vector. Vector for power-on/reset.
10
 *     2. Software Vector. Vector for handling the SI instruction (an
11
 *          explicit interrupt caused by software).
12
 *     3. Break Vector. Vector for handling the Break instruction.
13
 *     4. Device 0 Vector. Service vector for device zero.
14
 *     5. Device 1 Vector. Service vector for device one.
15
 *     6. Device 2 Vector. Service vector for device two.
16
 *     7. Device 3 Vector. Service vector for device three.
17
 *     8. Device 4 Vector. Service vector for device four.
18
 *     9. Device 5 Vector. Service vector for device five.
19
 *    10. Device 6 Vector. Service vector for device six.
20
 *    11. Device 7 Vector. Service vector for device seven.
21
 *
22
 *   The rest of the interrupt vectors are reserved for future use.
23
 *
24
 *
25
 * Each jump table entry consists of the following two instructions:
26
 *
27
 *   jmp Label          ; Label as appropriate
28
 *   nop                ; implemented as or r0,r0,r0
29
 *
30
 *   The following labels are reserved for the vectors named above,
31
 *   respectively:
32
 *
33
 *     _BOOTIVEC, _SOFTIVEC, _BRKIVEC, _DEV0IVEC, _DEV1IVEC, _DEV2IVEC,
34
 *     _DEV3IVEC, _DEV4IVEC, _DEV5IVEC, _DEV6IVEC, _DEV7IVEC
35
 *
36
 *
37
 *
38
 * Copyright (c) 2001, 2002, 2003, 2004 Morpho Technologies
39
 *
40
 */
41
 
42
        .section .startup, "a", @progbits
43
        .global __boot_start
44
__boot_start:
45
_INTERRUPT_VECTOR_TABLE:
46
        jmp     _BOOTIVEC               ; Boot vector
47
        or      r0, r0, r0
48
        jmp     _SOFTIVEC               ; Vector for SI instruction
49
        or      r0,r0,r0
50
        jmp     _BRKIVEC                ; Vector for Break instruction
51
        or      r0,r0,r0
52
        ; The illegal instruction trap is not implemented.
53
_RESERVED1_IVEC:
54
        jmp     _RESERVED1_IVEC         ; Vector for illegal instruction
55
        or      r0,r0,r0
56
        jmp     _OVFIVEC                ; Vector for overflow exception
57
        or      r0,r0,r0
58
_RESERVED2_IVEC:
59
        jmp     _RESERVED2_IVEC
60
        or      r0,r0,r0
61
_RESERVED3_IVEC:
62
        jmp     _RESERVED3_IVEC
63
        or      r0,r0,r0
64
_RESERVED4_IVEC:
65
        jmp     _RESERVED4_IVEC
66
        or      r0,r0,r0
67
 
68
        .text
69
 
70
        .equ SI_IOPORT_ADR, _DEBUG_SW_SYSREQ_REG
71
        .equ SI_IOPORT_BIT, 0x1
72
        .equ BRK_IOPORT_ADR, _DEBUG_BREAK_REG
73
        .equ BRK_IOPORT_BIT, 0x1
74
 
75
        .global _BOOTIVEC
76
_BOOTIVEC:
77
        ; Initialize the interrupt controller's interrupt vector registers
78
        ldui    r1, #%hi16(_IVEC_DEFAULT)
79
        ori     r1, r1, #%lo16(_IVEC_DEFAULT)
80
        stw     r1, r0, #%lo16(_DEV0_INTERRUPT_REG)
81
        stw     r1, r0, #%lo16(_DEV1_INTERRUPT_REG)
82
        stw     r1, r0, #%lo16(_DEV2_INTERRUPT_REG)
83
        stw     r1, r0, #%lo16(_DEV3_INTERRUPT_REG)
84
        stw     r1, r0, #%lo16(_DEV4_INTERRUPT_REG)
85
        stw     r1, r0, #%lo16(_DEV5_INTERRUPT_REG)
86
        stw     r1, r0, #%lo16(_DEV6_INTERRUPT_REG)
87
        stw     r1, r0, #%lo16(_DEV7_INTERRUPT_REG)
88
        stw     r1, r0, #%lo16(_DEV8_INTERRUPT_REG)
89
        stw     r1, r0, #%lo16(_DEV9_INTERRUPT_REG)
90
        stw     r1, r0, #%lo16(_DEV10_INTERRUPT_REG)
91
        stw     r1, r0, #%lo16(_DEV11_INTERRUPT_REG)
92
        stw     r1, r0, #%lo16(_DEV12_INTERRUPT_REG)
93
        stw     r1, r0, #%lo16(_DEV13_INTERRUPT_REG)
94
        stw     r1, r0, #%lo16(_DEV14_INTERRUPT_REG)
95
        stw     r1, r0, #%lo16(_DEV15_INTERRUPT_REG)
96
        stw     r1, r0, #%lo16(_DEV16_INTERRUPT_REG)
97
        stw     r1, r0, #%lo16(_DEV17_INTERRUPT_REG)
98
        stw     r1, r0, #%lo16(_DEV18_INTERRUPT_REG)
99
 
100
        ; Statically initialized data must be copied from ROM to RAM.
101
        ; This is done in the C run-time start-up code (crt0.o).
102
 
103
        ; Jump to the beginning of the application and enable interrupts.
104
        jmp     _start
105
        ei
106
 
107
 
108
 
109
        ; Handler for the SI instruction. To perform a system call, the
110
        ; C model uses a trapping mechanism which executes an SI instruction.
111
        ; The Morpho Technologies simulator simply performs a branch to
112
        ; this vector to simulate the SI instruction (this is as the hardware
113
        ; behaves). In order to trigger the simulator that a system call
114
        ; is needed a write into the I/O register at address $40005 to
115
        ; set bit #2 (0x4) is necessary.
116
        ;
117
        ; The above address has been changed to 0x00031C and the bit number
118
        ; is zero. (The manifest constants have been changed to reflect this.)
119
        .global _SOFTIVEC
120
_SOFTIVEC:
121
        ; Build a frame to save registers.
122
        subi    sp, sp, #$8
123
        stw     r9, sp, #$4
124
        ldui    r9, #%hi16(SI_IOPORT_ADR)
125
        stw     r10, sp, #$0
126
        ori     r9, r9, #%lo16(SI_IOPORT_ADR)
127
        ori     r10, r0, #SI_IOPORT_BIT
128
        stw     r10, r9, #$0
129
        or      r0, r0, r0      ; SYS_call is handled by simulator here...
130
        ldw     r10, sp, #$0
131
        or      r0, r0, r0
132
        ldw     r9, sp, #$4
133
        reti    r14
134
        addi    sp, sp, #$8
135
 
136
 
137
 
138
        ; Handler for BREAK instruction. This handler triggers the simulator
139
        ; to send a SIGTRAP signal to gdb by writing to the I/O register at
140
        ; address $40005, setting bit #0 (0x1).
141
        ;
142
        ; The above address has been changed to 0x000304 and the bit number
143
        ; is zero. (The manifest constants have been changed to reflect this.)
144
        .global _BRKIVEC
145
_BRKIVEC:
146
        ; Build a frame to save registers.
147
        subi    sp, sp, #$8
148
        stw     r9, sp, #$4
149
        ldui    r9, #%hi16(BRK_IOPORT_ADR)
150
        stw     r10, sp, #$0
151
        ori     r9, r9, #%lo16(BRK_IOPORT_ADR)
152
        ori     r10, r0, #BRK_IOPORT_BIT
153
        stw     r10, r9, #$0
154
        or      r0, r0, r0
155
        or      r0, r0, r0
156
        or      r0, r0, r0
157
        or      r0, r0, r0
158
        or      r0, r0, r0
159
        ldw     r10, sp, #$0
160
        ldw     r9, sp, #$4
161
        reti    r15
162
        addi    sp, sp, #$8
163
 
164
 
165
        ; The documentation is lacking in the specification of the Overflow
166
        ;   Exception generation. The address of the instruction causing the
167
        ;   overflow is placed into R15 and the overflow exception interrupt
168
        ;   is triggered. So, to continue execution, return to the address
169
        ;   of the next instruction (i.e., R15 + one instruction).
170
_OVFIVEC:
171
        addi    r15, r15, #$4
172
        or      r0, r0, r0
173
        reti    r15
174
        or      r0, r0, r0
175
 
176
 
177
        .global _IVEC_DEFAULT
178
_IVEC_DEFAULT:
179
        reti    r15
180
        or      r0, r0, r0
181
 
182
 
183
        .section .internal_io, "a", @nobits
184
        .fill 256               ; Fill the first page.
185
 
186
        ; This is the memory-mapped I/O region.
187
 
188
        ; Hardware Interrupt Registers
189
        ;.org 0xfff100
190
        .global _DEV0_INTERRUPT_REG
191
_DEV0_INTERRUPT_REG:
192
        .word 0x00000000
193
 
194
        .global _DEV1_INTERRUPT_REG
195
_DEV1_INTERRUPT_REG:
196
        .word 0x00000000
197
 
198
        .global _DEV2_INTERRUPT_REG
199
_DEV2_INTERRUPT_REG:
200
        .word 0x00000000
201
 
202
        .global _DEV3_INTERRUPT_REG
203
_DEV3_INTERRUPT_REG:
204
        .word 0x00000000
205
 
206
        .global _DEV4_INTERRUPT_REG
207
_DEV4_INTERRUPT_REG:
208
        .word 0x00000000
209
 
210
        .global _DEV5_INTERRUPT_REG
211
_DEV5_INTERRUPT_REG:
212
        .word 0x00000000
213
 
214
        .global _DEV6_INTERRUPT_REG
215
_DEV6_INTERRUPT_REG:
216
        .word 0x00000000
217
 
218
        .global _DEV7_INTERRUPT_REG
219
_DEV7_INTERRUPT_REG:
220
        .word 0x00000000
221
 
222
        .global _DEV8_INTERRUPT_REG
223
_DEV8_INTERRUPT_REG:
224
        .word 0x00000000
225
 
226
        .global _DEV9_INTERRUPT_REG
227
_DEV9_INTERRUPT_REG:
228
        .word 0x00000000
229
 
230
        .global _DEV10_INTERRUPT_REG
231
_DEV10_INTERRUPT_REG:
232
        .word 0x00000000
233
 
234
        .global _DEV11_INTERRUPT_REG
235
_DEV11_INTERRUPT_REG:
236
        .word 0x00000000
237
 
238
        .global _DEV12_INTERRUPT_REG
239
_DEV12_INTERRUPT_REG:
240
        .word 0x00000000
241
 
242
        .global _DEV13_INTERRUPT_REG
243
_DEV13_INTERRUPT_REG:
244
        .word 0x00000000
245
 
246
        .global _DEV14_INTERRUPT_REG
247
_DEV14_INTERRUPT_REG:
248
        .word 0x00000000
249
 
250
        .global _DEV15_INTERRUPT_REG
251
_DEV15_INTERRUPT_REG:
252
        .word 0x00000000
253
 
254
        .global _DEV16_INTERRUPT_REG
255
_DEV16_INTERRUPT_REG:
256
        .word 0x00000000
257
 
258
        .global _DEV17_INTERRUPT_REG
259
_DEV17_INTERRUPT_REG:
260
        .word 0x00000000
261
 
262
        .global _DEV18_INTERRUPT_REG
263
_DEV18_INTERRUPT_REG:
264
        .word 0x00000000
265
 
266
        ; 128 bytes minus ten registers (four bytes per register)
267
        .fill (128 - 19 * 4)
268
 
269
        .global _INTERRUPT_MASK_REG
270
_INTERRUPT_MASK_REG:
271
        .word 0x00000000
272
 
273
        ; 128 bytes minus one register (four bytes per register)
274
        .fill (128 - 1 * 4)
275
 
276
 
277
        ;.org 0xfff200
278
        ; MorphoSys Decoder Registers
279
        .global _MS_DEC_CIRC_BUFF_SEL_REG
280
_MS_DEC_CIRC_BUFF_SEL_REG:
281
        .word 0x00000000
282
 
283
        .global _MS_DEC_SKIP_FACTOR_REG
284
_MS_DEC_SKIP_FACTOR_REG:
285
        .word 0x00000000
286
 
287
        .global _MS_DEC_CUSTOM_PERM_REG
288
_MS_DEC_CUSTOM_PERM_REG:
289
        .word 0x00000000
290
 
291
        .global _MS_DEC_CTXT_BASE_REG
292
_MS_DEC_CTXT_BASE_REG:
293
        .word 0x00000000
294
 
295
        .global _MS_DEC_LOOKUP_TBL_REG
296
_MS_DEC_LOOKUP_TBL_REG:
297
        .word 0x00000000
298
 
299
        .global _MS_CIRC_BUFF0_END_REG
300
_MS_CIRC_BUFF0_END_REG:
301
        .word (__FRAME_BUFFER_END)
302
 
303
        .global _MS_CIRC_BUFF0_SIZE_REG
304
_MS_CIRC_BUFF0_SIZE_REG:
305
        .word __FRAME_BUFFER_SIZE
306
 
307
        .global _MS_DATA_BLK0_END_REG
308
_MS_DATA_BLK0_END_REG:
309
        .word 0x00000000
310
 
311
        .global _MS_DATA_BLK0_SIZE_REG
312
_MS_DATA_BLK0_SIZE_REG:
313
        .word 0x00000000
314
 
315
        .global _MS_CIRC_BUFF1_END_REG
316
_MS_CIRC_BUFF1_END_REG:
317
        .word (__FRAME_BUFFER_END)
318
 
319
        .global _MS_CIRC_BUFF1_SIZE_REG
320
_MS_CIRC_BUFF1_SIZE_REG:
321
        .word __FRAME_BUFFER_SIZE
322
 
323
        .global _MS_DATA_BLK1_END_REG
324
_MS_DATA_BLK1_END_REG:
325
        .word 0x00000000
326
 
327
        .global _MS_DATA_BLK1_SIZE_REG
328
_MS_DATA_BLK1_SIZE_REG:
329
        .word 0x00000000
330
 
331
        .global _MS_CIRC_BUFF2_END_REG
332
_MS_CIRC_BUFF2_END_REG:
333
        .word (__FRAME_BUFFER_END)
334
 
335
        .global _MS_CIRC_BUFF2_SIZE_REG
336
_MS_CIRC_BUFF2_SIZE_REG:
337
        .word __FRAME_BUFFER_SIZE
338
 
339
        .global _MS_DATA_BLK2_END_REG
340
_MS_DATA_BLK2_END_REG:
341
        .word 0x00000000
342
 
343
        .global _MS_DATA_BLK2_SIZE_REG
344
_MS_DATA_BLK2_SIZE_REG:
345
        .word 0x00000000
346
 
347
        .global _MS_CIRC_BUFF3_END_REG
348
_MS_CIRC_BUFF3_END_REG:
349
        .word (__FRAME_BUFFER_END)
350
 
351
        .global _MS_CIRC_BUFF3_SIZE_REG
352
_MS_CIRC_BUFF3_SIZE_REG:
353
        .word __FRAME_BUFFER_SIZE
354
 
355
        .global _MS_DATA_BLK3_END_REG
356
_MS_DATA_BLK3_END_REG:
357
        .word 0x00000000
358
 
359
        .global _MS_DATA_BLK3_SIZE_REG
360
_MS_DATA_BLK3_SIZE_REG:
361
        .word 0x00000000
362
 
363
        .global _MS_CIRC_BUFF4_END_REG
364
_MS_CIRC_BUFF4_END_REG:
365
        .word (__FRAME_BUFFER_END)
366
 
367
        .global _MS_CIRC_BUFF4_SIZE_REG
368
_MS_CIRC_BUFF4_SIZE_REG:
369
        .word __FRAME_BUFFER_SIZE
370
 
371
        .global _MS_DATA_BLK4_END_REG
372
_MS_DATA_BLK4_END_REG:
373
        .word 0x00000000
374
 
375
        .global _MS_DATA_BLK4_SIZE_REG
376
_MS_DATA_BLK4_SIZE_REG:
377
        .word 0x00000000
378
 
379
        .global _MS_CIRC_BUFF5_END_REG
380
_MS_CIRC_BUFF5_END_REG:
381
        .word (__FRAME_BUFFER_END)
382
 
383
        .global _MS_CIRC_BUFF5_SIZE_REG
384
_MS_CIRC_BUFF5_SIZE_REG:
385
        .word __FRAME_BUFFER_SIZE
386
 
387
        .global _MS_DATA_BLK5_END_REG
388
_MS_DATA_BLK5_END_REG:
389
        .word 0x00000000
390
 
391
        .global _MS_DATA_BLK5_SIZE_REG
392
_MS_DATA_BLK5_SIZE_REG:
393
        .word 0x00000000
394
 
395
        .global _MS_CIRC_BUFF6_END_REG
396
_MS_CIRC_BUFF6_END_REG:
397
        .word (__FRAME_BUFFER_END)
398
 
399
        .global _MS_CIRC_BUFF6_SIZE_REG
400
_MS_CIRC_BUFF6_SIZE_REG:
401
        .word __FRAME_BUFFER_SIZE
402
 
403
        .global _MS_DATA_BLK6_END_REG
404
_MS_DATA_BLK6_END_REG:
405
        .word 0x00000000
406
 
407
        .global _MS_DATA_BLK6_SIZE_REG
408
_MS_DATA_BLK6_SIZE_REG:
409
        .word 0x00000000
410
 
411
        .global _MS_CIRC_BUFF7_END_REG
412
_MS_CIRC_BUFF7_END_REG:
413
        .word (__FRAME_BUFFER_END)
414
 
415
        .global _MS_CIRC_BUFF7_SIZE_REG
416
_MS_CIRC_BUFF7_SIZE_REG:
417
        .word __FRAME_BUFFER_SIZE
418
 
419
        .global _MS_DATA_BLK7_END_REG
420
_MS_DATA_BLK7_END_REG:
421
        .word 0x00000000
422
 
423
        .global _MS_DATA_BLK7_SIZE_REG
424
_MS_DATA_BLK7_SIZE_REG:
425
        .word 0x00000000
426
 
427
        .global _MS_DEC_AUTO_INC0_REG
428
_MS_DEC_AUTO_INC0_REG:
429
        .word 0x00000000
430
 
431
        .global _MS_DEC_AUTO_INC1_REG
432
_MS_DEC_AUTO_INC1_REG:
433
        .word 0x00000000
434
 
435
        .global _MS_DEC_AUTO_INC2_REG
436
_MS_DEC_AUTO_INC2_REG:
437
        .word 0x00000000
438
 
439
        .global _MS_DEC_AUTO_INC3_REG
440
_MS_DEC_AUTO_INC3_REG:
441
        .word 0x00000000
442
 
443
        .global _MS_DEC_AUTO_INC4_REG
444
_MS_DEC_AUTO_INC4_REG:
445
        .word 0x00000000
446
 
447
        .global _MS_DEC_AUTO_INC5_REG
448
_MS_DEC_AUTO_INC5_REG:
449
        .word 0x00000000
450
 
451
        .global _MS_DEC_AUTO_INC6_REG
452
_MS_DEC_AUTO_INC6_REG:
453
        .word 0x00000000
454
 
455
        .global _MS_DEC_AUTO_INC7_REG
456
_MS_DEC_AUTO_INC7_REG:
457
        .word 0x00000000
458
 
459
 
460
        ; 256 bytes minus forty-five registers (four bytes per register)
461
        .fill (256 - 45 * 4)
462
 
463
 
464
 
465
        ;.org 0xfff300
466
        ; Debug Registers
467
        .global _DEBUG_HALT_REG
468
_DEBUG_HALT_REG:
469
        .word 0x00000000
470
 
471
        .global _DEBUG_BREAK_REG
472
_DEBUG_BREAK_REG:
473
        .word 0x00000000
474
 
475
        ; There are five reserved registers.
476
        .fill (5 * 4)
477
 
478
        .global _DEBUG_SW_SYSREQ_REG
479
_DEBUG_SW_SYSREQ_REG:
480
        .word 0x00000000
481
 
482
        ; 256 bytes minus eight registers (four bytes per register)
483
        .fill (256 - 8 * 4)
484
 
485
 
486
 
487
        ;.org 0xfff400
488
        ; Sequence Generator Registers
489
        .global _SEQ_GEN_CTRL_REG
490
_SEQ_GEN_CTRL_REG:
491
        .word 0x00000000
492
 
493
        .global _SEQ_GEN_MASK_REGS
494
_SEQ_GEN_MASK_REGS:
495
        ; The mask registers consume two pages (less one control register).
496
        ; 512 bytes minus one register (four bytes per register).
497
        .fill (256 + 256 - 1 * 4)
498
 
499
 
500
 
501
        ;.org 0xfff600
502
        ; Timer Registers
503
        .global _TIMER0_VAL_REG
504
_TIMER0_VAL_REG:
505
        .word 0x00000000
506
 
507
        .global _TIMER1_VAL_REG
508
_TIMER1_VAL_REG:
509
        .word 0x00000000
510
 
511
        .global _TIMER2_VAL_REG
512
_TIMER2_VAL_REG:
513
        .word 0x00000000
514
 
515
        .global _TIMER3_VAL_REG
516
_TIMER3_VAL_REG:
517
        .word 0x00000000
518
 
519
        ; 256 bytes minus four registers (four bytes per register)
520
        .fill (256 - 4 * 4)
521
 
522
 
523
 
524
        ;.org 0xfff700
525
        ; Output Line Control Registers
526
        .global _OUTPUT0_CTRL
527
_OUTPUT0_CTRL:
528
        .word 0x00000000
529
 
530
        .global _OUTPUT1_CTRL
531
_OUTPUT1_CTRL:
532
        .word 0x00000000
533
 
534
        .global _OUTPUT2_CTRL
535
_OUTPUT2_CTRL:
536
        .word 0x00000000
537
 
538
        .global _OUTPUT3_CTRL
539
_OUTPUT3_CTRL:
540
        .word 0x00000000
541
 
542
        .global _OUTPUT4_CTRL
543
_OUTPUT4_CTRL:
544
        .word 0x00000000
545
 
546
        .global _OUTPUT5_CTRL
547
_OUTPUT5_CTRL:
548
        .word 0x00000000
549
 
550
        .global _OUTPUT6_CTRL
551
_OUTPUT6_CTRL:
552
        .word 0x00000000
553
 
554
        .global _OUTPUT7_CTRL
555
_OUTPUT7_CTRL:
556
        .word 0x00000000
557
 
558
        .global _OUTPUT8_CTRL
559
_OUTPUT8_CTRL:
560
        .word 0x00000000
561
 
562
        .global _OUTPUT9_CTRL
563
_OUTPUT9_CTRL:
564
        .word 0x00000000
565
 
566
        .global _OUTPUT10_CTRL
567
_OUTPUT10_CTRL:
568
        .word 0x00000000
569
 
570
        ;; 128 bytes minus eleven registers (four bytes per register)
571
        ;.fill (128 - 11 * 4)
572
 
573
        .global _INPUT0_CTRL
574
_INPUT0_CTRL:
575
        .word 0x00000000
576
 
577
        ;; 128 bytes minus one register (four bytes per register)
578
        ;.fill (128 - 1 * 4)
579
        ; 256 bytes minus twelve registers (four bytes per register)
580
        .fill (256 - 12 * 4)
581
 
582
 
583
 
584
        ;.org 0xfff800
585
        ; IQ Buffer Registers
586
        .global _IQ_BUFF_CTRL_REG
587
_IQ_BUFF_CTRL_REG:
588
        .word 0x00000000
589
 
590
        .global _IQ_BUFF_PARAMETER1_REG
591
_IQ_BUFF_PARAMETER1_REG:
592
        .word 0x00000000
593
 
594
        .global _IQ_BUFF_DATA_SIZE1_REG
595
_IQ_BUFF_DATA_SIZE1_REG:
596
        .word 0x00000000
597
 
598
        .global _IQ_BUFF_TRANSFER_SIZE1_REG
599
_IQ_BUFF_TRANSFER_SIZE1_REG:
600
        .word 0x00000000
601
 
602
        .global _IQ_BUFF_FB_ADDR1_REG
603
_IQ_BUFF_FB_ADDR1_REG:
604
        .word 0x00000000
605
 
606
        .global _IQ_BUFF_PARAMETER2_REG
607
_IQ_BUFF_PARAMETER2_REG:
608
        .word 0x00000000
609
 
610
        .global _IQ_BUFF_DATA_SIZE2_REG
611
_IQ_BUFF_DATA_SIZE2_REG:
612
        .word 0x00000000
613
 
614
        .global _IQ_BUFF_TRANSFER_SIZE2_REG
615
_IQ_BUFF_TRANSFER_SIZE2_REG:
616
        .word 0x00000000
617
 
618
        .global _IQ_BUFF_FB_ADDR2_REG
619
_IQ_BUFF_FB_ADDR2_REG:
620
        .word 0x00000000
621
 
622
        ; 256 bytes minus nine registers (four bytes per register)
623
        .fill (256 - 9 * 4)
624
 
625
 
626
        ;.org 0xfff900
627
        ; Reserved memory-mapped space.
628
        .fill (0x1000 - 0x900)

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