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[/] [openrisc/] [trunk/] [gnu-old/] [newlib-1.17.0/] [libgloss/] [mt/] [startup-16-003.S] - Blame information for rev 148

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1 148 jeremybenn
/*
2
 * $Header: /cvs/src/src/libgloss/mt/startup-16-003.S,v 1.2 2006/03/22 12:47:59 nathan Exp $
3
 *
4
 * interrupt_vectors.s -- the interrupt handler jump table.
5
 *
6
 *
7
 * There are a total of 32 interrupt vector possible, however, only
8
 *   11 of those are currently used (the others are reserved). The
9
 *   order of vectors is as follows:
10
 *
11
 *     1. Boot Vector. Vector for power-on/reset.
12
 *     2. Software Vector. Vector for handling the SI instruction (an
13
 *          explicit interrupt caused by software).
14
 *     3. Break Vector. Vector for handling the Break instruction.
15
 *     4. Device 0 Vector. Service vector for device zero.
16
 *     5. Device 1 Vector. Service vector for device one.
17
 *     6. Device 2 Vector. Service vector for device two.
18
 *     7. Device 3 Vector. Service vector for device three.
19
 *     8. Device 4 Vector. Service vector for device four.
20
 *     9. Device 5 Vector. Service vector for device five.
21
 *    10. Device 6 Vector. Service vector for device six.
22
 *    11. Device 7 Vector. Service vector for device seven.
23
 *
24
 *   The rest of the interrupt vectors are reserved for future use.
25
 *
26
 *
27
 * Each jump table entry consists of the following two instructions:
28
 *
29
 *   jmp Label          ; Label as appropriate
30
 *   nop                ; implemented as or r0,r0,r0
31
 *
32
 *   The following labels are reserved for the vectors named above,
33
 *   respectively:
34
 *
35
 *     _BOOTIVEC, _SOFTIVEC, _BRKIVEC, _DEV0IVEC, _DEV1IVEC, _DEV2IVEC,
36
 *     _DEV3IVEC, _DEV4IVEC, _DEV5IVEC, _DEV6IVEC, _DEV7IVEC
37
 *
38
 *   09Jan04 (DJK) Modified internal I/O port definitions for the
39
 *                   MS1-16-003.
40
 *
41
 *   10Oct01 (DJK) The memory map is finalized and the first 4K of address
42
 *                   space is now reserved for memory-mapped I/O devices.
43
 *                   (There is over 2K unused, reserved space in this area.)
44
 *
45
 *   26Sep01 (DJK) The memory map is changed and the device interrupts are
46
 *                   now memory-mapped.
47
 *
48
 *
49
 *
50
 * Copyright (c) 2001, 2002, 2003, 2004 Morpho Technologies
51
 *
52
 */
53
 
54
        .section .startup, "a", @progbits
55
        .global __boot_start
56
__boot_start:
57
_INTERRUPT_VECTOR_TABLE:
58
        jmp     _BOOTIVEC               ; Boot vector
59
        or      r0, r0, r0
60
        jmp     _SOFTIVEC               ; Vector for SI instruction
61
        or      r0,r0,r0
62
        jmp     _BRKIVEC                ; Vector for Break instruction
63
        or      r0,r0,r0
64
        ; The illegal instruction trap is not implemented.
65
        ;jmp    _ILLIVEC                ; Vector for illegal instruction
66
        or      r0,r0,r0
67
        or      r0,r0,r0
68
_RESERVED1_IVEC:
69
        jmp     _RESERVED1_IVEC
70
        or      r0,r0,r0
71
_RESERVED2_IVEC:
72
        jmp     _RESERVED2_IVEC
73
        or      r0,r0,r0
74
_RESERVED3_IVEC:
75
        jmp     _RESERVED3_IVEC
76
        or      r0,r0,r0
77
_RESERVED4_IVEC:
78
        jmp     _RESERVED4_IVEC
79
        or      r0,r0,r0
80
 
81
 
82
        .text
83
 
84
        .equ SI_IOPORT_ADR, _DEBUG_SW_SYSREQ_REG
85
        .equ SI_IOPORT_BIT, 0x1
86
        .equ BRK_IOPORT_ADR, _DEBUG_BREAK_REG
87
        .equ BRK_IOPORT_BIT, 0x1
88
 
89
        .global _BOOTIVEC
90
_BOOTIVEC:
91
        ; Initialize the interrupt controller's interrupt vector registers
92
        ldui    r1, #%hi16(_IVEC_DEFAULT)
93
        ori     r1, r1, #%lo16(_IVEC_DEFAULT)
94
        stw     r1, r0, #%lo16(_DEV0_INTERRUPT_REG)
95
        stw     r1, r0, #%lo16(_DEV1_INTERRUPT_REG)
96
        stw     r1, r0, #%lo16(_DEV2_INTERRUPT_REG)
97
        stw     r1, r0, #%lo16(_DEV3_INTERRUPT_REG)
98
        stw     r1, r0, #%lo16(_DEV4_INTERRUPT_REG)
99
        stw     r1, r0, #%lo16(_DEV5_INTERRUPT_REG)
100
        stw     r1, r0, #%lo16(_DEV6_INTERRUPT_REG)
101
        stw     r1, r0, #%lo16(_DEV7_INTERRUPT_REG)
102
        stw     r1, r0, #%lo16(_DEV8_INTERRUPT_REG)
103
        stw     r1, r0, #%lo16(_DEV9_INTERRUPT_REG)
104
        stw     r1, r0, #%lo16(_DEV10_INTERRUPT_REG)
105
        stw     r1, r0, #%lo16(_DEV11_INTERRUPT_REG)
106
        stw     r1, r0, #%lo16(_DEV12_INTERRUPT_REG)
107
        stw     r1, r0, #%lo16(_DEV13_INTERRUPT_REG)
108
        stw     r1, r0, #%lo16(_DEV14_INTERRUPT_REG)
109
        stw     r1, r0, #%lo16(_DEV15_INTERRUPT_REG)
110
        stw     r1, r0, #%lo16(_DEV16_INTERRUPT_REG)
111
        stw     r1, r0, #%lo16(_DEV17_INTERRUPT_REG)
112
        stw     r1, r0, #%lo16(_DEV18_INTERRUPT_REG)
113
 
114
        ; Statically initialized data must be copied from ROM to RAM.
115
        ; This is done in the C run-time start-up code (crt0.o).
116
 
117
        ; Jump to the beginning of the application and enable interrupts.
118
        jmp     _start
119
        ei
120
 
121
 
122
        ; Handler for the SI instruction. To perform a system call, the
123
        ; C model uses a trapping mechanism which executes an SI instruction.
124
        ; The Morpho Technologies simulator simply performs a branch to
125
        ; this vector to simulate the SI instruction (this is as the hardware
126
        ; behaves). In order to trigger the simulator that a system call
127
        ; is needed a write into the I/O register at address $40005 to
128
        ; set bit #2 (0x4) is necessary.
129
        ;
130
        ; The above address has been changed to 0x00031C and the bit number
131
        ; is zero. (The manifest constants have been changed to reflect this.)
132
        .global _SOFTIVEC
133
_SOFTIVEC:
134
        ; Build a frame to save registers.
135
        subi    sp, sp, #$8
136
        stw     r9, sp, #$4
137
        ldui    r9, #%hi16(SI_IOPORT_ADR)
138
        stw     r10, sp, #$0
139
        ori     r9, r9, #%lo16(SI_IOPORT_ADR)
140
        ori     r10, r0, #SI_IOPORT_BIT
141
        stw     r10, r9, #$0
142
        ; SYS_call is handled by simulator here...
143
        or      r0, r0, r0
144
        ldw     r10, sp, #$0
145
        or      r0, r0, r0
146
        ldw     r9, sp, #$4
147
        reti    r14
148
        addi    sp, sp, #$8
149
 
150
 
151
 
152
        .global _BRKIVEC
153
_BRKIVEC:
154
        ; Build a frame to save registers.
155
        subi    sp, sp, #$8
156
        stw     r9, sp, #$4
157
        ldui    r9, #%hi16(BRK_IOPORT_ADR)
158
        stw     r10, sp, #$0
159
        ori     r9, r9, #%lo16(BRK_IOPORT_ADR)
160
        ori     r10, r0, #BRK_IOPORT_BIT
161
        stw     r10, r9, #$0
162
        or      r0, r0, r0
163
        or      r0, r0, r0
164
        or      r0, r0, r0
165
        or      r0, r0, r0
166
        or      r0, r0, r0
167
        ldw     r10, sp, #$0
168
        ldw     r9, sp, #$4
169
        reti    r15
170
        addi    sp, sp, #$8
171
 
172
 
173
.if 0
174
        ; Handler for illegal instruction.
175
        .global _ILLIVEC
176
_ILLIVEC:
177
        reti r15
178
        or r0, r0, r0
179
.endif
180
 
181
 
182
        .global _IVEC_DEFAULT
183
_IVEC_DEFAULT:
184
        reti    r15
185
        or      r0, r0, r0
186
 
187
 
188
        .section .internal_io, "a", @nobits
189
        .fill 256               ; Fill the first page.
190
 
191
        ; This is the memory-mapped I/O region.
192
 
193
        ; Hardware Interrupt Registers
194
        ;.org 0xfffff100
195
        .global _DEV0_INTERRUPT_REG
196
_DEV0_INTERRUPT_REG:
197
        .word 0x00000000
198
 
199
        .global _DEV1_INTERRUPT_REG
200
_DEV1_INTERRUPT_REG:
201
        .word 0x00000000
202
 
203
        .global _DEV2_INTERRUPT_REG
204
_DEV2_INTERRUPT_REG:
205
        .word 0x00000000
206
 
207
        .global _DEV3_INTERRUPT_REG
208
_DEV3_INTERRUPT_REG:
209
        .word 0x00000000
210
 
211
        .global _DEV4_INTERRUPT_REG
212
_DEV4_INTERRUPT_REG:
213
        .word 0x00000000
214
 
215
        .global _DEV5_INTERRUPT_REG
216
_DEV5_INTERRUPT_REG:
217
        .word 0x00000000
218
 
219
        .global _DEV6_INTERRUPT_REG
220
_DEV6_INTERRUPT_REG:
221
        .word 0x00000000
222
 
223
        .global _DEV7_INTERRUPT_REG
224
_DEV7_INTERRUPT_REG:
225
        .word 0x00000000
226
 
227
        .global _DEV8_INTERRUPT_REG
228
_DEV8_INTERRUPT_REG:
229
        .word 0x00000000
230
 
231
        .global _DEV9_INTERRUPT_REG
232
_DEV9_INTERRUPT_REG:
233
        .word 0x00000000
234
 
235
        .global _DEV10_INTERRUPT_REG
236
_DEV10_INTERRUPT_REG:
237
        .word 0x00000000
238
 
239
        .global _DEV11_INTERRUPT_REG
240
_DEV11_INTERRUPT_REG:
241
        .word 0x00000000
242
 
243
        .global _DEV12_INTERRUPT_REG
244
_DEV12_INTERRUPT_REG:
245
        .word 0x00000000
246
 
247
        .global _DEV13_INTERRUPT_REG
248
_DEV13_INTERRUPT_REG:
249
        .word 0x00000000
250
 
251
        .global _DEV14_INTERRUPT_REG
252
_DEV14_INTERRUPT_REG:
253
        .word 0x00000000
254
 
255
        .global _DEV15_INTERRUPT_REG
256
_DEV15_INTERRUPT_REG:
257
        .word 0x00000000
258
 
259
        .global _DEV16_INTERRUPT_REG
260
_DEV16_INTERRUPT_REG:
261
        .word 0x00000000
262
 
263
        .global _DEV17_INTERRUPT_REG
264
_DEV17_INTERRUPT_REG:
265
        .word 0x00000000
266
 
267
        .global _DEV18_INTERRUPT_REG
268
_DEV18_INTERRUPT_REG:
269
        .word 0x00000000
270
 
271
        ; 128 bytes minus nineteen registers (four bytes per register)
272
        .fill (128 - 19 * 4)
273
 
274
        .global _INTERRUPT_MASK_REG
275
_INTERRUPT_MASK_REG:
276
        .word 0x00000000
277
 
278
        .global _INTERRUPT_PENDING_REG
279
_INTERRUPT_PENDING_REG:
280
        .word 0x00000000
281
 
282
        ; 16 bytes minus two registers (four bytes per register)
283
        .fill (16 - 2 * 4)
284
 
285
        .global _DEV0_INTERRUPT_LEVEL_REG
286
_DEV0_INTERRUPT_LEVEL_REG:
287
        .word 0x00000000
288
 
289
        .global _DEV1_INTERRUPT_LEVEL_REG
290
_DEV1_INTERRUPT_LEVEL_REG:
291
        .word 0x00000000
292
 
293
        .global _DEV2_INTERRUPT_LEVEL_REG
294
_DEV2_INTERRUPT_LEVEL_REG:
295
        .word 0x00000000
296
 
297
        .global _DEV3_INTERRUPT_LEVEL_REG
298
_DEV3_INTERRUPT_LEVEL_REG:
299
        .word 0x00000000
300
 
301
        .global _DEV4_INTERRUPT_LEVEL_REG
302
_DEV4_INTERRUPT_LEVEL_REG:
303
        .word 0x00000000
304
 
305
        .global _DEV5_INTERRUPT_LEVEL_REG
306
_DEV5_INTERRUPT_LEVEL_REG:
307
        .word 0x00000000
308
 
309
        .global _DEV6_INTERRUPT_LEVEL_REG
310
_DEV6_INTERRUPT_LEVEL_REG:
311
        .word 0x00000000
312
 
313
        .global _DEV7_INTERRUPT_LEVEL_REG
314
_DEV7_INTERRUPT_LEVEL_REG:
315
        .word 0x00000000
316
 
317
        .global _DEV8_INTERRUPT_LEVEL_REG
318
_DEV8_INTERRUPT_LEVEL_REG:
319
        .word 0x00000000
320
 
321
        .global _DEV9_INTERRUPT_LEVEL_REG
322
_DEV9_INTERRUPT_LEVEL_REG:
323
        .word 0x00000000
324
 
325
        .global _DEV10_INTERRUPT_LEVEL_REG
326
_DEV10_INTERRUPT_LEVEL_REG:
327
        .word 0x00000000
328
 
329
        .global _DEV11_INTERRUPT_LEVEL_REG
330
_DEV11_INTERRUPT_LEVEL_REG:
331
        .word 0x00000000
332
 
333
        .global _DEV12_INTERRUPT_LEVEL_REG
334
_DEV12_INTERRUPT_LEVEL_REG:
335
        .word 0x00000000
336
 
337
        .global _DEV13_INTERRUPT_LEVEL_REG
338
_DEV13_INTERRUPT_LEVEL_REG:
339
        .word 0x00000000
340
 
341
        .global _DEV14_INTERRUPT_LEVEL_REG
342
_DEV14_INTERRUPT_LEVEL_REG:
343
        .word 0x00000000
344
 
345
        .global _DEV15_INTERRUPT_LEVEL_REG
346
_DEV15_INTERRUPT_LEVEL_REG:
347
        .word 0x00000000
348
 
349
        .global _DEV16_INTERRUPT_LEVEL_REG
350
_DEV16_INTERRUPT_LEVEL_REG:
351
        .word 0x00000000
352
 
353
        .global _DEV17_INTERRUPT_LEVEL_REG
354
_DEV17_INTERRUPT_LEVEL_REG:
355
        .word 0x00000000
356
 
357
        .global _DEV18_INTERRUPT_LEVEL_REG
358
_DEV18_INTERRUPT_LEVEL_REG:
359
        .word 0x00000000
360
 
361
        ; 128 bytes minus twenty-three registers (four bytes per register)
362
        .fill (128 - 23 * 4)
363
 
364
 
365
        ;.org 0xfffff200
366
        ; MorphoSys Decoder Registers
367
        .global _MS_DEC_CIRC_BUFF_SEL_REG
368
_MS_DEC_CIRC_BUFF_SEL_REG:
369
        .word 0x00000000
370
 
371
        .global _MS_DEC_SKIP_FACTOR_REG
372
_MS_DEC_SKIP_FACTOR_REG:
373
        .word 0x00000000
374
 
375
        .global _MS_DEC_CUSTOM_PERM_REG
376
_MS_DEC_CUSTOM_PERM_REG:
377
        .word 0x00000000
378
 
379
        .global _MS_DEC_CTXT_BASE_REG
380
_MS_DEC_CTXT_BASE_REG:
381
        .word 0x00000000
382
 
383
        .global _MS_DEC_LOOKUP_TBL_REG
384
_MS_DEC_LOOKUP_TBL_REG:
385
        .word 0x00000000
386
 
387
        .global _MS_CIRC_BUFF0_I_REG
388
_MS_CIRC_BUFF0_I_REG:
389
        .word (__FRAME_BUFFER_END)
390
 
391
        .global _MS_CIRC_BUFF0_P_REG
392
_MS_CIRC_BUFF0_P_REG:
393
        .word __FRAME_BUFFER_SIZE
394
 
395
        .global _MS_DATA_BUFF0_B_REG
396
_MS_DATA_BUFF0_B_REG:
397
        .word 0x00000000
398
 
399
        .global _MS_DATA_BUFF0_S_REG
400
_MS_DATA_BUFF0_S_REG:
401
        .word 0x00000000
402
 
403
        .global _MS_CIRC_BUFF1_I_REG
404
_MS_CIRC_BUFF1_I_REG:
405
        .word (__FRAME_BUFFER_END)
406
 
407
        .global _MS_CIRC_BUFF1_P_REG
408
_MS_CIRC_BUFF1_P_REG:
409
        .word __FRAME_BUFFER_SIZE
410
 
411
        .global _MS_DATA_BUFF1_B_REG
412
_MS_DATA_BUFF1_B_REG:
413
        .word 0x00000000
414
 
415
        .global _MS_DATA_BUFF1_S_REG
416
_MS_DATA_BUFF1_S_REG:
417
        .word 0x00000000
418
 
419
        .global _MS_CIRC_BUFF2_I_REG
420
_MS_CIRC_BUFF2_I_REG:
421
        .word (__FRAME_BUFFER_END)
422
 
423
        .global _MS_CIRC_BUFF2_P_REG
424
_MS_CIRC_BUFF2_P_REG:
425
        .word __FRAME_BUFFER_SIZE
426
 
427
        .global _MS_DATA_BUFF2_B_REG
428
_MS_DATA_BUFF2_B_REG:
429
        .word 0x00000000
430
 
431
        .global _MS_DATA_BUFF2_S_REG
432
_MS_DATA_BUFF2_S_REG:
433
        .word 0x00000000
434
 
435
        .global _MS_CIRC_BUFF3_I_REG
436
_MS_CIRC_BUFF3_I_REG:
437
        .word (__FRAME_BUFFER_END)
438
 
439
        .global _MS_CIRC_BUFF3_P_REG
440
_MS_CIRC_BUFF3_P_REG:
441
        .word __FRAME_BUFFER_SIZE
442
 
443
        .global _MS_DATA_BUFF3_B_REG
444
_MS_DATA_BUFF3_B_REG:
445
        .word 0x00000000
446
 
447
        .global _MS_DATA_BUFF3_S_REG
448
_MS_DATA_BUFF3_S_REG:
449
        .word 0x00000000
450
 
451
        .global _MS_CIRC_BUFF4_I_REG
452
_MS_CIRC_BUFF4_I_REG:
453
        .word (__FRAME_BUFFER_END)
454
 
455
        .global _MS_CIRC_BUFF4_P_REG
456
_MS_CIRC_BUFF4_P_REG:
457
        .word __FRAME_BUFFER_SIZE
458
 
459
        .global _MS_DATA_BUFF4_B_REG
460
_MS_DATA_BUFF4_B_REG:
461
        .word 0x00000000
462
 
463
        .global _MS_DATA_BUFF4_S_REG
464
_MS_DATA_BUFF4_S_REG:
465
        .word 0x00000000
466
 
467
        .global _MS_CIRC_BUFF5_I_REG
468
_MS_CIRC_BUFF5_I_REG:
469
        .word (__FRAME_BUFFER_END)
470
 
471
        .global _MS_CIRC_BUFF5_P_REG
472
_MS_CIRC_BUFF5_P_REG:
473
        .word __FRAME_BUFFER_SIZE
474
 
475
        .global _MS_DATA_BUFF5_B_REG
476
_MS_DATA_BUFF5_B_REG:
477
        .word 0x00000000
478
 
479
        .global _MS_DATA_BUFF5_S_REG
480
_MS_DATA_BUFF5_S_REG:
481
        .word 0x00000000
482
 
483
        .global _MS_CIRC_BUFF6_I_REG
484
_MS_CIRC_BUFF6_I_REG:
485
        .word (__FRAME_BUFFER_END)
486
 
487
        .global _MS_CIRC_BUFF6_P_REG
488
_MS_CIRC_BUFF6_P_REG:
489
        .word __FRAME_BUFFER_SIZE
490
 
491
        .global _MS_DATA_BUFF6_B_REG
492
_MS_DATA_BUFF6_B_REG:
493
        .word 0x00000000
494
 
495
        .global _MS_DATA_BUFF6_S_REG
496
_MS_DATA_BUFF6_S_REG:
497
        .word 0x00000000
498
 
499
        .global _MS_CIRC_BUFF7_I_REG
500
_MS_CIRC_BUFF7_I_REG:
501
        .word (__FRAME_BUFFER_END)
502
 
503
        .global _MS_CIRC_BUFF7_P_REG
504
_MS_CIRC_BUFF7_P_REG:
505
        .word __FRAME_BUFFER_SIZE
506
 
507
        .global _MS_DATA_BUFF7_B_REG
508
_MS_DATA_BUFF7_B_REG:
509
        .word 0x00000000
510
 
511
        .global _MS_DATA_BUFF7_S_REG
512
_MS_DATA_BUFF7_S_REG:
513
        .word 0x00000000
514
 
515
        .global _MS_OMEGA_PERM1_REG
516
_MS_OMEGA_PERM1_REG:
517
        .word 0x00000000
518
 
519
        .global _MS_WRITE_FB_ADDR_REG
520
_MS_WRITE_FB_ADDR_REG:
521
        .word 0x00000000
522
 
523
        .global _MS_OMEGA_PERM2_REG
524
_MS_OMEGA_PERM2_REG:
525
        .word 0x00000000
526
 
527
 
528
        ; 256 bytes minus forty registers (four bytes per register)
529
        .fill (256 - 40 * 4)
530
 
531
 
532
 
533
        ;.org 0xfffff300
534
        ; Debug Registers
535
        .global _DEBUG_HALT_REG
536
_DEBUG_HALT_REG:
537
        .word 0x00000000
538
 
539
        .global _DEBUG_BREAK_REG
540
_DEBUG_BREAK_REG:
541
        .word 0x00000000
542
 
543
        .global _DEBUG_CRITICAL_REG
544
_DEBUG_OWNERSHIP_REG:
545
        .word 0x00000000
546
 
547
        .global _DEBUG_KERNEL_ID_REG
548
_DEBUG_KERNEL_ID_REG:
549
        .word 0x00000000
550
 
551
        .global _DEBUG_IRQ_STATUS_REG
552
_DEBUG_IRQ_STATUS_REG:
553
        .word 0x00000000
554
 
555
        ; There are two reserved registers.
556
        .fill (2 * 4)
557
 
558
        .global _DEBUG_SW_SYSREQ_REG
559
_DEBUG_SW_SYSREQ_REG:
560
        .word 0x00000000
561
 
562
        ; 128 bytes minus eight registers (four bytes per register)
563
        .fill (128 - 8 * 4)
564
 
565
        .global _EXTENDED_GP0_REG
566
_EXTENDED_GP0_REG:
567
        .word 0x00000000
568
 
569
        .global _EXTENDED_GP1_REG
570
_EXTENDED_GP1_REG:
571
        .word 0x00000000
572
 
573
        .global _EXTENDED_GP2_REG
574
_EXTENDED_GP2_REG:
575
        .word 0x00000000
576
 
577
        .global _EXTENDED_GP3_REG
578
_EXTENDED_GP3_REG:
579
        .word 0x00000000
580
 
581
        .global _EXTENDED_GP4_REG
582
_EXTENDED_GP4_REG:
583
        .word 0x00000000
584
 
585
        .global _EXTENDED_GP5_REG
586
_EXTENDED_GP5_REG:
587
        .word 0x00000000
588
 
589
        .global _EXTENDED_GP6_REG
590
_EXTENDED_GP6_REG:
591
        .word 0x00000000
592
 
593
        .global _EXTENDED_GP7_REG
594
_EXTENDED_GP7_REG:
595
        .word 0x00000000
596
 
597
        .global _MEM_CTRL_EN_NC_MEM_REG
598
_MEM_CTRL_EN_NC_MEM_REG:
599
        .word 0x00000000
600
 
601
        .global _MEM_CTRL_BASE0_ADDR_REG
602
_MEM_CTRL_BASE0_ADDR_REG:
603
        .word 0x00000000
604
 
605
        .global _MEM_CTRL_MASK0_ADDR_REG
606
_MEM_CTRL_MASK0_ADDR_REG:
607
        .word 0x00000000
608
 
609
        .global _MEM_CTRL_BASE1_ADDR_REG
610
_MEM_CTRL_BASE1_ADDR_REG:
611
        .word 0x00000000
612
 
613
        .global _MEM_CTRL_MASK1_ADDR_REG
614
_MEM_CTRL_MASK1_ADDR_REG:
615
        .word 0x00000000
616
 
617
        .global _MEM_CTRL_BASE2_ADDR_REG
618
_MEM_CTRL_BASE2_ADDR_REG:
619
        .word 0x00000000
620
 
621
        .global _MEM_CTRL_MASK2_ADDR_REG
622
_MEM_CTRL_MASK2_ADDR_REG:
623
        .word 0x00000000
624
 
625
        .global _MEM_CTRL_BASE3_ADDR_REG
626
_MEM_CTRL_BASE3_ADDR_REG:
627
        .word 0x00000000
628
 
629
        .global _MEM_CTRL_MASK3_ADDR_REG
630
_MEM_CTRL_MASK3_ADDR_REG:
631
        .word 0x00000000
632
 
633
        ; 128 bytes minus seventeen registers (four bytes per register)
634
        .fill (128 - 17 * 4)
635
 
636
 
637
 
638
        ; Reserved memory-map space
639
        .fill (256 + 256)
640
 
641
 
642
 
643
        ;.org 0xfffff600
644
        ; Timer Registers
645
        .global _TIMER0_VAL_REG
646
_TIMER0_VAL_REG:
647
        .word 0x00000000
648
 
649
        .global _TIMER1_VAL_REG
650
_TIMER1_VAL_REG:
651
        .word 0x00000000
652
 
653
        .global _TIMER2_VAL_REG
654
_TIMER2_VAL_REG:
655
        .word 0x00000000
656
 
657
        .global _TIMER3_VAL_REG
658
_TIMER3_VAL_REG:
659
        .word 0x00000000
660
 
661
        ; 256 bytes minus four registers (four bytes per register)
662
        .fill (256 - 4 * 4)
663
 
664
 
665
 
666
        ;.org 0xfffff700
667
        ; Output Line Control Registers
668
        .global _OUTPUT0_CTRL
669
_OUTPUT0_CTRL:
670
        .word 0x00000000
671
 
672
        .global _OUTPUT1_CTRL
673
_OUTPUT1_CTRL:
674
        .word 0x00000000
675
 
676
        .global _OUTPUT2_CTRL
677
_OUTPUT2_CTRL:
678
        .word 0x00000000
679
 
680
        .global _OUTPUT3_CTRL
681
_OUTPUT3_CTRL:
682
        .word 0x00000000
683
 
684
        .global _OUTPUT4_CTRL
685
_OUTPUT4_CTRL:
686
        .word 0x00000000
687
 
688
        .global _OUTPUT5_CTRL
689
_OUTPUT5_CTRL:
690
        .word 0x00000000
691
 
692
        .global _OUTPUT6_CTRL
693
_OUTPUT6_CTRL:
694
        .word 0x00000000
695
 
696
        ; 128 bytes minus seven registers (four bytes per register)
697
        .fill (128 - 7 * 4)
698
 
699
        .global _INPUT0_CTRL
700
_INPUT0_CTRL:
701
        .word 0x00000000
702
 
703
        ; 128 bytes minus one register (four bytes per register)
704
        .fill (128 - 1 * 4)
705
 
706
 
707
 
708
        ;.org 0xfffff800
709
        ; IQ Buffer Registers
710
        .global _IQ_BUFF_CTRL_REG
711
_IQ_BUFF_CTRL_REG:
712
        .word 0x00000000
713
 
714
        .global _IQ_BUFF_STATUS_REG
715
_IQ_BUFF_STATUS_REG:
716
        .word 0x00000000
717
 
718
        .global _IQ_BUFF_PARAMETER1_REG
719
_IQ_BUFF_PARAMETER1_REG:
720
        .word 0x00000000
721
 
722
        .global _IQ_BUFF_TRANSFER_SIZE1_REG
723
_IQ_BUFF_TRANSFER_SIZE1_REG:
724
        .word 0x00000000
725
 
726
        .global _IQ_BUFF_FB_BASE1_REG
727
_IQ_BUFF_FB_BASE1_REG:
728
        .word 0x00000000
729
 
730
        .global _IQ_BUFF_FB_SIZE1_REG
731
_IQ_BUFF_FB_SIZE1_REG:
732
        .word 0x00000000
733
 
734
        .global _IQ_BUFF_PARAMETER2_REG
735
_IQ_BUFF_PARAMETER2_REG:
736
        .word 0x00000000
737
 
738
        .global _IQ_BUFF_TRANSFER_SIZE2_REG
739
_IQ_BUFF_TRANSFER_SIZE2_REG:
740
        .word 0x00000000
741
 
742
        .global _IQ_BUFF_FB_BASE2_REG
743
_IQ_BUFF_FB_BASE2_REG:
744
        .word 0x00000000
745
 
746
        .global _IQ_BUFF_FB_SIZE2_REG
747
_IQ_BUFF_FB_SIZE2_REG:
748
        .word 0x00000000
749
 
750
        ; 256 bytes minus ten registers (four bytes per register)
751
        .fill (256 - 10 * 4)
752
 
753
 
754
 
755
        ;.org 0xfffff900
756
        ; DMA Controller
757
        .global _DMA_CTRL_REG
758
_DMA_CTRL_REG:
759
        .word 0x00000000
760
 
761
        .global _DMA_STATUS_REG
762
_DMA_STATUS_REG:
763
        .word 0x00000000
764
 
765
        .global _DMA_CH0_EADDR_REG
766
_DMA_CH0_EADDR_REG:
767
        .word 0x00000000
768
 
769
        .global _DMA_CH0_IADDR_REG
770
_DMA_CH0_IADDR_REG:
771
        .word 0x00000000
772
 
773
        .global _DMA_CH0_SIZE_REG
774
_DMA_CH0_SIZE_REG:
775
        .word 0x00000000
776
 
777
        .global _DMA_CH1_EADDR_REG
778
_DMA_CH1_EADDR_REG:
779
        .word 0x00000000
780
 
781
        .global _DMA_CH1_IADDR_REG
782
_DMA_CH1_IADDR_REG:
783
        .word 0x00000000
784
 
785
        .global _DMA_CH1_SIZE_REG
786
_DMA_CH1_SIZE_REG:
787
        .word 0x00000000
788
 
789
        .global _DMA_CH2_EADDR_REG
790
_DMA_CH2_EADDR_REG:
791
        .word 0x00000000
792
 
793
        .global _DMA_CH2_IADDR_REG
794
_DMA_CH2_IADDR_REG:
795
        .word 0x00000000
796
 
797
        .global _DMA_CH2_SIZE_REG
798
_DMA_CH2_SIZE_REG:
799
        .word 0x00000000
800
 
801
        .global _DMA_CH3_EADDR_REG
802
_DMA_CH3_EADDR_REG:
803
        .word 0x00000000
804
 
805
        .global _DMA_CH3_IADDR_REG
806
_DMA_CH3_IADDR_REG:
807
        .word 0x00000000
808
 
809
        .global _DMA_CH3_SIZE_REG
810
_DMA_CH3_SIZE_REG:
811
        .word 0x00000000
812
 
813
        ; 256 bytes minus fourteen registers (four bytes per register)
814
        .fill (256 - 14 * 4)
815
 
816
 
817
 
818
        ;.org 0xfffffa00
819
        ; Sequence Generator
820
        .global _SEQ_GEN_CTRL_STATUS_REG
821
_SEQ_GEN_CTRL_STATUS_REG:
822
        .word 0x00000000
823
 
824
        .global _SEQ_GEN_MASK_REGS
825
_SEQ_GEN_MASK_REGS:
826
        .fill (302 * 4)
827
 
828
        .global _SEQ_GEN_SHIFT_REG
829
_SEQ_GEN_SHIFT_REG:
830
        .word 0x00000000
831
 
832
        ; 256 bytes minus seven registers (four bytes per register)
833
        .fill (256 - 48 * 4)
834
 
835
 
836
 
837
        ; Reserved memory-map space
838
        .fill (0x1000 - 0xf00)

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