OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [newlib-1.17.0/] [libgloss/] [or32/] [sim-uart.cfg] - Blame information for rev 822

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 184 jeremybenn
/* sim.cfg -- Simulator config file for use with Newlib
2
 *
3
 * Copyright (C) 2010, Embecosm Limited 
4
 *
5
 * Contributor Jeremy Bennett 
6
 *
7
 * This file is part of Newlib.
8
 *
9
 * This program is free software; you can redistribute it and/or modify it
10
 * under the terms of the GNU General Public License as published by the Free
11
 * Software Foundation; either version 2 of the License, or (at your option)
12
 * any later version.
13
 *
14
 * This program is distributed in the hope that it will be useful, but WITHOUT
15
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17
 * more details.
18
 *
19
 * You should have received a copy of the GNU General Public License along
20
 * with this program; if not, write to the Free Software Foundation, Inc., 675
21
 * Mass Ave, Cambridge, MA 02139, USA. */
22
/* -------------------------------------------------------------------------- */
23
/* This script is suitable for use with Or1ksim when used with newlib. There
24
 * are versions of this library which use a UART for input/output and a
25
 * version which provides just output via l.nop.
26
 *
27
 * For explanation of the different fields, see the default simulation
28
 * configuration file supplied with or1ksim (sim.cfg). */
29
/* -------------------------------------------------------------------------- */
30
 
31
section memory
32
  name     =      "RAM"
33
  type     =    unknown
34
  ce       =          0
35
  mc       =          0
36
  baseaddr = 0x00000000
37
  size     = 0x00800000
38
  delayr   =          1
39
  delayw   =          2
40
end
41
 
42
section sim
43
  verbose  =  0
44
  debug    =  0
45
  profile  =  0
46
  history  =  0
47
  clkcycle = 40ns               /* 25MHz clock */
48
end
49
 
50
section cpu
51
  ver         =   0x12
52
  cfg         =   0x00
53
  rev         = 0x0001
54
  superscalar =      0
55
  hazards     =      0
56
  dependstats =      0
57
  sbuf_len    =      0
58
end
59
 
60
/* Option sections which may be disabled on enabled, according to the precise
61
   options in or1ksim_board.h and the version of the library selected. */
62
 
63
section ic
64
  enabled   =   1
65
  nsets     = 256
66
  nways     =   1
67
  blocksize =  16
68
  hitdelay  =  20
69
  missdelay =  20
70
end
71
 
72
section dc
73
  enabled         =   0
74
  nsets           = 512
75
  nways           =   1
76
  blocksize       =  16
77
  load_hitdelay   =  20
78
  load_missdelay  =  20
79
  store_hitdelay  =  20
80
  store_missdelay =  20
81
end
82
 
83
section uart
84
  enabled  = 1
85
  baseaddr = 0x90000000
86
  channel  = "xterm:"
87
  16550    = 1
88
end
89
 
90
section debug
91
  enabled     =     0
92
end
93
 
94
/* Disabled Sections. The first one needs all its additional fields due to a
95
   bug in Or1ksim */
96
 
97
section immu
98
  enabled = 0
99
end
100
 
101
section dmmu
102
  enabled = 0
103
end
104
 
105
section VAPI
106
  enabled = 0
107
end
108
 
109
section dma
110
  enabled = 0
111
end
112
 
113
section pm
114
  enabled = 0
115
end
116
 
117
section bpb
118
  enabled = 0
119
end
120
 
121
section ethernet
122
  enabled = 0
123
end
124
 
125
section gpio
126
  enabled = 0
127
end
128
 
129
section ata
130
  enabled = 0
131
end
132
 
133
section vga
134
  enabled = 0
135
end
136
 
137
section fb
138
  enabled = 0
139
end
140
 
141
section kbd
142
  enabled = 0
143
end
144
 
145
section mc
146
  enabled = 0
147
end
148
 
149
section pic
150
  enabled = 0
151
end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.