OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [newlib-1.17.0/] [libgloss/] [sparc/] [erc32.ld] - Blame information for rev 832

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 148 jeremybenn
/*
2
 *uncomment this if you want the linker to output srecords.
3
OUTPUT_FORMAT(srec)
4
 *
5
 */
6
STARTUP(traps.o)
7
INPUT(sim-crt0.o)
8
OUTPUT_ARCH(sparc)
9
SEARCH_DIR(.)
10
__DYNAMIC  =  0;
11
GROUP(-lc -lsim -lgcc)
12
 
13
/*
14
 * The memory map looks like this:
15
 * +--------------------+ <- low memory
16
 * | .text              |
17
 * |        _stext       |
18
 * |        _etext      |
19
 * |        ctor list   | the ctor and dtor lists are for
20
 * |        dtor list   | C++ support
21
 * |        _end_text   |
22
 * +--------------------+
23
 * | .data              | initialized data goes here
24
 * |        _sdata      |
25
 * |        _edata      |
26
 * +--------------------+
27
 * | .bss               |
28
 * |        __bss_start | start of bss, cleared by crt0
29
 * |        _end        | start of heap, used by sbrk()
30
 * +--------------------+
31
 * |    heap space      |
32
 * |        _ENDHEAP    |
33
 * |    stack space     |
34
 * |        __stack     | top of stack
35
 * +--------------------+ <- high memory
36
 */
37
 
38
/*
39
 * User modifiable values:
40
 *
41
 * _CLOCK_SPEED               in Mhz (used to program the counter/timers)
42
 *
43
 * _PROM_SIZE                 size of PROM (permissible values are 4K, 8K, 16K
44
 *                               32K, 64K, 128K, 256K, and 512K)
45
 * _RAM_SIZE                  size of RAM (permissible values are 256K, 512K,
46
 *                               1MB, 2Mb, 4Mb, 8Mb, 16Mb, and 32Mb)
47
 *
48
 * These symbols are only used in assembler code, so they only need to
49
 * be listed once. They should always be refered to without SYM().
50
 */
51
 
52
_CLOCK_SPEED = 10;
53
 
54
_PROM_SIZE = 4M;
55
_RAM_SIZE = 2M;
56
 
57
_RAM_START = 0x02020000;
58
_RAM_END = _RAM_START + _RAM_SIZE;
59
_STACK_SIZE = (16 * 1024);
60
_PROM_START = 0x00000000;
61
_PROM_END = _PROM_START + _PROM_SIZE;
62
 
63
 
64
/*
65
 *  Base address of the on-CPU peripherals
66
 */
67
 
68
_ERC32_MEC = 0x01f80000;
69
 
70
/*
71
 * Setup the memory map for the SIS simulator.
72
 * stack grows up towards low memory.
73
 */
74
/*
75
MEMORY
76
{
77
  rom       : ORIGIN = 0x00000000, LENGTH = 4M
78
  ram (rwx) : ORIGIN = 0x02000000, LENGTH = 2M
79
}
80
*/
81
 
82
__stack = _RAM_START + _RAM_SIZE - 4 * 16;
83
__trap_stack = (_RAM_START + _RAM_SIZE - 4 * 16) - _STACK_SIZE;
84
 
85
/*
86
 * All the symbols that might be accessed from C code need to be
87
 * listed twice, once with an additional underscore. aout format needs
88
 * and extra underscore, whereas coff & elf doesn't. This is to work
89
 * with both.
90
 */
91
SECTIONS
92
{
93
  .text 0x02000000 :  {
94
    stext = .;
95
    _stext = .;
96
    *(.text)
97
     _etext  =  .;
98
    __CTOR_LIST__ = .;
99
    LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
100
    *(.ctors)
101
    LONG(0)
102
    __CTOR_END__ = .;
103
    __DTOR_LIST__ = .;
104
    LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
105
    *(.dtors)
106
    LONG(0)
107
    __DTOR_END__ = .;
108
    *(.lit)
109
    *(.shdata)
110
    _endtext = .;
111
  }  > ram
112
  .shbss SIZEOF(.text) + ADDR(.text) :  {
113
    *(.shbss)
114
  }
115
  .talias :      { }  > ram
116
  .data : {
117
    sdata  =  .;
118
    _sdata  =  .;
119
    *(.data)
120
    edata  =  .;
121
    _edata  =  .;
122
  } > ram
123
  .bss SIZEOF(.data) + ADDR(.data) :
124
  {
125
   sbss = . ;
126
   _sbss = . ;
127
   __bss_start = ALIGN(0x8);
128
   *(.bss)
129
   *(COMMON)
130
   end = ALIGN(0x8);
131
   _end = ALIGN(0x8);
132
   __end = ALIGN(0x8);
133
   ebss = .;
134
   _ebss = .;
135
  }
136
  .mstack  : { }  > ram
137
  .rstack  : { }  > ram
138
  .stab  0 (NOLOAD) :
139
  {
140
    [ .stab ]
141
  }
142
  .stabstr  0 (NOLOAD) :
143
  {
144
    [ .stabstr ]
145
  }
146
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.