OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [newlib-1.17.0/] [libgloss/] [sparc/] [sparclite.h] - Blame information for rev 148

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 148 jeremybenn
/* SPARClite defs
2
 *
3
 * Copyright (c) 1995 Cygnus Support
4
 *
5
 * The authors hereby grant permission to use, copy, modify, distribute,
6
 * and license this software and its documentation for any purpose, provided
7
 * that existing copyright notices are retained in all copies and that this
8
 * notice is included verbatim in any distributions. No written agreement,
9
 * license, or royalty fee is required for any of the authorized uses.
10
 * Modifications to this software may be copyrighted by their authors
11
 * and need not follow the licensing terms described here, provided that
12
 * the new terms are clearly indicated on the first page of each file where
13
 * they apply.
14
 */
15
 
16
/* Macros for reading and writing to arbitrary address spaces.  Note that ASI
17
   must be a constant (sorry, but the SPARC can only specify ASIs as part of an
18
   instruction.  */
19
 
20
#define read_asi(ASI, LOC)                                              \
21
  ({                                                                    \
22
    unsigned int val;                                                   \
23
    __asm__ volatile ("lda [%r1]%2,%0" : "=r" (val) : "rJ" (LOC), "I" (ASI)); \
24
    val;                                                                \
25
  })
26
 
27
#define write_asi(ASI, LOC, VAL) \
28
  __asm__ volatile ("sta %0,[%r1]%2" : : "r" (VAL), "rJ" (LOC), "I" (ASI))
29
 
30
/* Use this when modifying registers that cause memory to be modified.  This
31
   will cause GCC to reload all values after this point.  */
32
 
33
#define write_asi_volatile(ASI, LOC, VAL) \
34
  __asm__ volatile ("sta %0,[%r1]%2" : : "r" (VAL), "rJ" (LOC), "I" (ASI) \
35
                    : "memory")
36
 
37
/* Read the PSR (processor state register). */
38
 
39
#define read_psr()                                                      \
40
  ({                                                                    \
41
    unsigned int psr;                                                   \
42
    __asm__ ("mov %%psr, %0" : "=r" (psr));                             \
43
    psr;                                                                \
44
  })
45
 
46
/* Write the PSR. */
47
 
48
#define write_psr(VAL)                                                  \
49
  __asm__ ("mov %0, %%psr \n nop \n nop \n nop" : : "r" (VAL))
50
 
51
/* Read the specified Ancillary State Register. */
52
 
53
#define read_asr(REG) read_asr1(REG)
54
#define read_asr1(REG)                                                  \
55
  ({                                                                    \
56
    unsigned int val;                                                   \
57
    __asm__ ("rd %%asr" #REG ",%0" : "=r" (val));                       \
58
    val;                                                                \
59
  })
60
 
61
/* Write the specified Ancillary State Register. */
62
 
63
#define write_asr(REG, VAL) write_asr1(REG, VAL)
64
#define write_asr1(REG, VAL)                                            \
65
    __asm__ ("wr %0, 0, %%asr" #REG : : "r" (VAL))
66
 
67
/* Set window size for window overflow and underflow trap handlers.  Better to
68
   do this at at compile time than to calculate them at compile time each time
69
   we get a window overflow/underflow trap.  */
70
 
71
#ifdef SL933
72
        asm ("__WINSIZE=6");
73
#else
74
        asm ("__WINSIZE=8");
75
#endif
76
 
77
#define PSR_INIT   0x10c0       /* Disable traps, set s and ps */
78
#define TBR_INIT   0
79
#define WIM_INIT   2
80
#define STACK_SIZE 16 * 1024
81
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.