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[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [cpu/] [sh.cpu] - Blame information for rev 156

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1 38 julius
; Hitachi SH architecture description.  -*- Scheme -*-
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;
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; Copyright 2000, 2001, 2007 Free Software Foundation, Inc.
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;
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; Contributed by Red Hat Inc; developed under contract from Hitachi
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; Semiconductor (America) Inc.
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;
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; This file is part of the GNU Binutils.
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;
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; This program is free software; you can redistribute it and/or modify
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; it under the terms of the GNU General Public License as published by
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; the Free Software Foundation; either version 3 of the License, or
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; (at your option) any later version.
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;
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with this program; if not, write to the Free Software
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; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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; MA 02110-1301, USA.
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(include "simplify.inc")
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(define-arch
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  (name sh)
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  (comment "Hitachi SuperH (SH)")
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  (insn-lsb0? #t)
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  (machs sh2 sh3 sh3e sh4 sh5)
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  (isas compact media)
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)
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; Instruction sets.
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(define-isa
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  (name media)
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  (comment "SHmedia 32-bit instruction set")
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  (base-insn-bitsize 32)
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)
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(define-isa
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  (name compact)
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  (comment "SHcompact 16-bit instruction set")
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  (base-insn-bitsize 16)
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)
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; CPU family.
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(define-cpu
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  (name sh64)
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  (comment "SH 64-bit family")
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  (endian either)
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  (word-bitsize 32)
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)
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(define-mach
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  (name sh2)
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  (comment "SH-2 CPU core")
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  (cpu sh64)
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  (isas compact)
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)
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(define-mach
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  (name sh3)
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  (comment "SH-3 CPU core")
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  (cpu sh64)
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  (isas compact)
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)
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(define-mach
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  (name sh3e)
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  (comment "SH-3e CPU core")
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  (cpu sh64)
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  (isas compact)
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)
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(define-mach
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  (name sh4)
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  (comment "SH-4 CPU core")
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  (cpu sh64)
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  (isas compact)
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)
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(define-mach
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  (name sh5)
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  (comment "SH-5 CPU core")
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  (cpu sh64)
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  (isas compact media)
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)
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(define-model
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  (name sh5)
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  (comment "SH-5 reference implementation")
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  (mach sh5)
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  (unit u-exec "Execution unit" ()
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        1 1 ; issue done
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        () () () ())
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)
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; Hardware elements.
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(define-hardware
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  (name h-pc)
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  (comment "Program counter")
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  (attrs PC (ISA compact,media))
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  (type pc UDI)
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  (get () (raw-reg h-pc))
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  (set (newval) (sequence ()
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                          (set (raw-reg h-ism) (and newval 1))
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                          (set (raw-reg h-pc) (and newval (inv UDI 1)))))
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)
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(define-pmacro (-build-greg-name n) ((.sym r n) n))
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(define-hardware
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  (name h-gr)
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  (comment "General purpose integer registers")
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  (attrs (ISA media,compact))
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  (type register DI (64))
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  (indices keyword "" (.map -build-greg-name (.iota 64)))
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  (get (index)
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       (if DI (eq index 63)
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           (const 0)
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           (raw-reg h-gr index)))
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  (set (index newval)
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       (if (ne index 63)
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           (set (raw-reg h-gr index) newval)
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           (nop)))
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)
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(define-hardware
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  (name h-grc)
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  (comment "General purpose integer registers (SHcompact view)")
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  (attrs VIRTUAL (ISA compact))
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  (type register SI (16))
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  (indices keyword "" (.map -build-greg-name (.iota 16)))
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  (get (index)
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        (and (raw-reg h-gr index) (zext DI #xFFFFFFFF)))
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  (set (index newval)
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       (set (raw-reg h-gr index) (ext DI newval)))
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)
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(define-pmacro (-build-creg-name n) ((.sym cr n) n))
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(define-hardware
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  (name h-cr)
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  (comment "Control registers")
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  (attrs (ISA media))
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  (type register DI (64))
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  (indices keyword "" (.map -build-creg-name (.iota 64)))
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  (get (index)
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       (if DI (eq index 0)
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           (zext DI (reg h-sr))
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           (raw-reg h-cr index)))
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  (set (index newval)
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       (if (eq index 0)
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           (set (reg h-sr) newval)
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           (set (raw-reg h-cr index) newval)))
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)
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(define-hardware
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  (name h-sr)
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  (comment "Status register")
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  (attrs (ISA compact,media))
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  (type register SI)
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)
173
 
174
(define-hardware
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  (name h-fpscr)
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  (comment "Floating point status and control register")
177
  (attrs (ISA compact,media))
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  (type register SI)
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)
180
 
181
(define-hardware
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  (name h-frbit)
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  (comment "Floating point register file bit")
184
  (attrs (ISA media,compact) VIRTUAL)
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  (type register BI)
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  (get () (and (srl (reg h-sr) 14) 1))
187
  (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 14))) (sll SI newvalue 14))))
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)
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(define-hardware
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  (name h-szbit)
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  (comment "Floating point transfer size bit")
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  (attrs (ISA media,compact) VIRTUAL)
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  (type register BI)
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  (get () (and (srl (reg h-sr) 13) 1))
196
  (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 13))) (sll SI newvalue 13))))
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)
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(define-hardware
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  (name h-prbit)
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  (comment "Floating point precision bit")
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  (attrs (ISA media,compact) VIRTUAL)
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  (type register BI)
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  (get () (and (srl (reg h-sr) 12) 1))
205
  (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 12))) (sll SI newvalue 12))))
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)
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208
(define-hardware
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  (name h-sbit)
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  (comment "Multiply-accumulate saturation flag")
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  (attrs (ISA compact) VIRTUAL)
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  (type register BI)
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  (get () (and (srl (reg h-sr) 1) 1))
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  (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv 2)) (sll SI newvalue 1))))
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)
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(define-hardware
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  (name h-mbit)
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  (comment "Divide-step M flag")
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  (attrs (ISA compact) VIRTUAL)
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  (type register BI)
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  (get () (and (srl (reg h-sr) 9) 1))
223
  (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 9))) (sll SI newvalue 9))))
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)
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226
(define-hardware
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  (name h-qbit)
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  (comment "Divide-step Q flag")
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  (attrs (ISA compact) VIRTUAL)
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  (type register BI)
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  (get () (and (srl (reg h-sr) 8) 1))
232
  (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 8))) (sll SI newvalue 8))))
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)
234
 
235
(define-pmacro (-build-freg-name n) ((.sym fr n) n))
236
 
237
(define-hardware
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  (name h-fr)
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  (comment "Single precision floating point registers")
240
  (attrs (ISA media,compact))
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  (type register SF (64))
242
  (indices keyword "" (.map -build-freg-name (.iota 64)))
243
)
244
 
245
 
246
(define-pmacro (-build-fpair-name n) ((.sym fp n) n))
247
 
248
(define-hardware
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  (name h-fp)
250
  (comment "Single precision floating point register pairs")
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  (attrs (ISA media,compact))
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  (type register DF (32))
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  (indices keyword "" (.map -build-fpair-name (.iota 32)))
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)
255
 
256
(define-pmacro (-build-fvec-name n) ((.sym fv n) n))
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258
(define-hardware
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  (name h-fv)
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  (comment "Single precision floating point vectors")
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  (attrs VIRTUAL (ISA media,compact))
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  (type register SF (16))
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  (indices keyword "" (.map -build-fvec-name (.iota 16)))
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  ; Mask with $F to ensure 0 <= index < 15.
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  (get (index) (reg h-fr (mul (and UQI index 15) 4)))
266
  (set (index newval) (set (reg h-fr (mul (and UQI index 15) 4)) newval))
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)
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(define-hardware
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  (name h-fmtx)
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  (comment "Single precision floating point matrices")
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  (attrs VIRTUAL (ISA media))
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  (type register SF (4))
274
  (indices keyword "" ((mtrx0 0) (mtrx1 1) (mtrx2 2) (mtrx3 3)))
275
  ; Mask with $3 to ensure 0 <= index < 4.
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  (get (index) (reg h-fr (mul (and UQI index 3) 16)))
277
  (set (index newval) (set (reg h-fr (mul (and UQI index 3) 16)) newval))
278
)
279
 
280
(define-pmacro (-build-dreg-name n) ((.sym dr n) n))
281
 
282
(define-hardware
283
  (name h-dr)
284
  (comment "Double precision floating point registers")
285
  (attrs (ISA media,compact) VIRTUAL)
286
  (type register DF (32))
287
  (indices keyword "" (.map -build-dreg-name (.iota 64)))
288
  (get (index)
289
       (subword DF
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                (or
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                 (sll DI (zext DI (subword SI (reg h-fr index) 0)) 32)
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                 (zext DI (subword SI (reg h-fr (add index 1)) 0))) 0))
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  (set (index newval)
294
       (sequence ()
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                 (set (reg h-fr index)
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                      (subword SF (subword SI newval 0) 0))
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                 (set (reg h-fr (add index 1))
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                      (subword SF (subword SI newval 1) 0))))
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)
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(define-hardware
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  (name h-tr)
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  (comment "Branch target registers")
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  (attrs (ISA media))
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  (type register DI (8))
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  (indices keyword "" ((tr0 0) (tr1 1) (tr2 2) (tr3 3) (tr4 4) (tr5 5) (tr6 6) (tr7 7)))
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)
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(define-hardware
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  (name h-endian)
311
  (comment "Current endian mode")
312
  (attrs (ISA compact,media) VIRTUAL)
313
  (type register BI)
314
  (get () (c-call BI "sh64_endian"))
315
  (set (newval) (error "cannot alter target byte order mid-program"))
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)
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(define-hardware
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  (name h-ism)
320
  (comment "Current instruction set mode")
321
  (attrs (ISA compact,media))
322
  (type register BI)
323
  (get () (raw-reg h-ism))
324
  (set (newval) (error "cannot set ism directly"))
325
)
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; Operands.
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330
(dnop endian "Endian mode" ((ISA compact,media)) h-endian f-nil)
331
(dnop ism    "Instruction set mode" ((ISA compact,media)) h-ism f-nil)
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; Universally useful macros.
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335
; A pmacro for use in semantic bodies of unimplemented insns.
336
(define-pmacro (unimp mnemonic) (nop))
337
 
338
; Join 2 ints together in natural bit order.
339
(define-pmacro (-join-si s1 s0)
340
  (or (sll (zext DI s1) 32)
341
      (zext DI s0)))
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; Join 4 half-ints together in natural bit order.
344
(define-pmacro (-join-hi h3 h2 h1 h0)
345
  (or (sll (zext DI h3) 48)
346
      (or (sll (zext DI h2) 32)
347
          (or (sll (zext DI h1) 16)
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              (zext DI h0)))))
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; Join 8 quarter-ints together in natural bit order.
351
(define-pmacro (-join-qi b7 b6 b5 b4 b3 b2 b1 b0)
352
  (or (sll (zext DI b7) 56)
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      (or (sll (zext DI b6) 48)
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          (or (sll (zext DI b5) 40)
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              (or (sll (zext DI b4) 32)
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                  (or (sll (zext DI b3) 24)
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                      (or (sll (zext DI b2) 16)
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                          (or (sll (zext DI b1) 8)
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                              (zext DI b0)))))))))
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362
; Include the two instruction set descriptions from their respective
363
; source files.
364
 
365
(if (keep-isa? (compact))
366
    (include "sh64-compact.cpu"))
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(if (keep-isa? (media))
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    (include "sh64-media.cpu"))

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