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[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [gas/] [config/] [tc-d30v.c] - Blame information for rev 438

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1 38 julius
/* tc-d30v.c -- Assembler code for the Mitsubishi D30V
2
   Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008
3
   Free Software Foundation, Inc.
4
 
5
   This file is part of GAS, the GNU Assembler.
6
 
7
   GAS is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
 
12
   GAS is distributed in the hope that it will be useful,
13
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
   GNU General Public License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with GAS; see the file COPYING.  If not, write to
19
   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
20
   Boston, MA 02110-1301, USA.  */
21
 
22
#include "as.h"
23
#include "safe-ctype.h"
24
#include "subsegs.h"
25
#include "opcode/d30v.h"
26
 
27
const char comment_chars[]        = ";";
28
const char line_comment_chars[]   = "#";
29
const char line_separator_chars[] = "";
30
const char *md_shortopts          = "OnNcC";
31
const char EXP_CHARS[]            = "eE";
32
const char FLT_CHARS[]            = "dD";
33
 
34
#if HAVE_LIMITS_H
35
#include <limits.h>
36
#endif
37
 
38
#ifndef CHAR_BIT
39
#define CHAR_BIT 8
40
#endif
41
 
42
#define NOP_MULTIPLY 1
43
#define NOP_ALL 2
44
static int warn_nops = 0;
45
static int Optimizing = 0;
46
static int warn_register_name_conflicts = 1;
47
 
48
#define FORCE_SHORT     1
49
#define FORCE_LONG      2
50
 
51
/* EXEC types.  */
52
typedef enum _exec_type
53
{
54
  EXEC_UNKNOWN,                 /* No order specified.  */
55
  EXEC_PARALLEL,                /* Done in parallel (FM=00).  */
56
  EXEC_SEQ,                     /* Sequential (FM=01).  */
57
  EXEC_REVSEQ                   /* Reverse sequential (FM=10).  */
58
} exec_type_enum;
59
 
60
/* Fixups.  */
61
#define MAX_INSN_FIXUPS  5
62
 
63
struct d30v_fixup
64
{
65
  expressionS exp;
66
  int operand;
67
  int pcrel;
68
  int size;
69
  bfd_reloc_code_real_type reloc;
70
};
71
 
72
typedef struct _fixups
73
{
74
  int fc;
75
  struct d30v_fixup fix[MAX_INSN_FIXUPS];
76
  struct _fixups *next;
77
} Fixups;
78
 
79
static Fixups FixUps[2];
80
static Fixups *fixups;
81
 
82
/* Whether current and previous instruction are word multiply insns.  */
83
static int cur_mul32_p = 0;
84
static int prev_mul32_p = 0;
85
 
86
/*  The flag_explicitly_parallel is true iff the instruction being assembled
87
    has been explicitly written as a parallel short-instruction pair by the
88
    human programmer.  It is used in parallel_ok () to distinguish between
89
    those dangerous parallelizations attempted by the human, which are to be
90
    allowed, and those attempted by the assembler, which are not.  It is set
91
    from md_assemble ().  */
92
static int flag_explicitly_parallel = 0;
93
static int flag_xp_state = 0;
94
 
95
/* Whether current and previous left sub-instruction disables
96
   execution of right sub-instruction.  */
97
static int cur_left_kills_right_p = 0;
98
static int prev_left_kills_right_p = 0;
99
 
100
/* The known current alignment of the current section.  */
101
static int d30v_current_align;
102
static segT d30v_current_align_seg;
103
 
104
/* The last seen label in the current section.  This is used to auto-align
105
   labels preceding instructions.  */
106
static symbolS *d30v_last_label;
107
 
108
/* Two nops.  */
109
#define NOP_LEFT   ((long long) NOP << 32)
110
#define NOP_RIGHT  ((long long) NOP)
111
#define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
112
 
113
struct option md_longopts[] =
114
{
115
  {NULL, no_argument, NULL, 0}
116
};
117
 
118
size_t md_longopts_size = sizeof (md_longopts);
119
 
120
/* Opcode hash table.  */
121
static struct hash_control *d30v_hash;
122
 
123
/* Do a binary search of the pre_defined_registers array to see if
124
   NAME is a valid regiter name.  Return the register number from the
125
   array on success, or -1 on failure.  */
126
 
127
static int
128
reg_name_search (char *name)
129
{
130
  int middle, low, high;
131
  int cmp;
132
 
133
  low = 0;
134
  high = reg_name_cnt () - 1;
135
 
136
  do
137
    {
138
      middle = (low + high) / 2;
139
      cmp = strcasecmp (name, pre_defined_registers[middle].name);
140
      if (cmp < 0)
141
        high = middle - 1;
142
      else if (cmp > 0)
143
        low = middle + 1;
144
      else
145
        {
146
          if (symbol_find (name) != NULL)
147
            {
148
              if (warn_register_name_conflicts)
149
                as_warn (_("Register name %s conflicts with symbol of the same name"),
150
                         name);
151
            }
152
 
153
          return pre_defined_registers[middle].value;
154
        }
155
    }
156
  while (low <= high);
157
 
158
  return -1;
159
}
160
 
161
/* Check the string at input_line_pointer to see if it is a valid
162
   register name.  */
163
 
164
static int
165
register_name (expressionS *expressionP)
166
{
167
  int reg_number;
168
  char c, *p = input_line_pointer;
169
 
170
  while (*p && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')')
171
    p++;
172
 
173
  c = *p;
174
  if (c)
175
    *p++ = 0;
176
 
177
  /* Look to see if it's in the register table.  */
178
  reg_number = reg_name_search (input_line_pointer);
179
  if (reg_number >= 0)
180
    {
181
      expressionP->X_op = O_register;
182
      /* Temporarily store a pointer to the string here.  */
183
      expressionP->X_op_symbol = (symbolS *) input_line_pointer;
184
      expressionP->X_add_number = reg_number;
185
      input_line_pointer = p;
186
      return 1;
187
    }
188
  if (c)
189
    *(p - 1) = c;
190
  return 0;
191
}
192
 
193
static int
194
check_range (unsigned long num, int bits, int flags)
195
{
196
  long min, max;
197
 
198
  /* Don't bother checking 32-bit values.  */
199
  if (bits == 32)
200
    {
201
      if (sizeof (unsigned long) * CHAR_BIT == 32)
202
        return 0;
203
 
204
      /* We don't record signed or unsigned for 32-bit quantities.
205
         Allow either.  */
206
      min = -((unsigned long) 1 << (bits - 1));
207
      max = ((unsigned long) 1 << bits) - 1;
208
      return (long) num < min || (long) num > max;
209
    }
210
 
211
  if (flags & OPERAND_SHIFT)
212
    {
213
      /* We know that all shifts are right by three bits.  */
214
      num >>= 3;
215
 
216
      if (flags & OPERAND_SIGNED)
217
        {
218
          unsigned long sign_bit = ((unsigned long) -1L >> 4) + 1;
219
          num = (num ^ sign_bit) - sign_bit;
220
        }
221
    }
222
 
223
  if (flags & OPERAND_SIGNED)
224
    {
225
      max = ((unsigned long) 1 << (bits - 1)) - 1;
226
      min = - ((unsigned long) 1 << (bits - 1));
227
      return (long) num > max || (long) num < min;
228
    }
229
  else
230
    {
231
      max = ((unsigned long) 1 << bits) - 1;
232
      return num > (unsigned long) max;
233
    }
234
}
235
 
236
void
237
md_show_usage (FILE *stream)
238
{
239
  fprintf (stream, _("\nD30V options:\n\
240
-O                      Make adjacent short instructions parallel if possible.\n\
241
-n                      Warn about all NOPs inserted by the assembler.\n\
242
-N                      Warn about NOPs inserted after word multiplies.\n\
243
-c                      Warn about symbols whoes names match register names.\n\
244
-C                      Opposite of -C.  -c is the default.\n"));
245
}
246
 
247
int
248
md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
249
{
250
  switch (c)
251
    {
252
      /* Optimize.  Will attempt to parallelize operations.  */
253
    case 'O':
254
      Optimizing = 1;
255
      break;
256
 
257
      /* Warn about all NOPS that the assembler inserts.  */
258
    case 'n':
259
      warn_nops = NOP_ALL;
260
      break;
261
 
262
      /* Warn about the NOPS that the assembler inserts because of the
263
         multiply hazard.  */
264
    case 'N':
265
      warn_nops = NOP_MULTIPLY;
266
      break;
267
 
268
    case 'c':
269
      warn_register_name_conflicts = 1;
270
      break;
271
 
272
    case 'C':
273
      warn_register_name_conflicts = 0;
274
      break;
275
 
276
    default:
277
      return 0;
278
    }
279
  return 1;
280
}
281
 
282
symbolS *
283
md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
284
{
285
  return 0;
286
}
287
 
288
char *
289
md_atof (int type, char *litP, int *sizeP)
290
{
291
  return ieee_md_atof (type, litP, sizeP, TRUE);
292
}
293
 
294
void
295
md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
296
                 asection *sec ATTRIBUTE_UNUSED,
297
                 fragS *fragP ATTRIBUTE_UNUSED)
298
{
299
  abort ();
300
}
301
 
302
valueT
303
md_section_align (asection *seg, valueT addr)
304
{
305
  int align = bfd_get_section_alignment (stdoutput, seg);
306
  return ((addr + (1 << align) - 1) & (-1 << align));
307
}
308
 
309
void
310
md_begin (void)
311
{
312
  struct d30v_opcode *opcode;
313
  d30v_hash = hash_new ();
314
 
315
  /* Insert opcode names into a hash table.  */
316
  for (opcode = (struct d30v_opcode *) d30v_opcode_table; opcode->name; opcode++)
317
      hash_insert (d30v_hash, opcode->name, (char *) opcode);
318
 
319
  fixups = &FixUps[0];
320
  FixUps[0].next = &FixUps[1];
321
  FixUps[1].next = &FixUps[0];
322
 
323
  d30v_current_align_seg = now_seg;
324
}
325
 
326
/* Remove the postincrement or postdecrement operator ( '+' or '-' )
327
   from an expression.  */
328
 
329
static int
330
postfix (char *p)
331
{
332
  while (*p != '-' && *p != '+')
333
    {
334
      if (*p == 0 || *p == '\n' || *p == '\r' || *p == ' ' || *p == ',')
335
        break;
336
      p++;
337
    }
338
 
339
  if (*p == '-')
340
    {
341
      *p = ' ';
342
      return -1;
343
    }
344
 
345
  if (*p == '+')
346
    {
347
      *p = ' ';
348
      return 1;
349
    }
350
 
351
  return 0;
352
}
353
 
354
static bfd_reloc_code_real_type
355
get_reloc (const struct d30v_operand *op, int rel_flag)
356
{
357
  switch (op->bits)
358
    {
359
    case 6:
360
      if (op->flags & OPERAND_SHIFT)
361
        return BFD_RELOC_D30V_9_PCREL;
362
      else
363
        return BFD_RELOC_D30V_6;
364
      break;
365
    case 12:
366
      if (!(op->flags & OPERAND_SHIFT))
367
        as_warn (_("unexpected 12-bit reloc type"));
368
      if (rel_flag == RELOC_PCREL)
369
        return BFD_RELOC_D30V_15_PCREL;
370
      else
371
        return BFD_RELOC_D30V_15;
372
    case 18:
373
      if (!(op->flags & OPERAND_SHIFT))
374
        as_warn (_("unexpected 18-bit reloc type"));
375
      if (rel_flag == RELOC_PCREL)
376
        return BFD_RELOC_D30V_21_PCREL;
377
      else
378
        return BFD_RELOC_D30V_21;
379
    case 32:
380
      if (rel_flag == RELOC_PCREL)
381
        return BFD_RELOC_D30V_32_PCREL;
382
      else
383
        return BFD_RELOC_D30V_32;
384
    default:
385
      return 0;
386
    }
387
}
388
 
389
/* Parse a string of operands and return an array of expressions.  */
390
 
391
static int
392
get_operands (expressionS exp[], int cmp_hack)
393
{
394
  char *p = input_line_pointer;
395
  int numops = 0;
396
  int post = 0;
397
 
398
  if (cmp_hack)
399
    {
400
      exp[numops].X_op = O_absent;
401
      exp[numops++].X_add_number = cmp_hack - 1;
402
    }
403
 
404
  while (*p)
405
    {
406
      while (*p == ' ' || *p == '\t' || *p == ',')
407
        p++;
408
 
409
      if (*p == 0 || *p == '\n' || *p == '\r')
410
        break;
411
 
412
      if (*p == '@')
413
        {
414
          p++;
415
          exp[numops].X_op = O_absent;
416
          if (*p == '(')
417
            {
418
              p++;
419
              exp[numops].X_add_number = OPERAND_ATPAR;
420
              post = postfix (p);
421
            }
422
          else if (*p == '-')
423
            {
424
              p++;
425
              exp[numops].X_add_number = OPERAND_ATMINUS;
426
            }
427
          else
428
            {
429
              exp[numops].X_add_number = OPERAND_ATSIGN;
430
              post = postfix (p);
431
            }
432
          numops++;
433
          continue;
434
        }
435
 
436
      if (*p == ')')
437
        {
438
          /* Just skip the trailing paren.  */
439
          p++;
440
          continue;
441
        }
442
 
443
      input_line_pointer = p;
444
 
445
      /* Check to see if it might be a register name.  */
446
      if (!register_name (&exp[numops]))
447
        {
448
          /* Parse as an expression.  */
449
          expression (&exp[numops]);
450
        }
451
 
452
      if (exp[numops].X_op == O_illegal)
453
        as_bad (_("illegal operand"));
454
      else if (exp[numops].X_op == O_absent)
455
        as_bad (_("missing operand"));
456
 
457
      numops++;
458
      p = input_line_pointer;
459
 
460
      switch (post)
461
        {
462
        case -1:
463
          /* Postdecrement mode.  */
464
          exp[numops].X_op = O_absent;
465
          exp[numops++].X_add_number = OPERAND_MINUS;
466
          break;
467
        case 1:
468
          /* Postincrement mode.  */
469
          exp[numops].X_op = O_absent;
470
          exp[numops++].X_add_number = OPERAND_PLUS;
471
          break;
472
        }
473
      post = 0;
474
    }
475
 
476
  exp[numops].X_op = 0;
477
 
478
  return numops;
479
}
480
 
481
/* Generate the instruction.
482
   It does everything but write the FM bits.  */
483
 
484
static long long
485
build_insn (struct d30v_insn *opcode, expressionS *opers)
486
{
487
  int i, length, bits, shift, flags;
488
  unsigned long number, id = 0;
489
  long long insn;
490
  struct d30v_opcode *op = opcode->op;
491
  struct d30v_format *form = opcode->form;
492
 
493
  insn =
494
    opcode->ecc << 28 | op->op1 << 25 | op->op2 << 20 | form->modifier << 18;
495
 
496
  for (i = 0; form->operands[i]; i++)
497
    {
498
      flags = d30v_operand_table[form->operands[i]].flags;
499
 
500
      /* Must be a register or number.  */
501
      if (!(flags & OPERAND_REG) && !(flags & OPERAND_NUM)
502
          && !(flags & OPERAND_NAME) && !(flags & OPERAND_SPECIAL))
503
        continue;
504
 
505
      bits = d30v_operand_table[form->operands[i]].bits;
506
      if (flags & OPERAND_SHIFT)
507
        bits += 3;
508
 
509
      length = d30v_operand_table[form->operands[i]].length;
510
      shift = 12 - d30v_operand_table[form->operands[i]].position;
511
      if (opers[i].X_op != O_symbol)
512
        number = opers[i].X_add_number;
513
      else
514
        number = 0;
515
      if (flags & OPERAND_REG)
516
        {
517
          /* Check for mvfsys or mvtsys control registers.  */
518
          if (flags & OPERAND_CONTROL && (number & 0x7f) > MAX_CONTROL_REG)
519
            {
520
              /* PSWL or PSWH.  */
521
              id = (number & 0x7f) - MAX_CONTROL_REG;
522
              number = 0;
523
            }
524
          else if (number & OPERAND_FLAG)
525
            /* NUMBER is a flag register.  */
526
            id = 3;
527
 
528
          number &= 0x7F;
529
        }
530
      else if (flags & OPERAND_SPECIAL)
531
        number = id;
532
 
533
      if (opers[i].X_op != O_register && opers[i].X_op != O_constant
534
          && !(flags & OPERAND_NAME))
535
        {
536
          /* Now create a fixup.  */
537
          if (fixups->fc >= MAX_INSN_FIXUPS)
538
            as_fatal (_("too many fixups"));
539
 
540
          fixups->fix[fixups->fc].reloc =
541
            get_reloc (d30v_operand_table + form->operands[i], op->reloc_flag);
542
          fixups->fix[fixups->fc].size = 4;
543
          fixups->fix[fixups->fc].exp = opers[i];
544
          fixups->fix[fixups->fc].operand = form->operands[i];
545
          if (fixups->fix[fixups->fc].reloc == BFD_RELOC_D30V_9_PCREL)
546
            fixups->fix[fixups->fc].pcrel = RELOC_PCREL;
547
          else
548
            fixups->fix[fixups->fc].pcrel = op->reloc_flag;
549
          (fixups->fc)++;
550
        }
551
 
552
      /* Truncate to the proper number of bits.  */
553
      if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
554
        as_bad (_("operand out of range: %ld"), number);
555
      if (bits < 31)
556
        number &= 0x7FFFFFFF >> (31 - bits);
557
      if (flags & OPERAND_SHIFT)
558
        number >>= 3;
559
      if (bits == 32)
560
        {
561
          /* It's a LONG instruction.  */
562
          insn |= ((number & 0xffffffff) >> 26);        /* Top 6 bits.  */
563
          insn <<= 32;                  /* Shift the first word over.  */
564
          insn |= ((number & 0x03FC0000) << 2);         /* Next 8 bits.  */
565
          insn |= number & 0x0003FFFF;                  /* Bottom 18 bits.  */
566
        }
567
      else
568
        insn |= number << shift;
569
    }
570
 
571
  return insn;
572
}
573
 
574
static void
575
d30v_number_to_chars (char *buf,        /* Return 'nbytes' of chars here.  */
576
                      long long value,  /* The value of the bits.  */
577
                      int n)            /* Number of bytes in the output.  */
578
{
579
  while (n--)
580
    {
581
      buf[n] = value & 0xff;
582
      value >>= 8;
583
    }
584
}
585
 
586
/* Write out a long form instruction.  */
587
 
588
static void
589
write_long (struct d30v_insn *opcode ATTRIBUTE_UNUSED,
590
            long long insn,
591
            Fixups *fx)
592
{
593
  int i, where;
594
  char *f = frag_more (8);
595
 
596
  insn |= FM11;
597
  d30v_number_to_chars (f, insn, 8);
598
 
599
  for (i = 0; i < fx->fc; i++)
600
    {
601
      if (fx->fix[i].reloc)
602
        {
603
          where = f - frag_now->fr_literal;
604
          fix_new_exp (frag_now, where, fx->fix[i].size, &(fx->fix[i].exp),
605
                       fx->fix[i].pcrel, fx->fix[i].reloc);
606
        }
607
    }
608
 
609
  fx->fc = 0;
610
}
611
 
612
/* Write out a short form instruction by itself.  */
613
 
614
static void
615
write_1_short (struct d30v_insn *opcode,
616
               long long insn,
617
               Fixups *fx,
618
               int use_sequential)
619
{
620
  char *f = frag_more (8);
621
  int i, where;
622
 
623
  if (warn_nops == NOP_ALL)
624
    as_warn (_("%s NOP inserted"), use_sequential ?
625
             _("sequential") : _("parallel"));
626
 
627
  /* The other container needs to be NOP.  */
628
  if (use_sequential)
629
    {
630
      /* Use a sequential NOP rather than a parallel one,
631
         as the current instruction is a FLAG_MUL32 type one
632
         and the next instruction is a load.  */
633
 
634
      /* According to 4.3.1: for FM=01, sub-instructions performed
635
         only by IU cannot be encoded in L-container.  */
636
      if (opcode->op->unit == IU)
637
        /* Right then left.  */
638
        insn |= FM10 | NOP_LEFT;
639
      else
640
        /* Left then right.  */
641
        insn = FM01 | (insn << 32) | NOP_RIGHT;
642
    }
643
  else
644
    {
645
      /* According to 4.3.1: for FM=00, sub-instructions performed
646
         only by IU cannot be encoded in L-container.  */
647
      if (opcode->op->unit == IU)
648
        /* Right container.  */
649
        insn |= FM00 | NOP_LEFT;
650
      else
651
        /* Left container.  */
652
        insn = FM00 | (insn << 32) | NOP_RIGHT;
653
    }
654
 
655
  d30v_number_to_chars (f, insn, 8);
656
 
657
  for (i = 0; i < fx->fc; i++)
658
    {
659
      if (fx->fix[i].reloc)
660
        {
661
          where = f - frag_now->fr_literal;
662
          fix_new_exp (frag_now,
663
                       where,
664
                       fx->fix[i].size,
665
                       &(fx->fix[i].exp),
666
                       fx->fix[i].pcrel,
667
                       fx->fix[i].reloc);
668
        }
669
    }
670
 
671
  fx->fc = 0;
672
}
673
 
674
/* Check 2 instructions and determine if they can be safely
675
   executed in parallel.  Return 1 if they can be.  */
676
 
677
static int
678
parallel_ok (struct d30v_insn *op1,
679
             unsigned long insn1,
680
             struct d30v_insn *op2,
681
             unsigned long insn2,
682
             exec_type_enum exec_type)
683
{
684
  int i, j, shift, regno, bits, ecc;
685
  unsigned long flags, mask, flags_set1, flags_set2, flags_used1, flags_used2;
686
  unsigned long ins, mod_reg[2][3], used_reg[2][3], flag_reg[2];
687
  struct d30v_format *f;
688
  struct d30v_opcode *op;
689
 
690
  /* Section 4.3: Both instructions must not be IU or MU only.  */
691
  if ((op1->op->unit == IU && op2->op->unit == IU)
692
      || (op1->op->unit == MU && op2->op->unit == MU))
693
    return 0;
694
 
695
  /* First instruction must not be a jump to safely optimize, unless this
696
     is an explicit parallel operation.  */
697
  if (exec_type != EXEC_PARALLEL
698
      && (op1->op->flags_used & (FLAG_JMP | FLAG_JSR)))
699
    return 0;
700
 
701
  /* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
702
     then it is safe to allow the two to be done as parallel ops, since only
703
     one will ever be executed at a time.  */
704
  if ((op1->ecc == ECC_TX && op2->ecc == ECC_FX)
705
      || (op1->ecc == ECC_FX && op2->ecc == ECC_TX)
706
      || (op1->ecc == ECC_XT && op2->ecc == ECC_XF)
707
      || (op1->ecc == ECC_XF && op2->ecc == ECC_XT))
708
    return 1;
709
 
710
  /* [0] r0-r31
711
     [1] r32-r63
712
     [2] a0, a1, flag registers.  */
713
  for (j = 0; j < 2; j++)
714
    {
715
      if (j == 0)
716
        {
717
          f = op1->form;
718
          op = op1->op;
719
          ecc = op1->ecc;
720
          ins = insn1;
721
        }
722
      else
723
        {
724
          f = op2->form;
725
          op = op2->op;
726
          ecc = op2->ecc;
727
          ins = insn2;
728
        }
729
 
730
      flag_reg[j] = 0;
731
      mod_reg[j][0] = mod_reg[j][1] = 0;
732
      used_reg[j][0] = used_reg[j][1] = 0;
733
 
734
      if (flag_explicitly_parallel)
735
        {
736
          /* For human specified parallel instructions we have been asked
737
             to ignore the possibility that both instructions could modify
738
             bits in the PSW, so we initialise the mod & used arrays to 0.
739
             We have been asked, however, to refuse to allow parallel
740
             instructions which explicitly set the same flag register,
741
             eg "cmpne f0,r1,0x10 || cmpeq f0, r5, 0x2", so further on we test
742
             for the use of a flag register and set a bit in the mod or used
743
             array appropriately.  */
744
          mod_reg[j][2]  = 0;
745
          used_reg[j][2] = 0;
746
        }
747
      else
748
        {
749
          mod_reg[j][2] = (op->flags_set & FLAG_ALL);
750
          used_reg[j][2] = (op->flags_used & FLAG_ALL);
751
        }
752
 
753
      /* BSR/JSR always sets R62.  */
754
      if (op->flags_used & FLAG_JSR)
755
        mod_reg[j][1] = (1L << (62 - 32));
756
 
757
      /* Conditional execution affects the flags_used.  */
758
      switch (ecc)
759
        {
760
        case ECC_TX:
761
        case ECC_FX:
762
          used_reg[j][2] |= flag_reg[j] = FLAG_0;
763
          break;
764
 
765
        case ECC_XT:
766
        case ECC_XF:
767
          used_reg[j][2] |= flag_reg[j] = FLAG_1;
768
          break;
769
 
770
        case ECC_TT:
771
        case ECC_TF:
772
          used_reg[j][2] |= flag_reg[j] = (FLAG_0 | FLAG_1);
773
          break;
774
        }
775
 
776
      for (i = 0; f->operands[i]; i++)
777
        {
778
          flags = d30v_operand_table[f->operands[i]].flags;
779
          shift = 12 - d30v_operand_table[f->operands[i]].position;
780
          bits = d30v_operand_table[f->operands[i]].bits;
781
          if (bits == 32)
782
            mask = 0xffffffff;
783
          else
784
            mask = 0x7FFFFFFF >> (31 - bits);
785
 
786
          if ((flags & OPERAND_PLUS) || (flags & OPERAND_MINUS))
787
            {
788
              /* This is a post-increment or post-decrement.
789
                 The previous register needs to be marked as modified.  */
790
              shift = 12 - d30v_operand_table[f->operands[i - 1]].position;
791
              regno = (ins >> shift) & 0x3f;
792
              if (regno >= 32)
793
                mod_reg[j][1] |= 1L << (regno - 32);
794
              else
795
                mod_reg[j][0] |= 1L << regno;
796
            }
797
          else if (flags & OPERAND_REG)
798
            {
799
              regno = (ins >> shift) & mask;
800
              /* The memory write functions don't have a destination
801
                 register.  */
802
              if ((flags & OPERAND_DEST) && !(op->flags_set & FLAG_MEM))
803
                {
804
                  /* MODIFIED registers and flags.  */
805
                  if (flags & OPERAND_ACC)
806
                    {
807
                      if (regno == 0)
808
                        mod_reg[j][2] |= FLAG_A0;
809
                      else if (regno == 1)
810
                        mod_reg[j][2] |= FLAG_A1;
811
                      else
812
                        abort ();
813
                    }
814
                  else if (flags & OPERAND_FLAG)
815
                    mod_reg[j][2] |= 1L << regno;
816
                  else if (!(flags & OPERAND_CONTROL))
817
                    {
818
                      int r, z;
819
 
820
                      /* Need to check if there are two destination
821
                         registers, for example ld2w.  */
822
                      if (flags & OPERAND_2REG)
823
                        z = 1;
824
                      else
825
                        z = 0;
826
 
827
                      for (r = regno; r <= regno + z; r++)
828
                        {
829
                          if (r >= 32)
830
                            mod_reg[j][1] |= 1L << (r - 32);
831
                          else
832
                            mod_reg[j][0] |= 1L << r;
833
                        }
834
                    }
835
                }
836
              else
837
                {
838
                  /* USED, but not modified registers and flags.  */
839
                  if (flags & OPERAND_ACC)
840
                    {
841
                      if (regno == 0)
842
                        used_reg[j][2] |= FLAG_A0;
843
                      else if (regno == 1)
844
                        used_reg[j][2] |= FLAG_A1;
845
                      else
846
                        abort ();
847
                    }
848
                  else if (flags & OPERAND_FLAG)
849
                    used_reg[j][2] |= 1L << regno;
850
                  else if (!(flags & OPERAND_CONTROL))
851
                    {
852
                      int r, z;
853
 
854
                      /* Need to check if there are two source
855
                         registers, for example st2w.  */
856
                      if (flags & OPERAND_2REG)
857
                        z = 1;
858
                      else
859
                        z = 0;
860
 
861
                      for (r = regno; r <= regno + z; r++)
862
                        {
863
                          if (r >= 32)
864
                            used_reg[j][1] |= 1L << (r - 32);
865
                          else
866
                            used_reg[j][0] |= 1L << r;
867
                        }
868
                    }
869
                }
870
            }
871
        }
872
    }
873
 
874
  flags_set1 = op1->op->flags_set;
875
  flags_set2 = op2->op->flags_set;
876
  flags_used1 = op1->op->flags_used;
877
  flags_used2 = op2->op->flags_used;
878
 
879
  /* Check for illegal combinations with ADDppp/SUBppp.  */
880
  if (((flags_set1 & FLAG_NOT_WITH_ADDSUBppp) != 0
881
       && (flags_used2 & FLAG_ADDSUBppp) != 0)
882
      || ((flags_set2 & FLAG_NOT_WITH_ADDSUBppp) != 0
883
          && (flags_used1 & FLAG_ADDSUBppp) != 0))
884
    return 0;
885
 
886
  /* Load instruction combined with half-word multiply is illegal.  */
887
  if (((flags_used1 & FLAG_MEM) != 0 && (flags_used2 & FLAG_MUL16))
888
      || ((flags_used2 & FLAG_MEM) != 0 && (flags_used1 & FLAG_MUL16)))
889
    return 0;
890
 
891
  /* Specifically allow add || add by removing carry, overflow bits dependency.
892
     This is safe, even if an addc follows since the IU takes the argument in
893
     the right container, and it writes its results last.
894
     However, don't paralellize add followed by addc or sub followed by
895
     subb.  */
896
  if (mod_reg[0][2] == FLAG_CVVA && mod_reg[1][2] == FLAG_CVVA
897
      && (used_reg[0][2] & ~flag_reg[0]) == 0
898
      && (used_reg[1][2] & ~flag_reg[1]) == 0
899
      && op1->op->unit == EITHER && op2->op->unit == EITHER)
900
    {
901
      mod_reg[0][2] = mod_reg[1][2] = 0;
902
    }
903
 
904
  for (j = 0; j < 3; j++)
905
    {
906
      /* If the second instruction depends on the first, we obviously
907
         cannot parallelize.  Note, the mod flag implies use, so
908
         check that as well.  */
909
      /* If flag_explicitly_parallel is set, then the case of the
910
         second instruction using a register the first instruction
911
         modifies is assumed to be okay; we trust the human.  We
912
         don't trust the human if both instructions modify the same
913
         register but we do trust the human if they modify the same
914
         flags.  */
915
      /* We have now been requested not to trust the human if the
916
         instructions modify the same flag registers either.  */
917
      if (flag_explicitly_parallel)
918
        {
919
          if ((mod_reg[0][j] & mod_reg[1][j]) != 0)
920
            return 0;
921
        }
922
      else
923
        if ((mod_reg[0][j] & (mod_reg[1][j] | used_reg[1][j])) != 0)
924
          return 0;
925
    }
926
 
927
  return 1;
928
}
929
 
930
/* Write out a short form instruction if possible.
931
   Return number of instructions not written out.  */
932
 
933
static int
934
write_2_short (struct d30v_insn *opcode1,
935
               long long insn1,
936
               struct d30v_insn *opcode2,
937
               long long insn2,
938
               exec_type_enum exec_type,
939
               Fixups *fx)
940
{
941
  long long insn = NOP2;
942
  char *f;
943
  int i, j, where;
944
 
945
  if (exec_type == EXEC_SEQ
946
      && (opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR))
947
      && ((opcode1->op->flags_used & FLAG_DELAY) == 0)
948
      && ((opcode1->ecc == ECC_AL) || ! Optimizing))
949
    {
950
      /* Unconditional, non-delayed branches kill instructions in
951
         the right bin.  Conditional branches don't always but if
952
         we are not optimizing, then we have been asked to produce
953
         an error about such constructs.  For the purposes of this
954
         test, subroutine calls are considered to be branches.  */
955
      write_1_short (opcode1, insn1, fx->next, FALSE);
956
      return 1;
957
    }
958
 
959
  /* Note: we do not have to worry about subroutine calls occurring
960
     in the right hand container.  The return address is always
961
     aligned to the next 64 bit boundary, be that 64 or 32 bit away.  */
962
  switch (exec_type)
963
    {
964
    case EXEC_UNKNOWN:  /* Order not specified.  */
965
      if (Optimizing
966
          && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)
967
          && ! (   (opcode1->op->unit == EITHER_BUT_PREFER_MU
968
                 || opcode1->op->unit == MU)
969
                &&
970
                (   opcode2->op->unit == EITHER_BUT_PREFER_MU
971
                 || opcode2->op->unit == MU)))
972
        {
973
          /* Parallel.  */
974
          exec_type = EXEC_PARALLEL;
975
 
976
          if (opcode1->op->unit == IU
977
              || opcode2->op->unit == MU
978
              || opcode2->op->unit == EITHER_BUT_PREFER_MU)
979
            insn = FM00 | (insn2 << 32) | insn1;
980
          else
981
            {
982
              insn = FM00 | (insn1 << 32) | insn2;
983
              fx = fx->next;
984
            }
985
        }
986
      else if ((opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR)
987
                && ((opcode1->op->flags_used & FLAG_DELAY) == 0))
988
               || opcode1->op->flags_used & FLAG_RP)
989
        {
990
          /* We must emit (non-delayed) branch type instructions
991
             on their own with nothing in the right container.  */
992
          /* We must treat repeat instructions likewise, since the
993
             following instruction has to be separate from the repeat
994
             in order to be repeated.  */
995
          write_1_short (opcode1, insn1, fx->next, FALSE);
996
          return 1;
997
        }
998
      else if (prev_left_kills_right_p)
999
        {
1000
          /* The left instruction kils the right slot, so we
1001
             must leave it empty.  */
1002
          write_1_short (opcode1, insn1, fx->next, FALSE);
1003
          return 1;
1004
        }
1005
      else if (opcode1->op->unit == IU)
1006
        {
1007
          if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
1008
            {
1009
              /* Case 103810 is a request from Mitsubishi that opcodes
1010
                 with EITHER_BUT_PREFER_MU should not be executed in
1011
                 reverse sequential order.  */
1012
              write_1_short (opcode1, insn1, fx->next, FALSE);
1013
              return 1;
1014
            }
1015
 
1016
          /* Reverse sequential.  */
1017
          insn = FM10 | (insn2 << 32) | insn1;
1018
          exec_type = EXEC_REVSEQ;
1019
        }
1020
      else
1021
        {
1022
          /* Sequential.  */
1023
          insn = FM01 | (insn1 << 32) | insn2;
1024
          fx = fx->next;
1025
          exec_type = EXEC_SEQ;
1026
        }
1027
      break;
1028
 
1029
    case EXEC_PARALLEL: /* Parallel.  */
1030
      flag_explicitly_parallel = flag_xp_state;
1031
      if (! parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
1032
        as_bad (_("Instructions may not be executed in parallel"));
1033
      else if (opcode1->op->unit == IU)
1034
        {
1035
          if (opcode2->op->unit == IU)
1036
            as_bad (_("Two IU instructions may not be executed in parallel"));
1037
          as_warn (_("Swapping instruction order"));
1038
          insn = FM00 | (insn2 << 32) | insn1;
1039
        }
1040
      else if (opcode2->op->unit == MU)
1041
        {
1042
          if (opcode1->op->unit == MU)
1043
            as_bad (_("Two MU instructions may not be executed in parallel"));
1044
          else if (opcode1->op->unit == EITHER_BUT_PREFER_MU)
1045
            as_warn (_("Executing %s in IU may not work"), opcode1->op->name);
1046
          as_warn (_("Swapping instruction order"));
1047
          insn = FM00 | (insn2 << 32) | insn1;
1048
        }
1049
      else
1050
        {
1051
          if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
1052
            as_warn (_("Executing %s in IU may not work in parallel execution"),
1053
                     opcode2->op->name);
1054
 
1055
          insn = FM00 | (insn1 << 32) | insn2;
1056
          fx = fx->next;
1057
        }
1058
      flag_explicitly_parallel = 0;
1059
      break;
1060
 
1061
    case EXEC_SEQ:      /* Sequential.  */
1062
      if (opcode1->op->unit == IU)
1063
        as_bad (_("IU instruction may not be in the left container"));
1064
      if (prev_left_kills_right_p)
1065
        as_bad (_("special left instruction `%s' kills instruction "
1066
                  "`%s' in right container"),
1067
                opcode1->op->name, opcode2->op->name);
1068
      insn = FM01 | (insn1 << 32) | insn2;
1069
      fx = fx->next;
1070
      break;
1071
 
1072
    case EXEC_REVSEQ:   /* Reverse sequential.  */
1073
      if (opcode2->op->unit == MU)
1074
        as_bad (_("MU instruction may not be in the right container"));
1075
      if (opcode1->op->unit == EITHER_BUT_PREFER_MU)
1076
        as_warn (_("Executing %s in reverse serial with %s may not work"),
1077
                 opcode1->op->name, opcode2->op->name);
1078
      else if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
1079
        as_warn (_("Executing %s in IU in reverse serial may not work"),
1080
                 opcode2->op->name);
1081
      insn = FM10 | (insn1 << 32) | insn2;
1082
      fx = fx->next;
1083
      break;
1084
 
1085
    default:
1086
      as_fatal (_("unknown execution type passed to write_2_short()"));
1087
    }
1088
 
1089
  f = frag_more (8);
1090
  d30v_number_to_chars (f, insn, 8);
1091
 
1092
  /* If the previous instruction was a 32-bit multiply but it is put into a
1093
     parallel container, mark the current instruction as being a 32-bit
1094
     multiply.  */
1095
  if (prev_mul32_p && exec_type == EXEC_PARALLEL)
1096
    cur_mul32_p = 1;
1097
 
1098
  for (j = 0; j < 2; j++)
1099
    {
1100
      for (i = 0; i < fx->fc; i++)
1101
        {
1102
          if (fx->fix[i].reloc)
1103
            {
1104
              where = (f - frag_now->fr_literal) + 4 * j;
1105
 
1106
              fix_new_exp (frag_now,
1107
                           where,
1108
                           fx->fix[i].size,
1109
                           &(fx->fix[i].exp),
1110
                           fx->fix[i].pcrel,
1111
                           fx->fix[i].reloc);
1112
            }
1113
        }
1114
 
1115
      fx->fc = 0;
1116
      fx = fx->next;
1117
    }
1118
 
1119
  return 0;
1120
}
1121
 
1122
/* Get a pointer to an entry in the format table.
1123
   It must look at all formats for an opcode and use the operands
1124
   to choose the correct one.  Return NULL on error.  */
1125
 
1126
static struct d30v_format *
1127
find_format (struct d30v_opcode *opcode,
1128
             expressionS myops[],
1129
             int fsize,
1130
             int cmp_hack)
1131
{
1132
  int numops, match, index, i = 0, j, k;
1133
  struct d30v_format *fm;
1134
 
1135
  if (opcode == NULL)
1136
    return NULL;
1137
 
1138
  /* Get all the operands and save them as expressions.  */
1139
  numops = get_operands (myops, cmp_hack);
1140
 
1141
  while ((index = opcode->format[i++]) != 0)
1142
    {
1143
      if (fsize == FORCE_SHORT && index >= LONG)
1144
        continue;
1145
 
1146
      if (fsize == FORCE_LONG && index < LONG)
1147
        continue;
1148
 
1149
      fm = (struct d30v_format *) &d30v_format_table[index];
1150
      k = index;
1151
      while (fm->form == index)
1152
        {
1153
          match = 1;
1154
          /* Now check the operands for compatibility.  */
1155
          for (j = 0; match && fm->operands[j]; j++)
1156
            {
1157
              int flags = d30v_operand_table[fm->operands[j]].flags;
1158
              int bits = d30v_operand_table[fm->operands[j]].bits;
1159
              int X_op = myops[j].X_op;
1160
              int num = myops[j].X_add_number;
1161
 
1162
              if (flags & OPERAND_SPECIAL)
1163
                break;
1164
              else if (X_op == O_illegal)
1165
                match = 0;
1166
              else if (flags & OPERAND_REG)
1167
                {
1168
                  if (X_op != O_register
1169
                      || ((flags & OPERAND_ACC) && !(num & OPERAND_ACC))
1170
                      || (!(flags & OPERAND_ACC) && (num & OPERAND_ACC))
1171
                      || ((flags & OPERAND_FLAG) && !(num & OPERAND_FLAG))
1172
                      || (!(flags & (OPERAND_FLAG | OPERAND_CONTROL)) && (num & OPERAND_FLAG))
1173
                      || ((flags & OPERAND_CONTROL)
1174
                          && !(num & (OPERAND_CONTROL | OPERAND_FLAG))))
1175
                    match = 0;
1176
                }
1177
              else if (((flags & OPERAND_MINUS)
1178
                        && (X_op != O_absent || num != OPERAND_MINUS))
1179
                       || ((flags & OPERAND_PLUS)
1180
                           && (X_op != O_absent || num != OPERAND_PLUS))
1181
                       || ((flags & OPERAND_ATMINUS)
1182
                           && (X_op != O_absent || num != OPERAND_ATMINUS))
1183
                       || ((flags & OPERAND_ATPAR)
1184
                           && (X_op != O_absent || num != OPERAND_ATPAR))
1185
                       || ((flags & OPERAND_ATSIGN)
1186
                           && (X_op != O_absent || num != OPERAND_ATSIGN)))
1187
                match = 0;
1188
              else if (flags & OPERAND_NUM)
1189
                {
1190
                  /* A number can be a constant or symbol expression.  */
1191
 
1192
                  /* If we have found a register name, but that name
1193
                     also matches a symbol, then re-parse the name as
1194
                     an expression.  */
1195
                  if (X_op == O_register
1196
                      && symbol_find ((char *) myops[j].X_op_symbol))
1197
                    {
1198
                      input_line_pointer = (char *) myops[j].X_op_symbol;
1199
                      expression (&myops[j]);
1200
                    }
1201
 
1202
                  /* Turn an expression into a symbol for later resolution.  */
1203
                  if (X_op != O_absent && X_op != O_constant
1204
                      && X_op != O_symbol && X_op != O_register
1205
                      && X_op != O_big)
1206
                    {
1207
                      symbolS *sym = make_expr_symbol (&myops[j]);
1208
                      myops[j].X_op = X_op = O_symbol;
1209
                      myops[j].X_add_symbol = sym;
1210
                      myops[j].X_add_number = num = 0;
1211
                    }
1212
 
1213
                  if (fm->form >= LONG)
1214
                    {
1215
                      /* If we're testing for a LONG format, either fits.  */
1216
                      if (X_op != O_constant && X_op != O_symbol)
1217
                        match = 0;
1218
                    }
1219
                  else if (fm->form < LONG
1220
                           && ((fsize == FORCE_SHORT && X_op == O_symbol)
1221
                               || (fm->form == SHORT_D2 && j == 0)))
1222
                    match = 1;
1223
 
1224
                  /* This is the tricky part.  Will the constant or symbol
1225
                     fit into the space in the current format?  */
1226
                  else if (X_op == O_constant)
1227
                    {
1228
                      if (check_range (num, bits, flags))
1229
                        match = 0;
1230
                    }
1231
                  else if (X_op == O_symbol
1232
                           && S_IS_DEFINED (myops[j].X_add_symbol)
1233
                           && S_GET_SEGMENT (myops[j].X_add_symbol) == now_seg
1234
                           && opcode->reloc_flag == RELOC_PCREL)
1235
                    {
1236
                      /* If the symbol is defined, see if the value will fit
1237
                         into the form we're considering.  */
1238
                      fragS *f;
1239
                      long value;
1240
 
1241
                      /* Calculate the current address by running through the
1242
                         previous frags and adding our current offset.  */
1243
                      value = 0;
1244
                      for (f = frchain_now->frch_root; f; f = f->fr_next)
1245
                        value += f->fr_fix + f->fr_offset;
1246
                      value = (S_GET_VALUE (myops[j].X_add_symbol) - value
1247
                               - (obstack_next_free (&frchain_now->frch_obstack)
1248
                                  - frag_now->fr_literal));
1249
                      if (check_range (value, bits, flags))
1250
                        match = 0;
1251
                    }
1252
                  else
1253
                    match = 0;
1254
                }
1255
            }
1256
          /* We're only done if the operands matched so far AND there
1257
             are no more to check.  */
1258
          if (match && myops[j].X_op == 0)
1259
            {
1260
              /* Final check - issue a warning if an odd numbered register
1261
                 is used as the first register in an instruction that reads
1262
                 or writes 2 registers.  */
1263
 
1264
              for (j = 0; fm->operands[j]; j++)
1265
                if (myops[j].X_op == O_register
1266
                    && (myops[j].X_add_number & 1)
1267
                    && (d30v_operand_table[fm->operands[j]].flags & OPERAND_2REG))
1268
                  as_warn (_("Odd numbered register used as target of multi-register instruction"));
1269
 
1270
              return fm;
1271
            }
1272
          fm = (struct d30v_format *) &d30v_format_table[++k];
1273
        }
1274
    }
1275
  return NULL;
1276
}
1277
 
1278
/* Assemble a single instruction and return an opcode.
1279
   Return -1 (an invalid opcode) on error.  */
1280
 
1281
#define NAME_BUF_LEN    20
1282
 
1283
static long long
1284
do_assemble (char *str,
1285
             struct d30v_insn *opcode,
1286
             int shortp,
1287
             int is_parallel)
1288
{
1289
  char *op_start;
1290
  char *save;
1291
  char *op_end;
1292
  char           name[NAME_BUF_LEN];
1293
  int            cmp_hack;
1294
  int            nlen = 0;
1295
  int            fsize = (shortp ? FORCE_SHORT : 0);
1296
  expressionS    myops[6];
1297
  long long      insn;
1298
 
1299
  /* Drop leading whitespace.  */
1300
  while (*str == ' ')
1301
    str++;
1302
 
1303
  /* Find the opcode end.  */
1304
  for (op_start = op_end = str;
1305
       *op_end
1306
       && nlen < (NAME_BUF_LEN - 1)
1307
       && *op_end != '/'
1308
       && !is_end_of_line[(unsigned char) *op_end] && *op_end != ' ';
1309
       op_end++)
1310
    {
1311
      name[nlen] = TOLOWER (op_start[nlen]);
1312
      nlen++;
1313
    }
1314
 
1315
  if (nlen == 0)
1316
    return -1;
1317
 
1318
  name[nlen] = 0;
1319
 
1320
  /* If there is an execution condition code, handle it.  */
1321
  if (*op_end == '/')
1322
    {
1323
      int i = 0;
1324
      while ((i < ECC_MAX) && strncasecmp (d30v_ecc_names[i], op_end + 1, 2))
1325
        i++;
1326
 
1327
      if (i == ECC_MAX)
1328
        {
1329
          char tmp[4];
1330
          strncpy (tmp, op_end + 1, 2);
1331
          tmp[2] = 0;
1332
          as_bad (_("unknown condition code: %s"), tmp);
1333
          return -1;
1334
        }
1335
      opcode->ecc = i;
1336
      op_end += 3;
1337
    }
1338
  else
1339
    opcode->ecc = ECC_AL;
1340
 
1341
  /* CMP and CMPU change their name based on condition codes.  */
1342
  if (!strncmp (name, "cmp", 3))
1343
    {
1344
      int p, i;
1345
      char **str = (char **) d30v_cc_names;
1346
      if (name[3] == 'u')
1347
        p = 4;
1348
      else
1349
        p = 3;
1350
 
1351
      for (i = 1; *str && strncmp (*str, &name[p], 2); i++, str++)
1352
        ;
1353
 
1354
      /* cmpu only supports some condition codes.  */
1355
      if (p == 4)
1356
        {
1357
          if (i < 3 || i > 6)
1358
            {
1359
              name[p + 2] = 0;
1360
              as_bad (_("cmpu doesn't support condition code %s"), &name[p]);
1361
            }
1362
        }
1363
 
1364
      if (!*str)
1365
        {
1366
          name[p + 2] = 0;
1367
          as_bad (_("unknown condition code: %s"), &name[p]);
1368
        }
1369
 
1370
      cmp_hack = i;
1371
      name[p] = 0;
1372
    }
1373
  else
1374
    cmp_hack = 0;
1375
 
1376
  /* Need to look for .s or .l.  */
1377
  if (name[nlen - 2] == '.')
1378
    {
1379
      switch (name[nlen - 1])
1380
        {
1381
        case 's':
1382
          fsize = FORCE_SHORT;
1383
          break;
1384
        case 'l':
1385
          fsize = FORCE_LONG;
1386
          break;
1387
        }
1388
      name[nlen - 2] = 0;
1389
    }
1390
 
1391
  /* Find the first opcode with the proper name.  */
1392
  opcode->op = (struct d30v_opcode *) hash_find (d30v_hash, name);
1393
  if (opcode->op == NULL)
1394
    {
1395
      as_bad (_("unknown opcode: %s"), name);
1396
      return -1;
1397
    }
1398
 
1399
  save = input_line_pointer;
1400
  input_line_pointer = op_end;
1401
  while (!(opcode->form = find_format (opcode->op, myops, fsize, cmp_hack)))
1402
    {
1403
      opcode->op++;
1404
      if (opcode->op->name == NULL || strcmp (opcode->op->name, name))
1405
        {
1406
          as_bad (_("operands for opcode `%s' do not match any valid format"),
1407
                  name);
1408
          return -1;
1409
        }
1410
    }
1411
  input_line_pointer = save;
1412
 
1413
  insn = build_insn (opcode, myops);
1414
 
1415
  /* Propagate multiply status.  */
1416
  if (insn != -1)
1417
    {
1418
      if (is_parallel && prev_mul32_p)
1419
        cur_mul32_p = 1;
1420
      else
1421
        {
1422
          prev_mul32_p = cur_mul32_p;
1423
          cur_mul32_p  = (opcode->op->flags_used & FLAG_MUL32) != 0;
1424
        }
1425
    }
1426
 
1427
  /* Propagate left_kills_right status.  */
1428
  if (insn != -1)
1429
    {
1430
      prev_left_kills_right_p = cur_left_kills_right_p;
1431
 
1432
      if (opcode->op->flags_set & FLAG_LKR)
1433
        {
1434
          cur_left_kills_right_p = 1;
1435
 
1436
          if (strcmp (opcode->op->name, "mvtsys") == 0)
1437
            {
1438
              /* Left kills right for only mvtsys only for
1439
                 PSW/PSWH/PSWL/flags target.  */
1440
              if ((myops[0].X_op == O_register) &&
1441
                  ((myops[0].X_add_number == OPERAND_CONTROL) || /* psw */
1442
                   (myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+2) || /* pswh */
1443
                   (myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+1) || /* pswl */
1444
                   (myops[0].X_add_number == OPERAND_FLAG+0) || /* f0 */
1445
                   (myops[0].X_add_number == OPERAND_FLAG+1) || /* f1 */
1446
                   (myops[0].X_add_number == OPERAND_FLAG+2) || /* f2 */
1447
                   (myops[0].X_add_number == OPERAND_FLAG+3) || /* f3 */
1448
                   (myops[0].X_add_number == OPERAND_FLAG+4) || /* f4 */
1449
                   (myops[0].X_add_number == OPERAND_FLAG+5) || /* f5 */
1450
                   (myops[0].X_add_number == OPERAND_FLAG+6) || /* f6 */
1451
                   (myops[0].X_add_number == OPERAND_FLAG+7))) /* f7 */
1452
                {
1453
                  cur_left_kills_right_p = 1;
1454
                }
1455
              else
1456
                {
1457
                  /* Other mvtsys target registers don't kill right
1458
                     instruction.  */
1459
                  cur_left_kills_right_p = 0;
1460
                }
1461
            } /* mvtsys */
1462
        }
1463
      else
1464
        cur_left_kills_right_p = 0;
1465
    }
1466
 
1467
  return insn;
1468
}
1469
 
1470
/* Called internally to handle all alignment needs.  This takes care
1471
   of eliding calls to frag_align if'n the cached current alignment
1472
   says we've already got it, as well as taking care of the auto-aligning
1473
   labels wrt code.  */
1474
 
1475
static void
1476
d30v_align (int n, char *pfill, symbolS *label)
1477
{
1478
  /* The front end is prone to changing segments out from under us
1479
     temporarily when -g is in effect.  */
1480
  int switched_seg_p = (d30v_current_align_seg != now_seg);
1481
 
1482
  /* Do not assume that if 'd30v_current_align >= n' and
1483
     '! switched_seg_p' that it is safe to avoid performing
1484
     this alignment request.  The alignment of the current frag
1485
     can be changed under our feet, for example by a .ascii
1486
     directive in the source code.  cf testsuite/gas/d30v/reloc.s  */
1487
  d30v_cleanup (FALSE);
1488
 
1489
  if (pfill == NULL)
1490
    {
1491
      if (n > 2
1492
          && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
1493
        {
1494
          static char const nop[4] = { 0x00, 0xf0, 0x00, 0x00 };
1495
 
1496
          /* First, make sure we're on a four-byte boundary, in case
1497
             someone has been putting .byte values the text section.  */
1498
          if (d30v_current_align < 2 || switched_seg_p)
1499
            frag_align (2, 0, 0);
1500
          frag_align_pattern (n, nop, sizeof nop, 0);
1501
        }
1502
      else
1503
        frag_align (n, 0, 0);
1504
    }
1505
  else
1506
    frag_align (n, *pfill, 0);
1507
 
1508
  if (!switched_seg_p)
1509
    d30v_current_align = n;
1510
 
1511
  if (label != NULL)
1512
    {
1513
      symbolS     *sym;
1514
      int          label_seen = FALSE;
1515
      struct frag *old_frag;
1516
      valueT       old_value;
1517
      valueT       new_value;
1518
 
1519
      assert (S_GET_SEGMENT (label) == now_seg);
1520
 
1521
      old_frag  = symbol_get_frag (label);
1522
      old_value = S_GET_VALUE (label);
1523
      new_value = (valueT) frag_now_fix ();
1524
 
1525
      /* It is possible to have more than one label at a particular
1526
         address, especially if debugging is enabled, so we must
1527
         take care to adjust all the labels at this address in this
1528
         fragment.  To save time we search from the end of the symbol
1529
         list, backwards, since the symbols we are interested in are
1530
         almost certainly the ones that were most recently added.
1531
         Also to save time we stop searching once we have seen at least
1532
         one matching label, and we encounter a label that is no longer
1533
         in the target fragment.  Note, this search is guaranteed to
1534
         find at least one match when sym == label, so no special case
1535
         code is necessary.  */
1536
      for (sym = symbol_lastP; sym != NULL; sym = symbol_previous (sym))
1537
        {
1538
          if (symbol_get_frag (sym) == old_frag
1539
              && S_GET_VALUE (sym) == old_value)
1540
            {
1541
              label_seen = TRUE;
1542
              symbol_set_frag (sym, frag_now);
1543
              S_SET_VALUE (sym, new_value);
1544
            }
1545
          else if (label_seen && symbol_get_frag (sym) != old_frag)
1546
            break;
1547
        }
1548
    }
1549
 
1550
  record_alignment (now_seg, n);
1551
}
1552
 
1553
/* This is the main entry point for the machine-dependent assembler.
1554
   STR points to a machine-dependent instruction.  This function is
1555
   supposed to emit the frags/bytes it assembles to.  For the D30V, it
1556
   mostly handles the special VLIW parsing and packing and leaves the
1557
   difficult stuff to do_assemble ().  */
1558
 
1559
static long long prev_insn = -1;
1560
static struct d30v_insn prev_opcode;
1561
static subsegT prev_subseg;
1562
static segT prev_seg = 0;
1563
 
1564
void
1565
md_assemble (char *str)
1566
{
1567
  struct d30v_insn opcode;
1568
  long long insn;
1569
  /* Execution type; parallel, etc.  */
1570
  exec_type_enum extype = EXEC_UNKNOWN;
1571
  /* Saved extype.  Used for multiline instructions.  */
1572
  static exec_type_enum etype = EXEC_UNKNOWN;
1573
  char *str2;
1574
 
1575
  if ((prev_insn != -1) && prev_seg
1576
      && ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
1577
    d30v_cleanup (FALSE);
1578
 
1579
  if (d30v_current_align < 3)
1580
    d30v_align (3, NULL, d30v_last_label);
1581
  else if (d30v_current_align > 3)
1582
    d30v_current_align = 3;
1583
  d30v_last_label = NULL;
1584
 
1585
  flag_explicitly_parallel = 0;
1586
  flag_xp_state = 0;
1587
  if (etype == EXEC_UNKNOWN)
1588
    {
1589
      /* Look for the special multiple instruction separators.  */
1590
      str2 = strstr (str, "||");
1591
      if (str2)
1592
        {
1593
          extype = EXEC_PARALLEL;
1594
          flag_xp_state = 1;
1595
        }
1596
      else
1597
        {
1598
          str2 = strstr (str, "->");
1599
          if (str2)
1600
            extype = EXEC_SEQ;
1601
          else
1602
            {
1603
              str2 = strstr (str, "<-");
1604
              if (str2)
1605
                extype = EXEC_REVSEQ;
1606
            }
1607
        }
1608
 
1609
      /* STR2 points to the separator, if one.  */
1610
      if (str2)
1611
        {
1612
          *str2 = 0;
1613
 
1614
          /* If two instructions are present and we already have one saved,
1615
             then first write it out.  */
1616
          d30v_cleanup (FALSE);
1617
 
1618
          /* Assemble first instruction and save it.  */
1619
          prev_insn = do_assemble (str, &prev_opcode, 1, 0);
1620
          if (prev_insn == -1)
1621
            as_bad (_("Cannot assemble instruction"));
1622
          if (prev_opcode.form != NULL && prev_opcode.form->form >= LONG)
1623
            as_bad (_("First opcode is long.  Unable to mix instructions as specified."));
1624
          fixups = fixups->next;
1625
          str = str2 + 2;
1626
          prev_seg = now_seg;
1627
          prev_subseg = now_subseg;
1628
        }
1629
    }
1630
 
1631
  insn = do_assemble (str, &opcode,
1632
                      (extype != EXEC_UNKNOWN || etype != EXEC_UNKNOWN),
1633
                      extype == EXEC_PARALLEL);
1634
  if (insn == -1)
1635
    {
1636
      if (extype != EXEC_UNKNOWN)
1637
        etype = extype;
1638
      as_bad (_("Cannot assemble instruction"));
1639
      return;
1640
    }
1641
 
1642
  if (etype != EXEC_UNKNOWN)
1643
    {
1644
      extype = etype;
1645
      etype = EXEC_UNKNOWN;
1646
    }
1647
 
1648
  /* Word multiply instructions must not be followed by either a load or a
1649
     16-bit multiply instruction in the next cycle.  */
1650
  if (   (extype != EXEC_REVSEQ)
1651
      && prev_mul32_p
1652
      && (opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16)))
1653
    {
1654
      /* However, load and multiply should able to be combined in a parallel
1655
         operation, so check for that first.  */
1656
      if (prev_insn != -1
1657
          && (opcode.op->flags_used & FLAG_MEM)
1658
          && opcode.form->form < LONG
1659
          && (extype == EXEC_PARALLEL || (Optimizing && extype == EXEC_UNKNOWN))
1660
          && parallel_ok (&prev_opcode, (long) prev_insn,
1661
                          &opcode, (long) insn, extype)
1662
          && write_2_short (&prev_opcode, (long) prev_insn,
1663
                            &opcode, (long) insn, extype, fixups) == 0)
1664
        {
1665
          /* No instructions saved.  */
1666
          prev_insn = -1;
1667
          return;
1668
        }
1669
      else
1670
        {
1671
          /* Can't parallelize, flush previous instruction and emit a
1672
             word of NOPS, unless the previous instruction is a NOP,
1673
             in which case just flush it, as this will generate a word
1674
             of NOPs for us.  */
1675
 
1676
          if (prev_insn != -1 && (strcmp (prev_opcode.op->name, "nop") == 0))
1677
            d30v_cleanup (FALSE);
1678
          else
1679
            {
1680
              char *f;
1681
 
1682
              if (prev_insn != -1)
1683
                d30v_cleanup (TRUE);
1684
              else
1685
                {
1686
                  f = frag_more (8);
1687
                  d30v_number_to_chars (f, NOP2, 8);
1688
 
1689
                  if (warn_nops == NOP_ALL || warn_nops == NOP_MULTIPLY)
1690
                    {
1691
                      if (opcode.op->flags_used & FLAG_MEM)
1692
                        as_warn (_("word of NOPs added between word multiply and load"));
1693
                      else
1694
                        as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
1695
                    }
1696
                }
1697
            }
1698
 
1699
          extype = EXEC_UNKNOWN;
1700
        }
1701
    }
1702
  else if (   (extype == EXEC_REVSEQ)
1703
           && cur_mul32_p
1704
           && (prev_opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16)))
1705
    {
1706
      /* Can't parallelize, flush current instruction and add a
1707
         sequential NOP.  */
1708
      write_1_short (&opcode, (long) insn, fixups->next->next, TRUE);
1709
 
1710
      /* Make the previous instruction the current one.  */
1711
      extype = EXEC_UNKNOWN;
1712
      insn = prev_insn;
1713
      now_seg = prev_seg;
1714
      now_subseg = prev_subseg;
1715
      prev_insn = -1;
1716
      cur_mul32_p = prev_mul32_p;
1717
      prev_mul32_p = 0;
1718
      memcpy (&opcode, &prev_opcode, sizeof (prev_opcode));
1719
    }
1720
 
1721
  /* If this is a long instruction, write it and any previous short
1722
     instruction.  */
1723
  if (opcode.form->form >= LONG)
1724
    {
1725
      if (extype != EXEC_UNKNOWN)
1726
        as_bad (_("Instruction uses long version, so it cannot be mixed as specified"));
1727
      d30v_cleanup (FALSE);
1728
      write_long (&opcode, insn, fixups);
1729
      prev_insn = -1;
1730
    }
1731
  else if ((prev_insn != -1)
1732
           && (write_2_short
1733
               (&prev_opcode, (long) prev_insn, &opcode,
1734
                (long) insn, extype, fixups) == 0))
1735
    {
1736
      /* No instructions saved.  */
1737
      prev_insn = -1;
1738
    }
1739
  else
1740
    {
1741
      if (extype != EXEC_UNKNOWN)
1742
        as_bad (_("Unable to mix instructions as specified"));
1743
 
1744
      /* Save off last instruction so it may be packed on next pass.  */
1745
      memcpy (&prev_opcode, &opcode, sizeof (prev_opcode));
1746
      prev_insn = insn;
1747
      prev_seg = now_seg;
1748
      prev_subseg = now_subseg;
1749
      fixups = fixups->next;
1750
      prev_mul32_p = cur_mul32_p;
1751
    }
1752
}
1753
 
1754
/* If while processing a fixup, a reloc really needs to be created,
1755
   then it is done here.  */
1756
 
1757
arelent *
1758
tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
1759
{
1760
  arelent *reloc;
1761
  reloc = xmalloc (sizeof (arelent));
1762
  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
1763
  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1764
  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1765
  reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
1766
  if (reloc->howto == NULL)
1767
    {
1768
      as_bad_where (fixp->fx_file, fixp->fx_line,
1769
                    _("reloc %d not supported by object file format"),
1770
                    (int) fixp->fx_r_type);
1771
      return NULL;
1772
    }
1773
 
1774
  reloc->addend = 0;
1775
  return reloc;
1776
}
1777
 
1778
int
1779
md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
1780
                               asection *seg ATTRIBUTE_UNUSED)
1781
{
1782
  abort ();
1783
  return 0;
1784
}
1785
 
1786
long
1787
md_pcrel_from_section (fixS *fixp, segT sec)
1788
{
1789
  if (fixp->fx_addsy != (symbolS *) NULL
1790
      && (!S_IS_DEFINED (fixp->fx_addsy)
1791
          || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
1792
    return 0;
1793
  return fixp->fx_frag->fr_address + fixp->fx_where;
1794
}
1795
 
1796
/* Called after the assembler has finished parsing the input file or
1797
   after a label is defined.  Because the D30V assembler sometimes
1798
   saves short instructions to see if it can package them with the
1799
   next instruction, there may be a short instruction that still needs
1800
   written.  */
1801
 
1802
int
1803
d30v_cleanup (int use_sequential)
1804
{
1805
  segT seg;
1806
  subsegT subseg;
1807
 
1808
  if (prev_insn != -1)
1809
    {
1810
      seg = now_seg;
1811
      subseg = now_subseg;
1812
      subseg_set (prev_seg, prev_subseg);
1813
      write_1_short (&prev_opcode, (long) prev_insn, fixups->next,
1814
                     use_sequential);
1815
      subseg_set (seg, subseg);
1816
      prev_insn = -1;
1817
      if (use_sequential)
1818
        prev_mul32_p = FALSE;
1819
    }
1820
 
1821
  return 1;
1822
}
1823
 
1824
/* This function is called at the start of every line.  It checks to
1825
   see if the first character is a '.', which indicates the start of a
1826
   pseudo-op.  If it is, then write out any unwritten instructions.  */
1827
 
1828
void
1829
d30v_start_line (void)
1830
{
1831
  char *c = input_line_pointer;
1832
 
1833
  while (ISSPACE (*c))
1834
    c++;
1835
 
1836
  if (*c == '.')
1837
    d30v_cleanup (FALSE);
1838
}
1839
 
1840
static void
1841
check_size (long value, int bits, char *file, int line)
1842
{
1843
  int tmp, max;
1844
 
1845
  if (value < 0)
1846
    tmp = ~value;
1847
  else
1848
    tmp = value;
1849
 
1850
  max = (1 << (bits - 1)) - 1;
1851
 
1852
  if (tmp > max)
1853
    as_bad_where (file, line, _("value too large to fit in %d bits"), bits);
1854
}
1855
 
1856
/* d30v_frob_label() is called when after a label is recognized.  */
1857
 
1858
void
1859
d30v_frob_label (symbolS *lab)
1860
{
1861
  /* Emit any pending instructions.  */
1862
  d30v_cleanup (FALSE);
1863
 
1864
  /* Update the label's address with the current output pointer.  */
1865
  symbol_set_frag (lab, frag_now);
1866
  S_SET_VALUE (lab, (valueT) frag_now_fix ());
1867
 
1868
  /* Record this label for future adjustment after we find out what
1869
     kind of data it references, and the required alignment therewith.  */
1870
  d30v_last_label = lab;
1871
}
1872
 
1873
/* Hook into cons for capturing alignment changes.  */
1874
 
1875
void
1876
d30v_cons_align (int size)
1877
{
1878
  int log_size;
1879
 
1880
  log_size = 0;
1881
  while ((size >>= 1) != 0)
1882
    ++log_size;
1883
 
1884
  if (d30v_current_align < log_size)
1885
    d30v_align (log_size, (char *) NULL, NULL);
1886
  else if (d30v_current_align > log_size)
1887
    d30v_current_align = log_size;
1888
  d30v_last_label = NULL;
1889
}
1890
 
1891
void
1892
md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
1893
{
1894
  char *where;
1895
  unsigned long insn, insn2;
1896
  long value = *valP;
1897
 
1898
  if (fixP->fx_addsy == (symbolS *) NULL)
1899
    fixP->fx_done = 1;
1900
 
1901
  /* We don't support subtracting a symbol.  */
1902
  if (fixP->fx_subsy != (symbolS *) NULL)
1903
    as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
1904
 
1905
  /* Fetch the instruction, insert the fully resolved operand
1906
     value, and stuff the instruction back again.  */
1907
  where = fixP->fx_frag->fr_literal + fixP->fx_where;
1908
  insn = bfd_getb32 ((unsigned char *) where);
1909
 
1910
  switch (fixP->fx_r_type)
1911
    {
1912
    case BFD_RELOC_8:  /* Check for a bad .byte directive.  */
1913
      if (fixP->fx_addsy != NULL)
1914
        as_bad (_("line %d: unable to place address of symbol '%s' into a byte"),
1915
                fixP->fx_line, S_GET_NAME (fixP->fx_addsy));
1916
      else if (((unsigned)value) > 0xff)
1917
        as_bad (_("line %d: unable to place value %lx into a byte"),
1918
                fixP->fx_line, value);
1919
      else
1920
        *(unsigned char *) where = value;
1921
      break;
1922
 
1923
    case BFD_RELOC_16:  /* Check for a bad .short directive.  */
1924
      if (fixP->fx_addsy != NULL)
1925
        as_bad (_("line %d: unable to place address of symbol '%s' into a short"),
1926
                fixP->fx_line, S_GET_NAME (fixP->fx_addsy));
1927
      else if (((unsigned)value) > 0xffff)
1928
        as_bad (_("line %d: unable to place value %lx into a short"),
1929
                fixP->fx_line, value);
1930
      else
1931
        bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
1932
      break;
1933
 
1934
    case BFD_RELOC_64:  /* Check for a bad .quad directive.  */
1935
      if (fixP->fx_addsy != NULL)
1936
        as_bad (_("line %d: unable to place address of symbol '%s' into a quad"),
1937
                fixP->fx_line, S_GET_NAME (fixP->fx_addsy));
1938
      else
1939
        {
1940
          bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
1941
          bfd_putb32 (0, ((unsigned char *) where) + 4);
1942
        }
1943
      break;
1944
 
1945
    case BFD_RELOC_D30V_6:
1946
      check_size (value, 6, fixP->fx_file, fixP->fx_line);
1947
      insn |= value & 0x3F;
1948
      bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1949
      break;
1950
 
1951
    case BFD_RELOC_D30V_9_PCREL:
1952
      if (fixP->fx_where & 0x7)
1953
        {
1954
          if (fixP->fx_done)
1955
            value += 4;
1956
          else
1957
            fixP->fx_r_type = BFD_RELOC_D30V_9_PCREL_R;
1958
        }
1959
      check_size (value, 9, fixP->fx_file, fixP->fx_line);
1960
      insn |= ((value >> 3) & 0x3F) << 12;
1961
      bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1962
      break;
1963
 
1964
    case BFD_RELOC_D30V_15:
1965
      check_size (value, 15, fixP->fx_file, fixP->fx_line);
1966
      insn |= (value >> 3) & 0xFFF;
1967
      bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1968
      break;
1969
 
1970
    case BFD_RELOC_D30V_15_PCREL:
1971
      if (fixP->fx_where & 0x7)
1972
        {
1973
          if (fixP->fx_done)
1974
            value += 4;
1975
          else
1976
            fixP->fx_r_type = BFD_RELOC_D30V_15_PCREL_R;
1977
        }
1978
      check_size (value, 15, fixP->fx_file, fixP->fx_line);
1979
      insn |= (value >> 3) & 0xFFF;
1980
      bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1981
      break;
1982
 
1983
    case BFD_RELOC_D30V_21:
1984
      check_size (value, 21, fixP->fx_file, fixP->fx_line);
1985
      insn |= (value >> 3) & 0x3FFFF;
1986
      bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1987
      break;
1988
 
1989
    case BFD_RELOC_D30V_21_PCREL:
1990
      if (fixP->fx_where & 0x7)
1991
        {
1992
          if (fixP->fx_done)
1993
            value += 4;
1994
          else
1995
            fixP->fx_r_type = BFD_RELOC_D30V_21_PCREL_R;
1996
        }
1997
      check_size (value, 21, fixP->fx_file, fixP->fx_line);
1998
      insn |= (value >> 3) & 0x3FFFF;
1999
      bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
2000
      break;
2001
 
2002
    case BFD_RELOC_D30V_32:
2003
      insn2 = bfd_getb32 ((unsigned char *) where + 4);
2004
      insn |= (value >> 26) & 0x3F;             /* Top 6 bits.  */
2005
      insn2 |= ((value & 0x03FC0000) << 2);     /* Next 8 bits.  */
2006
      insn2 |= value & 0x0003FFFF;              /* Bottom 18 bits.  */
2007
      bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
2008
      bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4);
2009
      break;
2010
 
2011
    case BFD_RELOC_D30V_32_PCREL:
2012
      insn2 = bfd_getb32 ((unsigned char *) where + 4);
2013
      insn |= (value >> 26) & 0x3F;             /* Top 6 bits.  */
2014
      insn2 |= ((value & 0x03FC0000) << 2);     /* Next 8 bits.  */
2015
      insn2 |= value & 0x0003FFFF;              /* Bottom 18 bits.  */
2016
      bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
2017
      bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4);
2018
      break;
2019
 
2020
    case BFD_RELOC_32:
2021
      bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
2022
      break;
2023
 
2024
    default:
2025
      as_bad (_("line %d: unknown relocation type: 0x%x"),
2026
              fixP->fx_line, fixP->fx_r_type);
2027
    }
2028
}
2029
 
2030
/* Handle the .align pseudo-op.  This aligns to a power of two.  We
2031
   hook here to latch the current alignment.  */
2032
 
2033
static void
2034
s_d30v_align (int ignore ATTRIBUTE_UNUSED)
2035
{
2036
  int align;
2037
  char fill, *pfill = NULL;
2038
  long max_alignment = 15;
2039
 
2040
  align = get_absolute_expression ();
2041
  if (align > max_alignment)
2042
    {
2043
      align = max_alignment;
2044
      as_warn (_("Alignment too large: %d assumed"), align);
2045
    }
2046
  else if (align < 0)
2047
    {
2048
      as_warn (_("Alignment negative: 0 assumed"));
2049
      align = 0;
2050
    }
2051
 
2052
  if (*input_line_pointer == ',')
2053
    {
2054
      input_line_pointer++;
2055
      fill = get_absolute_expression ();
2056
      pfill = &fill;
2057
    }
2058
 
2059
  d30v_last_label = NULL;
2060
  d30v_align (align, pfill, NULL);
2061
 
2062
  demand_empty_rest_of_line ();
2063
}
2064
 
2065
/* Handle the .text pseudo-op.  This is like the usual one, but it
2066
   clears the saved last label and resets known alignment.  */
2067
 
2068
static void
2069
s_d30v_text (int i)
2070
 
2071
{
2072
  s_text (i);
2073
  d30v_last_label = NULL;
2074
  d30v_current_align = 0;
2075
  d30v_current_align_seg = now_seg;
2076
}
2077
 
2078
/* Handle the .data pseudo-op.  This is like the usual one, but it
2079
   clears the saved last label and resets known alignment.  */
2080
 
2081
static void
2082
s_d30v_data (int i)
2083
{
2084
  s_data (i);
2085
  d30v_last_label = NULL;
2086
  d30v_current_align = 0;
2087
  d30v_current_align_seg = now_seg;
2088
}
2089
 
2090
/* Handle the .section pseudo-op.  This is like the usual one, but it
2091
   clears the saved last label and resets known alignment.  */
2092
 
2093
static void
2094
s_d30v_section (int ignore)
2095
{
2096
  obj_elf_section (ignore);
2097
  d30v_last_label = NULL;
2098
  d30v_current_align = 0;
2099
  d30v_current_align_seg = now_seg;
2100
}
2101
 
2102
/* The target specific pseudo-ops which we support.  */
2103
const pseudo_typeS md_pseudo_table[] =
2104
{
2105
  { "word", cons, 4 },
2106
  { "hword", cons, 2 },
2107
  { "align", s_d30v_align, 0 },
2108
  { "text", s_d30v_text, 0 },
2109
  { "data", s_d30v_data, 0 },
2110
  { "section", s_d30v_section, 0 },
2111
  { "section.s", s_d30v_section, 0 },
2112
  { "sect", s_d30v_section, 0 },
2113
  { "sect.s", s_d30v_section, 0 },
2114
  { NULL, NULL, 0 }
2115
};
2116
 

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