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julius |
.\" Automatically generated by Pod::Man v1.37, Pod::Parser v1.14
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.\"
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.\" Standard preamble:
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.\" ========================================================================
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.de Sh \" Subsection heading
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.PP
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..
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.de Sp \" Vertical space (when we can't use .PP)
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..
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.\" Set up some character translations and predefined strings. \*(-- will
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.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left
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.\" double quote, and \*(R" will give a right double quote. | will give a
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.\" real vertical bar. \*(C+ will give a nicer C++. Capital omega is used to
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.\" do unbreakable dashes and therefore won't be available. \*(C` and \*(C'
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.\" expand to `' in nroff, nothing in troff, for use with C<>.
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.tr \(*W-|\(bv\*(Tr
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.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p'
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.ie n \{\
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. ds -- \(*W-
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. ds PI pi
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. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
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. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch
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. ds L" ""
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. ds R" ""
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. ds C` ""
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. ds C' ""
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'br\}
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.el\{\
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. ds -- \|\(em\|
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. ds PI \(*p
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. ds L" ``
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. ds R" ''
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'br\}
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.\"
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.\" If the F register is turned on, we'll generate index entries on stderr for
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.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index
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.\" entries marked with X<> in POD. Of course, you'll have to process the
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.\" output yourself in some meaningful fashion.
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.if \nF \{\
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. de IX
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. tm Index:\\$1\t\\n%\t"\\$2"
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..
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. nr % 0
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. rr F
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.\}
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.\"
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.\" For nroff, turn off justification. Always turn off hyphenation; it makes
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.\" way too many mistakes in technical documents.
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.hy 0
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.\"
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.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2).
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.\" Fear. Run. Save yourself. No user-serviceable parts.
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. \" fudge factors for nroff and troff
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.if n \{\
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. ds #H 0
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. ds #V .8m
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. ds #F .3m
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. ds #[ \f1
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.\}
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.if t \{\
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. ds #H ((1u-(\\\\n(.fu%2u))*.13m)
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. ds #] \&
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.\}
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. \" simple accents for nroff and troff
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.if n \{\
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. ds /
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.\}
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.if t \{\
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. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u"
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. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u'
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. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u'
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. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u'
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. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u'
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. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u'
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.\}
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. \" troff and (daisy-wheel) nroff accents
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.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V'
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.ds 8 \h'\*(#H'\(*b\h'-\*(#H'
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.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#]
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.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H'
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.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u'
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.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#]
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.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#]
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.ds ae a\h'-(\w'a'u*4/10)'e
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.ds Ae A\h'-(\w'A'u*4/10)'E
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. \" corrections for vroff
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.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u'
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.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u'
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. \" for low resolution devices (crt and lpr)
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.if \n(.H>23 .if \n(.V>19 \
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\{\
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. ds : e
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. ds 8 ss
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. ds o a
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. ds d- d\h'-1'\(ga
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. ds D- D\h'-1'\(hy
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. ds th \o'bp'
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. ds Th \o'LP'
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. ds ae ae
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. ds Ae AE
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.\}
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.rm #[ #] #H #V #F C
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.\" ========================================================================
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.\"
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.IX Title "AS 1"
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.TH AS 1 "2008-05-06" "binutils-2.18.50" "GNU Development Tools"
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.SH "NAME"
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AS \- the portable GNU assembler.
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.SH "SYNOPSIS"
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.IX Header "SYNOPSIS"
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as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-\-alternate\fR] [\fB\-D\fR]
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[\fB\-\-debug\-prefix\-map\fR \fIold\fR=\fInew\fR]
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[\fB\-\-defsym\fR \fIsym\fR=\fIval\fR] [\fB\-f\fR] [\fB\-g\fR] [\fB\-\-gstabs\fR]
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[\fB\-\-gstabs+\fR] [\fB\-\-gdwarf\-2\fR] [\fB\-\-help\fR] [\fB\-I\fR \fIdir\fR] [\fB\-J\fR]
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[\fB\-K\fR] [\fB\-L\fR] [\fB\-\-listing\-lhs\-width\fR=\fI\s-1NUM\s0\fR]
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[\fB\-\-listing\-lhs\-width2\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-rhs\-width\fR=\fI\s-1NUM\s0\fR]
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[\fB\-\-listing\-cont\-lines\fR=\fI\s-1NUM\s0\fR] [\fB\-\-keep\-locals\fR] [\fB\-o\fR
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\fIobjfile\fR] [\fB\-R\fR] [\fB\-\-reduce\-memory\-overheads\fR] [\fB\-\-statistics\fR]
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| 144 |
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[\fB\-v\fR] [\fB\-version\fR] [\fB\-\-version\fR] [\fB\-W\fR] [\fB\-\-warn\fR]
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| 145 |
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[\fB\-\-fatal\-warnings\fR] [\fB\-w\fR] [\fB\-x\fR] [\fB\-Z\fR] [\fB@\fR\fI\s-1FILE\s0\fR]
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[\fB\-\-target\-help\fR] [\fItarget-options\fR]
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| 147 |
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[\fB\-\-\fR|\fIfiles\fR ...]
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.PP
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| 149 |
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\&\fITarget Alpha options:\fR
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| 150 |
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[\fB\-m\fR\fIcpu\fR]
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| 151 |
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[\fB\-mdebug\fR | \fB\-no\-mdebug\fR]
|
| 152 |
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[\fB\-relax\fR] [\fB\-g\fR] [\fB\-G\fR\fIsize\fR]
|
| 153 |
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[\fB\-F\fR] [\fB\-32addr\fR]
|
| 154 |
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.PP
|
| 155 |
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\&\fITarget \s-1ARC\s0 options:\fR
|
| 156 |
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[\fB\-marc[5|6|7|8]\fR]
|
| 157 |
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[\fB\-EB\fR|\fB\-EL\fR]
|
| 158 |
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.PP
|
| 159 |
|
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\&\fITarget \s-1ARM\s0 options:\fR
|
| 160 |
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[\fB\-mcpu\fR=\fIprocessor\fR[+\fIextension\fR...]]
|
| 161 |
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[\fB\-march\fR=\fIarchitecture\fR[+\fIextension\fR...]]
|
| 162 |
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[\fB\-mfpu\fR=\fIfloating-point-format\fR]
|
| 163 |
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[\fB\-mfloat\-abi\fR=\fIabi\fR]
|
| 164 |
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[\fB\-meabi\fR=\fIver\fR]
|
| 165 |
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[\fB\-mthumb\fR]
|
| 166 |
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[\fB\-EB\fR|\fB\-EL\fR]
|
| 167 |
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[\fB\-mapcs\-32\fR|\fB\-mapcs\-26\fR|\fB\-mapcs\-float\fR|
|
| 168 |
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\fB\-mapcs\-reentrant\fR]
|
| 169 |
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[\fB\-mthumb\-interwork\fR] [\fB\-k\fR]
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| 170 |
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.PP
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| 171 |
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\&\fITarget \s-1CRIS\s0 options:\fR
|
| 172 |
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[\fB\-\-underscore\fR | \fB\-\-no\-underscore\fR]
|
| 173 |
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[\fB\-\-pic\fR] [\fB\-N\fR]
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| 174 |
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[\fB\-\-emulation=criself\fR | \fB\-\-emulation=crisaout\fR]
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| 175 |
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[\fB\-\-march=v0_v10\fR | \fB\-\-march=v10\fR | \fB\-\-march=v32\fR | \fB\-\-march=common_v10_v32\fR]
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| 176 |
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.PP
|
| 177 |
|
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\&\fITarget D10V options:\fR
|
| 178 |
|
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[\fB\-O\fR]
|
| 179 |
|
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.PP
|
| 180 |
|
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\&\fITarget D30V options:\fR
|
| 181 |
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[\fB\-O\fR|\fB\-n\fR|\fB\-N\fR]
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| 182 |
|
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.PP
|
| 183 |
|
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\&\fITarget i386 options:\fR
|
| 184 |
|
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[\fB\-\-32\fR|\fB\-\-64\fR] [\fB\-n\fR]
|
| 185 |
|
|
[\fB\-march\fR=\fI\s-1CPU\s0\fR[+\fI\s-1EXTENSION\s0\fR...]] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR]
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| 186 |
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.PP
|
| 187 |
|
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\&\fITarget i960 options:\fR
|
| 188 |
|
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[\fB\-ACA\fR|\fB\-ACA_A\fR|\fB\-ACB\fR|\fB\-ACC\fR|\fB\-AKA\fR|\fB\-AKB\fR|
|
| 189 |
|
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\fB\-AKC\fR|\fB\-AMC\fR]
|
| 190 |
|
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[\fB\-b\fR] [\fB\-no\-relax\fR]
|
| 191 |
|
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.PP
|
| 192 |
|
|
\&\fITarget \s-1IA\-64\s0 options:\fR
|
| 193 |
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[\fB\-mconstant\-gp\fR|\fB\-mauto\-pic\fR]
|
| 194 |
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[\fB\-milp32\fR|\fB\-milp64\fR|\fB\-mlp64\fR|\fB\-mp64\fR]
|
| 195 |
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[\fB\-mle\fR|\fBmbe\fR]
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| 196 |
|
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[\fB\-mtune=itanium1\fR|\fB\-mtune=itanium2\fR]
|
| 197 |
|
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[\fB\-munwind\-check=warning\fR|\fB\-munwind\-check=error\fR]
|
| 198 |
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[\fB\-mhint.b=ok\fR|\fB\-mhint.b=warning\fR|\fB\-mhint.b=error\fR]
|
| 199 |
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[\fB\-x\fR|\fB\-xexplicit\fR] [\fB\-xauto\fR] [\fB\-xdebug\fR]
|
| 200 |
|
|
.PP
|
| 201 |
|
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\&\fITarget \s-1IP2K\s0 options:\fR
|
| 202 |
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[\fB\-mip2022\fR|\fB\-mip2022ext\fR]
|
| 203 |
|
|
.PP
|
| 204 |
|
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\&\fITarget M32C options:\fR
|
| 205 |
|
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[\fB\-m32c\fR|\fB\-m16c\fR]
|
| 206 |
|
|
.PP
|
| 207 |
|
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\&\fITarget M32R options:\fR
|
| 208 |
|
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[\fB\-\-m32rx\fR|\fB\-\-[no\-]warn\-explicit\-parallel\-conflicts\fR|
|
| 209 |
|
|
\fB\-\-W[n]p\fR]
|
| 210 |
|
|
.PP
|
| 211 |
|
|
\&\fITarget M680X0 options:\fR
|
| 212 |
|
|
[\fB\-l\fR] [\fB\-m68000\fR|\fB\-m68010\fR|\fB\-m68020\fR|...]
|
| 213 |
|
|
.PP
|
| 214 |
|
|
\&\fITarget M68HC11 options:\fR
|
| 215 |
|
|
[\fB\-m68hc11\fR|\fB\-m68hc12\fR|\fB\-m68hcs12\fR]
|
| 216 |
|
|
[\fB\-mshort\fR|\fB\-mlong\fR]
|
| 217 |
|
|
[\fB\-mshort\-double\fR|\fB\-mlong\-double\fR]
|
| 218 |
|
|
[\fB\-\-force\-long\-branches\fR] [\fB\-\-short\-branches\fR]
|
| 219 |
|
|
[\fB\-\-strict\-direct\-mode\fR] [\fB\-\-print\-insn\-syntax\fR]
|
| 220 |
|
|
[\fB\-\-print\-opcodes\fR] [\fB\-\-generate\-example\fR]
|
| 221 |
|
|
.PP
|
| 222 |
|
|
\&\fITarget \s-1MCORE\s0 options:\fR
|
| 223 |
|
|
[\fB\-jsri2bsr\fR] [\fB\-sifilter\fR] [\fB\-relax\fR]
|
| 224 |
|
|
[\fB\-mcpu=[210|340]\fR]
|
| 225 |
|
|
.PP
|
| 226 |
|
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\&\fITarget \s-1MIPS\s0 options:\fR
|
| 227 |
|
|
[\fB\-nocpp\fR] [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR[\fIoptimization level\fR]]
|
| 228 |
|
|
[\fB\-g\fR[\fIdebug level\fR]] [\fB\-G\fR \fInum\fR] [\fB\-KPIC\fR] [\fB\-call_shared\fR]
|
| 229 |
|
|
[\fB\-non_shared\fR] [\fB\-xgot\fR [\fB\-mvxworks\-pic\fR]
|
| 230 |
|
|
[\fB\-mabi\fR=\fI\s-1ABI\s0\fR] [\fB\-32\fR] [\fB\-n32\fR] [\fB\-64\fR] [\fB\-mfp32\fR] [\fB\-mgp32\fR]
|
| 231 |
|
|
[\fB\-march\fR=\fI\s-1CPU\s0\fR] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR] [\fB\-mips1\fR] [\fB\-mips2\fR]
|
| 232 |
|
|
[\fB\-mips3\fR] [\fB\-mips4\fR] [\fB\-mips5\fR] [\fB\-mips32\fR] [\fB\-mips32r2\fR]
|
| 233 |
|
|
[\fB\-mips64\fR] [\fB\-mips64r2\fR]
|
| 234 |
|
|
[\fB\-construct\-floats\fR] [\fB\-no\-construct\-floats\fR]
|
| 235 |
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|
[\fB\-trap\fR] [\fB\-no\-break\fR] [\fB\-break\fR] [\fB\-no\-trap\fR]
|
| 236 |
|
|
[\fB\-mfix7000\fR] [\fB\-mno\-fix7000\fR]
|
| 237 |
|
|
[\fB\-mips16\fR] [\fB\-no\-mips16\fR]
|
| 238 |
|
|
[\fB\-msmartmips\fR] [\fB\-mno\-smartmips\fR]
|
| 239 |
|
|
[\fB\-mips3d\fR] [\fB\-no\-mips3d\fR]
|
| 240 |
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[\fB\-mdmx\fR] [\fB\-no\-mdmx\fR]
|
| 241 |
|
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[\fB\-mdsp\fR] [\fB\-mno\-dsp\fR]
|
| 242 |
|
|
[\fB\-mdspr2\fR] [\fB\-mno\-dspr2\fR]
|
| 243 |
|
|
[\fB\-mmt\fR] [\fB\-mno\-mt\fR]
|
| 244 |
|
|
[\fB\-mdebug\fR] [\fB\-no\-mdebug\fR]
|
| 245 |
|
|
[\fB\-mpdr\fR] [\fB\-mno\-pdr\fR]
|
| 246 |
|
|
.PP
|
| 247 |
|
|
\&\fITarget \s-1MMIX\s0 options:\fR
|
| 248 |
|
|
[\fB\-\-fixed\-special\-register\-names\fR] [\fB\-\-globalize\-symbols\fR]
|
| 249 |
|
|
[\fB\-\-gnu\-syntax\fR] [\fB\-\-relax\fR] [\fB\-\-no\-predefined\-symbols\fR]
|
| 250 |
|
|
[\fB\-\-no\-expand\fR] [\fB\-\-no\-merge\-gregs\fR] [\fB\-x\fR]
|
| 251 |
|
|
[\fB\-\-linker\-allocated\-gregs\fR]
|
| 252 |
|
|
.PP
|
| 253 |
|
|
\&\fITarget \s-1PDP11\s0 options:\fR
|
| 254 |
|
|
[\fB\-mpic\fR|\fB\-mno\-pic\fR] [\fB\-mall\fR] [\fB\-mno\-extensions\fR]
|
| 255 |
|
|
[\fB\-m\fR\fIextension\fR|\fB\-mno\-\fR\fIextension\fR]
|
| 256 |
|
|
[\fB\-m\fR\fIcpu\fR] [\fB\-m\fR\fImachine\fR]
|
| 257 |
|
|
.PP
|
| 258 |
|
|
\&\fITarget picoJava options:\fR
|
| 259 |
|
|
[\fB\-mb\fR|\fB\-me\fR]
|
| 260 |
|
|
.PP
|
| 261 |
|
|
\&\fITarget PowerPC options:\fR
|
| 262 |
|
|
[\fB\-mpwrx\fR|\fB\-mpwr2\fR|\fB\-mpwr\fR|\fB\-m601\fR|\fB\-mppc\fR|\fB\-mppc32\fR|\fB\-m603\fR|\fB\-m604\fR|
|
| 263 |
|
|
\fB\-m403\fR|\fB\-m405\fR|\fB\-mppc64\fR|\fB\-m620\fR|\fB\-mppc64bridge\fR|\fB\-mbooke\fR|
|
| 264 |
|
|
\fB\-mbooke32\fR|\fB\-mbooke64\fR]
|
| 265 |
|
|
[\fB\-mcom\fR|\fB\-many\fR|\fB\-maltivec\fR] [\fB\-memb\fR]
|
| 266 |
|
|
[\fB\-mregnames\fR|\fB\-mno\-regnames\fR]
|
| 267 |
|
|
[\fB\-mrelocatable\fR|\fB\-mrelocatable\-lib\fR]
|
| 268 |
|
|
[\fB\-mlittle\fR|\fB\-mlittle\-endian\fR|\fB\-mbig\fR|\fB\-mbig\-endian\fR]
|
| 269 |
|
|
[\fB\-msolaris\fR|\fB\-mno\-solaris\fR]
|
| 270 |
|
|
.PP
|
| 271 |
|
|
\&\fITarget \s-1SPARC\s0 options:\fR
|
| 272 |
|
|
[\fB\-Av6\fR|\fB\-Av7\fR|\fB\-Av8\fR|\fB\-Asparclet\fR|\fB\-Asparclite\fR
|
| 273 |
|
|
\fB\-Av8plus\fR|\fB\-Av8plusa\fR|\fB\-Av9\fR|\fB\-Av9a\fR]
|
| 274 |
|
|
[\fB\-xarch=v8plus\fR|\fB\-xarch=v8plusa\fR] [\fB\-bump\fR]
|
| 275 |
|
|
[\fB\-32\fR|\fB\-64\fR]
|
| 276 |
|
|
.PP
|
| 277 |
|
|
\&\fITarget \s-1TIC54X\s0 options:\fR
|
| 278 |
|
|
[\fB\-mcpu=54[123589]\fR|\fB\-mcpu=54[56]lp\fR] [\fB\-mfar\-mode\fR|\fB\-mf\fR]
|
| 279 |
|
|
[\fB\-merrors\-to\-file\fR \fI\fR|\fB\-me\fR \fI\fR]
|
| 280 |
|
|
.PP
|
| 281 |
|
|
\&\fITarget Z80 options:\fR
|
| 282 |
|
|
[\fB\-z80\fR] [\fB\-r800\fR]
|
| 283 |
|
|
[ \fB\-ignore\-undocumented\-instructions\fR] [\fB\-Wnud\fR]
|
| 284 |
|
|
[ \fB\-ignore\-unportable\-instructions\fR] [\fB\-Wnup\fR]
|
| 285 |
|
|
[ \fB\-warn\-undocumented\-instructions\fR] [\fB\-Wud\fR]
|
| 286 |
|
|
[ \fB\-warn\-unportable\-instructions\fR] [\fB\-Wup\fR]
|
| 287 |
|
|
[ \fB\-forbid\-undocumented\-instructions\fR] [\fB\-Fud\fR]
|
| 288 |
|
|
[ \fB\-forbid\-unportable\-instructions\fR] [\fB\-Fup\fR]
|
| 289 |
|
|
.PP
|
| 290 |
|
|
\&\fITarget Xtensa options:\fR
|
| 291 |
|
|
[\fB\-\-[no\-]text\-section\-literals\fR] [\fB\-\-[no\-]absolute\-literals\fR]
|
| 292 |
|
|
[\fB\-\-[no\-]target\-align\fR] [\fB\-\-[no\-]longcalls\fR]
|
| 293 |
|
|
[\fB\-\-[no\-]transform\fR]
|
| 294 |
|
|
[\fB\-\-rename\-section\fR \fIoldname\fR=\fInewname\fR]
|
| 295 |
|
|
.SH "DESCRIPTION"
|
| 296 |
|
|
.IX Header "DESCRIPTION"
|
| 297 |
|
|
\&\s-1GNU\s0 \fBas\fR is really a family of assemblers.
|
| 298 |
|
|
If you use (or have used) the \s-1GNU\s0 assembler on one architecture, you
|
| 299 |
|
|
should find a fairly similar environment when you use it on another
|
| 300 |
|
|
architecture. Each version has much in common with the others,
|
| 301 |
|
|
including object file formats, most assembler directives (often called
|
| 302 |
|
|
\&\fIpseudo-ops\fR) and assembler syntax.
|
| 303 |
|
|
.PP
|
| 304 |
|
|
\&\fBas\fR is primarily intended to assemble the output of the
|
| 305 |
|
|
\&\s-1GNU\s0 C compiler \f(CW\*(C`gcc\*(C'\fR for use by the linker
|
| 306 |
|
|
\&\f(CW\*(C`ld\*(C'\fR. Nevertheless, we've tried to make \fBas\fR
|
| 307 |
|
|
assemble correctly everything that other assemblers for the same
|
| 308 |
|
|
machine would assemble.
|
| 309 |
|
|
Any exceptions are documented explicitly.
|
| 310 |
|
|
This doesn't mean \fBas\fR always uses the same syntax as another
|
| 311 |
|
|
assembler for the same architecture; for example, we know of several
|
| 312 |
|
|
incompatible versions of 680x0 assembly language syntax.
|
| 313 |
|
|
.PP
|
| 314 |
|
|
Each time you run \fBas\fR it assembles exactly one source
|
| 315 |
|
|
program. The source program is made up of one or more files.
|
| 316 |
|
|
(The standard input is also a file.)
|
| 317 |
|
|
.PP
|
| 318 |
|
|
You give \fBas\fR a command line that has zero or more input file
|
| 319 |
|
|
names. The input files are read (from left file name to right). A
|
| 320 |
|
|
command line argument (in any position) that has no special meaning
|
| 321 |
|
|
is taken to be an input file name.
|
| 322 |
|
|
.PP
|
| 323 |
|
|
If you give \fBas\fR no file names it attempts to read one input file
|
| 324 |
|
|
from the \fBas\fR standard input, which is normally your terminal. You
|
| 325 |
|
|
may have to type \fBctl-D\fR to tell \fBas\fR there is no more program
|
| 326 |
|
|
to assemble.
|
| 327 |
|
|
.PP
|
| 328 |
|
|
Use \fB\-\-\fR if you need to explicitly name the standard input file
|
| 329 |
|
|
in your command line.
|
| 330 |
|
|
.PP
|
| 331 |
|
|
If the source is empty, \fBas\fR produces a small, empty object
|
| 332 |
|
|
file.
|
| 333 |
|
|
.PP
|
| 334 |
|
|
\&\fBas\fR may write warnings and error messages to the standard error
|
| 335 |
|
|
file (usually your terminal). This should not happen when a compiler
|
| 336 |
|
|
runs \fBas\fR automatically. Warnings report an assumption made so
|
| 337 |
|
|
that \fBas\fR could keep assembling a flawed program; errors report a
|
| 338 |
|
|
grave problem that stops the assembly.
|
| 339 |
|
|
.PP
|
| 340 |
|
|
If you are invoking \fBas\fR via the \s-1GNU\s0 C compiler,
|
| 341 |
|
|
you can use the \fB\-Wa\fR option to pass arguments through to the assembler.
|
| 342 |
|
|
The assembler arguments must be separated from each other (and the \fB\-Wa\fR)
|
| 343 |
|
|
by commas. For example:
|
| 344 |
|
|
.PP
|
| 345 |
|
|
.Vb 1
|
| 346 |
|
|
\& gcc -c -g -O -Wa,-alh,-L file.c
|
| 347 |
|
|
.Ve
|
| 348 |
|
|
.PP
|
| 349 |
|
|
This passes two options to the assembler: \fB\-alh\fR (emit a listing to
|
| 350 |
|
|
standard output with high-level and assembly source) and \fB\-L\fR (retain
|
| 351 |
|
|
local symbols in the symbol table).
|
| 352 |
|
|
.PP
|
| 353 |
|
|
Usually you do not need to use this \fB\-Wa\fR mechanism, since many compiler
|
| 354 |
|
|
command-line options are automatically passed to the assembler by the compiler.
|
| 355 |
|
|
(You can call the \s-1GNU\s0 compiler driver with the \fB\-v\fR option to see
|
| 356 |
|
|
precisely what options it passes to each compilation pass, including the
|
| 357 |
|
|
assembler.)
|
| 358 |
|
|
.SH "OPTIONS"
|
| 359 |
|
|
.IX Header "OPTIONS"
|
| 360 |
|
|
.IP "\fB@\fR\fIfile\fR" 4
|
| 361 |
|
|
.IX Item "@file"
|
| 362 |
|
|
Read command-line options from \fIfile\fR. The options read are
|
| 363 |
|
|
inserted in place of the original @\fIfile\fR option. If \fIfile\fR
|
| 364 |
|
|
does not exist, or cannot be read, then the option will be treated
|
| 365 |
|
|
literally, and not removed.
|
| 366 |
|
|
.Sp
|
| 367 |
|
|
Options in \fIfile\fR are separated by whitespace. A whitespace
|
| 368 |
|
|
character may be included in an option by surrounding the entire
|
| 369 |
|
|
option in either single or double quotes. Any character (including a
|
| 370 |
|
|
backslash) may be included by prefixing the character to be included
|
| 371 |
|
|
with a backslash. The \fIfile\fR may itself contain additional
|
| 372 |
|
|
@\fIfile\fR options; any such options will be processed recursively.
|
| 373 |
|
|
.IP "\fB\-a[cdghlmns]\fR" 4
|
| 374 |
|
|
.IX Item "-a[cdghlmns]"
|
| 375 |
|
|
Turn on listings, in any of a variety of ways:
|
| 376 |
|
|
.RS 4
|
| 377 |
|
|
.IP "\fB\-ac\fR" 4
|
| 378 |
|
|
.IX Item "-ac"
|
| 379 |
|
|
omit false conditionals
|
| 380 |
|
|
.IP "\fB\-ad\fR" 4
|
| 381 |
|
|
.IX Item "-ad"
|
| 382 |
|
|
omit debugging directives
|
| 383 |
|
|
.IP "\fB\-ag\fR" 4
|
| 384 |
|
|
.IX Item "-ag"
|
| 385 |
|
|
include general information, like as version and options passed
|
| 386 |
|
|
.IP "\fB\-ah\fR" 4
|
| 387 |
|
|
.IX Item "-ah"
|
| 388 |
|
|
include high-level source
|
| 389 |
|
|
.IP "\fB\-al\fR" 4
|
| 390 |
|
|
.IX Item "-al"
|
| 391 |
|
|
include assembly
|
| 392 |
|
|
.IP "\fB\-am\fR" 4
|
| 393 |
|
|
.IX Item "-am"
|
| 394 |
|
|
include macro expansions
|
| 395 |
|
|
.IP "\fB\-an\fR" 4
|
| 396 |
|
|
.IX Item "-an"
|
| 397 |
|
|
omit forms processing
|
| 398 |
|
|
.IP "\fB\-as\fR" 4
|
| 399 |
|
|
.IX Item "-as"
|
| 400 |
|
|
include symbols
|
| 401 |
|
|
.IP "\fB=file\fR" 4
|
| 402 |
|
|
.IX Item "=file"
|
| 403 |
|
|
set the name of the listing file
|
| 404 |
|
|
.RE
|
| 405 |
|
|
.RS 4
|
| 406 |
|
|
.Sp
|
| 407 |
|
|
You may combine these options; for example, use \fB\-aln\fR for assembly
|
| 408 |
|
|
listing without forms processing. The \fB=file\fR option, if used, must be
|
| 409 |
|
|
the last one. By itself, \fB\-a\fR defaults to \fB\-ahls\fR.
|
| 410 |
|
|
.RE
|
| 411 |
|
|
.IP "\fB\-\-alternate\fR" 4
|
| 412 |
|
|
.IX Item "--alternate"
|
| 413 |
|
|
Begin in alternate macro mode.
|
| 414 |
|
|
.IP "\fB\-D\fR" 4
|
| 415 |
|
|
.IX Item "-D"
|
| 416 |
|
|
Ignored. This option is accepted for script compatibility with calls to
|
| 417 |
|
|
other assemblers.
|
| 418 |
|
|
.IP "\fB\-\-debug\-prefix\-map\fR \fIold\fR\fB=\fR\fInew\fR" 4
|
| 419 |
|
|
.IX Item "--debug-prefix-map old=new"
|
| 420 |
|
|
When assembling files in directory \fI\fIold\fI\fR, record debugging
|
| 421 |
|
|
information describing them as in \fI\fInew\fI\fR instead.
|
| 422 |
|
|
.IP "\fB\-\-defsym\fR \fIsym\fR\fB=\fR\fIvalue\fR" 4
|
| 423 |
|
|
.IX Item "--defsym sym=value"
|
| 424 |
|
|
Define the symbol \fIsym\fR to be \fIvalue\fR before assembling the input file.
|
| 425 |
|
|
\&\fIvalue\fR must be an integer constant. As in C, a leading \fB0x\fR
|
| 426 |
|
|
indicates a hexadecimal value, and a leading \fB0\fR indicates an octal
|
| 427 |
|
|
value. The value of the symbol can be overridden inside a source file via the
|
| 428 |
|
|
use of a \f(CW\*(C`.set\*(C'\fR pseudo\-op.
|
| 429 |
|
|
.IP "\fB\-f\fR" 4
|
| 430 |
|
|
.IX Item "-f"
|
| 431 |
|
|
\&\*(L"fast\*(R"\-\-\-skip whitespace and comment preprocessing (assume source is
|
| 432 |
|
|
compiler output).
|
| 433 |
|
|
.IP "\fB\-g\fR" 4
|
| 434 |
|
|
.IX Item "-g"
|
| 435 |
|
|
.PD 0
|
| 436 |
|
|
.IP "\fB\-\-gen\-debug\fR" 4
|
| 437 |
|
|
.IX Item "--gen-debug"
|
| 438 |
|
|
.PD
|
| 439 |
|
|
Generate debugging information for each assembler source line using whichever
|
| 440 |
|
|
debug format is preferred by the target. This currently means either \s-1STABS\s0,
|
| 441 |
|
|
\&\s-1ECOFF\s0 or \s-1DWARF2\s0.
|
| 442 |
|
|
.IP "\fB\-\-gstabs\fR" 4
|
| 443 |
|
|
.IX Item "--gstabs"
|
| 444 |
|
|
Generate stabs debugging information for each assembler line. This
|
| 445 |
|
|
may help debugging assembler code, if the debugger can handle it.
|
| 446 |
|
|
.IP "\fB\-\-gstabs+\fR" 4
|
| 447 |
|
|
.IX Item "--gstabs+"
|
| 448 |
|
|
Generate stabs debugging information for each assembler line, with \s-1GNU\s0
|
| 449 |
|
|
extensions that probably only gdb can handle, and that could make other
|
| 450 |
|
|
debuggers crash or refuse to read your program. This
|
| 451 |
|
|
may help debugging assembler code. Currently the only \s-1GNU\s0 extension is
|
| 452 |
|
|
the location of the current working directory at assembling time.
|
| 453 |
|
|
.IP "\fB\-\-gdwarf\-2\fR" 4
|
| 454 |
|
|
.IX Item "--gdwarf-2"
|
| 455 |
|
|
Generate \s-1DWARF2\s0 debugging information for each assembler line. This
|
| 456 |
|
|
may help debugging assembler code, if the debugger can handle it. Note\-\-\-this
|
| 457 |
|
|
option is only supported by some targets, not all of them.
|
| 458 |
|
|
.IP "\fB\-\-help\fR" 4
|
| 459 |
|
|
.IX Item "--help"
|
| 460 |
|
|
Print a summary of the command line options and exit.
|
| 461 |
|
|
.IP "\fB\-\-target\-help\fR" 4
|
| 462 |
|
|
.IX Item "--target-help"
|
| 463 |
|
|
Print a summary of all target specific options and exit.
|
| 464 |
|
|
.IP "\fB\-I\fR \fIdir\fR" 4
|
| 465 |
|
|
.IX Item "-I dir"
|
| 466 |
|
|
Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR directives.
|
| 467 |
|
|
.IP "\fB\-J\fR" 4
|
| 468 |
|
|
.IX Item "-J"
|
| 469 |
|
|
Don't warn about signed overflow.
|
| 470 |
|
|
.IP "\fB\-K\fR" 4
|
| 471 |
|
|
.IX Item "-K"
|
| 472 |
|
|
Issue warnings when difference tables altered for long displacements.
|
| 473 |
|
|
.IP "\fB\-L\fR" 4
|
| 474 |
|
|
.IX Item "-L"
|
| 475 |
|
|
.PD 0
|
| 476 |
|
|
.IP "\fB\-\-keep\-locals\fR" 4
|
| 477 |
|
|
.IX Item "--keep-locals"
|
| 478 |
|
|
.PD
|
| 479 |
|
|
Keep (in the symbol table) local symbols. These symbols start with
|
| 480 |
|
|
system-specific local label prefixes, typically \fB.L\fR for \s-1ELF\s0 systems
|
| 481 |
|
|
or \fBL\fR for traditional a.out systems.
|
| 482 |
|
|
.IP "\fB\-\-listing\-lhs\-width=\fR\fInumber\fR" 4
|
| 483 |
|
|
.IX Item "--listing-lhs-width=number"
|
| 484 |
|
|
Set the maximum width, in words, of the output data column for an assembler
|
| 485 |
|
|
listing to \fInumber\fR.
|
| 486 |
|
|
.IP "\fB\-\-listing\-lhs\-width2=\fR\fInumber\fR" 4
|
| 487 |
|
|
.IX Item "--listing-lhs-width2=number"
|
| 488 |
|
|
Set the maximum width, in words, of the output data column for continuation
|
| 489 |
|
|
lines in an assembler listing to \fInumber\fR.
|
| 490 |
|
|
.IP "\fB\-\-listing\-rhs\-width=\fR\fInumber\fR" 4
|
| 491 |
|
|
.IX Item "--listing-rhs-width=number"
|
| 492 |
|
|
Set the maximum width of an input source line, as displayed in a listing, to
|
| 493 |
|
|
\&\fInumber\fR bytes.
|
| 494 |
|
|
.IP "\fB\-\-listing\-cont\-lines=\fR\fInumber\fR" 4
|
| 495 |
|
|
.IX Item "--listing-cont-lines=number"
|
| 496 |
|
|
Set the maximum number of lines printed in a listing for a single line of input
|
| 497 |
|
|
to \fInumber\fR + 1.
|
| 498 |
|
|
.IP "\fB\-o\fR \fIobjfile\fR" 4
|
| 499 |
|
|
.IX Item "-o objfile"
|
| 500 |
|
|
Name the object-file output from \fBas\fR \fIobjfile\fR.
|
| 501 |
|
|
.IP "\fB\-R\fR" 4
|
| 502 |
|
|
.IX Item "-R"
|
| 503 |
|
|
Fold the data section into the text section.
|
| 504 |
|
|
.Sp
|
| 505 |
|
|
Set the default size of \s-1GAS\s0's hash tables to a prime number close to
|
| 506 |
|
|
\&\fInumber\fR. Increasing this value can reduce the length of time it takes the
|
| 507 |
|
|
assembler to perform its tasks, at the expense of increasing the assembler's
|
| 508 |
|
|
memory requirements. Similarly reducing this value can reduce the memory
|
| 509 |
|
|
requirements at the expense of speed.
|
| 510 |
|
|
.IP "\fB\-\-reduce\-memory\-overheads\fR" 4
|
| 511 |
|
|
.IX Item "--reduce-memory-overheads"
|
| 512 |
|
|
This option reduces \s-1GAS\s0's memory requirements, at the expense of making the
|
| 513 |
|
|
assembly processes slower. Currently this switch is a synonym for
|
| 514 |
|
|
\&\fB\-\-hash\-size=4051\fR, but in the future it may have other effects as well.
|
| 515 |
|
|
.IP "\fB\-\-statistics\fR" 4
|
| 516 |
|
|
.IX Item "--statistics"
|
| 517 |
|
|
Print the maximum space (in bytes) and total time (in seconds) used by
|
| 518 |
|
|
assembly.
|
| 519 |
|
|
.IP "\fB\-\-strip\-local\-absolute\fR" 4
|
| 520 |
|
|
.IX Item "--strip-local-absolute"
|
| 521 |
|
|
Remove local absolute symbols from the outgoing symbol table.
|
| 522 |
|
|
.IP "\fB\-v\fR" 4
|
| 523 |
|
|
.IX Item "-v"
|
| 524 |
|
|
.PD 0
|
| 525 |
|
|
.IP "\fB\-version\fR" 4
|
| 526 |
|
|
.IX Item "-version"
|
| 527 |
|
|
.PD
|
| 528 |
|
|
Print the \fBas\fR version.
|
| 529 |
|
|
.IP "\fB\-\-version\fR" 4
|
| 530 |
|
|
.IX Item "--version"
|
| 531 |
|
|
Print the \fBas\fR version and exit.
|
| 532 |
|
|
.IP "\fB\-W\fR" 4
|
| 533 |
|
|
.IX Item "-W"
|
| 534 |
|
|
.PD 0
|
| 535 |
|
|
.IP "\fB\-\-no\-warn\fR" 4
|
| 536 |
|
|
.IX Item "--no-warn"
|
| 537 |
|
|
.PD
|
| 538 |
|
|
Suppress warning messages.
|
| 539 |
|
|
.IP "\fB\-\-fatal\-warnings\fR" 4
|
| 540 |
|
|
.IX Item "--fatal-warnings"
|
| 541 |
|
|
Treat warnings as errors.
|
| 542 |
|
|
.IP "\fB\-\-warn\fR" 4
|
| 543 |
|
|
.IX Item "--warn"
|
| 544 |
|
|
Don't suppress warning messages or treat them as errors.
|
| 545 |
|
|
.IP "\fB\-w\fR" 4
|
| 546 |
|
|
.IX Item "-w"
|
| 547 |
|
|
Ignored.
|
| 548 |
|
|
.IP "\fB\-x\fR" 4
|
| 549 |
|
|
.IX Item "-x"
|
| 550 |
|
|
Ignored.
|
| 551 |
|
|
.IP "\fB\-Z\fR" 4
|
| 552 |
|
|
.IX Item "-Z"
|
| 553 |
|
|
Generate an object file even after errors.
|
| 554 |
|
|
.IP "\fB\-\- |\fR \fIfiles\fR \fB...\fR" 4
|
| 555 |
|
|
.IX Item "-- | files ..."
|
| 556 |
|
|
Standard input, or source files to assemble.
|
| 557 |
|
|
.PP
|
| 558 |
|
|
The following options are available when as is configured for
|
| 559 |
|
|
an \s-1ARC\s0 processor.
|
| 560 |
|
|
.IP "\fB\-marc[5|6|7|8]\fR" 4
|
| 561 |
|
|
.IX Item "-marc[5|6|7|8]"
|
| 562 |
|
|
This option selects the core processor variant.
|
| 563 |
|
|
.IP "\fB\-EB | \-EL\fR" 4
|
| 564 |
|
|
.IX Item "-EB | -EL"
|
| 565 |
|
|
Select either big-endian (\-EB) or little-endian (\-EL) output.
|
| 566 |
|
|
.PP
|
| 567 |
|
|
The following options are available when as is configured for the \s-1ARM\s0
|
| 568 |
|
|
processor family.
|
| 569 |
|
|
.IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
|
| 570 |
|
|
.IX Item "-mcpu=processor[+extension...]"
|
| 571 |
|
|
Specify which \s-1ARM\s0 processor variant is the target.
|
| 572 |
|
|
.IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
|
| 573 |
|
|
.IX Item "-march=architecture[+extension...]"
|
| 574 |
|
|
Specify which \s-1ARM\s0 architecture variant is used by the target.
|
| 575 |
|
|
.IP "\fB\-mfpu=\fR\fIfloating-point-format\fR" 4
|
| 576 |
|
|
.IX Item "-mfpu=floating-point-format"
|
| 577 |
|
|
Select which Floating Point architecture is the target.
|
| 578 |
|
|
.IP "\fB\-mfloat\-abi=\fR\fIabi\fR" 4
|
| 579 |
|
|
.IX Item "-mfloat-abi=abi"
|
| 580 |
|
|
Select which floating point \s-1ABI\s0 is in use.
|
| 581 |
|
|
.IP "\fB\-mthumb\fR" 4
|
| 582 |
|
|
.IX Item "-mthumb"
|
| 583 |
|
|
Enable Thumb only instruction decoding.
|
| 584 |
|
|
.IP "\fB\-mapcs\-32 | \-mapcs\-26 | \-mapcs\-float | \-mapcs\-reentrant\fR" 4
|
| 585 |
|
|
.IX Item "-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant"
|
| 586 |
|
|
Select which procedure calling convention is in use.
|
| 587 |
|
|
.IP "\fB\-EB | \-EL\fR" 4
|
| 588 |
|
|
.IX Item "-EB | -EL"
|
| 589 |
|
|
Select either big-endian (\-EB) or little-endian (\-EL) output.
|
| 590 |
|
|
.IP "\fB\-mthumb\-interwork\fR" 4
|
| 591 |
|
|
.IX Item "-mthumb-interwork"
|
| 592 |
|
|
Specify that the code has been generated with interworking between Thumb and
|
| 593 |
|
|
\&\s-1ARM\s0 code in mind.
|
| 594 |
|
|
.IP "\fB\-k\fR" 4
|
| 595 |
|
|
.IX Item "-k"
|
| 596 |
|
|
Specify that \s-1PIC\s0 code has been generated.
|
| 597 |
|
|
.PP
|
| 598 |
|
|
See the info pages for documentation of the CRIS-specific options.
|
| 599 |
|
|
.PP
|
| 600 |
|
|
The following options are available when as is configured for
|
| 601 |
|
|
a D10V processor.
|
| 602 |
|
|
.IP "\fB\-O\fR" 4
|
| 603 |
|
|
.IX Item "-O"
|
| 604 |
|
|
Optimize output by parallelizing instructions.
|
| 605 |
|
|
.PP
|
| 606 |
|
|
The following options are available when as is configured for a D30V
|
| 607 |
|
|
processor.
|
| 608 |
|
|
.IP "\fB\-O\fR" 4
|
| 609 |
|
|
.IX Item "-O"
|
| 610 |
|
|
Optimize output by parallelizing instructions.
|
| 611 |
|
|
.IP "\fB\-n\fR" 4
|
| 612 |
|
|
.IX Item "-n"
|
| 613 |
|
|
Warn when nops are generated.
|
| 614 |
|
|
.IP "\fB\-N\fR" 4
|
| 615 |
|
|
.IX Item "-N"
|
| 616 |
|
|
Warn when a nop after a 32\-bit multiply instruction is generated.
|
| 617 |
|
|
.PP
|
| 618 |
|
|
The following options are available when as is configured for the
|
| 619 |
|
|
Intel 80960 processor.
|
| 620 |
|
|
.IP "\fB\-ACA | \-ACA_A | \-ACB | \-ACC | \-AKA | \-AKB | \-AKC | \-AMC\fR" 4
|
| 621 |
|
|
.IX Item "-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC"
|
| 622 |
|
|
Specify which variant of the 960 architecture is the target.
|
| 623 |
|
|
.IP "\fB\-b\fR" 4
|
| 624 |
|
|
.IX Item "-b"
|
| 625 |
|
|
Add code to collect statistics about branches taken.
|
| 626 |
|
|
.IP "\fB\-no\-relax\fR" 4
|
| 627 |
|
|
.IX Item "-no-relax"
|
| 628 |
|
|
Do not alter compare-and-branch instructions for long displacements;
|
| 629 |
|
|
error if necessary.
|
| 630 |
|
|
.PP
|
| 631 |
|
|
The following options are available when as is configured for the
|
| 632 |
|
|
Ubicom \s-1IP2K\s0 series.
|
| 633 |
|
|
.IP "\fB\-mip2022ext\fR" 4
|
| 634 |
|
|
.IX Item "-mip2022ext"
|
| 635 |
|
|
Specifies that the extended \s-1IP2022\s0 instructions are allowed.
|
| 636 |
|
|
.IP "\fB\-mip2022\fR" 4
|
| 637 |
|
|
.IX Item "-mip2022"
|
| 638 |
|
|
Restores the default behaviour, which restricts the permitted instructions to
|
| 639 |
|
|
just the basic \s-1IP2022\s0 ones.
|
| 640 |
|
|
.PP
|
| 641 |
|
|
The following options are available when as is configured for the
|
| 642 |
|
|
Renesas M32C and M16C processors.
|
| 643 |
|
|
.IP "\fB\-m32c\fR" 4
|
| 644 |
|
|
.IX Item "-m32c"
|
| 645 |
|
|
Assemble M32C instructions.
|
| 646 |
|
|
.IP "\fB\-m16c\fR" 4
|
| 647 |
|
|
.IX Item "-m16c"
|
| 648 |
|
|
Assemble M16C instructions (the default).
|
| 649 |
|
|
.PP
|
| 650 |
|
|
The following options are available when as is configured for the
|
| 651 |
|
|
Renesas M32R (formerly Mitsubishi M32R) series.
|
| 652 |
|
|
.IP "\fB\-\-m32rx\fR" 4
|
| 653 |
|
|
.IX Item "--m32rx"
|
| 654 |
|
|
Specify which processor in the M32R family is the target. The default
|
| 655 |
|
|
is normally the M32R, but this option changes it to the M32RX.
|
| 656 |
|
|
.IP "\fB\-\-warn\-explicit\-parallel\-conflicts or \-\-Wp\fR" 4
|
| 657 |
|
|
.IX Item "--warn-explicit-parallel-conflicts or --Wp"
|
| 658 |
|
|
Produce warning messages when questionable parallel constructs are
|
| 659 |
|
|
encountered.
|
| 660 |
|
|
.IP "\fB\-\-no\-warn\-explicit\-parallel\-conflicts or \-\-Wnp\fR" 4
|
| 661 |
|
|
.IX Item "--no-warn-explicit-parallel-conflicts or --Wnp"
|
| 662 |
|
|
Do not produce warning messages when questionable parallel constructs are
|
| 663 |
|
|
encountered.
|
| 664 |
|
|
.PP
|
| 665 |
|
|
The following options are available when as is configured for the
|
| 666 |
|
|
Motorola 68000 series.
|
| 667 |
|
|
.IP "\fB\-l\fR" 4
|
| 668 |
|
|
.IX Item "-l"
|
| 669 |
|
|
Shorten references to undefined symbols, to one word instead of two.
|
| 670 |
|
|
.IP "\fB\-m68000 | \-m68008 | \-m68010 | \-m68020 | \-m68030\fR" 4
|
| 671 |
|
|
.IX Item "-m68000 | -m68008 | -m68010 | -m68020 | -m68030"
|
| 672 |
|
|
.PD 0
|
| 673 |
|
|
.IP "\fB| \-m68040 | \-m68060 | \-m68302 | \-m68331 | \-m68332\fR" 4
|
| 674 |
|
|
.IX Item "| -m68040 | -m68060 | -m68302 | -m68331 | -m68332"
|
| 675 |
|
|
.IP "\fB| \-m68333 | \-m68340 | \-mcpu32 | \-m5200\fR" 4
|
| 676 |
|
|
.IX Item "| -m68333 | -m68340 | -mcpu32 | -m5200"
|
| 677 |
|
|
.PD
|
| 678 |
|
|
Specify what processor in the 68000 family is the target. The default
|
| 679 |
|
|
is normally the 68020, but this can be changed at configuration time.
|
| 680 |
|
|
.IP "\fB\-m68881 | \-m68882 | \-mno\-68881 | \-mno\-68882\fR" 4
|
| 681 |
|
|
.IX Item "-m68881 | -m68882 | -mno-68881 | -mno-68882"
|
| 682 |
|
|
The target machine does (or does not) have a floating-point coprocessor.
|
| 683 |
|
|
The default is to assume a coprocessor for 68020, 68030, and cpu32. Although
|
| 684 |
|
|
the basic 68000 is not compatible with the 68881, a combination of the
|
| 685 |
|
|
two can be specified, since it's possible to do emulation of the
|
| 686 |
|
|
coprocessor instructions with the main processor.
|
| 687 |
|
|
.IP "\fB\-m68851 | \-mno\-68851\fR" 4
|
| 688 |
|
|
.IX Item "-m68851 | -mno-68851"
|
| 689 |
|
|
The target machine does (or does not) have a memory-management
|
| 690 |
|
|
unit coprocessor. The default is to assume an \s-1MMU\s0 for 68020 and up.
|
| 691 |
|
|
.PP
|
| 692 |
|
|
For details about the \s-1PDP\-11\s0 machine dependent features options,
|
| 693 |
|
|
see \fBPDP\-11\-Options\fR.
|
| 694 |
|
|
.IP "\fB\-mpic | \-mno\-pic\fR" 4
|
| 695 |
|
|
.IX Item "-mpic | -mno-pic"
|
| 696 |
|
|
Generate position-independent (or position\-dependent) code. The
|
| 697 |
|
|
default is \fB\-mpic\fR.
|
| 698 |
|
|
.IP "\fB\-mall\fR" 4
|
| 699 |
|
|
.IX Item "-mall"
|
| 700 |
|
|
.PD 0
|
| 701 |
|
|
.IP "\fB\-mall\-extensions\fR" 4
|
| 702 |
|
|
.IX Item "-mall-extensions"
|
| 703 |
|
|
.PD
|
| 704 |
|
|
Enable all instruction set extensions. This is the default.
|
| 705 |
|
|
.IP "\fB\-mno\-extensions\fR" 4
|
| 706 |
|
|
.IX Item "-mno-extensions"
|
| 707 |
|
|
Disable all instruction set extensions.
|
| 708 |
|
|
.IP "\fB\-m\fR\fIextension\fR \fB| \-mno\-\fR\fIextension\fR" 4
|
| 709 |
|
|
.IX Item "-mextension | -mno-extension"
|
| 710 |
|
|
Enable (or disable) a particular instruction set extension.
|
| 711 |
|
|
.IP "\fB\-m\fR\fIcpu\fR" 4
|
| 712 |
|
|
.IX Item "-mcpu"
|
| 713 |
|
|
Enable the instruction set extensions supported by a particular \s-1CPU\s0, and
|
| 714 |
|
|
disable all other extensions.
|
| 715 |
|
|
.IP "\fB\-m\fR\fImachine\fR" 4
|
| 716 |
|
|
.IX Item "-mmachine"
|
| 717 |
|
|
Enable the instruction set extensions supported by a particular machine
|
| 718 |
|
|
model, and disable all other extensions.
|
| 719 |
|
|
.PP
|
| 720 |
|
|
The following options are available when as is configured for
|
| 721 |
|
|
a picoJava processor.
|
| 722 |
|
|
.IP "\fB\-mb\fR" 4
|
| 723 |
|
|
.IX Item "-mb"
|
| 724 |
|
|
Generate \*(L"big endian\*(R" format output.
|
| 725 |
|
|
.IP "\fB\-ml\fR" 4
|
| 726 |
|
|
.IX Item "-ml"
|
| 727 |
|
|
Generate \*(L"little endian\*(R" format output.
|
| 728 |
|
|
.PP
|
| 729 |
|
|
The following options are available when as is configured for the
|
| 730 |
|
|
Motorola 68HC11 or 68HC12 series.
|
| 731 |
|
|
.IP "\fB\-m68hc11 | \-m68hc12 | \-m68hcs12\fR" 4
|
| 732 |
|
|
.IX Item "-m68hc11 | -m68hc12 | -m68hcs12"
|
| 733 |
|
|
Specify what processor is the target. The default is
|
| 734 |
|
|
defined by the configuration option when building the assembler.
|
| 735 |
|
|
.IP "\fB\-mshort\fR" 4
|
| 736 |
|
|
.IX Item "-mshort"
|
| 737 |
|
|
Specify to use the 16\-bit integer \s-1ABI\s0.
|
| 738 |
|
|
.IP "\fB\-mlong\fR" 4
|
| 739 |
|
|
.IX Item "-mlong"
|
| 740 |
|
|
Specify to use the 32\-bit integer \s-1ABI\s0.
|
| 741 |
|
|
.IP "\fB\-mshort\-double\fR" 4
|
| 742 |
|
|
.IX Item "-mshort-double"
|
| 743 |
|
|
Specify to use the 32\-bit double \s-1ABI\s0.
|
| 744 |
|
|
.IP "\fB\-mlong\-double\fR" 4
|
| 745 |
|
|
.IX Item "-mlong-double"
|
| 746 |
|
|
Specify to use the 64\-bit double \s-1ABI\s0.
|
| 747 |
|
|
.IP "\fB\-\-force\-long\-branches\fR" 4
|
| 748 |
|
|
.IX Item "--force-long-branches"
|
| 749 |
|
|
Relative branches are turned into absolute ones. This concerns
|
| 750 |
|
|
conditional branches, unconditional branches and branches to a
|
| 751 |
|
|
sub routine.
|
| 752 |
|
|
.IP "\fB\-S | \-\-short\-branches\fR" 4
|
| 753 |
|
|
.IX Item "-S | --short-branches"
|
| 754 |
|
|
Do not turn relative branches into absolute ones
|
| 755 |
|
|
when the offset is out of range.
|
| 756 |
|
|
.IP "\fB\-\-strict\-direct\-mode\fR" 4
|
| 757 |
|
|
.IX Item "--strict-direct-mode"
|
| 758 |
|
|
Do not turn the direct addressing mode into extended addressing mode
|
| 759 |
|
|
when the instruction does not support direct addressing mode.
|
| 760 |
|
|
.IP "\fB\-\-print\-insn\-syntax\fR" 4
|
| 761 |
|
|
.IX Item "--print-insn-syntax"
|
| 762 |
|
|
Print the syntax of instruction in case of error.
|
| 763 |
|
|
.IP "\fB\-\-print\-opcodes\fR" 4
|
| 764 |
|
|
.IX Item "--print-opcodes"
|
| 765 |
|
|
print the list of instructions with syntax and then exit.
|
| 766 |
|
|
.IP "\fB\-\-generate\-example\fR" 4
|
| 767 |
|
|
.IX Item "--generate-example"
|
| 768 |
|
|
print an example of instruction for each possible instruction and then exit.
|
| 769 |
|
|
This option is only useful for testing \fBas\fR.
|
| 770 |
|
|
.PP
|
| 771 |
|
|
The following options are available when \fBas\fR is configured
|
| 772 |
|
|
for the \s-1SPARC\s0 architecture:
|
| 773 |
|
|
.IP "\fB\-Av6 | \-Av7 | \-Av8 | \-Asparclet | \-Asparclite\fR" 4
|
| 774 |
|
|
.IX Item "-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite"
|
| 775 |
|
|
.PD 0
|
| 776 |
|
|
.IP "\fB\-Av8plus | \-Av8plusa | \-Av9 | \-Av9a\fR" 4
|
| 777 |
|
|
.IX Item "-Av8plus | -Av8plusa | -Av9 | -Av9a"
|
| 778 |
|
|
.PD
|
| 779 |
|
|
Explicitly select a variant of the \s-1SPARC\s0 architecture.
|
| 780 |
|
|
.Sp
|
| 781 |
|
|
\&\fB\-Av8plus\fR and \fB\-Av8plusa\fR select a 32 bit environment.
|
| 782 |
|
|
\&\fB\-Av9\fR and \fB\-Av9a\fR select a 64 bit environment.
|
| 783 |
|
|
.Sp
|
| 784 |
|
|
\&\fB\-Av8plusa\fR and \fB\-Av9a\fR enable the \s-1SPARC\s0 V9 instruction set with
|
| 785 |
|
|
UltraSPARC extensions.
|
| 786 |
|
|
.IP "\fB\-xarch=v8plus | \-xarch=v8plusa\fR" 4
|
| 787 |
|
|
.IX Item "-xarch=v8plus | -xarch=v8plusa"
|
| 788 |
|
|
For compatibility with the Solaris v9 assembler. These options are
|
| 789 |
|
|
equivalent to \-Av8plus and \-Av8plusa, respectively.
|
| 790 |
|
|
.IP "\fB\-bump\fR" 4
|
| 791 |
|
|
.IX Item "-bump"
|
| 792 |
|
|
Warn when the assembler switches to another architecture.
|
| 793 |
|
|
.PP
|
| 794 |
|
|
The following options are available when as is configured for the 'c54x
|
| 795 |
|
|
architecture.
|
| 796 |
|
|
.IP "\fB\-mfar\-mode\fR" 4
|
| 797 |
|
|
.IX Item "-mfar-mode"
|
| 798 |
|
|
Enable extended addressing mode. All addresses and relocations will assume
|
| 799 |
|
|
extended addressing (usually 23 bits).
|
| 800 |
|
|
.IP "\fB\-mcpu=\fR\fI\s-1CPU_VERSION\s0\fR" 4
|
| 801 |
|
|
.IX Item "-mcpu=CPU_VERSION"
|
| 802 |
|
|
Sets the \s-1CPU\s0 version being compiled for.
|
| 803 |
|
|
.IP "\fB\-merrors\-to\-file\fR \fI\s-1FILENAME\s0\fR" 4
|
| 804 |
|
|
.IX Item "-merrors-to-file FILENAME"
|
| 805 |
|
|
Redirect error output to a file, for broken systems which don't support such
|
| 806 |
|
|
behaviour in the shell.
|
| 807 |
|
|
.PP
|
| 808 |
|
|
The following options are available when as is configured for
|
| 809 |
|
|
a \s-1MIPS\s0 processor.
|
| 810 |
|
|
.IP "\fB\-G\fR \fInum\fR" 4
|
| 811 |
|
|
.IX Item "-G num"
|
| 812 |
|
|
This option sets the largest size of an object that can be referenced
|
| 813 |
|
|
implicitly with the \f(CW\*(C`gp\*(C'\fR register. It is only accepted for targets that
|
| 814 |
|
|
use \s-1ECOFF\s0 format, such as a DECstation running Ultrix. The default value is 8.
|
| 815 |
|
|
.IP "\fB\-EB\fR" 4
|
| 816 |
|
|
.IX Item "-EB"
|
| 817 |
|
|
Generate \*(L"big endian\*(R" format output.
|
| 818 |
|
|
.IP "\fB\-EL\fR" 4
|
| 819 |
|
|
.IX Item "-EL"
|
| 820 |
|
|
Generate \*(L"little endian\*(R" format output.
|
| 821 |
|
|
.IP "\fB\-mips1\fR" 4
|
| 822 |
|
|
.IX Item "-mips1"
|
| 823 |
|
|
.PD 0
|
| 824 |
|
|
.IP "\fB\-mips2\fR" 4
|
| 825 |
|
|
.IX Item "-mips2"
|
| 826 |
|
|
.IP "\fB\-mips3\fR" 4
|
| 827 |
|
|
.IX Item "-mips3"
|
| 828 |
|
|
.IP "\fB\-mips4\fR" 4
|
| 829 |
|
|
.IX Item "-mips4"
|
| 830 |
|
|
.IP "\fB\-mips5\fR" 4
|
| 831 |
|
|
.IX Item "-mips5"
|
| 832 |
|
|
.IP "\fB\-mips32\fR" 4
|
| 833 |
|
|
.IX Item "-mips32"
|
| 834 |
|
|
.IP "\fB\-mips32r2\fR" 4
|
| 835 |
|
|
.IX Item "-mips32r2"
|
| 836 |
|
|
.IP "\fB\-mips64\fR" 4
|
| 837 |
|
|
.IX Item "-mips64"
|
| 838 |
|
|
.IP "\fB\-mips64r2\fR" 4
|
| 839 |
|
|
.IX Item "-mips64r2"
|
| 840 |
|
|
.PD
|
| 841 |
|
|
Generate code for a particular \s-1MIPS\s0 Instruction Set Architecture level.
|
| 842 |
|
|
\&\fB\-mips1\fR is an alias for \fB\-march=r3000\fR, \fB\-mips2\fR is an
|
| 843 |
|
|
alias for \fB\-march=r6000\fR, \fB\-mips3\fR is an alias for
|
| 844 |
|
|
\&\fB\-march=r4000\fR and \fB\-mips4\fR is an alias for \fB\-march=r8000\fR.
|
| 845 |
|
|
\&\fB\-mips5\fR, \fB\-mips32\fR, \fB\-mips32r2\fR, \fB\-mips64\fR, and
|
| 846 |
|
|
\&\fB\-mips64r2\fR
|
| 847 |
|
|
correspond to generic
|
| 848 |
|
|
\&\fB\s-1MIPS\s0 V\fR, \fB\s-1MIPS32\s0\fR, \fB\s-1MIPS32\s0 Release 2\fR, \fB\s-1MIPS64\s0\fR,
|
| 849 |
|
|
and \fB\s-1MIPS64\s0 Release 2\fR
|
| 850 |
|
|
\&\s-1ISA\s0 processors, respectively.
|
| 851 |
|
|
.IP "\fB\-march=\fR\fI\s-1CPU\s0\fR" 4
|
| 852 |
|
|
.IX Item "-march=CPU"
|
| 853 |
|
|
Generate code for a particular \s-1MIPS\s0 cpu.
|
| 854 |
|
|
.IP "\fB\-mtune=\fR\fIcpu\fR" 4
|
| 855 |
|
|
.IX Item "-mtune=cpu"
|
| 856 |
|
|
Schedule and tune for a particular \s-1MIPS\s0 cpu.
|
| 857 |
|
|
.IP "\fB\-mfix7000\fR" 4
|
| 858 |
|
|
.IX Item "-mfix7000"
|
| 859 |
|
|
.PD 0
|
| 860 |
|
|
.IP "\fB\-mno\-fix7000\fR" 4
|
| 861 |
|
|
.IX Item "-mno-fix7000"
|
| 862 |
|
|
.PD
|
| 863 |
|
|
Cause nops to be inserted if the read of the destination register
|
| 864 |
|
|
of an mfhi or mflo instruction occurs in the following two instructions.
|
| 865 |
|
|
.IP "\fB\-mdebug\fR" 4
|
| 866 |
|
|
.IX Item "-mdebug"
|
| 867 |
|
|
.PD 0
|
| 868 |
|
|
.IP "\fB\-no\-mdebug\fR" 4
|
| 869 |
|
|
.IX Item "-no-mdebug"
|
| 870 |
|
|
.PD
|
| 871 |
|
|
Cause stabs-style debugging output to go into an ECOFF-style .mdebug
|
| 872 |
|
|
section instead of the standard \s-1ELF\s0 .stabs sections.
|
| 873 |
|
|
.IP "\fB\-mpdr\fR" 4
|
| 874 |
|
|
.IX Item "-mpdr"
|
| 875 |
|
|
.PD 0
|
| 876 |
|
|
.IP "\fB\-mno\-pdr\fR" 4
|
| 877 |
|
|
.IX Item "-mno-pdr"
|
| 878 |
|
|
.PD
|
| 879 |
|
|
Control generation of \f(CW\*(C`.pdr\*(C'\fR sections.
|
| 880 |
|
|
.IP "\fB\-mgp32\fR" 4
|
| 881 |
|
|
.IX Item "-mgp32"
|
| 882 |
|
|
.PD 0
|
| 883 |
|
|
.IP "\fB\-mfp32\fR" 4
|
| 884 |
|
|
.IX Item "-mfp32"
|
| 885 |
|
|
.PD
|
| 886 |
|
|
The register sizes are normally inferred from the \s-1ISA\s0 and \s-1ABI\s0, but these
|
| 887 |
|
|
flags force a certain group of registers to be treated as 32 bits wide at
|
| 888 |
|
|
all times. \fB\-mgp32\fR controls the size of general-purpose registers
|
| 889 |
|
|
and \fB\-mfp32\fR controls the size of floating-point registers.
|
| 890 |
|
|
.IP "\fB\-mips16\fR" 4
|
| 891 |
|
|
.IX Item "-mips16"
|
| 892 |
|
|
.PD 0
|
| 893 |
|
|
.IP "\fB\-no\-mips16\fR" 4
|
| 894 |
|
|
.IX Item "-no-mips16"
|
| 895 |
|
|
.PD
|
| 896 |
|
|
Generate code for the \s-1MIPS\s0 16 processor. This is equivalent to putting
|
| 897 |
|
|
\&\f(CW\*(C`.set mips16\*(C'\fR at the start of the assembly file. \fB\-no\-mips16\fR
|
| 898 |
|
|
turns off this option.
|
| 899 |
|
|
.IP "\fB\-msmartmips\fR" 4
|
| 900 |
|
|
.IX Item "-msmartmips"
|
| 901 |
|
|
.PD 0
|
| 902 |
|
|
.IP "\fB\-mno\-smartmips\fR" 4
|
| 903 |
|
|
.IX Item "-mno-smartmips"
|
| 904 |
|
|
.PD
|
| 905 |
|
|
Enables the SmartMIPS extension to the \s-1MIPS32\s0 instruction set. This is
|
| 906 |
|
|
equivalent to putting \f(CW\*(C`.set smartmips\*(C'\fR at the start of the assembly file.
|
| 907 |
|
|
\&\fB\-mno\-smartmips\fR turns off this option.
|
| 908 |
|
|
.IP "\fB\-mips3d\fR" 4
|
| 909 |
|
|
.IX Item "-mips3d"
|
| 910 |
|
|
.PD 0
|
| 911 |
|
|
.IP "\fB\-no\-mips3d\fR" 4
|
| 912 |
|
|
.IX Item "-no-mips3d"
|
| 913 |
|
|
.PD
|
| 914 |
|
|
Generate code for the \s-1MIPS\-3D\s0 Application Specific Extension.
|
| 915 |
|
|
This tells the assembler to accept \s-1MIPS\-3D\s0 instructions.
|
| 916 |
|
|
\&\fB\-no\-mips3d\fR turns off this option.
|
| 917 |
|
|
.IP "\fB\-mdmx\fR" 4
|
| 918 |
|
|
.IX Item "-mdmx"
|
| 919 |
|
|
.PD 0
|
| 920 |
|
|
.IP "\fB\-no\-mdmx\fR" 4
|
| 921 |
|
|
.IX Item "-no-mdmx"
|
| 922 |
|
|
.PD
|
| 923 |
|
|
Generate code for the \s-1MDMX\s0 Application Specific Extension.
|
| 924 |
|
|
This tells the assembler to accept \s-1MDMX\s0 instructions.
|
| 925 |
|
|
\&\fB\-no\-mdmx\fR turns off this option.
|
| 926 |
|
|
.IP "\fB\-mdsp\fR" 4
|
| 927 |
|
|
.IX Item "-mdsp"
|
| 928 |
|
|
.PD 0
|
| 929 |
|
|
.IP "\fB\-mno\-dsp\fR" 4
|
| 930 |
|
|
.IX Item "-mno-dsp"
|
| 931 |
|
|
.PD
|
| 932 |
|
|
Generate code for the \s-1DSP\s0 Release 1 Application Specific Extension.
|
| 933 |
|
|
This tells the assembler to accept \s-1DSP\s0 Release 1 instructions.
|
| 934 |
|
|
\&\fB\-mno\-dsp\fR turns off this option.
|
| 935 |
|
|
.IP "\fB\-mdspr2\fR" 4
|
| 936 |
|
|
.IX Item "-mdspr2"
|
| 937 |
|
|
.PD 0
|
| 938 |
|
|
.IP "\fB\-mno\-dspr2\fR" 4
|
| 939 |
|
|
.IX Item "-mno-dspr2"
|
| 940 |
|
|
.PD
|
| 941 |
|
|
Generate code for the \s-1DSP\s0 Release 2 Application Specific Extension.
|
| 942 |
|
|
This option implies \-mdsp.
|
| 943 |
|
|
This tells the assembler to accept \s-1DSP\s0 Release 2 instructions.
|
| 944 |
|
|
\&\fB\-mno\-dspr2\fR turns off this option.
|
| 945 |
|
|
.IP "\fB\-mmt\fR" 4
|
| 946 |
|
|
.IX Item "-mmt"
|
| 947 |
|
|
.PD 0
|
| 948 |
|
|
.IP "\fB\-mno\-mt\fR" 4
|
| 949 |
|
|
.IX Item "-mno-mt"
|
| 950 |
|
|
.PD
|
| 951 |
|
|
Generate code for the \s-1MT\s0 Application Specific Extension.
|
| 952 |
|
|
This tells the assembler to accept \s-1MT\s0 instructions.
|
| 953 |
|
|
\&\fB\-mno\-mt\fR turns off this option.
|
| 954 |
|
|
.IP "\fB\-\-construct\-floats\fR" 4
|
| 955 |
|
|
.IX Item "--construct-floats"
|
| 956 |
|
|
.PD 0
|
| 957 |
|
|
.IP "\fB\-\-no\-construct\-floats\fR" 4
|
| 958 |
|
|
.IX Item "--no-construct-floats"
|
| 959 |
|
|
.PD
|
| 960 |
|
|
The \fB\-\-no\-construct\-floats\fR option disables the construction of
|
| 961 |
|
|
double width floating point constants by loading the two halves of the
|
| 962 |
|
|
value into the two single width floating point registers that make up
|
| 963 |
|
|
the double width register. By default \fB\-\-construct\-floats\fR is
|
| 964 |
|
|
selected, allowing construction of these floating point constants.
|
| 965 |
|
|
.IP "\fB\-\-emulation=\fR\fIname\fR" 4
|
| 966 |
|
|
.IX Item "--emulation=name"
|
| 967 |
|
|
This option causes \fBas\fR to emulate \fBas\fR configured
|
| 968 |
|
|
for some other target, in all respects, including output format (choosing
|
| 969 |
|
|
between \s-1ELF\s0 and \s-1ECOFF\s0 only), handling of pseudo-opcodes which may generate
|
| 970 |
|
|
debugging information or store symbol table information, and default
|
| 971 |
|
|
endianness. The available configuration names are: \fBmipsecoff\fR,
|
| 972 |
|
|
\&\fBmipself\fR, \fBmipslecoff\fR, \fBmipsbecoff\fR, \fBmipslelf\fR,
|
| 973 |
|
|
\&\fBmipsbelf\fR. The first two do not alter the default endianness from that
|
| 974 |
|
|
of the primary target for which the assembler was configured; the others change
|
| 975 |
|
|
the default to little\- or big-endian as indicated by the \fBb\fR or \fBl\fR
|
| 976 |
|
|
in the name. Using \fB\-EB\fR or \fB\-EL\fR will override the endianness
|
| 977 |
|
|
selection in any case.
|
| 978 |
|
|
.Sp
|
| 979 |
|
|
This option is currently supported only when the primary target
|
| 980 |
|
|
\&\fBas\fR is configured for is a \s-1MIPS\s0 \s-1ELF\s0 or \s-1ECOFF\s0 target.
|
| 981 |
|
|
Furthermore, the primary target or others specified with
|
| 982 |
|
|
\&\fB\-\-enable\-targets=...\fR at configuration time must include support for
|
| 983 |
|
|
the other format, if both are to be available. For example, the Irix 5
|
| 984 |
|
|
configuration includes support for both.
|
| 985 |
|
|
.Sp
|
| 986 |
|
|
Eventually, this option will support more configurations, with more
|
| 987 |
|
|
fine-grained control over the assembler's behavior, and will be supported for
|
| 988 |
|
|
more processors.
|
| 989 |
|
|
.IP "\fB\-nocpp\fR" 4
|
| 990 |
|
|
.IX Item "-nocpp"
|
| 991 |
|
|
\&\fBas\fR ignores this option. It is accepted for compatibility with
|
| 992 |
|
|
the native tools.
|
| 993 |
|
|
.IP "\fB\-\-trap\fR" 4
|
| 994 |
|
|
.IX Item "--trap"
|
| 995 |
|
|
.PD 0
|
| 996 |
|
|
.IP "\fB\-\-no\-trap\fR" 4
|
| 997 |
|
|
.IX Item "--no-trap"
|
| 998 |
|
|
.IP "\fB\-\-break\fR" 4
|
| 999 |
|
|
.IX Item "--break"
|
| 1000 |
|
|
.IP "\fB\-\-no\-break\fR" 4
|
| 1001 |
|
|
.IX Item "--no-break"
|
| 1002 |
|
|
.PD
|
| 1003 |
|
|
Control how to deal with multiplication overflow and division by zero.
|
| 1004 |
|
|
\&\fB\-\-trap\fR or \fB\-\-no\-break\fR (which are synonyms) take a trap exception
|
| 1005 |
|
|
(and only work for Instruction Set Architecture level 2 and higher);
|
| 1006 |
|
|
\&\fB\-\-break\fR or \fB\-\-no\-trap\fR (also synonyms, and the default) take a
|
| 1007 |
|
|
break exception.
|
| 1008 |
|
|
.IP "\fB\-n\fR" 4
|
| 1009 |
|
|
.IX Item "-n"
|
| 1010 |
|
|
When this option is used, \fBas\fR will issue a warning every
|
| 1011 |
|
|
time it generates a nop instruction from a macro.
|
| 1012 |
|
|
.PP
|
| 1013 |
|
|
The following options are available when as is configured for
|
| 1014 |
|
|
an MCore processor.
|
| 1015 |
|
|
.IP "\fB\-jsri2bsr\fR" 4
|
| 1016 |
|
|
.IX Item "-jsri2bsr"
|
| 1017 |
|
|
.PD 0
|
| 1018 |
|
|
.IP "\fB\-nojsri2bsr\fR" 4
|
| 1019 |
|
|
.IX Item "-nojsri2bsr"
|
| 1020 |
|
|
.PD
|
| 1021 |
|
|
Enable or disable the \s-1JSRI\s0 to \s-1BSR\s0 transformation. By default this is enabled.
|
| 1022 |
|
|
The command line option \fB\-nojsri2bsr\fR can be used to disable it.
|
| 1023 |
|
|
.IP "\fB\-sifilter\fR" 4
|
| 1024 |
|
|
.IX Item "-sifilter"
|
| 1025 |
|
|
.PD 0
|
| 1026 |
|
|
.IP "\fB\-nosifilter\fR" 4
|
| 1027 |
|
|
.IX Item "-nosifilter"
|
| 1028 |
|
|
.PD
|
| 1029 |
|
|
Enable or disable the silicon filter behaviour. By default this is disabled.
|
| 1030 |
|
|
The default can be overridden by the \fB\-sifilter\fR command line option.
|
| 1031 |
|
|
.IP "\fB\-relax\fR" 4
|
| 1032 |
|
|
.IX Item "-relax"
|
| 1033 |
|
|
Alter jump instructions for long displacements.
|
| 1034 |
|
|
.IP "\fB\-mcpu=[210|340]\fR" 4
|
| 1035 |
|
|
.IX Item "-mcpu=[210|340]"
|
| 1036 |
|
|
Select the cpu type on the target hardware. This controls which instructions
|
| 1037 |
|
|
can be assembled.
|
| 1038 |
|
|
.IP "\fB\-EB\fR" 4
|
| 1039 |
|
|
.IX Item "-EB"
|
| 1040 |
|
|
Assemble for a big endian target.
|
| 1041 |
|
|
.IP "\fB\-EL\fR" 4
|
| 1042 |
|
|
.IX Item "-EL"
|
| 1043 |
|
|
Assemble for a little endian target.
|
| 1044 |
|
|
.PP
|
| 1045 |
|
|
See the info pages for documentation of the MMIX-specific options.
|
| 1046 |
|
|
.PP
|
| 1047 |
|
|
The following options are available when as is configured for
|
| 1048 |
|
|
an Xtensa processor.
|
| 1049 |
|
|
.IP "\fB\-\-text\-section\-literals | \-\-no\-text\-section\-literals\fR" 4
|
| 1050 |
|
|
.IX Item "--text-section-literals | --no-text-section-literals"
|
| 1051 |
|
|
With \fB\-\-text\-section\-literals\fR, literal pools are interspersed
|
| 1052 |
|
|
in the text section. The default is
|
| 1053 |
|
|
\&\fB\-\-no\-text\-section\-literals\fR, which places literals in a
|
| 1054 |
|
|
separate section in the output file. These options only affect literals
|
| 1055 |
|
|
referenced via PC-relative \f(CW\*(C`L32R\*(C'\fR instructions; literals for
|
| 1056 |
|
|
absolute mode \f(CW\*(C`L32R\*(C'\fR instructions are handled separately.
|
| 1057 |
|
|
.IP "\fB\-\-absolute\-literals | \-\-no\-absolute\-literals\fR" 4
|
| 1058 |
|
|
.IX Item "--absolute-literals | --no-absolute-literals"
|
| 1059 |
|
|
Indicate to the assembler whether \f(CW\*(C`L32R\*(C'\fR instructions use absolute
|
| 1060 |
|
|
or PC-relative addressing. The default is to assume absolute addressing
|
| 1061 |
|
|
if the Xtensa processor includes the absolute \f(CW\*(C`L32R\*(C'\fR addressing
|
| 1062 |
|
|
option. Otherwise, only the PC-relative \f(CW\*(C`L32R\*(C'\fR mode can be used.
|
| 1063 |
|
|
.IP "\fB\-\-target\-align | \-\-no\-target\-align\fR" 4
|
| 1064 |
|
|
.IX Item "--target-align | --no-target-align"
|
| 1065 |
|
|
Enable or disable automatic alignment to reduce branch penalties at the
|
| 1066 |
|
|
expense of some code density. The default is \fB\-\-target\-align\fR.
|
| 1067 |
|
|
.IP "\fB\-\-longcalls | \-\-no\-longcalls\fR" 4
|
| 1068 |
|
|
.IX Item "--longcalls | --no-longcalls"
|
| 1069 |
|
|
Enable or disable transformation of call instructions to allow calls
|
| 1070 |
|
|
across a greater range of addresses. The default is
|
| 1071 |
|
|
\&\fB\-\-no\-longcalls\fR.
|
| 1072 |
|
|
.IP "\fB\-\-transform | \-\-no\-transform\fR" 4
|
| 1073 |
|
|
.IX Item "--transform | --no-transform"
|
| 1074 |
|
|
Enable or disable all assembler transformations of Xtensa instructions.
|
| 1075 |
|
|
The default is \fB\-\-transform\fR;
|
| 1076 |
|
|
\&\fB\-\-no\-transform\fR should be used only in the rare cases when the
|
| 1077 |
|
|
instructions must be exactly as specified in the assembly source.
|
| 1078 |
|
|
.IP "\fB\-\-rename\-section\fR \fIoldname\fR\fB=\fR\fInewname\fR" 4
|
| 1079 |
|
|
.IX Item "--rename-section oldname=newname"
|
| 1080 |
|
|
When generating output sections, rename the \fIoldname\fR section to
|
| 1081 |
|
|
\&\fInewname\fR.
|
| 1082 |
|
|
.PP
|
| 1083 |
|
|
The following options are available when as is configured for
|
| 1084 |
|
|
a Z80 family processor.
|
| 1085 |
|
|
.IP "\fB\-z80\fR" 4
|
| 1086 |
|
|
.IX Item "-z80"
|
| 1087 |
|
|
Assemble for Z80 processor.
|
| 1088 |
|
|
.IP "\fB\-r800\fR" 4
|
| 1089 |
|
|
.IX Item "-r800"
|
| 1090 |
|
|
Assemble for R800 processor.
|
| 1091 |
|
|
.IP "\fB\-ignore\-undocumented\-instructions\fR" 4
|
| 1092 |
|
|
.IX Item "-ignore-undocumented-instructions"
|
| 1093 |
|
|
.PD 0
|
| 1094 |
|
|
.IP "\fB\-Wnud\fR" 4
|
| 1095 |
|
|
.IX Item "-Wnud"
|
| 1096 |
|
|
.PD
|
| 1097 |
|
|
Assemble undocumented Z80 instructions that also work on R800 without warning.
|
| 1098 |
|
|
.IP "\fB\-ignore\-unportable\-instructions\fR" 4
|
| 1099 |
|
|
.IX Item "-ignore-unportable-instructions"
|
| 1100 |
|
|
.PD 0
|
| 1101 |
|
|
.IP "\fB\-Wnup\fR" 4
|
| 1102 |
|
|
.IX Item "-Wnup"
|
| 1103 |
|
|
.PD
|
| 1104 |
|
|
Assemble all undocumented Z80 instructions without warning.
|
| 1105 |
|
|
.IP "\fB\-warn\-undocumented\-instructions\fR" 4
|
| 1106 |
|
|
.IX Item "-warn-undocumented-instructions"
|
| 1107 |
|
|
.PD 0
|
| 1108 |
|
|
.IP "\fB\-Wud\fR" 4
|
| 1109 |
|
|
.IX Item "-Wud"
|
| 1110 |
|
|
.PD
|
| 1111 |
|
|
Issue a warning for undocumented Z80 instructions that also work on R800.
|
| 1112 |
|
|
.IP "\fB\-warn\-unportable\-instructions\fR" 4
|
| 1113 |
|
|
.IX Item "-warn-unportable-instructions"
|
| 1114 |
|
|
.PD 0
|
| 1115 |
|
|
.IP "\fB\-Wup\fR" 4
|
| 1116 |
|
|
.IX Item "-Wup"
|
| 1117 |
|
|
.PD
|
| 1118 |
|
|
Issue a warning for undocumented Z80 instructions that do not work on R800.
|
| 1119 |
|
|
.IP "\fB\-forbid\-undocumented\-instructions\fR" 4
|
| 1120 |
|
|
.IX Item "-forbid-undocumented-instructions"
|
| 1121 |
|
|
.PD 0
|
| 1122 |
|
|
.IP "\fB\-Fud\fR" 4
|
| 1123 |
|
|
.IX Item "-Fud"
|
| 1124 |
|
|
.PD
|
| 1125 |
|
|
Treat all undocumented instructions as errors.
|
| 1126 |
|
|
.IP "\fB\-forbid\-unportable\-instructions\fR" 4
|
| 1127 |
|
|
.IX Item "-forbid-unportable-instructions"
|
| 1128 |
|
|
.PD 0
|
| 1129 |
|
|
.IP "\fB\-Fup\fR" 4
|
| 1130 |
|
|
.IX Item "-Fup"
|
| 1131 |
|
|
.PD
|
| 1132 |
|
|
Treat undocumented Z80 instructions that do not work on R800 as errors.
|
| 1133 |
|
|
.SH "SEE ALSO"
|
| 1134 |
|
|
.IX Header "SEE ALSO"
|
| 1135 |
|
|
\&\fIgcc\fR\|(1), \fIld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR.
|
| 1136 |
|
|
.SH "COPYRIGHT"
|
| 1137 |
|
|
.IX Header "COPYRIGHT"
|
| 1138 |
|
|
Copyright (c) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002,
|
| 1139 |
|
|
2006, 2007 Free Software Foundation, Inc.
|
| 1140 |
|
|
.PP
|
| 1141 |
|
|
Permission is granted to copy, distribute and/or modify this document
|
| 1142 |
|
|
under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.1
|
| 1143 |
|
|
or any later version published by the Free Software Foundation;
|
| 1144 |
|
|
with no Invariant Sections, with no Front-Cover Texts, and with no
|
| 1145 |
|
|
Back-Cover Texts. A copy of the license is included in the
|
| 1146 |
|
|
section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R".
|
