OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [gas/] [doc/] [c-msp430.texi] - Blame information for rev 449

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
@c Copyright 2002, 2004 Free Software Foundation, Inc.
2
@c This is part of the GAS manual.
3
@c For copying conditions, see the file as.texinfo.
4
@ifset GENERIC
5
@page
6
@node MSP430-Dependent
7
@chapter MSP 430 Dependent Features
8
@end ifset
9
@ifclear GENERIC
10
@node Machine Dependencies
11
@chapter MSP 430 Dependent Features
12
@end ifclear
13
 
14
@cindex MSP 430 support
15
@cindex 430 support
16
@menu
17
* MSP430 Options::              Options
18
* MSP430 Syntax::               Syntax
19
* MSP430 Floating Point::       Floating Point
20
* MSP430 Directives::           MSP 430 Machine Directives
21
* MSP430 Opcodes::              Opcodes
22
* MSP430 Profiling Capability:: Profiling Capability
23
@end menu
24
 
25
@node MSP430 Options
26
@section Options
27
@cindex MSP 430 options (none)
28
@cindex options for MSP430 (none)
29
@table @code
30
 
31
@item -m
32
select the mpu arch. Currently has no effect.
33
@item -mP
34
enables polymorph instructions handler.
35
 
36
@item -mQ
37
enables relaxation at assembly time. DANGEROUS!
38
 
39
@end table
40
 
41
@node MSP430 Syntax
42
@section Syntax
43
@menu
44
* MSP430-Macros::               Macros
45
* MSP430-Chars::                Special Characters
46
* MSP430-Regs::                 Register Names
47
* MSP430-Ext::                  Assembler Extensions
48
@end menu
49
 
50
@node MSP430-Macros
51
@subsection Macros
52
 
53
@cindex Macros, MSP 430
54
@cindex MSP 430 macros
55
The macro syntax used on the MSP 430 is like that described in the MSP
56
430 Family Assembler Specification.  Normal @code{@value{AS}}
57
macros should still work.
58
 
59
Additional built-in macros are:
60
 
61
@table @code
62
 
63
@item llo(exp)
64
Extracts least significant word from 32-bit expression 'exp'.
65
 
66
@item lhi(exp)
67
Extracts most significant word from 32-bit expression 'exp'.
68
 
69
@item hlo(exp)
70
Extracts 3rd word from 64-bit expression 'exp'.
71
 
72
@item   hhi(exp)
73
Extracts 4rd word from 64-bit expression 'exp'.
74
 
75
@end table
76
 
77
They normally being used as an immediate source operand.
78
@smallexample
79
    mov #llo(1), r10    ;       == mov  #1, r10
80
    mov #lhi(1), r10    ;       == mov  #0, r10
81
@end smallexample
82
 
83
@node MSP430-Chars
84
@subsection Special Characters
85
 
86
@cindex line comment character, MSP 430
87
@cindex MSP 430 line comment character
88
@samp{;} is the line comment character.
89
 
90
@cindex identifiers, MSP 430
91
@cindex MSP 430 identifiers
92
The character @samp{$} in jump instructions indicates current location and
93
implemented only for TI syntax compatibility.
94
 
95
@node MSP430-Regs
96
@subsection Register Names
97
 
98
@cindex MSP 430 register names
99
@cindex register names, MSP 430
100
General-purpose registers are represented by predefined symbols of the
101
form @samp{r@var{N}} (for global registers), where @var{N} represents
102
a number between @code{0} and @code{15}.  The leading
103
letters may be in either upper or lower case; for example, @samp{r13}
104
and @samp{R7} are both valid register names.
105
 
106
@cindex special purpose registers, MSP 430
107
Register names @samp{PC}, @samp{SP} and @samp{SR} cannot be used as register names
108
and will be treated as variables. Use @samp{r0}, @samp{r1}, and @samp{r2} instead.
109
 
110
 
111
@node MSP430-Ext
112
@subsection Assembler Extensions
113
@cindex MSP430 Assembler Extensions
114
 
115
@table @code
116
 
117
@item @@rN
118
As destination operand being treated as @samp{0(rn)}
119
 
120
@item 0(rN)
121
As source operand being treated as @samp{@@rn}
122
 
123
@item jCOND +N
124
Skips next N bytes followed by jump instruction and equivalent to
125
@samp{jCOND $+N+2}
126
 
127
@end table
128
 
129
Also, there are some instructions, which cannot be found in other assemblers.
130
These are branch instructions, which has different opcodes upon jump distance.
131
They all got PC relative addressing mode.
132
 
133
@table @code
134
@item   beq label
135
A polymorph instruction which is @samp{jeq label} in case if jump distance
136
within allowed range for cpu's jump instruction. If not, this unrolls into
137
a sequence of
138
@smallexample
139
  jne $+6
140
  br  label
141
@end smallexample
142
 
143
@item bne label
144
A polymorph instruction which is @samp{jne label} or @samp{jeq +4; br label}
145
 
146
@item blt label
147
A polymorph instruction which is @samp{jl label} or @samp{jge +4; br label}
148
 
149
@item bltn label
150
A polymorph instruction which is @samp{jn label} or @samp{jn +2; jmp +4; br label}
151
 
152
@item bltu label
153
A polymorph instruction which is @samp{jlo label} or @samp{jhs +2; br label}
154
 
155
@item bge label
156
A polymorph instruction which is @samp{jge label} or @samp{jl +4; br label}
157
 
158
@item bgeu label
159
A polymorph instruction which is @samp{jhs label} or @samp{jlo +4; br label}
160
 
161
@item bgt label
162
A polymorph instruction which is @samp{jeq +2; jge label} or @samp{jeq +6; jl  +4; br label}
163
 
164
@item bgtu label
165
A polymorph instruction which is @samp{jeq +2; jhs label} or @samp{jeq +6; jlo +4; br label}
166
 
167
@item bleu label
168
A polymorph instruction which is @samp{jeq label; jlo label} or @samp{jeq +2; jhs +4; br label}
169
 
170
@item ble label
171
A polymorph instruction which is @samp{jeq label; jl  label} or @samp{jeq +2; jge +4; br label}
172
 
173
@item jump label
174
A polymorph instruction which is @samp{jmp label} or @samp{br label}
175
@end table
176
 
177
 
178
@node MSP430 Floating Point
179
@section Floating Point
180
 
181
@cindex floating point, MSP 430 (@sc{ieee})
182
@cindex MSP 430 floating point (@sc{ieee})
183
The MSP 430 family uses @sc{ieee} 32-bit floating-point numbers.
184
 
185
@node MSP430 Directives
186
@section MSP 430 Machine Directives
187
 
188
@cindex machine directives, MSP 430
189
@cindex MSP 430 machine directives
190
@table @code
191
@cindex @code{file} directive, MSP 430
192
@item .file
193
This directive is ignored; it is accepted for compatibility with other
194
MSP 430 assemblers.
195
 
196
@quotation
197
@emph{Warning:} in other versions of the @sc{gnu} assembler, @code{.file} is
198
used for the directive called @code{.app-file} in the MSP 430 support.
199
@end quotation
200
 
201
@cindex @code{line} directive, MSP 430
202
@item .line
203
This directive is ignored; it is accepted for compatibility with other
204
MSP 430 assemblers.
205
 
206
@cindex @code{sect} directive, MSP 430
207
@item .arch
208
Currently this directive is ignored; it is accepted for compatibility with other
209
MSP 430 assemblers.
210
 
211
@cindex @code{profiler} directive, MSP 430
212
@item .profiler
213
This directive instructs assembler to add new profile entry to the object file.
214
 
215
@end table
216
 
217
@node MSP430 Opcodes
218
@section Opcodes
219
 
220
@cindex MSP 430 opcodes
221
@cindex opcodes for MSP 430
222
@code{@value{AS}} implements all the standard MSP 430 opcodes.  No
223
additional pseudo-instructions are needed on this family.
224
 
225
For information on the 430 machine instruction set, see @cite{MSP430
226
User's Manual, document slau049d}, Texas Instrument, Inc.
227
 
228
@node MSP430 Profiling Capability
229
@section Profiling Capability
230
 
231
@cindex MSP 430 profiling capability
232
@cindex profiling capability for MSP 430
233
It is a performance hit to use gcc's profiling approach for this tiny target.
234
Even more -- jtag hardware facility does not perform any profiling functions.
235
However we've got gdb's built-in simulator where we can do anything.
236
 
237
We define new section @samp{.profiler} which holds all profiling information.
238
We define new pseudo operation @samp{.profiler} which will instruct assembler to
239
add new profile entry to the object file. Profile should take place at the
240
present address.
241
 
242
Pseudo operation format:
243
 
244
@samp{.profiler flags,function_to_profile [, cycle_corrector, extra]}
245
 
246
 
247
where:
248
 
249
@table @code
250
 
251
@table @code
252
 
253
@samp{flags} is a combination of the following characters:
254
 
255
@item  s
256
function entry
257
@item  x
258
function exit
259
@item  i
260
function is in init section
261
@item  f
262
function is in fini section
263
@item  l
264
library call
265
@item  c
266
libc standard call
267
@item  d
268
stack value demand
269
@item  I
270
interrupt service routine
271
@item  P
272
prologue start
273
@item  p
274
prologue end
275
@item  E
276
epilogue start
277
@item  e
278
epilogue end
279
@item  j
280
long jump / sjlj unwind
281
@item  a
282
an arbitrary code fragment
283
@item t
284
extra parameter saved (a constant value like frame size)
285
@end table
286
 
287
@item function_to_profile
288
a function address
289
@item cycle_corrector
290
a value which should be added to the cycle counter, zero if omitted.
291
@item extra
292
any extra parameter, zero if omitted.
293
 
294
@end table
295
 
296
For example:
297
@smallexample
298
.global fxx
299
.type fxx,@@function
300
fxx:
301
.LFrameOffset_fxx=0x08
302
.profiler "scdP", fxx     ; function entry.
303
                          ; we also demand stack value to be saved
304
  push r11
305
  push r10
306
  push r9
307
  push r8
308
.profiler "cdpt",fxx,0, .LFrameOffset_fxx  ; check stack value at this point
309
                                          ; (this is a prologue end)
310
                                          ; note, that spare var filled with
311
                                          ; the farme size
312
  mov r15,r8
313
...
314
.profiler cdE,fxx         ; check stack
315
  pop r8
316
  pop r9
317
  pop r10
318
  pop r11
319
.profiler xcde,fxx,3      ; exit adds 3 to the cycle counter
320
  ret                     ; cause 'ret' insn takes 3 cycles
321
@end smallexample

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.