OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [gas/] [doc/] [c-pdp11.texi] - Blame information for rev 438

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
@c Copyright 2001, 2002 Free Software Foundation, Inc.
2
@c This is part of the GAS manual.
3
@c For copying conditions, see the file as.texinfo.
4
@ifset GENERIC
5
@page
6
@node PDP-11-Dependent
7
@chapter PDP-11 Dependent Features
8
@end ifset
9
@ifclear GENERIC
10
@node Machine Dependencies
11
@chapter PDP-11 Dependent Features
12
@end ifclear
13
 
14
@cindex PDP-11 support
15
 
16
@menu
17
* PDP-11-Options::              Options
18
* PDP-11-Pseudos::              Assembler Directives
19
* PDP-11-Syntax::               DEC Syntax versus BSD Syntax
20
* PDP-11-Mnemonics::            Instruction Naming
21
* PDP-11-Synthetic::            Synthetic Instructions
22
@end menu
23
 
24
@node PDP-11-Options
25
@section Options
26
 
27
@cindex options for PDP-11
28
 
29
The PDP-11 version of @code{@value{AS}} has a rich set of machine
30
dependent options.
31
 
32
@subsection Code Generation Options
33
 
34
@table @code
35
@cindex -mpic
36
@cindex -mno-pic
37
@item -mpic | -mno-pic
38
Generate position-independent (or position-dependent) code.
39
 
40
The default is to generate position-independent code.
41
@end table
42
 
43
@subsection Instruction Set Extension Options
44
 
45
These options enables or disables the use of extensions over the base
46
line instruction set as introduced by the first PDP-11 CPU: the KA11.
47
Most options come in two variants: a @code{-m}@var{extension} that
48
enables @var{extension}, and a @code{-mno-}@var{extension} that disables
49
@var{extension}.
50
 
51
The default is to enable all extensions.
52
 
53
@table @code
54
@cindex -mall
55
@cindex -mall-extensions
56
@item -mall | -mall-extensions
57
Enable all instruction set extensions.
58
 
59
@cindex -mno-extensions
60
@item -mno-extensions
61
Disable all instruction set extensions.
62
 
63
@cindex -mcis
64
@cindex -mno-cis
65
@item -mcis | -mno-cis
66
Enable (or disable) the use of the commercial instruction set, which
67
consists of these instructions: @code{ADDNI}, @code{ADDN}, @code{ADDPI},
68
@code{ADDP}, @code{ASHNI}, @code{ASHN}, @code{ASHPI}, @code{ASHP},
69
@code{CMPCI}, @code{CMPC}, @code{CMPNI}, @code{CMPN}, @code{CMPPI},
70
@code{CMPP}, @code{CVTLNI}, @code{CVTLN}, @code{CVTLPI}, @code{CVTLP},
71
@code{CVTNLI}, @code{CVTNL}, @code{CVTNPI}, @code{CVTNP}, @code{CVTPLI},
72
@code{CVTPL}, @code{CVTPNI}, @code{CVTPN}, @code{DIVPI}, @code{DIVP},
73
@code{L2DR}, @code{L3DR}, @code{LOCCI}, @code{LOCC}, @code{MATCI},
74
@code{MATC}, @code{MOVCI}, @code{MOVC}, @code{MOVRCI}, @code{MOVRC},
75
@code{MOVTCI}, @code{MOVTC}, @code{MULPI}, @code{MULP}, @code{SCANCI},
76
@code{SCANC}, @code{SKPCI}, @code{SKPC}, @code{SPANCI}, @code{SPANC},
77
@code{SUBNI}, @code{SUBN}, @code{SUBPI}, and @code{SUBP}.
78
 
79
@cindex -mcsm
80
@cindex -mno-csm
81
@item -mcsm | -mno-csm
82
Enable (or disable) the use of the @code{CSM} instruction.
83
 
84
@cindex -meis
85
@cindex -mno-eis
86
@item -meis | -mno-eis
87
Enable (or disable) the use of the extended instruction set, which
88
consists of these instructions: @code{ASHC}, @code{ASH}, @code{DIV},
89
@code{MARK}, @code{MUL}, @code{RTT}, @code{SOB} @code{SXT}, and
90
@code{XOR}.
91
 
92
@cindex -mfis
93
@cindex -mno-fis
94
@cindex -mkev11
95
@cindex -mkev11
96
@cindex -mno-kev11
97
@item -mfis | -mkev11
98
@itemx -mno-fis | -mno-kev11
99
Enable (or disable) the use of the KEV11 floating-point instructions:
100
@code{FADD}, @code{FDIV}, @code{FMUL}, and @code{FSUB}.
101
 
102
@cindex -mfpp
103
@cindex -mno-fpp
104
@cindex -mfpu
105
@cindex -mno-fpu
106
@cindex -mfp-11
107
@cindex -mno-fp-11
108
@item -mfpp | -mfpu | -mfp-11
109
@itemx -mno-fpp | -mno-fpu | -mno-fp-11
110
Enable (or disable) the use of FP-11 floating-point instructions:
111
@code{ABSF}, @code{ADDF}, @code{CFCC}, @code{CLRF}, @code{CMPF},
112
@code{DIVF}, @code{LDCFF}, @code{LDCIF}, @code{LDEXP}, @code{LDF},
113
@code{LDFPS}, @code{MODF}, @code{MULF}, @code{NEGF}, @code{SETD},
114
@code{SETF}, @code{SETI}, @code{SETL}, @code{STCFF}, @code{STCFI},
115
@code{STEXP}, @code{STF}, @code{STFPS}, @code{STST}, @code{SUBF}, and
116
@code{TSTF}.
117
 
118
@cindex -mlimited-eis
119
@cindex -mno-limited-eis
120
@item -mlimited-eis | -mno-limited-eis
121
Enable (or disable) the use of the limited extended instruction set:
122
@code{MARK}, @code{RTT}, @code{SOB}, @code{SXT}, and @code{XOR}.
123
 
124
The -mno-limited-eis options also implies -mno-eis.
125
 
126
@cindex -mmfpt
127
@cindex -mno-mfpt
128
@item -mmfpt | -mno-mfpt
129
Enable (or disable) the use of the @code{MFPT} instruction.
130
 
131
@cindex -mmutiproc
132
@cindex -mno-mutiproc
133
@item -mmultiproc | -mno-multiproc
134
Enable (or disable) the use of multiprocessor instructions: @code{TSTSET} and
135
@code{WRTLCK}.
136
 
137
@cindex -mmxps
138
@cindex -mno-mxps
139
@item -mmxps | -mno-mxps
140
Enable (or disable) the use of the @code{MFPS} and @code{MTPS} instructions.
141
 
142
@cindex -mspl
143
@cindex -mno-spl
144
@item -mspl | -mno-spl
145
Enable (or disable) the use of the @code{SPL} instruction.
146
 
147
@cindex -mmicrocode
148
@cindex -mno-microcode
149
Enable (or disable) the use of the microcode instructions: @code{LDUB},
150
@code{MED}, and @code{XFC}.
151
@end table
152
 
153
@subsection CPU Model Options
154
 
155
These options enable the instruction set extensions supported by a
156
particular CPU, and disables all other extensions.
157
 
158
@table @code
159
@cindex -mka11
160
@item -mka11
161
KA11 CPU.  Base line instruction set only.
162
 
163
@cindex -mkb11
164
@item -mkb11
165
KB11 CPU.  Enable extended instruction set and @code{SPL}.
166
 
167
@cindex -mkd11a
168
@item -mkd11a
169
KD11-A CPU.  Enable limited extended instruction set.
170
 
171
@cindex -mkd11b
172
@item -mkd11b
173
KD11-B CPU.  Base line instruction set only.
174
 
175
@cindex -mkd11d
176
@item -mkd11d
177
KD11-D CPU.  Base line instruction set only.
178
 
179
@cindex -mkd11e
180
@item -mkd11e
181
KD11-E CPU.  Enable extended instruction set, @code{MFPS}, and @code{MTPS}.
182
 
183
@cindex -mkd11f
184
@cindex -mkd11h
185
@cindex -mkd11q
186
@item -mkd11f | -mkd11h | -mkd11q
187
KD11-F, KD11-H, or KD11-Q CPU.  Enable limited extended instruction set,
188
@code{MFPS}, and @code{MTPS}.
189
 
190
@cindex -mkd11k
191
@item -mkd11k
192
KD11-K CPU.  Enable extended instruction set, @code{LDUB}, @code{MED},
193
@code{MFPS}, @code{MFPT}, @code{MTPS}, and @code{XFC}.
194
 
195
@cindex -mkd11z
196
@item -mkd11z
197
KD11-Z CPU.  Enable extended instruction set, @code{CSM}, @code{MFPS},
198
@code{MFPT}, @code{MTPS}, and @code{SPL}.
199
 
200
@cindex -mf11
201
@item -mf11
202
F11 CPU.  Enable extended instruction set, @code{MFPS}, @code{MFPT}, and
203
@code{MTPS}.
204
 
205
@cindex -mj11
206
@item -mj11
207
J11 CPU.  Enable extended instruction set, @code{CSM}, @code{MFPS},
208
@code{MFPT}, @code{MTPS}, @code{SPL}, @code{TSTSET}, and @code{WRTLCK}.
209
 
210
@cindex -mt11
211
@item -mt11
212
T11 CPU.  Enable limited extended instruction set, @code{MFPS}, and
213
@code{MTPS}.
214
@end table
215
 
216
@subsection Machine Model Options
217
 
218
These options enable the instruction set extensions supported by a
219
particular machine model, and disables all other extensions.
220
 
221
@table @code
222
@cindex -m11/03
223
@item -m11/03
224
Same as @code{-mkd11f}.
225
 
226
@cindex -m11/04
227
@item -m11/04
228
Same as @code{-mkd11d}.
229
 
230
@cindex -m11/05
231
@cindex -m11/10
232
@item -m11/05 | -m11/10
233
Same as @code{-mkd11b}.
234
 
235
@cindex -m11/15
236
@cindex -m11/20
237
@item -m11/15 | -m11/20
238
Same as @code{-mka11}.
239
 
240
@cindex -m11/21
241
@item -m11/21
242
Same as @code{-mt11}.
243
 
244
@cindex -m11/23
245
@cindex -m11/24
246
@item -m11/23 | -m11/24
247
Same as @code{-mf11}.
248
 
249
@cindex -m11/34
250
@item -m11/34
251
Same as @code{-mkd11e}.
252
 
253
@cindex -m11/34a
254
@item -m11/34a
255
Ame as @code{-mkd11e} @code{-mfpp}.
256
 
257
@cindex -m11/35
258
@cindex -m11/40
259
@item -m11/35 | -m11/40
260
Same as @code{-mkd11a}.
261
 
262
@cindex -m11/44
263
@item -m11/44
264
Same as @code{-mkd11z}.
265
 
266
@cindex -m11/45
267
@cindex -m11/50
268
@cindex -m11/55
269
@cindex -m11/70
270
@item -m11/45 | -m11/50 | -m11/55 | -m11/70
271
Same as @code{-mkb11}.
272
 
273
@cindex -m11/53
274
@cindex -m11/73
275
@cindex -m11/83
276
@cindex -m11/84
277
@cindex -m11/93
278
@cindex -m11/94
279
@item -m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94
280
Same as @code{-mj11}.
281
 
282
@cindex -m11/60
283
@item -m11/60
284
Same as @code{-mkd11k}.
285
@end table
286
 
287
@node PDP-11-Pseudos
288
@section Assembler Directives
289
 
290
The PDP-11 version of @code{@value{AS}} has a few machine
291
dependent assembler directives.
292
 
293
@table @code
294
@item .bss
295
Switch to the @code{bss} section.
296
 
297
@item .even
298
Align the location counter to an even number.
299
@end table
300
 
301
@node PDP-11-Syntax
302
@section PDP-11 Assembly Language Syntax
303
 
304
@cindex PDP-11 syntax
305
 
306
@cindex DEC syntax
307
@cindex BSD syntax
308
@code{@value{AS}} supports both DEC syntax and BSD syntax.  The only
309
difference is that in DEC syntax, a @code{#} character is used to denote
310
an immediate constants, while in BSD syntax the character for this
311
purpose is @code{$}.
312
 
313
@cindex PDP-11 general-purpose register syntax
314
general-purpose registers are named @code{r0} through @code{r7}.
315
Mnemonic alternatives for @code{r6} and @code{r7} are @code{sp} and
316
@code{pc}, respectively.
317
 
318
@cindex PDP-11 floating-point register syntax
319
Floating-point registers are named @code{ac0} through @code{ac3}, or
320
alternatively @code{fr0} through @code{fr3}.
321
 
322
@cindex PDP-11 comments
323
Comments are started with a @code{#} or a @code{/} character, and extend
324
to the end of the line.  (FIXME: clash with immediates?)
325
 
326
@node PDP-11-Mnemonics
327
@section Instruction Naming
328
 
329
@cindex PDP-11 instruction naming
330
 
331
Some instructions have alternative names.
332
 
333
@table @code
334
@item BCC
335
@code{BHIS}
336
 
337
@item BCS
338
@code{BLO}
339
 
340
@item L2DR
341
@code{L2D}
342
 
343
@item L3DR
344
@code{L3D}
345
 
346
@item SYS
347
@code{TRAP}
348
@end table
349
 
350
@node PDP-11-Synthetic
351
@section Synthetic Instructions
352
 
353
The @code{JBR} and @code{J}@var{CC} synthetic instructions are not
354
supported yet.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.