OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [gas/] [itbl-ops.h] - Blame information for rev 609

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
/* itbl-ops.h
2
   Copyright 1997, 1999, 2000, 2003, 2006, 2007 Free Software Foundation, Inc.
3
 
4
   This file is part of GAS, the GNU Assembler.
5
 
6
   GAS is free software; you can redistribute it and/or modify
7
   it under the terms of the GNU General Public License as published by
8
   the Free Software Foundation; either version 3, or (at your option)
9
   any later version.
10
 
11
   GAS is distributed in the hope that it will be useful,
12
   but WITHOUT ANY WARRANTY; without even the implied warranty of
13
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
   GNU General Public License for more details.
15
 
16
   You should have received a copy of the GNU General Public License
17
   along with GAS; see the file COPYING.  If not, write to the Free
18
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19
   02110-1301, USA.  */
20
 
21
/* External functions, constants and defines for itbl support */
22
 
23
#ifdef HAVE_ITBL_CPU
24
#include "itbl-cpu.h"
25
#endif
26
 
27
/* Defaults for definitions required by generic code */
28
#ifndef ITBL_NUMBER_OF_PROCESSORS
29
#define ITBL_NUMBER_OF_PROCESSORS 1
30
#endif
31
 
32
#ifndef ITBL_MAX_BITPOS
33
#define ITBL_MAX_BITPOS 31
34
#endif
35
 
36
#ifndef ITBL_TYPE
37
#define ITBL_TYPE unsigned long
38
#endif
39
 
40
#ifndef ITBL_IS_INSN
41
#define ITBL_IS_INSN(insn) 1
42
#endif
43
 
44
#ifndef ITBL_DECODE_PNUM
45
#define ITBL_DECODE_PNUM(insn) 0
46
#endif
47
 
48
#ifndef ITBL_ENCODE_PNUM
49
#define ITBL_ENCODE_PNUM(pnum) 0
50
#endif
51
 
52
typedef ITBL_TYPE t_insn;
53
 
54
/* types of entries */
55
typedef enum
56
  {
57
    e_insn,
58
    e_dreg,
59
    e_regtype0 = e_dreg,
60
    e_creg,
61
    e_greg,
62
    e_addr,
63
    e_nregtypes = e_greg + 1,
64
    e_immed,
65
    e_ntypes,
66
    e_invtype                   /* invalid type */
67
  } e_type;
68
 
69
typedef enum
70
  {
71
    e_p0,
72
    e_nprocs = ITBL_NUMBER_OF_PROCESSORS,
73
    e_invproc                   /* invalid processor */
74
  } e_processor;
75
 
76
/* 0 means an instruction table was not specified.  */
77
extern int itbl_have_entries;
78
 
79
/* These routines are visible to the main part of the assembler */
80
 
81
int itbl_parse (char *insntbl);
82
void itbl_init (void);
83
char *itbl_get_field (char **s);
84
unsigned long itbl_assemble (char *name, char *operands);
85
int itbl_disassemble (char *str, unsigned long insn);
86
int itbl_parse (char *tbl);     /* parses insn tbl */
87
int itbl_get_reg_val (char *name, unsigned long *pval);
88
int itbl_get_val (e_processor processor, e_type type, char *name,
89
                  unsigned long *pval);
90
char *itbl_get_name (e_processor processor, e_type type, unsigned long val);
91
 
92
/* These routines are called by the table parser used to build the
93
   dynamic list of new processor instructions and registers.  */
94
 
95
struct itbl_entry *itbl_add_reg (int yyproc, int yytype,
96
                                 char *regname, int regnum);
97
struct itbl_entry *itbl_add_insn (int yyproc, char *name,
98
             unsigned long value, int sbit, int ebit, unsigned long flags);
99
struct itbl_field *itbl_add_operand (struct itbl_entry * e, int yytype,
100
                                  int sbit, int ebit, unsigned long flags);

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.