URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [arm/] [arm7dm.d] - Blame information for rev 156

Line No.	Rev	Author	Line
1	38	julius	`# name: ARM 7DM instructions`
2			`# as: -mcpu=arm7dm`
3			`# objdump: -dr --prefix-addresses --show-raw-insn`
4
5			`.: +file format .arm.*`
6
7			`Disassembly of section .text:`
8			`0+00 <[^>]+> e0c10392 ? smull r0, r1, r2, r3`
9			`0+04 <[^>]+> e0810392 ? umull r0, r1, r2, r3`
10			`0+08 <[^>]+> e0e10392 ? smlal r0, r1, r2, r3`
11			`0+0c <[^>]+> e0a10394 ? umlal r0, r1, r4, r3`
12			`0+10 <[^>]+> 10c10493 ? smullne r0, r1, r3, r4`
13			`0+14 <[^>]+> e0d01b99 ? smulls r1, r0, r9, fp`
14			`0+18 <[^>]+> 00b92994 ? umlalseq r2, r9, r4, r9`
15			`0+1c <[^>]+> a0eaee98 ? smlalge lr, sl, r8, lr`
16			`0+20 <[^>]+> e322f000 ? msr CPSR_x, #0 ; 0x0`
17			`0+24 <[^>]+> e1a00000 ? nop \(mov r0,r0\)`
18			`0+28 <[^>]+> e1a00000 ? nop \(mov r0,r0\)`
19			`0+2c <[^>]+> e1a00000 ? nop \(mov r0,r0\)`