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[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [arm/] [t16-bad.s] - Blame information for rev 156

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Line No. Rev Author Line
1 38 julius
        @ Things you can't do with 16-bit Thumb instructions, but you can
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        @ do with the equivalent ARM instruction.  Does not include errors
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        @ caught by fixup processing (e.g. out-of-range immediates).
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        .text
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        .code 16
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        .thumb_func
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l:
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        @ Arithmetic instruction templates
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        .macro  ar2 opc
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        \opc    r8,r0
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        \opc    r0,r8
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        .endm
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        .macro  ar2sh opc
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        ar2     \opc
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        \opc    r0,#12
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        \opc    r0,r1,lsl #2
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        \opc    r0,r1,lsl r3
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        .endm
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        .macro  ar2r opc
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        ar2     \opc
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        \opc    r0,r1,ror #8
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        .endm
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        .macro  ar3 opc
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        \opc    r1,r2,r3
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        \opc    r8,r0
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        \opc    r0,r8
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        .endm
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        .macro ar3sh opc
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        ar3     \opc
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        \opc    r0,#12
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        \opc    r0,r1,lsl #2
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        \opc    r0,r1,lsl r3
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        .endm
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        ar2sh   tst
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        ar2sh   cmn
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        ar2sh   mvn
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        ar2     neg
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        ar2     rev
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        ar2     rev16
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        ar2     revsh
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        ar2r    sxtb
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        ar2r    sxth
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        ar2r    uxtb
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        ar2r    uxth
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        ar3sh   adc
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        ar3sh   and
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        ar3sh   bic
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        ar3sh   eor
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        ar3sh   orr
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        ar3sh   sbc
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        ar3     mul
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        @ Shift instruction template
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        .macro  shift opc
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        \opc    r8,r0,#12  @ form 1
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        \opc    r0,r8,#12
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        ar2     \opc       @ form 2
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        .endm
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        shift   asr
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        shift   lsl
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        shift   lsr
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        shift   ror
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        ror     r0,r1,#12
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        @ add/sub/mov/cmp are idiosyncratic
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        add     r0,r1,lsl #2
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        add     r0,r1,lsl r3
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        add     r8,r0,#1        @ form 1
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        add     r0,r8,#1
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        add     r8,#10          @ form 2
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        add     r8,r1,r2        @ form 3
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        add     r1,r8,r2
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        add     r1,r2,r8
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        add     r8,pc,#4        @ form 5
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        add     r8,sp,#4        @ form 6
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        ar3sh   sub
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        sub     r8,r0,#1        @ form 1
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        sub     r0,r8,#1
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        sub     r8,#10          @ form 2
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        sub     r8,r1,r2        @ form 3
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        sub     r1,r8,r2
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        sub     r1,r2,r8
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        cmp     r0,r1,lsl #2
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        cmp     r0,r1,lsl r3
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        cmp     r8,#255
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        mov     r0,r1,lsl #2
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        mov     r0,r1,lsl r3
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        mov     r8,#255
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        @ Load/store template
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        .macro  ldst opc
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        \opc    r8,[r0]
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        \opc    r0,[r8]
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        \opc    r0,[r0,r8]
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        \opc    r0,[r1,#4]!
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        \opc    r0,[r1],#4
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        \opc    r0,[r1,-r2]
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        \opc    r0,[r1],r2
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        .endm
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        ldst    ldr
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        ldst    ldrb
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        ldst    ldrh
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        ldst    ldrsb
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        ldst    ldrsh
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        ldst    str
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        ldst    strb
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        ldst    strh
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        ldr     r0,[r1,r2,lsl #1]
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        str     r0,[r1,r2,lsl #1]
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        @ Load/store multiple
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        ldmia   r8!,{r1,r2}
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        ldmia   r7!,{r8}
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        ldmia   r7,{r1,r2}
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        ldmia   r7!,{r1,r7}
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        stmia   r8!,{r1,r2}
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        stmia   r7!,{r8}
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        stmia   r7,{r1,r2}
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        stmia   r7!,{r1,r7}
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        push    {r8,r9}
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        pop     {r8,r9}
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        @ Miscellaneous
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        bkpt    #257
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        cpsie   ai,#5
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        cpsid   ai,#5
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        @ Conditional suffixes
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        addeq   r0,r1,r2
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        @ low register non flag setting add.
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        .syntax unified
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        add     r0, r1
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