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@ VFP Instructions for D variants (Double precision)
        .text
        .global F
F:
        @ First we test the basic syntax and bit patterns of the opcodes.
        @ Most of these tests deliberatly use d0/r0 to avoid setting
        @ any more bits than necessary.
 
        @ Comparison operations
 
        fcmped  d0, d0
        fcmpezd d0
        fcmpd   d0, d0
        fcmpzd  d0
 
        @ Monadic data operations
 
        fabsd   d0, d0
        fcpyd   d0, d0
        fnegd   d0, d0
        fsqrtd  d0, d0
 
        @ Dyadic data operations
 
        faddd   d0, d0, d0
        fdivd   d0, d0, d0
        fmacd   d0, d0, d0
        fmscd   d0, d0, d0
        fmuld   d0, d0, d0
        fnmacd  d0, d0, d0
        fnmscd  d0, d0, d0
        fnmuld  d0, d0, d0
        fsubd   d0, d0, d0
 
        @ Load/store operations
 
        fldd    d0, [r0]
        fstd    d0, [r0]
 
        @ Load/store multiple operations
 
        fldmiad r0, {d0}
        fldmfdd r0, {d0}
        fldmiad r0!, {d0}
        fldmfdd r0!, {d0}
        fldmdbd r0!, {d0}
        fldmead r0!, {d0}
 
        fstmiad r0, {d0}
        fstmead r0, {d0}
        fstmiad r0!, {d0}
        fstmead r0!, {d0}
        fstmdbd r0!, {d0}
        fstmfdd r0!, {d0}
 
        @ Conversion operations
 
        fsitod  d0, s0
        fuitod  d0, s0
 
        ftosid  s0, d0
        ftosizd s0, d0
        ftouid  s0, d0
        ftouizd s0, d0
 
        fcvtds  d0, s0
        fcvtsd  s0, d0
 
        @ ARM from VFP operations
 
        fmrdh   r0, d0
        fmrdl   r0, d0
 
        @ VFP From ARM operations
 
        fmdhr   d0, r0
        fmdlr   d0, r0
 
        @ Now we test that the register fields are updated correctly for
        @ each class of instruction.
 
        @ Single register operations (compare-zero):
 
        fcmpzd  d1
        fcmpzd  d2
        fcmpzd  d15
 
        @ Two register comparison operations:
 
        fcmpd   d0, d1
        fcmpd   d0, d2
        fcmpd   d0, d15
        fcmpd   d1, d0
        fcmpd   d2, d0
        fcmpd   d15, d0
        fcmpd   d5, d12
 
        @ Two register data operations (monadic)
 
        fnegd   d0, d1
        fnegd   d0, d2
        fnegd   d0, d15
        fnegd   d1, d0
        fnegd   d2, d0
        fnegd   d15, d0
        fnegd   d12, d5
 
        @ Three register data operations (dyadic)
 
        faddd   d0, d0, d1
        faddd   d0, d0, d2
        faddd   d0, d0, d15
        faddd   d0, d1, d0
        faddd   d0, d2, d0
        faddd   d0, d15, d0
        faddd   d1, d0, d0
        faddd   d2, d0, d0
        faddd   d15, d0, d0
        faddd   d12, d9, d5
 
        @ Conversion operations
 
        fcvtds  d0, s1
        fcvtds  d0, s2
        fcvtds  d0, s31
        fcvtds  d1, s0
        fcvtds  d2, s0
        fcvtds  d15, s0
        fcvtsd  s1, d0
        fcvtsd  s2, d0
        fcvtsd  s31, d0
        fcvtsd  s0, d1
        fcvtsd  s0, d2
        fcvtsd  s0, d15
 
        @ Move to VFP from ARM
 
        fmrdh   r1, d0
        fmrdh   r14, d0
        fmrdh   r0, d1
        fmrdh   r0, d2
        fmrdh   r0, d15
        fmrdl   r1, d0
        fmrdl   r14, d0
        fmrdl   r0, d1
        fmrdl   r0, d2
        fmrdl   r0, d15
 
        @ Move to ARM from VFP
 
        fmdhr   d0, r1
        fmdhr   d0, r14
        fmdhr   d1, r0
        fmdhr   d2, r0
        fmdhr   d15, r0
        fmdlr   d0, r1
        fmdlr   d0, r14
        fmdlr   d1, r0
        fmdlr   d2, r0
        fmdlr   d15, r0
 
        @ Load/store operations
 
        fldd    d0, [r1]
        fldd    d0, [r14]
        fldd    d0, [r0, #0]
        fldd    d0, [r0, #1020]
        fldd    d0, [r0, #-1020]
        fldd    d1, [r0]
        fldd    d2, [r0]
        fldd    d15, [r0]
        fstd    d12, [r12, #804]
 
        @ Load/store multiple operations
 
        fldmiad r0, {d1}
        fldmiad r0, {d2}
        fldmiad r0, {d15}
        fldmiad r0, {d0-d1}
        fldmiad r0, {d0-d2}
        fldmiad r0, {d0-d15}
        fldmiad r0, {d1-d15}
        fldmiad r0, {d2-d15}
        fldmiad r0, {d14-d15}
        fldmiad r1, {d0}
        fldmiad r14, {d0}
 
        @ Check that we assemble all the register names correctly
 
        fcmpzd  d0
        fcmpzd  d1
        fcmpzd  d2
        fcmpzd  d3
        fcmpzd  d4
        fcmpzd  d5
        fcmpzd  d6
        fcmpzd  d7
        fcmpzd  d8
        fcmpzd  d9
        fcmpzd  d10
        fcmpzd  d11
        fcmpzd  d12
        fcmpzd  d13
        fcmpzd  d14
        fcmpzd  d15
 
        @ Now we check the placement of the conditional execution substring.
        @ On VFP this is always at the end of the instruction.
 
        @ Comparison operations
 
        fcmpedeq        d1, d15
        fcmpezdeq       d2
        fcmpdeq d3, d14
        fcmpzdeq        d4
 
        @ Monadic data operations
 
        fabsdeq d5, d13
        fcpydeq d6, d12
        fnegdeq d7, d11
        fsqrtdeq        d8, d10
 
        @ Dyadic data operations
 
        fadddeq d9, d1, d15
        fdivdeq d2, d3, d14
        fmacdeq d4, d13, d12
        fmscdeq d5, d6, d11
        fmuldeq d7, d10, d9
        fnmacdeq        d8, d9, d10
        fnmscdeq        d7, d6, d11
        fnmuldeq        d5, d4, d12
        fsubdeq d3, d13, d14
 
        @ Load/store operations
 
        flddeq  d2, [r5]
        fstdeq  d1, [r12]
 
        @ Load/store multiple operations
 
        fldmiadeq       r1, {d1}
        fldmfddeq       r2, {d2}
        fldmiadeq       r3!, {d3}
        fldmfddeq       r4!, {d4}
        fldmdbdeq       r5!, {d5}
        fldmeadeq       r6!, {d6}
 
        fstmiadeq       r7, {d15}
        fstmeadeq       r8, {d14}
        fstmiadeq       r9!, {d13}
        fstmeadeq       r10!, {d12}
        fstmdbdeq       r11!, {d11}
        fstmfddeq       r12!, {d10}
 
        @ Conversion operations
 
        fsitodeq        d15, s1
        fuitodeq        d1, s31
 
        ftosideq        s1, d15
        ftosizdeq       s31, d2
        ftouideq        s15, d2
        ftouizdeq       s11, d3
 
        fcvtdseq        d1, s10
        fcvtsdeq        s11, d1
 
        @ ARM from VFP operations
 
        fmrdheq r8, d1
        fmrdleq r7, d15
 
        @ VFP From ARM operations
 
        fmdhreq d1, r15
        fmdlreq d15, r1
 
        # Add three nop instructions to ensure that the
        # output is 32-byte aligned as required for arm-aout.
        nop
        nop
        nop

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[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [arm/] [vfp1.s] - Blame information for rev 438

Line No.	Rev	Author	Line
1	38	julius	`@ VFP Instructions for D variants (Double precision)`
2			`.text`
3			`.global F`
4			`F:`
5			`@ First we test the basic syntax and bit patterns of the opcodes.`
6			`@ Most of these tests deliberatly use d0/r0 to avoid setting`
7			`@ any more bits than necessary.`
8
9			`@ Comparison operations`
10
11			`fcmped d0, d0`
12			`fcmpezd d0`
13			`fcmpd d0, d0`
14			`fcmpzd d0`
15
16			`@ Monadic data operations`
17
18			`fabsd d0, d0`
19			`fcpyd d0, d0`
20			`fnegd d0, d0`
21			`fsqrtd d0, d0`
22
23			`@ Dyadic data operations`
24
25			`faddd d0, d0, d0`
26			`fdivd d0, d0, d0`
27			`fmacd d0, d0, d0`
28			`fmscd d0, d0, d0`
29			`fmuld d0, d0, d0`
30			`fnmacd d0, d0, d0`
31			`fnmscd d0, d0, d0`
32			`fnmuld d0, d0, d0`
33			`fsubd d0, d0, d0`
34
35			`@ Load/store operations`
36
37			`fldd d0, [r0]`
38			`fstd d0, [r0]`
39
40			`@ Load/store multiple operations`
41
42			`fldmiad r0, {d0}`
43			`fldmfdd r0, {d0}`
44			`fldmiad r0!, {d0}`
45			`fldmfdd r0!, {d0}`
46			`fldmdbd r0!, {d0}`
47			`fldmead r0!, {d0}`
48
49			`fstmiad r0, {d0}`
50			`fstmead r0, {d0}`
51			`fstmiad r0!, {d0}`
52			`fstmead r0!, {d0}`
53			`fstmdbd r0!, {d0}`
54			`fstmfdd r0!, {d0}`
55
56			`@ Conversion operations`
57
58			`fsitod d0, s0`
59			`fuitod d0, s0`
60
61			`ftosid s0, d0`
62			`ftosizd s0, d0`
63			`ftouid s0, d0`
64			`ftouizd s0, d0`
65
66			`fcvtds d0, s0`
67			`fcvtsd s0, d0`
68
69			`@ ARM from VFP operations`
70
71			`fmrdh r0, d0`
72			`fmrdl r0, d0`
73
74			`@ VFP From ARM operations`
75
76			`fmdhr d0, r0`
77			`fmdlr d0, r0`
78
79			`@ Now we test that the register fields are updated correctly for`
80			`@ each class of instruction.`
81
82			`@ Single register operations (compare-zero):`
83
84			`fcmpzd d1`
85			`fcmpzd d2`
86			`fcmpzd d15`
87
88			`@ Two register comparison operations:`
89
90			`fcmpd d0, d1`
91			`fcmpd d0, d2`
92			`fcmpd d0, d15`
93			`fcmpd d1, d0`
94			`fcmpd d2, d0`
95			`fcmpd d15, d0`
96			`fcmpd d5, d12`
97
98			`@ Two register data operations (monadic)`
99
100			`fnegd d0, d1`
101			`fnegd d0, d2`
102			`fnegd d0, d15`
103			`fnegd d1, d0`
104			`fnegd d2, d0`
105			`fnegd d15, d0`
106			`fnegd d12, d5`
107
108			`@ Three register data operations (dyadic)`
109
110			`faddd d0, d0, d1`
111			`faddd d0, d0, d2`
112			`faddd d0, d0, d15`
113			`faddd d0, d1, d0`
114			`faddd d0, d2, d0`
115			`faddd d0, d15, d0`
116			`faddd d1, d0, d0`
117			`faddd d2, d0, d0`
118			`faddd d15, d0, d0`
119			`faddd d12, d9, d5`
120
121			`@ Conversion operations`
122
123			`fcvtds d0, s1`
124			`fcvtds d0, s2`
125			`fcvtds d0, s31`
126			`fcvtds d1, s0`
127			`fcvtds d2, s0`
128			`fcvtds d15, s0`
129			`fcvtsd s1, d0`
130			`fcvtsd s2, d0`
131			`fcvtsd s31, d0`
132			`fcvtsd s0, d1`
133			`fcvtsd s0, d2`
134			`fcvtsd s0, d15`
135
136			`@ Move to VFP from ARM`
137
138			`fmrdh r1, d0`
139			`fmrdh r14, d0`
140			`fmrdh r0, d1`
141			`fmrdh r0, d2`
142			`fmrdh r0, d15`
143			`fmrdl r1, d0`
144			`fmrdl r14, d0`
145			`fmrdl r0, d1`
146			`fmrdl r0, d2`
147			`fmrdl r0, d15`
148
149			`@ Move to ARM from VFP`
150
151			`fmdhr d0, r1`
152			`fmdhr d0, r14`
153			`fmdhr d1, r0`
154			`fmdhr d2, r0`
155			`fmdhr d15, r0`
156			`fmdlr d0, r1`
157			`fmdlr d0, r14`
158			`fmdlr d1, r0`
159			`fmdlr d2, r0`
160			`fmdlr d15, r0`
161
162			`@ Load/store operations`
163
164			`fldd d0, [r1]`
165			`fldd d0, [r14]`
166			`fldd d0, [r0, #0]`
167			`fldd d0, [r0, #1020]`
168			`fldd d0, [r0, #-1020]`
169			`fldd d1, [r0]`
170			`fldd d2, [r0]`
171			`fldd d15, [r0]`
172			`fstd d12, [r12, #804]`
173
174			`@ Load/store multiple operations`
175
176			`fldmiad r0, {d1}`
177			`fldmiad r0, {d2}`
178			`fldmiad r0, {d15}`
179			`fldmiad r0, {d0-d1}`
180			`fldmiad r0, {d0-d2}`
181			`fldmiad r0, {d0-d15}`
182			`fldmiad r0, {d1-d15}`
183			`fldmiad r0, {d2-d15}`
184			`fldmiad r0, {d14-d15}`
185			`fldmiad r1, {d0}`
186			`fldmiad r14, {d0}`
187
188			`@ Check that we assemble all the register names correctly`
189
190			`fcmpzd d0`
191			`fcmpzd d1`
192			`fcmpzd d2`
193			`fcmpzd d3`
194			`fcmpzd d4`
195			`fcmpzd d5`
196			`fcmpzd d6`
197			`fcmpzd d7`
198			`fcmpzd d8`
199			`fcmpzd d9`
200			`fcmpzd d10`
201			`fcmpzd d11`
202			`fcmpzd d12`
203			`fcmpzd d13`
204			`fcmpzd d14`
205			`fcmpzd d15`
206
207			`@ Now we check the placement of the conditional execution substring.`
208			`@ On VFP this is always at the end of the instruction.`
209
210			`@ Comparison operations`
211
212			`fcmpedeq d1, d15`
213			`fcmpezdeq d2`
214			`fcmpdeq d3, d14`
215			`fcmpzdeq d4`
216
217			`@ Monadic data operations`
218
219			`fabsdeq d5, d13`
220			`fcpydeq d6, d12`
221			`fnegdeq d7, d11`
222			`fsqrtdeq d8, d10`
223
224			`@ Dyadic data operations`
225
226			`fadddeq d9, d1, d15`
227			`fdivdeq d2, d3, d14`
228			`fmacdeq d4, d13, d12`
229			`fmscdeq d5, d6, d11`
230			`fmuldeq d7, d10, d9`
231			`fnmacdeq d8, d9, d10`
232			`fnmscdeq d7, d6, d11`
233			`fnmuldeq d5, d4, d12`
234			`fsubdeq d3, d13, d14`
235
236			`@ Load/store operations`
237
238			`flddeq d2, [r5]`
239			`fstdeq d1, [r12]`
240
241			`@ Load/store multiple operations`
242
243			`fldmiadeq r1, {d1}`
244			`fldmfddeq r2, {d2}`
245			`fldmiadeq r3!, {d3}`
246			`fldmfddeq r4!, {d4}`
247			`fldmdbdeq r5!, {d5}`
248			`fldmeadeq r6!, {d6}`
249
250			`fstmiadeq r7, {d15}`
251			`fstmeadeq r8, {d14}`
252			`fstmiadeq r9!, {d13}`
253			`fstmeadeq r10!, {d12}`
254			`fstmdbdeq r11!, {d11}`
255			`fstmfddeq r12!, {d10}`
256
257			`@ Conversion operations`
258
259			`fsitodeq d15, s1`
260			`fuitodeq d1, s31`
261
262			`ftosideq s1, d15`
263			`ftosizdeq s31, d2`
264			`ftouideq s15, d2`
265			`ftouizdeq s11, d3`
266
267			`fcvtdseq d1, s10`
268			`fcvtsdeq s11, d1`
269
270			`@ ARM from VFP operations`
271
272			`fmrdheq r8, d1`
273			`fmrdleq r7, d15`
274
275			`@ VFP From ARM operations`
276
277			`fmdhreq d1, r15`
278			`fmdlreq d15, r1`
279
280			`# Add three nop instructions to ensure that the`
281			`# output is 32-byte aligned as required for arm-aout.`
282			`nop`
283			`nop`
284			`nop`