OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [bfin/] [bit.d] - Blame information for rev 156

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
#objdump: -dr
2
#name: bit
3
.*: +file format .*
4
Disassembly of section .text:
5
 
6
00000000 :
7
   0:   fc 4c           BITCLR \(R4, 0x1f\);.*
8
   2:   00 4c           BITCLR \(R0, 0x0\);.*
9
 
10
00000004 :
11
   4:   f2 4a           BITSET \(R2, 0x1e\);.*
12
   6:   eb 4a           BITSET \(R3, 0x1d\);.*
13
 
14
00000008 :
15
   8:   b7 4b           BITTGL \(R7, 0x16\);.*
16
   a:   86 4b           BITTGL \(R6, 0x10\);.*
17
 
18
0000000c :
19
   c:   f8 49           CC = BITTST \(R0, 0x1f\);.*
20
   e:   01 49           CC = BITTST \(R1, 0x0\);.*
21
  10:   7f 49           CC = BITTST \(R7, 0xf\);.*
22
 
23
00000012 :
24
  12:   0a c6 13 8a     R5 = DEPOSIT \(R3, R2\);
25
  16:   0a c6 37 c0     R0 = DEPOSIT \(R7, R6\) \(X\);
26
 
27
0000001a :
28
  1a:   0a c6 0a 08     R4 = EXTRACT \(R2, R1.L\) \(Z\);
29
  1e:   0a c6 10 04     R2 = EXTRACT \(R0, R2.L\) \(Z\);
30
  22:   0a c6 23 4e     R7 = EXTRACT \(R3, R4.L\) \(X\);
31
  26:   0a c6 0e 4a     R5 = EXTRACT \(R6, R1.L\) \(X\);
32
 
33
0000002a :
34
  2a:   08 c6 08 00     BITMUX \(R1, R0, A0\) \(ASR\);
35
  2e:   08 c6 13 00     BITMUX \(R2, R3, A0\) \(ASR\);
36
  32:   08 c6 25 40     BITMUX \(R4, R5, A0\) \(ASL\);
37
  36:   08 c6 3e 40     BITMUX \(R7, R6, A0\) \(ASL\);
38
 
39
0000003a :
40
  3a:   06 c6 00 ca     R5.L = ONES R0;
41
  3e:   06 c6 02 ce     R7.L = ONES R2;
42
        ...

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.