OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [iq2000/] [yield2.s] - Blame information for rev 156

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
# This test case includes a single case of a yield instruction
2
# (e.g. SLEEP) appearing in the branch delay slot.  We expect
3
# the assembler to issue a warning about this!
4
 
5
.text
6
        sleep
7
        beq %0, %0, foo
8
        # sleep insn in the branch delay slot.
9
        sleep
10
foo:    nop

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.