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[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [m32r/] [m32r2.d] - Blame information for rev 438

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Line No. Rev Author Line
1 38 julius
#as: -m32r2
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#objdump: -dr
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#name: m32r2
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.*: +file format .*
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Disassembly of section .text:
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0+0000 :
10
   0:   71 c1 71 ff     setpsw #0xc1 -> setpsw #0xff
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0+0004 :
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   4:   72 c1 72 ff     clrpsw #0xc1 -> clrpsw #0xff
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0+0008 :
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   8:   a0 61 00 04     bset #0x0,@\(4,r1\)
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   c:   a1 61 00 04     bset #0x1,@\(4,r1\)
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  10:   a7 61 00 04     bset #0x7,@\(4,r1\)
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0+0014 :
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  14:   a0 71 00 04     bclr #0x0,@\(4,r1\)
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  18:   a1 71 00 04     bclr #0x1,@\(4,r1\)
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  1c:   a7 71 00 04     bclr #0x7,@\(4,r1\)
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0+0020 :
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  20:   00 fd 01 fd     btst #0x0,fp -> btst #0x1,fp
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  24:   07 fd f0 00     btst #0x7,fp \|\| nop
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  28:   01 fd 90 82     btst #0x1,fp \|\| mv r0,r2
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  2c:   01 fd 90 82     btst #0x1,fp \|\| mv r0,r2
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0+0030 :
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  30:   9d 1d 00 10     divuh fp,fp
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0+0034 :
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  34:   9d 0d 00 18     divb fp,fp
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0+0038 :
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  38:   9d 1d 00 18     divub fp,fp
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0+003c :
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  3c:   9d 2d 00 10     remh fp,fp
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0+0040 :
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  40:   9d 3d 00 10     remuh fp,fp
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0+0044 :
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  44:   9d 2d 00 18     remb fp,fp
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0+0048 :
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  48:   9d 3d 00 18     remub fp,fp
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0+004c :
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  4c:   10 41 92 43     sll r0,r1 \|\| sll r2,r3
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  50:   12 43 90 61     sll r2,r3 \|\| mul r0,r1
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  54:   10 41 92 63     sll r0,r1 \|\| mul r2,r3
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  58:   60 01 92 43     ldi r0,#1 \|\| sll r2,r3
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  5c:   10 41 e2 01     sll r0,r1 \|\| ldi r2,#1
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0+0060 :
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  60:   50 41 d2 5f     slli r0,#0x1 \|\| slli r2,#0x1f
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  64:   52 5f 90 61     slli r2,#0x1f \|\| mul r0,r1
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  68:   50 41 92 63     slli r0,#0x1 \|\| mul r2,r3
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  6c:   60 01 d2 5f     ldi r0,#1 \|\| slli r2,#0x1f
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  70:   50 41 e2 01     slli r0,#0x1 \|\| ldi r2,#1
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0+0074 :
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  74:   10 21 92 23     sra r0,r1 \|\| sra r2,r3
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  78:   12 23 90 61     sra r2,r3 \|\| mul r0,r1
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  7c:   10 21 92 63     sra r0,r1 \|\| mul r2,r3
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  80:   60 01 92 23     ldi r0,#1 \|\| sra r2,r3
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  84:   10 21 e2 01     sra r0,r1 \|\| ldi r2,#1
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0+0088 :
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  88:   50 21 d2 3f     srai r0,#0x1 \|\| srai r2,#0x1f
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  8c:   52 3f 90 61     srai r2,#0x1f \|\| mul r0,r1
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  90:   50 21 92 63     srai r0,#0x1 \|\| mul r2,r3
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  94:   60 01 d2 3f     ldi r0,#1 \|\| srai r2,#0x1f
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  98:   50 21 e2 01     srai r0,#0x1 \|\| ldi r2,#1
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0+009c :
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  9c:   10 01 92 03     srl r0,r1 \|\| srl r2,r3
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  a0:   12 03 90 61     srl r2,r3 \|\| mul r0,r1
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  a4:   10 01 92 63     srl r0,r1 \|\| mul r2,r3
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  a8:   60 01 92 03     ldi r0,#1 \|\| srl r2,r3
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  ac:   10 01 e2 01     srl r0,r1 \|\| ldi r2,#1
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0+00b0 :
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  b0:   50 01 d2 1f     srli r0,#0x1 \|\| srli r2,#0x1f
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  b4:   52 1f 90 61     srli r2,#0x1f \|\| mul r0,r1
90
  b8:   50 01 92 63     srli r0,#0x1 \|\| mul r2,r3
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  bc:   60 01 d2 1f     ldi r0,#1 \|\| srli r2,#0x1f
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  c0:   50 01 e2 01     srli r0,#0x1 \|\| ldi r2,#1

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