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[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [m68hc11/] [insns-dwarf2.d] - Blame information for rev 156

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1 38 julius 
#objdump: -S
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#as: -m68hc11 -gdwarf2
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#name: Dwarf2 test on insns.s
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#source: insns.s
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# Test handling of basic instructions.
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.*: +file format elf32\-m68hc11
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Disassembly of section .text:
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00000000 <_start>:
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#...
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        .globl _start
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        .sect .text
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_start:
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        lds #stack\+1024
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   0:   8e 04 00        lds     #400
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        ldx #1
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   3:   ce 00 01        ldx     #1 <_start\+0x1>
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0+06 :
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Loop:
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        jsr test
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   6:   bd 00 00        jsr     0 <_start>
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        dex
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   9:   09              dex
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        bne Loop
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   a:   26 fa           bne     6
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0000000c :
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   c:   cd 03           .byte   0xcd, 0x03
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Stop:
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        .byte 0xcd
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        .byte 3
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        bra _start
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   e:   20 f0           bra     0 <_start>
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00000010 :
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test:
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        ldd #2
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  10:   cc 00 02        ldd     #2 <_start\+0x2>
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        jsr test2
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  13:   bd 00 00        jsr     0 <_start>
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        rts
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  16:   39              rts
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00000017 :
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D_low = 50
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value = 23
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        .globl test2
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test2:
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        ldx value,y
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  17:   cd ee 17        ldx     23,y
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        std value,x
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  1a:   ed 17           std     23,x
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        ldd ,x
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  1c:   ec 00           ldd     0,x
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        sty ,y
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  1e:   18 ef 00        sty     0,y
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        stx ,y
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  21:   cd ef 00        stx     0,y
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        brclr 6,x,#4,test2
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  24:   1f 06 04 ef     brclr   6,x #\$04 17
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        brclr 12,x #8 test2
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  28:   1f 0c 08 eb     brclr   12,x #\$08 17
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        ldd \*ZD1
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  2c:   dc 00           ldd     \*0 <_start>
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        ldx \*ZD1\+2
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  2e:   de 02           ldx     \*2 <_start\+0x2>
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        clr \*ZD2
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  30:   7f 00 00        clr     0 <_start>
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        clr \*ZD2\+1
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  33:   7f 00 01        clr     1 <_start\+0x1>
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        bne .-4
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  36:   26 fc           bne     34
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        beq .\+2
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  38:   27 02           beq     3c
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        bclr \*ZD1\+1, #32
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  3a:   15 01 20        bclr    \*1 <_start\+0x1> #\$20
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        brclr \*ZD2\+2, #40, test2
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  3d:   13 02 28 d6     brclr   \*2 <_start\+0x2> #\$28 17
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        ldy #24\+_start-44
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  41:   18 ce ff ec     ldy     #ffec
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        ldd B_low,y
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  45:   18 ec 0c        ldd     12,y
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        addd A_low,y
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  48:   18 e3 2c        addd    44,y
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        addd D_low,y
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  4b:   18 e3 32        addd    50,y
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        subd A_low
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  4e:   b3 00 2c        subd    2c
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        subd #A_low
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  51:   83 00 2c        subd    #2c
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        jmp Stop
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  54:   7e 00 00        jmp     0 <_start>
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00000057 :
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L1:
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        anda #%lo\(test2\)
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  57:   84 17           anda    #23
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        andb #%hi\(test2\)
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  59:   c4 00           andb    #0
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        ldab #%page\(test2\)    ; Check that the relocs are against symbol
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  5b:   c6 00           ldab    #0
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        ldy  #%addr\(test2\)    ; otherwise linker relaxation fails
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  5d:   18 ce 00 00     ldy     #0 <_start>
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        rts
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  61:   39              rts

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