OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [ppc/] [test1elf32.d] - Blame information for rev 156

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
#objdump: -Drx
2
#name: PowerPC Test 1, 32 bit elf
3
 
4
.*: +file format elf32-powerpc
5
.*
6
architecture: powerpc:common, flags 0x00000011:
7
HAS_RELOC, HAS_SYMS
8
start address 0x00000000
9
 
10
Sections:
11
Idx Name +Size +VMA +LMA +File off +Algn
12
 
13
 +CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
14
  1 \.data +00000018  0+0000  0+0000  .*
15
 +CONTENTS, ALLOC, LOAD, RELOC, DATA
16
  2 \.bss  +00000000  0+0000  0+0000  .*
17
 +ALLOC
18
SYMBOL TABLE:
19
0+0000 l    d  \.text   0+0000 (|\.text)
20
0+0000 l    d  \.data   0+0000 (|\.data)
21
0+0000 l    d  \.bss    0+0000 (|\.bss)
22
0+0000 l       \.data   0+0000 dsym0
23
0+0004 l       \.data   0+0000 dsym1
24
0+0004 l       \.data   0+0000 usym0
25
0+0008 l       \.data   0+0000 usym1
26
0+0008 l       \.data   0+0000 datpt
27
0+000c l       \.data   0+0000 dat0
28
0+0010 l       \.data   0+0000 dat1
29
0+0014 l       \.data   0+0000 dat2
30
0+0000         \*UND\*  0+0000 esym0
31
0+0000         \*UND\*  0+0000 esym1
32
0+0000         \*UND\*  0+0000 jk
33
 
34
 
35
Disassembly of section \.text:
36
 
37
0+0000 <\.text>:
38
   0:   80 63 00 00     lwz     r3,0\(r3\)
39
                        2: R_PPC_ADDR16_LO      \.data
40
   4:   80 63 00 04     lwz     r3,4\(r3\)
41
                        6: R_PPC_ADDR16_LO      \.data\+0x4
42
   8:   80 63 00 04     lwz     r3,4\(r3\)
43
                        a: R_PPC_ADDR16_LO      \.data\+0x4
44
   c:   80 63 00 08     lwz     r3,8\(r3\)
45
                        e: R_PPC_ADDR16_LO      \.data\+0x8
46
  10:   80 63 00 00     lwz     r3,0\(r3\)
47
                        12: R_PPC_ADDR16_LO     esym0
48
  14:   80 63 00 00     lwz     r3,0\(r3\)
49
                        16: R_PPC_ADDR16_LO     esym1
50
  18:   38 60 00 04     li      r3,4
51
  1c:   38 60 ff fc     li      r3,-4
52
  20:   38 60 00 04     li      r3,4
53
  24:   38 60 ff fc     li      r3,-4
54
  28:   38 60 ff fc     li      r3,-4
55
  2c:   38 60 00 04     li      r3,4
56
  30:   38 60 00 00     li      r3,0
57
                        32: R_PPC_ADDR16_LO     \.data
58
  34:   38 60 00 00     li      r3,0
59
                        36: R_PPC_ADDR16_HI     \.data
60
  38:   38 60 00 00     li      r3,0
61
                        3a: R_PPC_ADDR16_HA     \.data
62
  3c:   38 60 ff fc     li      r3,-4
63
  40:   38 60 ff ff     li      r3,-1
64
  44:   38 60 00 00     li      r3,0
65
  48:   80 64 00 04     lwz     r3,4\(r4\)
66
  4c:   80 60 00 00     lwz     r3,0\(0\)
67
                        4e: R_PPC_ADDR16_LO     \.text
68
Disassembly of section \.data:
69
 
70
0+0000 :
71
   0:   de ad be ef     stfdu   f21,-16657\(r13\)
72
 
73
0+0004 :
74
   4:   ca fe ba be     lfd     f23,-17730\(r30\)
75
 
76
0+0008 :
77
   8:   00 98 96 80     \.long 0x989680
78
                        8: R_PPC_REL32  jk\+0x989680
79
 
80
0+000c :
81
   c:   ff ff ff fc     fnmsub  f31,f31,f31,f31
82
                        c: R_PPC_REL32  jk\+0xf+fffc
83
 
84
0+0010 :
85
  10:   00 00 00 00     \.long 0x0
86
                        10: R_PPC_REL32 jk
87
 
88
0+0014 :
89
  14:   00 00 00 04     \.long 0x4
90
                        14: R_PPC_REL32 jk\+0x4

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.