OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [score/] [tcond.s] - Blame information for rev 156

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius 
/*
2 
 * test relax
3 
 * Tcond <-> Tcond!
4 
 * sdbbp <-> sdbbp!
5 
 
6 
 * Author: ligang
7 
 */
8 
 
9 
.macro tran insn32, insn16
10 
/* This block transform 32b instruction to 16b. */
11 
.align 4
12 
 
13 
  \insn32               #32b -> 16b
14 
  \insn16
15 
 
16 
  \insn32               #32b -> 16b
17 
  \insn32               #32b -> 16b
18 
 
19 
  \insn16
20 
  \insn32               #32b -> 16b
21 
 
22 
  \insn32               #No transform
23 
  add r18, r20, r24
24 
 
25 
/* This block transform 16b instruction to 32b. */
26 
.align 4
27 
 
28 
  \insn16               #No transform
29 
  \insn32
30 
 
31 
  \insn16               #No transform
32 
  \insn16
33 
 
34 
  \insn16               #16b -> 32b
35 
  xor r18, r20, r24
36 
 
37 
.endm
38 
 
39 
  tran "tset", "tset!"
40 
  tran "tcs",  "tcs!"
41 
  tran "tcc",  "tcc!"
42 
  tran "tgtu", "tgtu!"
43 
  tran "tleu", "tleu!"
44 
  tran "teq",  "teq!"
45 
  tran "tne",  "tne!"
46 
  tran "tgt",  "tgt!"
47 
  tran "tle",  "tle!"
48 
  tran "tge",  "tge!"
49 
  tran "tlt",  "tlt!"
50 
  tran "tmi",  "tmi!"
51 
  tran "tpl",  "tpl!"
52 
  tran "tvs",  "tvs!"
53 
  tran "tvc",  "tvc!"
54 
  tran "tcnz", "tcnz!"
55 
  tran "sdbbp 12", "sdbbp! 12"

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.