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[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [include/] [opcode/] [ChangeLog] - Blame information for rev 156

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Line No. Rev Author Line
1 38 julius
2008-04-28  Adam Nemet  
2
 
3
        * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
4
        (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
5
 
6
2008-04-14  Edmar Wienskoski  
7
 
8
        * ppc.h: (PPC_OPCODE_E500MC): New.
9
 
10
2008-04-03  H.J. Lu  
11
 
12
        * i386.h (MAX_OPERANDS): Set to 5.
13
        (MAX_MNEM_SIZE): Changed to 20.
14
 
15
2008-03-28  Eric B. Weddington  
16
 
17
        * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
18
 
19
2008-03-09  Paul Brook  
20
 
21
        * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
22
 
23
2008-03-04  Paul Brook  
24
 
25
        * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
26
        (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
27
        (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
28
 
29
2008-02-27  Denis Vlasenko  
30
            Nick Clifton  
31
 
32
        PR 3134
33
        * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
34
        with a 32-bit displacement but without the top bit of the 4th byte
35
        set.
36
 
37
2008-02-18  M R Swami Reddy 
38
 
39
        * cr16.h (cr16_num_optab): Declared.
40
 
41
2008-02-14  Hakan Ardo  
42
 
43
        PR gas/2626
44
        * avr.h (AVR_ISA_2xxe): Define.
45
 
46
2008-02-04  Adam Nemet  
47
 
48
        * mips.h: Update copyright.
49
        (INSN_CHIP_MASK): New macro.
50
        (INSN_OCTEON): New macro.
51
        (CPU_OCTEON): New macro.
52
        (OPCODE_IS_MEMBER): Handle Octeon instructions.
53
 
54
2008-01-23  Eric B. Weddington  
55
 
56
        * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
57
 
58
2008-01-03  Eric B. Weddington  
59
 
60
        * avr.h (AVR_ISA_USB162): Add new opcode set.
61
        (AVR_ISA_AVR3): Likewise.
62
 
63
2007-11-29  Mark Shinwell  
64
 
65
        * mips.h (INSN_LOONGSON_2E): New.
66
        (INSN_LOONGSON_2F): New.
67
        (CPU_LOONGSON_2E): New.
68
        (CPU_LOONGSON_2F): New.
69
        (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
70
 
71
2007-11-29  Mark Shinwell  
72
 
73
        * mips.h (INSN_ISA*): Redefine certain values as an
74
        enumeration.  Update comments.
75
        (mips_isa_table): New.
76
        (ISA_MIPS*): Redefine to match enumeration.
77
        (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
78
        values.
79
 
80
2007-08-08  Ben Elliston  
81
 
82
        * ppc.h (PPC_OPCODE_PPCPS): New.
83
 
84
2007-07-03  Nathan Sidwell  
85
 
86
        * m68k.h: Document j K & E.
87
 
88
2007-06-29  M R Swami Reddy  
89
 
90
        * cr16.h: New file for CR16 target.
91
 
92
2007-05-02  Alan Modra  
93
 
94
        * ppc.h (PPC_OPERAND_PLUS1): Update comment.
95
 
96
2007-04-23  Nathan Sidwell  
97
 
98
        * m68k.h (mcfisa_c): New.
99
        (mcfusp, mcf_mask): Adjust.
100
 
101
2007-04-20  Alan Modra  
102
 
103
        * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
104
        (num_powerpc_operands): Declare.
105
        (PPC_OPERAND_SIGNED et al): Redefine as hex.
106
        (PPC_OPERAND_PLUS1): Define.
107
 
108
2007-03-21  H.J. Lu  
109
 
110
        * i386.h (REX_MODE64): Renamed to ...
111
        (REX_W): This.
112
        (REX_EXTX): Renamed to ...
113
        (REX_R): This.
114
        (REX_EXTY): Renamed to ...
115
        (REX_X): This.
116
        (REX_EXTZ): Renamed to ...
117
        (REX_B): This.
118
 
119
2007-03-15  H.J. Lu  
120
 
121
        * i386.h: Add entries from config/tc-i386.h and move tables
122
        to opcodes/i386-opc.h.
123
 
124
2007-03-13  H.J. Lu  
125
 
126
        * i386.h (FloatDR): Removed.
127
        (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
128
 
129
2007-03-01  Alan Modra  
130
 
131
        * spu-insns.h: Add soma double-float insns.
132
 
133
2007-02-20  Thiemo Seufer  
134
            Chao-Ying Fu  
135
 
136
        * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
137
        (INSN_DSPR2): Add flag for DSP R2 instructions.
138
        (M_BALIGN): New macro.
139
 
140
2007-02-14  Alan Modra  
141
 
142
        * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
143
        and Seg3ShortFrom with Shortform.
144
 
145
2007-02-11  H.J. Lu  
146
 
147
        PR gas/4027
148
        * i386.h (i386_optab): Put the real "test" before the pseudo
149
        one.
150
 
151
2007-01-08  Kazu Hirata  
152
 
153
        * m68k.h (m68010up): OR fido_a.
154
 
155
2006-12-25  Kazu Hirata  
156
 
157
        * m68k.h (fido_a): New.
158
 
159
2006-12-24  Kazu Hirata  
160
 
161
        * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
162
        mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
163
        values.
164
 
165
2006-11-08  H.J. Lu  
166
 
167
        * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
168
 
169
2006-10-31  Mei Ligang  
170
 
171
        * score-inst.h (enum score_insn_type): Add Insn_internal.
172
 
173
2006-10-25  Trevor Smigiel  
174
            Yukishige Shibata  
175
            Nobuhisa Fujinami  
176
            Takeaki Fukuoka  
177
            Alan Modra  
178
 
179
        * spu-insns.h: New file.
180
        * spu.h: New file.
181
 
182
2006-10-24  Andrew Pinski  
183
 
184
        * ppc.h (PPC_OPCODE_CELL): Define.
185
 
186
2006-10-23  Dwarakanath Rajagopal  
187
 
188
        * i386.h :  Modify opcode to support for the change in POPCNT opcode
189
        in amdfam10 architecture.
190
 
191
2006-09-28  H.J. Lu  
192
 
193
        * i386.h: Replace CpuMNI with CpuSSSE3.
194
 
195
2006-09-26  Mark Shinwell  
196
            Joseph Myers  
197
            Ian Lance Taylor  
198
            Ben Elliston  
199
 
200
        * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
201
 
202
2006-09-17  Mei Ligang  
203
 
204
        * score-datadep.h: New file.
205
        * score-inst.h: New file.
206
 
207
2006-07-14  H.J. Lu  
208
 
209
        * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
210
        movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
211
        movdq2q and movq2dq.
212
 
213
2006-07-10 Dwarakanath Rajagopal        
214
           Michael Meissner             
215
 
216
        * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
217
 
218
2006-06-12  H.J. Lu  
219
 
220
        * i386.h (i386_optab): Add "nop" with memory reference.
221
 
222
2006-06-12  H.J. Lu  
223
 
224
        * i386.h (i386_optab): Update comment for 64bit NOP.
225
 
226
2006-06-06  Ben Elliston  
227
            Anton Blanchard  
228
 
229
        * ppc.h (PPC_OPCODE_POWER6): Define.
230
        Adjust whitespace.
231
 
232
2006-06-05  Thiemo Seufer  
233
 
234
        * mips.h: Improve description of MT flags.
235
 
236
2006-05-25  Richard Sandiford  
237
 
238
        * m68k.h (mcf_mask): Define.
239
 
240
2006-05-05  Thiemo Seufer  
241
            David Ung  
242
 
243
        * mips.h (enum): Add macro M_CACHE_AB.
244
 
245
2006-05-04  Thiemo Seufer  
246
            Nigel Stephens  
247
            David Ung  
248
 
249
        * mips.h: Add INSN_SMARTMIPS define.
250
 
251
2006-04-30  Thiemo Seufer  
252
            David Ung  
253
 
254
        * mips.h: Defines udi bits and masks.  Add description of
255
        characters which may appear in the args field of udi
256
        instructions.
257
 
258
2006-04-26  Thiemo Seufer  
259
 
260
        * mips.h: Improve comments describing the bitfield instruction
261
        fields.
262
 
263
2006-04-26  Julian Brown  
264
 
265
        * arm.h (FPU_VFP_EXT_V3): Define constant.
266
        (FPU_NEON_EXT_V1): Likewise.
267
        (FPU_VFP_HARD): Update.
268
        (FPU_VFP_V3): Define macro.
269
        (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
270
 
271
2006-04-07  Joerg Wunsch  
272
 
273
        * avr.h (AVR_ISA_PWMx): New.
274
 
275
2006-03-28  Nathan Sidwell  
276
 
277
        * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
278
        cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
279
        cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
280
        cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
281
        cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
282
 
283
2006-03-10  Paul Brook  
284
 
285
        * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
286
 
287
2006-03-04  John David Anglin  
288
 
289
        * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
290
        first.  Correct mask of bb "B" opcode.
291
 
292
2006-02-27  H.J. Lu 
293
 
294
        * i386.h (i386_optab): Support Intel Merom New Instructions.
295
 
296
2006-02-24  Paul Brook  
297
 
298
        * arm.h: Add V7 feature bits.
299
 
300
2006-02-23  H.J. Lu  
301
 
302
        * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
303
 
304
2006-01-31  Paul Brook  
305
        Richard Earnshaw 
306
 
307
        * arm.h: Use ARM_CPU_FEATURE.
308
        (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
309
        (arm_feature_set): Change to a structure.
310
        (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
311
        ARM_FEATURE): New macros.
312
 
313
2005-12-07  Hans-Peter Nilsson  
314
 
315
        * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
316
        (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
317
        (ADD_PC_INCR_OPCODE): Don't define.
318
 
319
2005-12-06  H.J. Lu  
320
 
321
        PR gas/1874
322
        * i386.h (i386_optab): Add 64bit support for monitor and mwait.
323
 
324
2005-11-14  David Ung  
325
 
326
        * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
327
        instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
328
        save/restore encoding of the args field.
329
 
330
2005-10-28  Dave Brolley  
331
 
332
        Contribute the following changes:
333
        2005-02-16  Dave Brolley  
334
 
335
        * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
336
        cgen_isa_mask_* to cgen_bitset_*.
337
        * cgen.h: Likewise.
338
 
339
        2003-10-21  Richard Sandiford  
340
 
341
        * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
342
        (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
343
        (CGEN_CPU_TABLE): Make isas a ponter.
344
 
345
        2003-09-29  Dave Brolley  
346
 
347
        * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
348
        (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
349
        (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
350
 
351
        2002-12-13  Dave Brolley  
352
 
353
        * cgen.h (symcat.h): #include it.
354
        (cgen-bitset.h): #include it.
355
        (CGEN_ATTR_VALUE_TYPE): Now a union.
356
        (CGEN_ATTR_VALUE): Reference macros generated in opcodes/-desc.h.
357
        (CGEN_ATTR_ENTRY): 'value' now unsigned.
358
        (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
359
        * cgen-bitset.h: New file.
360
 
361
2005-09-30  Catherine Moore  
362
 
363
        * bfin.h: New file.
364
 
365
2005-10-24  Jan Beulich  
366
 
367
        * ia64.h (enum ia64_opnd): Move memory operand out of set of
368
        indirect operands.
369
 
370
2005-10-16  John David Anglin  
371
 
372
        * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
373
        Add FLAG_STRICT to pa10 ftest opcode.
374
 
375
2005-10-12  John David Anglin  
376
 
377
        * hppa.h (pa_opcodes): Remove lha entries.
378
 
379
2005-10-08  John David Anglin  
380
 
381
        * hppa.h (FLAG_STRICT): Revise comment.
382
        (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
383
        before corresponding pa11 opcodes.  Add strict pa10 register-immediate
384
        entries for "fdc".
385
 
386
2005-09-30  Catherine Moore  
387
 
388
        * bfin.h: New file.
389
 
390
2005-09-24  John David Anglin  
391
 
392
        * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
393
 
394
2005-09-06  Chao-ying Fu  
395
 
396
        * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
397
        OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
398
        define.
399
        Document !, $, *, &, g, +t, +T operand formats for MT instructions.
400
        (INSN_ASE_MASK): Update to include INSN_MT.
401
        (INSN_MT): New define for MT ASE.
402
 
403
2005-08-25  Chao-ying Fu  
404
 
405
        * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
406
        OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
407
        OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
408
        OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
409
        OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
410
        Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
411
        instructions.
412
        (INSN_DSP): New define for DSP ASE.
413
 
414
2005-08-18  Alan Modra  
415
 
416
        * a29k.h: Delete.
417
 
418
2005-08-15  Daniel Jacobowitz  
419
 
420
        * ppc.h (PPC_OPCODE_E300): Define.
421
 
422
2005-08-12 Martin Schwidefsky  
423
 
424
        * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
425
 
426
2005-07-28  John David Anglin  
427
 
428
        PR gas/336
429
        * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
430
        and pitlb.
431
 
432
2005-07-27  Jan Beulich  
433
 
434
        * i386.h (i386_optab): Add comment to movd. Use LongMem for all
435
        movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
436
        Add movq-s as 64-bit variants of movd-s.
437
 
438
2005-07-18  John David Anglin  
439
 
440
        * hppa.h: Fix punctuation in comment.
441
 
442
        * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
443
        implicit space-register addressing.  Set space-register bits on opcodes
444
        using implicit space-register addressing.  Add various missing pa20
445
        long-immediate opcodes.  Remove various opcodes using implicit 3-bit
446
        space-register addressing.  Use "fE" instead of "fe" in various
447
        fstw opcodes.
448
 
449
2005-07-18  Jan Beulich  
450
 
451
        * i386.h (i386_optab): Operands of aam and aad are unsigned.
452
 
453
2007-07-15  H.J. Lu 
454
 
455
        * i386.h (i386_optab): Support Intel VMX Instructions.
456
 
457
2005-07-10  John David Anglin  
458
 
459
        * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
460
 
461
2005-07-05  Jan Beulich  
462
 
463
        * i386.h (i386_optab): Add new insns.
464
 
465
2005-07-01  Nick Clifton  
466
 
467
        * sparc.h: Add typedefs to structure declarations.
468
 
469
2005-06-20  H.J. Lu  
470
 
471
        PR 1013
472
        * i386.h (i386_optab): Update comments for 64bit addressing on
473
        mov. Allow 64bit addressing for mov and movq.
474
 
475
2005-06-11  John David Anglin  
476
 
477
        * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
478
        respectively, in various floating-point load and store patterns.
479
 
480
2005-05-23  John David Anglin  
481
 
482
        * hppa.h (FLAG_STRICT): Correct comment.
483
        (pa_opcodes): Update load and store entries to allow both PA 1.X and
484
        PA 2.0 mneumonics when equivalent.  Entries with cache control
485
        completers now require PA 1.1.  Adjust whitespace.
486
 
487
2005-05-19  Anton Blanchard  
488
 
489
        * ppc.h (PPC_OPCODE_POWER5): Define.
490
 
491
2005-05-10  Nick Clifton  
492
 
493
        * Update the address and phone number of the FSF organization in
494
        the GPL notices in the following files:
495
        a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
496
        crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
497
        i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
498
        mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
499
        pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
500
        tic54x.h, tic80.h, v850.h, vax.h
501
 
502
2005-05-09  Jan Beulich  
503
 
504
        * i386.h (i386_optab): Add ht and hnt.
505
 
506
2005-04-18  Mark Kettenis  
507
 
508
        * i386.h: Insert hyphens into selected VIA PadLock extensions.
509
        Add xcrypt-ctr.  Provide aliases without hyphens.
510
 
511
2005-04-13  H.J. Lu  
512
 
513
        Moved from ../ChangeLog
514
 
515
        2005-04-12  Paul Brook  
516
        * m88k.h: Rename psr macros to avoid conflicts.
517
 
518
        2005-03-12  Zack Weinberg  
519
        * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
520
        Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
521
        and ARM_ARCH_V6ZKT2.
522
 
523
        2004-11-29  Tomer Levi  
524
        * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
525
        Remove redundant instruction types.
526
        (struct argument): X_op - new field.
527
        (struct cst4_entry): Remove.
528
        (no_op_insn): Declare.
529
 
530
        2004-11-05  Tomer Levi  
531
        * crx.h (enum argtype): Rename types, remove unused types.
532
 
533
        2004-10-27  Tomer Levi  
534
        * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
535
        (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
536
        (enum operand_type): Rearrange operands, edit comments.
537
        replace us with ui for unsigned immediate.
538
        replace d with disps/dispu/dispe for signed/unsigned/escaped
539
        displacements (respectively).
540
        replace rbase_ridx_scl2_dispu with rindex_disps for register index.
541
        (instruction type): Add NO_TYPE_INS.
542
        (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
543
        (operand_entry): New field - 'flags'.
544
        (operand flags): New.
545
 
546
        2004-10-21  Tomer Levi  
547
        * crx.h (operand_type): Remove redundant types i3, i4,
548
        i5, i8, i12.
549
        Add new unsigned immediate types us3, us4, us5, us16.
550
 
551
2005-04-12  Mark Kettenis  
552
 
553
        * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
554
        adjust them accordingly.
555
 
556
2005-04-01  Jan Beulich  
557
 
558
        * i386.h (i386_optab): Add rdtscp.
559
 
560
2005-03-29  H.J. Lu  
561
 
562
        * i386.h (i386_optab): Don't allow the `l' suffix for moving
563
        between memory and segment register. Allow movq for moving between
564
        general-purpose register and segment register.
565
 
566
2005-02-09  Jan Beulich  
567
 
568
        PR gas/707
569
        * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
570
        FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
571
        fnstsw.
572
 
573
2006-02-07  Nathan Sidwell  
574
 
575
        * m68k.h (m68008, m68ec030, m68882): Remove.
576
        (m68k_mask): New.
577
        (cpu_m68k, cpu_cf): New.
578
        (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
579
        mcf5470, mcf5480): Rename to cpu_. Add m680x0 variants.
580
 
581
2005-01-25  Alexandre Oliva  
582
 
583
        2004-11-10  Alexandre Oliva  
584
        * cgen.h (enum cgen_parse_operand_type): Add
585
        CGEN_PARSE_OPERAND_SYMBOLIC.
586
 
587
2005-01-21  Fred Fish  
588
 
589
        * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
590
        Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
591
        Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
592
 
593
2005-01-19  Fred Fish  
594
 
595
        * mips.h (struct mips_opcode): Add new pinfo2 member.
596
        (INSN_ALIAS): New define for opcode table entries that are
597
        specific instances of another entry, such as 'move' for an 'or'
598
        with a zero operand.
599
        (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
600
        (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
601
 
602
2004-12-09  Ian Lance Taylor  
603
 
604
        * mips.h (CPU_RM9000): Define.
605
        (OPCODE_IS_MEMBER): Handle CPU_RM9000.
606
 
607
2004-11-25 Jan Beulich  
608
 
609
        * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
610
        to/from test registers are illegal in 64-bit mode. Add missing
611
        NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
612
        (previously one had to explicitly encode a rex64 prefix). Re-enable
613
        lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
614
        support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
615
 
616
2004-11-23 Jan Beulich  
617
 
618
        * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
619
        available only with SSE2. Change the MMX additions introduced by SSE
620
        and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
621
        instructions by their now designated identifier (since combining i686
622
        and 3DNow! does not really imply 3DNow!A).
623
 
624
2004-11-19  Alan Modra  
625
 
626
        * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
627
        struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
628
 
629
2004-11-08  Inderpreet Singh   
630
            Vineet Sharma      
631
 
632
        * maxq.h: New file: Disassembly information for the maxq port.
633
 
634
2004-11-05  H.J. Lu  
635
 
636
        * i386.h (i386_optab): Put back "movzb".
637
 
638
2004-11-04  Hans-Peter Nilsson  
639
 
640
        * cris.h (enum cris_insn_version_usage): Tweak formatting and
641
        comments.  Remove member cris_ver_sim.  Add members
642
        cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
643
        cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
644
        (struct cris_support_reg, struct cris_cond15): New types.
645
        (cris_conds15): Declare.
646
        (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
647
        (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
648
        (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
649
        (NOP_Z_BITS): Define in terms of NOP_OPCODE.
650
        (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
651
        SIZE_FIELD_UNSIGNED.
652
 
653
2004-11-04 Jan Beulich  
654
 
655
        * i386.h (sldx_Suf): Remove.
656
        (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
657
        (q_FP): Define, implying no REX64.
658
        (x_FP, sl_FP): Imply FloatMF.
659
        (i386_optab): Split reg and mem forms of moving from segment registers
660
        so that the memory forms can ignore the 16-/32-bit operand size
661
        distinction. Adjust a few others for Intel mode. Remove *FP uses from
662
        all non-floating-point instructions. Unite 32- and 64-bit forms of
663
        movsx, movzx, and movd. Adjust floating point operations for the above
664
        changes to the *FP macros. Add DefaultSize to floating point control
665
        insns operating on larger memory ranges. Remove left over comments
666
        hinting at certain insns being Intel-syntax ones where the ones
667
        actually meant are already gone.
668
 
669
2004-10-07  Tomer Levi  
670
 
671
        * crx.h: Add COPS_REG_INS - Coprocessor Special register
672
        instruction type.
673
 
674
2004-09-30  Paul Brook  
675
 
676
        * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
677
        (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
678
 
679
2004-09-11  Theodore A. Roth  
680
 
681
        * avr.h: Add support for
682
        atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
683
 
684
2004-09-09  Segher Boessenkool  
685
 
686
        * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
687
 
688
2004-08-24  Dmitry Diky  
689
 
690
        * msp430.h (msp430_opc): Add new instructions.
691
        (msp430_rcodes): Declare new instructions.
692
        (msp430_hcodes): Likewise..
693
 
694
2004-08-13  Nick Clifton  
695
 
696
        PR/301
697
        * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
698
        processors.
699
 
700
2004-08-30  Michal Ludvig  
701
 
702
        * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
703
 
704
2004-07-22  H.J. Lu  
705
 
706
        * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
707
 
708
2004-07-21  Jan Beulich  
709
 
710
        * i386.h: Adjust instruction descriptions to better match the
711
        specification.
712
 
713
2004-07-16  Richard Earnshaw  
714
 
715
        * arm.h: Remove all old content.  Replace with architecture defines
716
        from gas/config/tc-arm.c.
717
 
718
2004-07-09  Andreas Schwab  
719
 
720
        * m68k.h: Fix comment.
721
 
722
2004-07-07  Tomer Levi  
723
 
724
        * crx.h: New file.
725
 
726
2004-06-24  Alan Modra  
727
 
728
        * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
729
 
730
2004-05-24  Peter Barada  
731
 
732
        * m68k.h: Add 'size' to m68k_opcode.
733
 
734
2004-05-05  Peter Barada  
735
 
736
        * m68k.h: Switch from ColdFire chip name to core variant.
737
 
738
2004-04-22  Peter Barada  
739
 
740
        * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
741
        descriptions for new EMAC cases.
742
        Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
743
        handle Motorola MAC syntax.
744
        Allow disassembly of ColdFire V4e object files.
745
 
746
2004-03-16  Alan Modra  
747
 
748
        * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
749
 
750
2004-03-12  Jakub Jelinek  
751
 
752
        * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
753
 
754
2004-03-12  Michal Ludvig  
755
 
756
        * i386.h (i386_optab): Added xstore as an alias for xstorerng.
757
 
758
2004-03-12  Michal Ludvig  
759
 
760
        * i386.h (i386_optab): Added xstore/xcrypt insns.
761
 
762
2004-02-09  Anil Paranjpe  
763
 
764
        * h8300.h (32bit ldc/stc): Add relaxing support.
765
 
766
2004-01-12  Anil Paranjpe  
767
 
768
        * h8300.h (BITOP): Pass MEMRELAX flag.
769
 
770
2004-01-09  Anil Paranjpe  
771
 
772
        * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
773
        except for the H8S.
774
 
775
For older changes see ChangeLog-9103
776
 
777
Local Variables:
778
mode: change-log
779
left-margin: 8
780
fill-column: 74
781
version-control: never
782
End:

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