OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [ld/] [testsuite/] [ld-sh/] [vxworks1-lib-le.dd] - Blame information for rev 262

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius 
 
2 
.*:     file format .*
3 
 
4 
Disassembly of section \.plt:
5 
 
6 
00080800 <_PROCEDURE_LINKAGE_TABLE_>:
7 
   80800:       01 d0           mov\.l  80808 <_PROCEDURE_LINKAGE_TABLE_\+0x8>,r0       ! c
8 
   80802:       ce 00           mov\.l  @\(r0,r12\),r0
9 
   80804:       2b 40           jmp     @r0
10 
   80806:       09 00           nop
11 
   80808:       0c 00 .*
12 
   8080a:       00 00 .*
13 
   8080c:       01 d0           mov\.l  80814 <_PROCEDURE_LINKAGE_TABLE_\+0x14>,r0       ! 0
14 
   8080e:       c2 51           mov\.l  @\(8,r12\),r1
15 
   80810:       2b 41           jmp     @r1
16 
   80812:       09 00           nop
17 
   80814:       00 00 .*
18 
        \.\.\.
19 
 
20 
00080818 <_sexternal@plt>:
21 
   80818:       01 d0           mov\.l  80820 <_sexternal@plt\+0x8>,r0       ! 10
22 
   8081a:       ce 00           mov\.l  @\(r0,r12\),r0
23 
   8081c:       2b 40           jmp     @r0
24 
   8081e:       09 00           nop
25 
   80820:       10 00 .*
26 
   80822:       00 00 .*
27 
   80824:       01 d0           mov\.l  8082c <_sexternal@plt\+0x14>,r0       ! c
28 
   80826:       c2 51           mov\.l  @\(8,r12\),r1
29 
   80828:       2b 41           jmp     @r1
30 
   8082a:       09 00           nop
31 
   8082c:       0c 00 .*
32 
        \.\.\.
33 
Disassembly of section \.text:
34 
 
35 
00080c00 <_foo>:
36 
   80c00:       c6 2f           mov\.l  r12,@-r15
37 
   80c02:       22 4f           sts\.l  pr,@-r15
38 
   80c04:       0a dc           mov\.l  80c30 <_foo\+0x30>,r12      ! 0
39 
   80c06:       c2 6c           mov\.l  @r12,r12
40 
   80c08:       0a d0           mov\.l  80c34 <_foo\+0x34>,r0       ! 0
41 
   80c0a:       ce 0c           mov\.l  @\(r0,r12\),r12
42 
   80c0c:       0a d0           mov\.l  80c38 <_foo\+0x38>,r0       ! 14
43 
   80c0e:       ce 01           mov\.l  @\(r0,r12\),r1
44 
   80c10:       12 62           mov\.l  @r1,r2
45 
   80c12:       01 72           add     #1,r2
46 
   80c14:       22 21           mov\.l  r2,@r1
47 
   80c16:       09 d0           mov\.l  80c3c <_foo\+0x3c>,r0       ! 2c
48 
   80c18:       03 00           bsrf    r0
49 
   80c1a:       09 00           nop
50 
   80c1c:       08 d0           mov\.l  80c40 <_foo\+0x40>,r0       ! fffffbde
51 
   80c1e:       03 00           bsrf    r0
52 
   80c20:       09 00           nop
53 
   80c22:       08 d0           mov\.l  80c44 <_foo\+0x44>,r0       ! fffffbf0
54 
   80c24:       03 00           bsrf    r0
55 
   80c26:       09 00           nop
56 
   80c28:       26 4f           lds\.l  @r15\+,pr
57 
   80c2a:       0b 00           rts
58 
   80c2c:       f6 6c           mov\.l  @r15\+,r12
59 
   80c2e:       09 00           nop
60 
        ...
61 
   80c38:       14 00 .*
62 
   80c3a:       00 00 .*
63 
   80c3c:       2c 00 .*
64 
   80c3e:       00 00 .*
65 
   80c40:       de fb .*
66 
   80c42:       ff ff .*
67 
   80c44:       f0 fb .*
68 
   80c46:       ff ff .*
69 
 
70 
00080c48 <_slocal>:
71 
   80c48:       0b 00           rts
72 
   80c4a:       09 00           nop
73 
 
74 
00080c4c <_sglobal>:
75 
   80c4c:       0b 00           rts
76 
   80c4e:       09 00           nop

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.