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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [ld/] [testsuite/] [ld-sh/] [vxworks1-lib.dd] - Blame information for rev 38

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Line No. Rev Author Line
1 38 julius 
 
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.*:     file format .*
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Disassembly of section \.plt:
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00080800 <_PROCEDURE_LINKAGE_TABLE_>:
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   80800:       d0 01           mov\.l  80808 <_PROCEDURE_LINKAGE_TABLE_\+0x8>,r0       ! c
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   80802:       00 ce           mov\.l  @\(r0,r12\),r0
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   80804:       40 2b           jmp     @r0
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   80806:       00 09           nop
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   80808:       00 00 .*
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   8080a:       00 0c .*
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   8080c:       d0 01           mov\.l  80814 <_PROCEDURE_LINKAGE_TABLE_\+0x14>,r0       ! 0
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   8080e:       51 c2           mov\.l  @\(8,r12\),r1
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   80810:       41 2b           jmp     @r1
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   80812:       00 09           nop
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   80814:       00 00 .*
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        \.\.\.
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00080818 <_sexternal@plt>:
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   80818:       d0 01           mov\.l  80820 <_sexternal@plt\+0x8>,r0       ! 10
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   8081a:       00 ce           mov\.l  @\(r0,r12\),r0
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   8081c:       40 2b           jmp     @r0
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   8081e:       00 09           nop
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   80820:       00 00 .*
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   80822:       00 10 .*
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   80824:       d0 01           mov\.l  8082c <_sexternal@plt\+0x14>,r0       ! c
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   80826:       51 c2           mov\.l  @\(8,r12\),r1
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   80828:       41 2b           jmp     @r1
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   8082a:       00 09           nop
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   8082c:       00 00 .*
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   8082e:       00 0c .*
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Disassembly of section \.text:
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00080c00 <_foo>:
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   80c00:       2f c6           mov\.l  r12,@-r15
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   80c02:       4f 22           sts\.l  pr,@-r15
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   80c04:       dc 0a           mov\.l  80c30 <_foo\+0x30>,r12      ! 0
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   80c06:       6c c2           mov\.l  @r12,r12
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   80c08:       d0 0a           mov\.l  80c34 <_foo\+0x34>,r0       ! 0
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   80c0a:       0c ce           mov\.l  @\(r0,r12\),r12
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   80c0c:       d0 0a           mov\.l  80c38 <_foo\+0x38>,r0       ! 14
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   80c0e:       01 ce           mov\.l  @\(r0,r12\),r1
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   80c10:       62 12           mov\.l  @r1,r2
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   80c12:       72 01           add     #1,r2
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   80c14:       21 22           mov\.l  r2,@r1
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   80c16:       d0 09           mov\.l  80c3c <_foo\+0x3c>,r0       ! 2c
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   80c18:       00 03           bsrf    r0
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   80c1a:       00 09           nop
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   80c1c:       d0 08           mov\.l  80c40 <_foo\+0x40>,r0       ! fffffbde
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   80c1e:       00 03           bsrf    r0
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   80c20:       00 09           nop
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   80c22:       d0 08           mov\.l  80c44 <_foo\+0x44>,r0       ! fffffbf0
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   80c24:       00 03           bsrf    r0
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   80c26:       00 09           nop
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   80c28:       4f 26           lds\.l  @r15\+,pr
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   80c2a:       00 0b           rts
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   80c2c:       6c f6           mov\.l  @r15\+,r12
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   80c2e:       00 09           nop
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        ...
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   80c38:       00 00 .*
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   80c3a:       00 14 .*
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   80c3c:       00 00 .*
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   80c3e:       00 2c .*
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   80c40:       ff ff .*
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   80c42:       fb de .*
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   80c44:       ff ff .*
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   80c46:       fb f0 .*
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00080c48 <_slocal>:
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   80c48:       00 0b           rts
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   80c4a:       00 09           nop
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00080c4c <_sglobal>:
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   80c4c:       00 0b           rts
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   80c4e:       00 09           nop

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