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[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [opcodes/] [bfin-dis.c] - Blame information for rev 221

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1 38 julius 
/* Disassemble ADI Blackfin Instructions.
2 
   Copyright 2005, 2007 Free Software Foundation, Inc.
3 
 
4 
   This file is part of libopcodes.
5 
 
6 
   This library is free software; you can redistribute it and/or modify
7 
   it under the terms of the GNU General Public License as published by
8 
   the Free Software Foundation; either version 3, or (at your option)
9 
   any later version.
10 
 
11 
   It is distributed in the hope that it will be useful, but WITHOUT
12 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14 
   License for more details.
15 
 
16 
   You should have received a copy of the GNU General Public License
17 
   along with this program; if not, write to the Free Software
18 
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 
   MA 02110-1301, USA.  */
20 
 
21 
#include <stdio.h>
22 
#include <stdlib.h>
23 
#include <string.h>
24 
 
25 
#include "opcode/bfin.h"
26 
 
27 
#define M_S2RND 1
28 
#define M_T     2
29 
#define M_W32   3
30 
#define M_FU    4
31 
#define M_TFU   6
32 
#define M_IS    8
33 
#define M_ISS2  9
34 
#define M_IH    11
35 
#define M_IU    12
36 
 
37 
#ifndef PRINTF
38 
#define PRINTF printf
39 
#endif
40 
 
41 
#ifndef EXIT
42 
#define EXIT exit
43 
#endif
44 
 
45 
typedef long TIword;
46 
 
47 
#define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
48 
#define XFIELD(w,p,s)       (((w) & ((1 << (s)) - 1) << (p)) >> (p))
49 
#define SIGNEXTEND(v, n)    ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
50 
#define MASKBITS(val, bits) (val & ((1 << bits) - 1))
51 
 
52 
#include "dis-asm.h"
53 
 
54 
typedef unsigned int bu32;
55 
 
56 
typedef enum
57 
{
58 
  c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
59 
  c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
60 
  c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
61 
  c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
62 
  c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
63 
} const_forms_t;
64 
 
65 
static struct
66 
{
67 
  char *name;
68 
  int nbits;
69 
  char reloc;
70 
  char issigned;
71 
  char pcrel;
72 
  char scale;
73 
  char offset;
74 
  char negative;
75 
  char positive;
76 
  char decimal;
77 
  char leading;
78 
  char exact;
79 
} constant_formats[] =
80 
{
81 
  { "0",          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
82 
  { "1",          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
83 
  { "4",          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
84 
  { "2",          0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
85 
  { "uimm2",      2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
86 
  { "uimm3",      3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
87 
  { "imm3",       3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
88 
  { "pcrel4",     4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
89 
  { "imm4",       4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
90 
  { "uimm4s4",    4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
91 
  { "uimm4s4d",   4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
92 
  { "uimm4",      4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
93 
  { "uimm4s2",    4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
94 
  { "negimm5s4",  5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
95 
  { "imm5",       5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
96 
  { "imm5d",      5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
97 
  { "uimm5",      5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
98 
  { "imm6",       6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
99 
  { "imm7",       7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
100 
  { "imm7d",      7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
101 
  { "imm8",       8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
102 
  { "uimm8",      8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
103 
  { "pcrel8",     8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
104 
  { "uimm8s4",    8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
105 
  { "pcrel8s4",   8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
106 
  { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
107 
  { "pcrel10",   10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
108 
  { "pcrel12",   12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
109 
  { "imm16s4",   16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
110 
  { "luimm16",   16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
111 
  { "imm16",     16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
112 
  { "imm16d",    16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
113 
  { "huimm16",   16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
114 
  { "rimm16",    16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
115 
  { "imm16s2",   16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
116 
  { "uimm16s4",  16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
117 
  { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
118 
  { "uimm16",    16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
119 
  { "pcrel24",   24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
120 
  { "uimm32",    32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
121 
  { "imm32",     32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
122 
  { "huimm32",   32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
123 
  { "huimm32e",  32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
124 
};
125 
 
126 
int _print_insn_bfin (bfd_vma pc, disassemble_info * outf);
127 
int print_insn_bfin (bfd_vma pc, disassemble_info * outf);
128 
 
129 
static char comment = 0;
130 
static char parallel = 0;
131 
 
132 
static char *
133 
fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info * outf)
134 
{
135 
  static char buf[60];
136 
 
137 
  if (constant_formats[cf].reloc)
138 
    {
139 
      bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
140 
                      : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
141 
      if (constant_formats[cf].pcrel)
142 
        ea += pc;
143 
 
144 
     if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
145 
       {
146 
          outf->print_address_func (ea, outf);
147 
          return "";
148 
       }
149 
     else
150 
       {
151 
          sprintf (buf, "%lx", x);
152 
          return buf;
153 
       }
154 
    }
155 
 
156 
  /* Negative constants have an implied sign bit.  */
157 
  if (constant_formats[cf].negative)
158 
    {
159 
      int nb = constant_formats[cf].nbits + 1;
160 
 
161 
      x = x | (1 << constant_formats[cf].nbits);
162 
      x = SIGNEXTEND (x, nb);
163 
    }
164 
  else
165 
    x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
166 
 
167 
  if (constant_formats[cf].offset)
168 
    x += constant_formats[cf].offset;
169 
 
170 
  if (constant_formats[cf].scale)
171 
    x <<= constant_formats[cf].scale;
172 
 
173 
  if (constant_formats[cf].decimal)
174 
    {
175 
      if (constant_formats[cf].leading)
176 
        {
177 
          char ps[10];
178 
          sprintf (ps, "%%%ii", constant_formats[cf].leading);
179 
          sprintf (buf, ps, x);
180 
        }
181 
      else
182 
        sprintf (buf, "%li", x);
183 
    }
184 
  else
185 
    {
186 
      if (constant_formats[cf].issigned && x < 0)
187 
        sprintf (buf, "-0x%x", abs (x));
188 
      else
189 
        sprintf (buf, "0x%lx", x);
190 
    }
191 
 
192 
  return buf;
193 
}
194 
 
195 
static bu32
196 
fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
197 
{
198 
  if (0 && constant_formats[cf].reloc)
199 
    {
200 
      bu32 ea = (((constant_formats[cf].pcrel
201 
                   ? SIGNEXTEND (x, constant_formats[cf].nbits)
202 
                   : x) + constant_formats[cf].offset)
203 
                 << constant_formats[cf].scale);
204 
      if (constant_formats[cf].pcrel)
205 
        ea += pc;
206 
 
207 
      return ea;
208 
    }
209 
 
210 
  /* Negative constants have an implied sign bit.  */
211 
  if (constant_formats[cf].negative)
212 
    {
213 
      int nb = constant_formats[cf].nbits + 1;
214 
      x = x | (1 << constant_formats[cf].nbits);
215 
      x = SIGNEXTEND (x, nb);
216 
    }
217 
  else if (constant_formats[cf].issigned)
218 
    x = SIGNEXTEND (x, constant_formats[cf].nbits);
219 
 
220 
  x += constant_formats[cf].offset;
221 
  x <<= constant_formats[cf].scale;
222 
 
223 
  return x;
224 
}
225 
 
226 
enum machine_registers
227 
{
228 
  REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
229 
  REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
230 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
231 
  REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
232 
  REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
233 
  REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
234 
  REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
235 
  REG_L2, REG_L3,
236 
  REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
237 
  REG_AQ, REG_V, REG_VS,
238 
  REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
239 
  REG_LC1, REG_GP, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
240 
  REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
241 
  REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
242 
  REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
243 
  REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
244 
  REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
245 
  REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
246 
  REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
247 
  REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
248 
  REG_LASTREG,
249 
};
250 
 
251 
enum reg_class
252 
{
253 
  rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
254 
  rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
255 
  rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
256 
  rc_sysregs3, rc_allregs,
257 
  LIM_REG_CLASSES
258 
};
259 
 
260 
static char *reg_names[] =
261 
{
262 
  "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
263 
  "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
264 
  "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
265 
  "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
266 
  "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
267 
  "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
268 
  "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
269 
  "L2", "L3",
270 
  "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
271 
  "AQ", "V", "VS",
272 
  "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
273 
  "LC1", "GP", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
274 
  "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
275 
  "RETE", "EMUDAT",
276 
  "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
277 
  "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
278 
  "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
279 
  "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
280 
  "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
281 
  "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
282 
  "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
283 
  "LASTREG",
284 
 
285 
};
286 
 
287 
#define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
288 
 
289 
/* RL(0..7).  */
290 
static enum machine_registers decode_dregs_lo[] =
291 
{
292 
  REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
293 
};
294 
 
295 
#define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
296 
 
297 
/* RH(0..7).  */
298 
static enum machine_registers decode_dregs_hi[] =
299 
{
300 
  REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
301 
};
302 
 
303 
#define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
304 
 
305 
/* R(0..7).  */
306 
static enum machine_registers decode_dregs[] =
307 
{
308 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
309 
};
310 
 
311 
#define dregs(x) REGNAME (decode_dregs[(x) & 7])
312 
 
313 
/* R BYTE(0..7).  */
314 
static enum machine_registers decode_dregs_byte[] =
315 
{
316 
  REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
317 
};
318 
 
319 
#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
320 
#define dregs_pair(x) REGNAME (decode_dregs_pair[(x) & 7])
321 
 
322 
/* P(0..5) SP FP.  */
323 
static enum machine_registers decode_pregs[] =
324 
{
325 
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
326 
};
327 
 
328 
#define pregs(x)        REGNAME (decode_pregs[(x) & 7])
329 
#define spfp(x)         REGNAME (decode_spfp[(x) & 1])
330 
#define dregs_hilo(x,i) REGNAME (decode_dregs_hilo[((i) << 3)|x])
331 
#define accum_ext(x)    REGNAME (decode_accum_ext[(x) & 1])
332 
#define accum_word(x)   REGNAME (decode_accum_word[(x) & 1])
333 
#define accum(x)        REGNAME (decode_accum[(x) & 1])
334 
 
335 
/* I(0..3).  */
336 
static enum machine_registers decode_iregs[] =
337 
{
338 
  REG_I0, REG_I1, REG_I2, REG_I3,
339 
};
340 
 
341 
#define iregs(x) REGNAME (decode_iregs[(x) & 3])
342 
 
343 
/* M(0..3).  */
344 
static enum machine_registers decode_mregs[] =
345 
{
346 
  REG_M0, REG_M1, REG_M2, REG_M3,
347 
};
348 
 
349 
#define mregs(x) REGNAME (decode_mregs[(x) & 3])
350 
#define bregs(x) REGNAME (decode_bregs[(x) & 3])
351 
#define lregs(x) REGNAME (decode_lregs[(x) & 3])
352 
 
353 
/* dregs pregs.  */
354 
static enum machine_registers decode_dpregs[] =
355 
{
356 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
357 
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
358 
};
359 
 
360 
#define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
361 
 
362 
/* [dregs pregs].  */
363 
static enum machine_registers decode_gregs[] =
364 
{
365 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
366 
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
367 
};
368 
 
369 
#define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x])
370 
 
371 
/* [dregs pregs (iregs mregs) (bregs lregs)].  */
372 
static enum machine_registers decode_regs[] =
373 
{
374 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
375 
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
376 
  REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
377 
  REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
378 
};
379 
 
380 
#define regs(x,i) REGNAME (decode_regs[((i) << 3)|x])
381 
 
382 
/* [dregs pregs (iregs mregs) (bregs lregs) Low Half].  */
383 
static enum machine_registers decode_regs_lo[] =
384 
{
385 
  REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
386 
  REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
387 
  REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
388 
  REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
389 
};
390 
 
391 
#define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x])
392 
/* [dregs pregs (iregs mregs) (bregs lregs) High Half].  */
393 
static enum machine_registers decode_regs_hi[] =
394 
{
395 
  REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
396 
  REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
397 
  REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_LH2, REG_MH3,
398 
  REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
399 
};
400 
 
401 
#define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x])
402 
 
403 
static enum machine_registers decode_statbits[] =
404 
{
405 
  REG_AZ, REG_AN, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
406 
  REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
407 
  REG_AV0, REG_AV0S, REG_AV1, REG_AV1S, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
408 
  REG_V, REG_VS, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
409 
};
410 
 
411 
#define statbits(x)     REGNAME (decode_statbits[(x) & 31])
412 
#define ignore_bits(x)  REGNAME (decode_ignore_bits[(x) & 7])
413 
#define ccstat(x)       REGNAME (decode_ccstat[(x) & 0])
414 
 
415 
/* LC0 LC1.  */
416 
static enum machine_registers decode_counters[] =
417 
{
418 
  REG_LC0, REG_LC1,
419 
};
420 
 
421 
#define counters(x)        REGNAME (decode_counters[(x) & 1])
422 
#define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
423 
 
424 
/* [dregs pregs (iregs mregs) (bregs lregs)
425 
   dregs2_sysregs1 open sysregs2 sysregs3].  */
426 
static enum machine_registers decode_allregs[] =
427 
{
428 
  REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
429 
  REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
430 
  REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
431 
  REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
432 
  REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS,
433 
  REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
434 
  REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
435 
  REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT, REG_LASTREG,
436 
};
437 
 
438 
#define allregs(x,i)    REGNAME (decode_allregs[((i) << 3) | x])
439 
#define uimm16s4(x)     fmtconst (c_uimm16s4, x, 0, outf)
440 
#define uimm16s4d(x)    fmtconst (c_uimm16s4d, x, 0, outf)
441 
#define pcrel4(x)       fmtconst (c_pcrel4, x, pc, outf)
442 
#define pcrel8(x)       fmtconst (c_pcrel8, x, pc, outf)
443 
#define pcrel8s4(x)     fmtconst (c_pcrel8s4, x, pc, outf)
444 
#define pcrel10(x)      fmtconst (c_pcrel10, x, pc, outf)
445 
#define pcrel12(x)      fmtconst (c_pcrel12, x, pc, outf)
446 
#define negimm5s4(x)    fmtconst (c_negimm5s4, x, 0, outf)
447 
#define rimm16(x)       fmtconst (c_rimm16, x, 0, outf)
448 
#define huimm16(x)      fmtconst (c_huimm16, x, 0, outf)
449 
#define imm16(x)        fmtconst (c_imm16, x, 0, outf)
450 
#define imm16d(x)       fmtconst (c_imm16d, x, 0, outf)
451 
#define uimm2(x)        fmtconst (c_uimm2, x, 0, outf)
452 
#define uimm3(x)        fmtconst (c_uimm3, x, 0, outf)
453 
#define luimm16(x)      fmtconst (c_luimm16, x, 0, outf)
454 
#define uimm4(x)        fmtconst (c_uimm4, x, 0, outf)
455 
#define uimm5(x)        fmtconst (c_uimm5, x, 0, outf)
456 
#define imm16s2(x)      fmtconst (c_imm16s2, x, 0, outf)
457 
#define uimm8(x)        fmtconst (c_uimm8, x, 0, outf)
458 
#define imm16s4(x)      fmtconst (c_imm16s4, x, 0, outf)
459 
#define uimm4s2(x)      fmtconst (c_uimm4s2, x, 0, outf)
460 
#define uimm4s4(x)      fmtconst (c_uimm4s4, x, 0, outf)
461 
#define uimm4s4d(x)     fmtconst (c_uimm4s4d, x, 0, outf)
462 
#define lppcrel10(x)    fmtconst (c_lppcrel10, x, pc, outf)
463 
#define imm3(x)         fmtconst (c_imm3, x, 0, outf)
464 
#define imm4(x)         fmtconst (c_imm4, x, 0, outf)
465 
#define uimm8s4(x)      fmtconst (c_uimm8s4, x, 0, outf)
466 
#define imm5(x)         fmtconst (c_imm5, x, 0, outf)
467 
#define imm5d(x)        fmtconst (c_imm5d, x, 0, outf)
468 
#define imm6(x)         fmtconst (c_imm6, x, 0, outf)
469 
#define imm7(x)         fmtconst (c_imm7, x, 0, outf)
470 
#define imm7d(x)        fmtconst (c_imm7d, x, 0, outf)
471 
#define imm8(x)         fmtconst (c_imm8, x, 0, outf)
472 
#define pcrel24(x)      fmtconst (c_pcrel24, x, pc, outf)
473 
#define uimm16(x)       fmtconst (c_uimm16, x, 0, outf)
474 
#define uimm32(x)       fmtconst (c_uimm32, x, 0, outf)
475 
#define imm32(x)        fmtconst (c_imm32, x, 0, outf)
476 
#define huimm32(x)      fmtconst (c_huimm32, x, 0, outf)
477 
#define huimm32e(x)     fmtconst (c_huimm32e, x, 0, outf)
478 
#define imm7_val(x)     fmtconst_val (c_imm7, x, 0)
479 
#define imm16_val(x)    fmtconst_val (c_uimm16, x, 0)
480 
#define luimm16_val(x)  fmtconst_val (c_luimm16, x, 0)
481 
 
482 
/* (arch.pm)arch_disassembler_functions.  */
483 
#ifndef OUTS
484 
#define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, txt) :0) :0)
485 
#endif
486 
 
487 
static void
488 
amod0 (int s0, int x0, disassemble_info *outf)
489 
{
490 
  if (s0 == 1 && x0 == 0)
491 
    OUTS (outf, " (S)");
492 
  else if (s0 == 0 && x0 == 1)
493 
    OUTS (outf, " (CO)");
494 
  else if (s0 == 1 && x0 == 1)
495 
    OUTS (outf, " (SCO)");
496 
}
497 
 
498 
static void
499 
amod1 (int s0, int x0, disassemble_info *outf)
500 
{
501 
  if (s0 == 0 && x0 == 0)
502 
    OUTS (outf, " (NS)");
503 
  else if (s0 == 1 && x0 == 0)
504 
    OUTS (outf, " (S)");
505 
}
506 
 
507 
static void
508 
amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
509 
{
510 
  if (s0 == 1 && x0 == 0 && aop0 == 0)
511 
    OUTS (outf, " (S)");
512 
  else if (s0 == 0 && x0 == 1 && aop0 == 0)
513 
    OUTS (outf, " (CO)");
514 
  else if (s0 == 1 && x0 == 1 && aop0 == 0)
515 
    OUTS (outf, " (SCO)");
516 
  else if (s0 == 0 && x0 == 0 && aop0 == 2)
517 
    OUTS (outf, " (ASR)");
518 
  else if (s0 == 1 && x0 == 0 && aop0 == 2)
519 
    OUTS (outf, " (S, ASR)");
520 
  else if (s0 == 0 && x0 == 1 && aop0 == 2)
521 
    OUTS (outf, " (CO, ASR)");
522 
  else if (s0 == 1 && x0 == 1 && aop0 == 2)
523 
    OUTS (outf, " (SCO, ASR)");
524 
  else if (s0 == 0 && x0 == 0 && aop0 == 3)
525 
    OUTS (outf, " (ASL)");
526 
  else if (s0 == 1 && x0 == 0 && aop0 == 3)
527 
    OUTS (outf, " (S, ASL)");
528 
  else if (s0 == 0 && x0 == 1 && aop0 == 3)
529 
    OUTS (outf, " (CO, ASL)");
530 
  else if (s0 == 1 && x0 == 1 && aop0 == 3)
531 
    OUTS (outf, " (SCO, ASL)");
532 
}
533 
 
534 
static void
535 
searchmod (int r0, disassemble_info *outf)
536 
{
537 
  if (r0 == 0)
538 
    OUTS (outf, "GT");
539 
  else if (r0 == 1)
540 
    OUTS (outf, "GE");
541 
  else if (r0 == 2)
542 
    OUTS (outf, "LT");
543 
  else if (r0 == 3)
544 
    OUTS (outf, "LE");
545 
}
546 
 
547 
static void
548 
aligndir (int r0, disassemble_info *outf)
549 
{
550 
  if (r0 == 1)
551 
    OUTS (outf, " (R)");
552 
}
553 
 
554 
static int
555 
decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf)
556 
{
557 
  char *s0, *s1;
558 
 
559 
  if (h0)
560 
    s0 = dregs_hi (src0);
561 
  else
562 
    s0 = dregs_lo (src0);
563 
 
564 
  if (h1)
565 
    s1 = dregs_hi (src1);
566 
  else
567 
    s1 = dregs_lo (src1);
568 
 
569 
  OUTS (outf, s0);
570 
  OUTS (outf, " * ");
571 
  OUTS (outf, s1);
572 
  return 0;
573 
}
574 
 
575 
static int
576 
decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info * outf)
577 
{
578 
  char *a;
579 
  char *sop = "<unknown op>";
580 
 
581 
  if (which)
582 
    a = "A1";
583 
  else
584 
    a = "A0";
585 
 
586 
  if (op == 3)
587 
    {
588 
      OUTS (outf, a);
589 
      return 0;
590 
    }
591 
 
592 
  switch (op)
593 
    {
594 
    case 0: sop = " = ";   break;
595 
    case 1: sop = " += ";  break;
596 
    case 2: sop = " -= ";  break;
597 
    default: break;
598 
    }
599 
 
600 
  OUTS (outf, a);
601 
  OUTS (outf, sop);
602 
  decode_multfunc (h0, h1, src0, src1, outf);
603 
 
604 
  return 0;
605 
}
606 
 
607 
static void
608 
decode_optmode (int mod, int MM, disassemble_info *outf)
609 
{
610 
  if (mod == 0 && MM == 0)
611 
    return;
612 
 
613 
  OUTS (outf, " (");
614 
 
615 
  if (MM && !mod)
616 
    {
617 
      OUTS (outf, "M)");
618 
      return;
619 
    }
620 
 
621 
  if (MM)
622 
    OUTS (outf, "M, ");
623 
 
624 
  if (mod == M_S2RND)
625 
    OUTS (outf, "S2RND");
626 
  else if (mod == M_T)
627 
    OUTS (outf, "T");
628 
  else if (mod == M_W32)
629 
    OUTS (outf, "W32");
630 
  else if (mod == M_FU)
631 
    OUTS (outf, "FU");
632 
  else if (mod == M_TFU)
633 
    OUTS (outf, "TFU");
634 
  else if (mod == M_IS)
635 
    OUTS (outf, "IS");
636 
  else if (mod == M_ISS2)
637 
    OUTS (outf, "ISS2");
638 
  else if (mod == M_IH)
639 
    OUTS (outf, "IH");
640 
  else if (mod == M_IU)
641 
    OUTS (outf, "IU");
642 
  else
643 
    abort ();
644 
 
645 
  OUTS (outf, ")");
646 
}
647 
 
648 
struct saved_state
649 
{
650 
  bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
651 
  bu32 a0x, a0w, a1x, a1w;
652 
  bu32 lt[2], lc[2], lb[2];
653 
  int ac0, ac0_copy, ac1, an, aq;
654 
  int av0, av0s, av1, av1s, az, cc, v, v_copy, vs;
655 
  int rnd_mod;
656 
  int v_internal;
657 
  bu32 pc, rets;
658 
 
659 
  int ticks;
660 
  int insts;
661 
 
662 
  int exception;
663 
 
664 
  int end_of_registers;
665 
 
666 
  int msize;
667 
  unsigned char *memory;
668 
  unsigned long bfd_mach;
669 
}  saved_state;
670 
 
671 
#define DREG(x)         (saved_state.dpregs[x])
672 
#define GREG(x,i)       DPREG ((x) | (i << 3))
673 
#define DPREG(x)        (saved_state.dpregs[x])
674 
#define DREG(x)         (saved_state.dpregs[x])
675 
#define PREG(x)         (saved_state.dpregs[x + 8])
676 
#define SPREG           PREG (6)
677 
#define FPREG           PREG (7)
678 
#define IREG(x)         (saved_state.iregs[x])
679 
#define MREG(x)         (saved_state.mregs[x])
680 
#define BREG(x)         (saved_state.bregs[x])
681 
#define LREG(x)         (saved_state.lregs[x])
682 
#define A0XREG          (saved_state.a0x)
683 
#define A0WREG          (saved_state.a0w)
684 
#define A1XREG          (saved_state.a1x)
685 
#define A1WREG          (saved_state.a1w)
686 
#define CCREG           (saved_state.cc)
687 
#define LC0REG          (saved_state.lc[0])
688 
#define LT0REG          (saved_state.lt[0])
689 
#define LB0REG          (saved_state.lb[0])
690 
#define LC1REG          (saved_state.lc[1])
691 
#define LT1REG          (saved_state.lt[1])
692 
#define LB1REG          (saved_state.lb[1])
693 
#define RETSREG         (saved_state.rets)
694 
#define PCREG           (saved_state.pc)
695 
 
696 
static bu32 *
697 
get_allreg (int grp, int reg)
698 
{
699 
  int fullreg = (grp << 3) | reg;
700 
  /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
701 
     REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
702 
     REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
703 
     REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
704 
     REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
705 
     , , , , , , , ,
706 
     REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
707 
     REG_CYCLES2,
708 
     REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
709 
     REG_LASTREG */
710 
  switch (fullreg >> 2)
711 
    {
712 
    case 0: case 1: return &DREG (reg); break;
713 
    case 2: case 3: return &PREG (reg); break;
714 
    case 4: return &IREG (reg & 3); break;
715 
    case 5: return &MREG (reg & 3); break;
716 
    case 6: return &BREG (reg & 3); break;
717 
    case 7: return &LREG (reg & 3); break;
718 
    default:
719 
      switch (fullreg)
720 
        {
721 
        case 32: return &saved_state.a0x;
722 
        case 33: return &saved_state.a0w;
723 
        case 34: return &saved_state.a1x;
724 
        case 35: return &saved_state.a1w;
725 
        case 39: return &saved_state.rets;
726 
        case 48: return &LC0REG;
727 
        case 49: return &LT0REG;
728 
        case 50: return &LB0REG;
729 
        case 51: return &LC1REG;
730 
        case 52: return &LT1REG;
731 
        case 53: return &LB1REG;
732 
        }
733 
      return 0;
734 
    }
735 
}
736 
 
737 
static int
738 
decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
739 
{
740 
  /* ProgCtrl
741 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
742 
     | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
743 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
744 
  int poprnd  = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
745 
  int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
746 
 
747 
  if (prgfunc == 0 && poprnd == 0)
748 
    OUTS (outf, "NOP");
749 
  else if (prgfunc == 1 && poprnd == 0)
750 
    OUTS (outf, "RTS");
751 
  else if (prgfunc == 1 && poprnd == 1)
752 
    OUTS (outf, "RTI");
753 
  else if (prgfunc == 1 && poprnd == 2)
754 
    OUTS (outf, "RTX");
755 
  else if (prgfunc == 1 && poprnd == 3)
756 
    OUTS (outf, "RTN");
757 
  else if (prgfunc == 1 && poprnd == 4)
758 
    OUTS (outf, "RTE");
759 
  else if (prgfunc == 2 && poprnd == 0)
760 
    OUTS (outf, "IDLE");
761 
  else if (prgfunc == 2 && poprnd == 3)
762 
    OUTS (outf, "CSYNC");
763 
  else if (prgfunc == 2 && poprnd == 4)
764 
    OUTS (outf, "SSYNC");
765 
  else if (prgfunc == 2 && poprnd == 5)
766 
    OUTS (outf, "EMUEXCPT");
767 
  else if (prgfunc == 3)
768 
    {
769 
      OUTS (outf, "CLI ");
770 
      OUTS (outf, dregs (poprnd));
771 
    }
772 
  else if (prgfunc == 4)
773 
    {
774 
      OUTS (outf, "STI ");
775 
      OUTS (outf, dregs (poprnd));
776 
    }
777 
  else if (prgfunc == 5)
778 
    {
779 
      OUTS (outf, "JUMP (");
780 
      OUTS (outf, pregs (poprnd));
781 
      OUTS (outf, ")");
782 
    }
783 
  else if (prgfunc == 6)
784 
    {
785 
      OUTS (outf, "CALL (");
786 
      OUTS (outf, pregs (poprnd));
787 
      OUTS (outf, ")");
788 
    }
789 
  else if (prgfunc == 7)
790 
    {
791 
      OUTS (outf, "CALL (PC + ");
792 
      OUTS (outf, pregs (poprnd));
793 
      OUTS (outf, ")");
794 
    }
795 
  else if (prgfunc == 8)
796 
    {
797 
      OUTS (outf, "JUMP (PC + ");
798 
      OUTS (outf, pregs (poprnd));
799 
      OUTS (outf, ")");
800 
    }
801 
  else if (prgfunc == 9)
802 
    {
803 
      OUTS (outf, "RAISE ");
804 
      OUTS (outf, uimm4 (poprnd));
805 
    }
806 
  else if (prgfunc == 10)
807 
    {
808 
      OUTS (outf, "EXCPT ");
809 
      OUTS (outf, uimm4 (poprnd));
810 
    }
811 
  else if (prgfunc == 11)
812 
    {
813 
      OUTS (outf, "TESTSET (");
814 
      OUTS (outf, pregs (poprnd));
815 
      OUTS (outf, ")");
816 
    }
817 
  else
818 
    return 0;
819 
  return 2;
820 
}
821 
 
822 
static int
823 
decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
824 
{
825 
  /* CaCTRL
826 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
827 
     | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
828 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
829 
  int a   = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
830 
  int op  = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
831 
  int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
832 
 
833 
  if (a == 0 && op == 0)
834 
    {
835 
      OUTS (outf, "PREFETCH[");
836 
      OUTS (outf, pregs (reg));
837 
      OUTS (outf, "]");
838 
    }
839 
  else if (a == 0 && op == 1)
840 
    {
841 
      OUTS (outf, "FLUSHINV[");
842 
      OUTS (outf, pregs (reg));
843 
      OUTS (outf, "]");
844 
    }
845 
  else if (a == 0 && op == 2)
846 
    {
847 
      OUTS (outf, "FLUSH[");
848 
      OUTS (outf, pregs (reg));
849 
      OUTS (outf, "]");
850 
    }
851 
  else if (a == 0 && op == 3)
852 
    {
853 
      OUTS (outf, "IFLUSH[");
854 
      OUTS (outf, pregs (reg));
855 
      OUTS (outf, "]");
856 
    }
857 
  else if (a == 1 && op == 0)
858 
    {
859 
      OUTS (outf, "PREFETCH[");
860 
      OUTS (outf, pregs (reg));
861 
      OUTS (outf, "++]");
862 
    }
863 
  else if (a == 1 && op == 1)
864 
    {
865 
      OUTS (outf, "FLUSHINV[");
866 
      OUTS (outf, pregs (reg));
867 
      OUTS (outf, "++]");
868 
    }
869 
  else if (a == 1 && op == 2)
870 
    {
871 
      OUTS (outf, "FLUSH[");
872 
      OUTS (outf, pregs (reg));
873 
      OUTS (outf, "++]");
874 
    }
875 
  else if (a == 1 && op == 3)
876 
    {
877 
      OUTS (outf, "IFLUSH[");
878 
      OUTS (outf, pregs (reg));
879 
      OUTS (outf, "++]");
880 
    }
881 
  else
882 
    return 0;
883 
  return 2;
884 
}
885 
 
886 
static int
887 
decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
888 
{
889 
  /* PushPopReg
890 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
891 
     | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
892 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
893 
  int W   = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
894 
  int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
895 
  int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
896 
 
897 
  if (W == 0)
898 
    {
899 
      OUTS (outf, allregs (reg, grp));
900 
      OUTS (outf, " = [SP++]");
901 
    }
902 
  else if (W == 1)
903 
    {
904 
      OUTS (outf, "[--SP] = ");
905 
      OUTS (outf, allregs (reg, grp));
906 
    }
907 
  else
908 
    return 0;
909 
  return 2;
910 
}
911 
 
912 
static int
913 
decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
914 
{
915 
  /* PushPopMultiple
916 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
917 
     | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
918 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
919 
  int p  = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
920 
  int d  = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
921 
  int W  = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
922 
  int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
923 
  int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
924 
 
925 
  if (W == 1 && d == 1 && p == 1)
926 
    {
927 
      OUTS (outf, "[--SP] = (R7:");
928 
      OUTS (outf, imm5d (dr));
929 
      OUTS (outf, ", P5:");
930 
      OUTS (outf, imm5d (pr));
931 
      OUTS (outf, ")");
932 
    }
933 
  else if (W == 1 && d == 1 && p == 0)
934 
    {
935 
      OUTS (outf, "[--SP] = (R7:");
936 
      OUTS (outf, imm5d (dr));
937 
      OUTS (outf, ")");
938 
    }
939 
  else if (W == 1 && d == 0 && p == 1)
940 
    {
941 
      OUTS (outf, "[--SP] = (P5:");
942 
      OUTS (outf, imm5d (pr));
943 
      OUTS (outf, ")");
944 
    }
945 
  else if (W == 0 && d == 1 && p == 1)
946 
    {
947 
      OUTS (outf, "(R7:");
948 
      OUTS (outf, imm5d (dr));
949 
      OUTS (outf, ", P5:");
950 
      OUTS (outf, imm5d (pr));
951 
      OUTS (outf, ") = [SP++]");
952 
    }
953 
  else if (W == 0 && d == 1 && p == 0)
954 
    {
955 
      OUTS (outf, "(R7:");
956 
      OUTS (outf, imm5d (dr));
957 
      OUTS (outf, ") = [SP++]");
958 
    }
959 
  else if (W == 0 && d == 0 && p == 1)
960 
    {
961 
      OUTS (outf, "(P5:");
962 
      OUTS (outf, imm5d (pr));
963 
      OUTS (outf, ") = [SP++]");
964 
    }
965 
  else
966 
    return 0;
967 
  return 2;
968 
}
969 
 
970 
static int
971 
decode_ccMV_0 (TIword iw0, disassemble_info *outf)
972 
{
973 
  /* ccMV
974 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
975 
     | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
976 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
977 
  int s  = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
978 
  int d  = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
979 
  int T  = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
980 
  int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
981 
  int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
982 
 
983 
  if (T == 1)
984 
    {
985 
      OUTS (outf, "IF CC ");
986 
      OUTS (outf, gregs (dst, d));
987 
      OUTS (outf, " = ");
988 
      OUTS (outf, gregs (src, s));
989 
    }
990 
  else if (T == 0)
991 
    {
992 
      OUTS (outf, "IF !CC ");
993 
      OUTS (outf, gregs (dst, d));
994 
      OUTS (outf, " = ");
995 
      OUTS (outf, gregs (src, s));
996 
    }
997 
  else
998 
    return 0;
999 
  return 2;
1000 
}
1001 
 
1002 
static int
1003 
decode_CCflag_0 (TIword iw0, disassemble_info *outf)
1004 
{
1005 
  /* CCflag
1006 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1007 
     | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1008 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1009 
  int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1010 
  int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1011 
  int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1012 
  int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1013 
  int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1014 
 
1015 
  if (opc == 0 && I == 0 && G == 0)
1016 
    {
1017 
      OUTS (outf, "CC = ");
1018 
      OUTS (outf, dregs (x));
1019 
      OUTS (outf, " == ");
1020 
      OUTS (outf, dregs (y));
1021 
    }
1022 
  else if (opc == 1 && I == 0 && G == 0)
1023 
    {
1024 
      OUTS (outf, "CC = ");
1025 
      OUTS (outf, dregs (x));
1026 
      OUTS (outf, " < ");
1027 
      OUTS (outf, dregs (y));
1028 
    }
1029 
  else if (opc == 2 && I == 0 && G == 0)
1030 
    {
1031 
      OUTS (outf, "CC = ");
1032 
      OUTS (outf, dregs (x));
1033 
      OUTS (outf, " <= ");
1034 
      OUTS (outf, dregs (y));
1035 
    }
1036 
  else if (opc == 3 && I == 0 && G == 0)
1037 
    {
1038 
      OUTS (outf, "CC = ");
1039 
      OUTS (outf, dregs (x));
1040 
      OUTS (outf, " < ");
1041 
      OUTS (outf, dregs (y));
1042 
      OUTS (outf, " (IU)");
1043 
    }
1044 
  else if (opc == 4 && I == 0 && G == 0)
1045 
    {
1046 
      OUTS (outf, "CC = ");
1047 
      OUTS (outf, dregs (x));
1048 
      OUTS (outf, " <= ");
1049 
      OUTS (outf, dregs (y));
1050 
      OUTS (outf, " (IU)");
1051 
    }
1052 
  else if (opc == 0 && I == 1 && G == 0)
1053 
    {
1054 
      OUTS (outf, "CC = ");
1055 
      OUTS (outf, dregs (x));
1056 
      OUTS (outf, " == ");
1057 
      OUTS (outf, imm3 (y));
1058 
    }
1059 
  else if (opc == 1 && I == 1 && G == 0)
1060 
    {
1061 
      OUTS (outf, "CC = ");
1062 
      OUTS (outf, dregs (x));
1063 
      OUTS (outf, " < ");
1064 
      OUTS (outf, imm3 (y));
1065 
    }
1066 
  else if (opc == 2 && I == 1 && G == 0)
1067 
    {
1068 
      OUTS (outf, "CC = ");
1069 
      OUTS (outf, dregs (x));
1070 
      OUTS (outf, " <= ");
1071 
      OUTS (outf, imm3 (y));
1072 
    }
1073 
  else if (opc == 3 && I == 1 && G == 0)
1074 
    {
1075 
      OUTS (outf, "CC = ");
1076 
      OUTS (outf, dregs (x));
1077 
      OUTS (outf, " < ");
1078 
      OUTS (outf, uimm3 (y));
1079 
      OUTS (outf, " (IU)");
1080 
    }
1081 
  else if (opc == 4 && I == 1 && G == 0)
1082 
    {
1083 
      OUTS (outf, "CC = ");
1084 
      OUTS (outf, dregs (x));
1085 
      OUTS (outf, " <= ");
1086 
      OUTS (outf, uimm3 (y));
1087 
      OUTS (outf, " (IU)");
1088 
    }
1089 
  else if (opc == 0 && I == 0 && G == 1)
1090 
    {
1091 
      OUTS (outf, "CC = ");
1092 
      OUTS (outf, pregs (x));
1093 
      OUTS (outf, " == ");
1094 
      OUTS (outf, pregs (y));
1095 
    }
1096 
  else if (opc == 1 && I == 0 && G == 1)
1097 
    {
1098 
      OUTS (outf, "CC = ");
1099 
      OUTS (outf, pregs (x));
1100 
      OUTS (outf, " < ");
1101 
      OUTS (outf, pregs (y));
1102 
    }
1103 
  else if (opc == 2 && I == 0 && G == 1)
1104 
    {
1105 
      OUTS (outf, "CC = ");
1106 
      OUTS (outf, pregs (x));
1107 
      OUTS (outf, " <= ");
1108 
      OUTS (outf, pregs (y));
1109 
    }
1110 
  else if (opc == 3 && I == 0 && G == 1)
1111 
    {
1112 
      OUTS (outf, "CC = ");
1113 
      OUTS (outf, pregs (x));
1114 
      OUTS (outf, " < ");
1115 
      OUTS (outf, pregs (y));
1116 
      OUTS (outf, " (IU)");
1117 
    }
1118 
  else if (opc == 4 && I == 0 && G == 1)
1119 
    {
1120 
      OUTS (outf, "CC = ");
1121 
      OUTS (outf, pregs (x));
1122 
      OUTS (outf, " <= ");
1123 
      OUTS (outf, pregs (y));
1124 
      OUTS (outf, " (IU)");
1125 
    }
1126 
  else if (opc == 0 && I == 1 && G == 1)
1127 
    {
1128 
      OUTS (outf, "CC = ");
1129 
      OUTS (outf, pregs (x));
1130 
      OUTS (outf, " == ");
1131 
      OUTS (outf, imm3 (y));
1132 
    }
1133 
  else if (opc == 1 && I == 1 && G == 1)
1134 
    {
1135 
      OUTS (outf, "CC = ");
1136 
      OUTS (outf, pregs (x));
1137 
      OUTS (outf, " < ");
1138 
      OUTS (outf, imm3 (y));
1139 
    }
1140 
  else if (opc == 2 && I == 1 && G == 1)
1141 
    {
1142 
      OUTS (outf, "CC = ");
1143 
      OUTS (outf, pregs (x));
1144 
      OUTS (outf, " <= ");
1145 
      OUTS (outf, imm3 (y));
1146 
    }
1147 
  else if (opc == 3 && I == 1 && G == 1)
1148 
    {
1149 
      OUTS (outf, "CC = ");
1150 
      OUTS (outf, pregs (x));
1151 
      OUTS (outf, " < ");
1152 
      OUTS (outf, uimm3 (y));
1153 
      OUTS (outf, " (IU)");
1154 
    }
1155 
  else if (opc == 4 && I == 1 && G == 1)
1156 
    {
1157 
      OUTS (outf, "CC = ");
1158 
      OUTS (outf, pregs (x));
1159 
      OUTS (outf, " <= ");
1160 
      OUTS (outf, uimm3 (y));
1161 
      OUTS (outf, " (IU)");
1162 
    }
1163 
  else if (opc == 5 && I == 0 && G == 0)
1164 
    OUTS (outf, "CC = A0 == A1");
1165 
 
1166 
  else if (opc == 6 && I == 0 && G == 0)
1167 
    OUTS (outf, "CC = A0 < A1");
1168 
 
1169 
  else if (opc == 7 && I == 0 && G == 0)
1170 
    OUTS (outf, "CC = A0 <= A1");
1171 
 
1172 
  else
1173 
    return 0;
1174 
  return 2;
1175 
}
1176 
 
1177 
static int
1178 
decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1179 
{
1180 
  /* CC2dreg
1181 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1182 
     | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1183 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1184 
  int op  = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1185 
  int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1186 
 
1187 
  if (op == 0)
1188 
    {
1189 
      OUTS (outf, dregs (reg));
1190 
      OUTS (outf, " = CC");
1191 
    }
1192 
  else if (op == 1)
1193 
    {
1194 
      OUTS (outf, "CC = ");
1195 
      OUTS (outf, dregs (reg));
1196 
    }
1197 
  else if (op == 3)
1198 
    OUTS (outf, "CC = !CC");
1199 
  else
1200 
    return 0;
1201 
 
1202 
  return 2;
1203 
}
1204 
 
1205 
static int
1206 
decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1207 
{
1208 
  /* CC2stat
1209 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1210 
     | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1211 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1212 
  int D    = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1213 
  int op   = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1214 
  int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1215 
 
1216 
  if (op == 0 && D == 0)
1217 
    {
1218 
      OUTS (outf, "CC = ");
1219 
      OUTS (outf, statbits (cbit));
1220 
    }
1221 
  else if (op == 1 && D == 0)
1222 
    {
1223 
      OUTS (outf, "CC |= ");
1224 
      OUTS (outf, statbits (cbit));
1225 
    }
1226 
  else if (op == 2 && D == 0)
1227 
    {
1228 
      OUTS (outf, "CC &= ");
1229 
      OUTS (outf, statbits (cbit));
1230 
    }
1231 
  else if (op == 3 && D == 0)
1232 
    {
1233 
      OUTS (outf, "CC ^= ");
1234 
      OUTS (outf, statbits (cbit));
1235 
    }
1236 
  else if (op == 0 && D == 1)
1237 
    {
1238 
      OUTS (outf, statbits (cbit));
1239 
      OUTS (outf, " = CC");
1240 
    }
1241 
  else if (op == 1 && D == 1)
1242 
    {
1243 
      OUTS (outf, statbits (cbit));
1244 
      OUTS (outf, " |= CC");
1245 
    }
1246 
  else if (op == 2 && D == 1)
1247 
    {
1248 
      OUTS (outf, statbits (cbit));
1249 
      OUTS (outf, " &= CC");
1250 
    }
1251 
  else if (op == 3 && D == 1)
1252 
    {
1253 
      OUTS (outf, statbits (cbit));
1254 
      OUTS (outf, " ^= CC");
1255 
    }
1256 
  else
1257 
    return 0;
1258 
 
1259 
  return 2;
1260 
}
1261 
 
1262 
static int
1263 
decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1264 
{
1265 
  /* BRCC
1266 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1267 
     | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1268 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1269 
  int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1270 
  int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1271 
  int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1272 
 
1273 
  if (T == 1 && B == 1)
1274 
    {
1275 
      OUTS (outf, "IF CC JUMP 0x");
1276 
      OUTS (outf, pcrel10 (offset));
1277 
      OUTS (outf, " (BP)");
1278 
    }
1279 
  else if (T == 0 && B == 1)
1280 
    {
1281 
      OUTS (outf, "IF !CC JUMP 0x");
1282 
      OUTS (outf, pcrel10 (offset));
1283 
      OUTS (outf, " (BP)");
1284 
    }
1285 
  else if (T == 1)
1286 
    {
1287 
      OUTS (outf, "IF CC JUMP 0x");
1288 
      OUTS (outf, pcrel10 (offset));
1289 
    }
1290 
  else if (T == 0)
1291 
    {
1292 
      OUTS (outf, "IF !CC JUMP 0x");
1293 
      OUTS (outf, pcrel10 (offset));
1294 
    }
1295 
  else
1296 
    return 0;
1297 
 
1298 
  return 2;
1299 
}
1300 
 
1301 
static int
1302 
decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1303 
{
1304 
  /* UJUMP
1305 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1306 
     | 0 | 0 | 1 | 0 |.offset........................................|
1307 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1308 
  int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1309 
 
1310 
  OUTS (outf, "JUMP.S 0x");
1311 
  OUTS (outf, pcrel12 (offset));
1312 
  return 2;
1313 
}
1314 
 
1315 
static int
1316 
decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1317 
{
1318 
  /* REGMV
1319 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1320 
     | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1321 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1322 
  int gs  = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1323 
  int gd  = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1324 
  int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1325 
  int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1326 
 
1327 
  OUTS (outf, allregs (dst, gd));
1328 
  OUTS (outf, " = ");
1329 
  OUTS (outf, allregs (src, gs));
1330 
  return 2;
1331 
}
1332 
 
1333 
static int
1334 
decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1335 
{
1336 
  /* ALU2op
1337 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1338 
     | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1339 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1340 
  int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1341 
  int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1342 
  int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1343 
 
1344 
  if (opc == 0)
1345 
    {
1346 
      OUTS (outf, dregs (dst));
1347 
      OUTS (outf, " >>>= ");
1348 
      OUTS (outf, dregs (src));
1349 
    }
1350 
  else if (opc == 1)
1351 
    {
1352 
      OUTS (outf, dregs (dst));
1353 
      OUTS (outf, " >>= ");
1354 
      OUTS (outf, dregs (src));
1355 
    }
1356 
  else if (opc == 2)
1357 
    {
1358 
      OUTS (outf, dregs (dst));
1359 
      OUTS (outf, " <<= ");
1360 
      OUTS (outf, dregs (src));
1361 
    }
1362 
  else if (opc == 3)
1363 
    {
1364 
      OUTS (outf, dregs (dst));
1365 
      OUTS (outf, " *= ");
1366 
      OUTS (outf, dregs (src));
1367 
    }
1368 
  else if (opc == 4)
1369 
    {
1370 
      OUTS (outf, dregs (dst));
1371 
      OUTS (outf, " = (");
1372 
      OUTS (outf, dregs (dst));
1373 
      OUTS (outf, " + ");
1374 
      OUTS (outf, dregs (src));
1375 
      OUTS (outf, ") << 0x1");
1376 
    }
1377 
  else if (opc == 5)
1378 
    {
1379 
      OUTS (outf, dregs (dst));
1380 
      OUTS (outf, " = (");
1381 
      OUTS (outf, dregs (dst));
1382 
      OUTS (outf, " + ");
1383 
      OUTS (outf, dregs (src));
1384 
      OUTS (outf, ") << 0x2");
1385 
    }
1386 
  else if (opc == 8)
1387 
    {
1388 
      OUTS (outf, "DIVQ (");
1389 
      OUTS (outf, dregs (dst));
1390 
      OUTS (outf, ", ");
1391 
      OUTS (outf, dregs (src));
1392 
      OUTS (outf, ")");
1393 
    }
1394 
  else if (opc == 9)
1395 
    {
1396 
      OUTS (outf, "DIVS (");
1397 
      OUTS (outf, dregs (dst));
1398 
      OUTS (outf, ", ");
1399 
      OUTS (outf, dregs (src));
1400 
      OUTS (outf, ")");
1401 
    }
1402 
  else if (opc == 10)
1403 
    {
1404 
      OUTS (outf, dregs (dst));
1405 
      OUTS (outf, " = ");
1406 
      OUTS (outf, dregs_lo (src));
1407 
      OUTS (outf, " (X)");
1408 
    }
1409 
  else if (opc == 11)
1410 
    {
1411 
      OUTS (outf, dregs (dst));
1412 
      OUTS (outf, " = ");
1413 
      OUTS (outf, dregs_lo (src));
1414 
      OUTS (outf, " (Z)");
1415 
    }
1416 
  else if (opc == 12)
1417 
    {
1418 
      OUTS (outf, dregs (dst));
1419 
      OUTS (outf, " = ");
1420 
      OUTS (outf, dregs_byte (src));
1421 
      OUTS (outf, " (X)");
1422 
    }
1423 
  else if (opc == 13)
1424 
    {
1425 
      OUTS (outf, dregs (dst));
1426 
      OUTS (outf, " = ");
1427 
      OUTS (outf, dregs_byte (src));
1428 
      OUTS (outf, " (Z)");
1429 
    }
1430 
  else if (opc == 14)
1431 
    {
1432 
      OUTS (outf, dregs (dst));
1433 
      OUTS (outf, " = -");
1434 
      OUTS (outf, dregs (src));
1435 
    }
1436 
  else if (opc == 15)
1437 
    {
1438 
      OUTS (outf, dregs (dst));
1439 
      OUTS (outf, " =~ ");
1440 
      OUTS (outf, dregs (src));
1441 
    }
1442 
  else
1443 
    return 0;
1444 
 
1445 
  return 2;
1446 
}
1447 
 
1448 
static int
1449 
decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1450 
{
1451 
  /* PTR2op
1452 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1453 
     | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1454 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1455 
  int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1456 
  int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1457 
  int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1458 
 
1459 
  if (opc == 0)
1460 
    {
1461 
      OUTS (outf, pregs (dst));
1462 
      OUTS (outf, " -= ");
1463 
      OUTS (outf, pregs (src));
1464 
    }
1465 
  else if (opc == 1)
1466 
    {
1467 
      OUTS (outf, pregs (dst));
1468 
      OUTS (outf, " = ");
1469 
      OUTS (outf, pregs (src));
1470 
      OUTS (outf, " << 0x2");
1471 
    }
1472 
  else if (opc == 3)
1473 
    {
1474 
      OUTS (outf, pregs (dst));
1475 
      OUTS (outf, " = ");
1476 
      OUTS (outf, pregs (src));
1477 
      OUTS (outf, " >> 0x2");
1478 
    }
1479 
  else if (opc == 4)
1480 
    {
1481 
      OUTS (outf, pregs (dst));
1482 
      OUTS (outf, " = ");
1483 
      OUTS (outf, pregs (src));
1484 
      OUTS (outf, " >> 0x1");
1485 
    }
1486 
  else if (opc == 5)
1487 
    {
1488 
      OUTS (outf, pregs (dst));
1489 
      OUTS (outf, " += ");
1490 
      OUTS (outf, pregs (src));
1491 
      OUTS (outf, " (BREV)");
1492 
    }
1493 
  else if (opc == 6)
1494 
    {
1495 
      OUTS (outf, pregs (dst));
1496 
      OUTS (outf, " = (");
1497 
      OUTS (outf, pregs (dst));
1498 
      OUTS (outf, " + ");
1499 
      OUTS (outf, pregs (src));
1500 
      OUTS (outf, ") << 0x1");
1501 
    }
1502 
  else if (opc == 7)
1503 
    {
1504 
      OUTS (outf, pregs (dst));
1505 
      OUTS (outf, " = (");
1506 
      OUTS (outf, pregs (dst));
1507 
      OUTS (outf, " + ");
1508 
      OUTS (outf, pregs (src));
1509 
      OUTS (outf, ") << 0x2");
1510 
    }
1511 
  else
1512 
    return 0;
1513 
 
1514 
  return 2;
1515 
}
1516 
 
1517 
static int
1518 
decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1519 
{
1520 
  /* LOGI2op
1521 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1522 
     | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1523 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1524 
  int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1525 
  int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1526 
  int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1527 
 
1528 
  if (opc == 0)
1529 
    {
1530 
      OUTS (outf, "CC = !BITTST (");
1531 
      OUTS (outf, dregs (dst));
1532 
      OUTS (outf, ", ");
1533 
      OUTS (outf, uimm5 (src));
1534 
      OUTS (outf, ");\t\t/* bit");
1535 
      OUTS (outf, imm7d (src));
1536 
      OUTS (outf, " */");
1537 
      comment = 1;
1538 
    }
1539 
  else if (opc == 1)
1540 
    {
1541 
      OUTS (outf, "CC = BITTST (");
1542 
      OUTS (outf, dregs (dst));
1543 
      OUTS (outf, ", ");
1544 
      OUTS (outf, uimm5 (src));
1545 
      OUTS (outf, ");\t\t/* bit");
1546 
      OUTS (outf, imm7d (src));
1547 
      OUTS (outf, " */");
1548 
      comment = 1;
1549 
    }
1550 
  else if (opc == 2)
1551 
    {
1552 
      OUTS (outf, "BITSET (");
1553 
      OUTS (outf, dregs (dst));
1554 
      OUTS (outf, ", ");
1555 
      OUTS (outf, uimm5 (src));
1556 
      OUTS (outf, ");\t\t/* bit");
1557 
      OUTS (outf, imm7d (src));
1558 
      OUTS (outf, " */");
1559 
      comment = 1;
1560 
    }
1561 
  else if (opc == 3)
1562 
    {
1563 
      OUTS (outf, "BITTGL (");
1564 
      OUTS (outf, dregs (dst));
1565 
      OUTS (outf, ", ");
1566 
      OUTS (outf, uimm5 (src));
1567 
      OUTS (outf, ");\t\t/* bit");
1568 
      OUTS (outf, imm7d (src));
1569 
      OUTS (outf, " */");
1570 
      comment = 1;
1571 
    }
1572 
  else if (opc == 4)
1573 
    {
1574 
      OUTS (outf, "BITCLR (");
1575 
      OUTS (outf, dregs (dst));
1576 
      OUTS (outf, ", ");
1577 
      OUTS (outf, uimm5 (src));
1578 
      OUTS (outf, ");\t\t/* bit");
1579 
      OUTS (outf, imm7d (src));
1580 
      OUTS (outf, " */");
1581 
      comment = 1;
1582 
    }
1583 
  else if (opc == 5)
1584 
    {
1585 
      OUTS (outf, dregs (dst));
1586 
      OUTS (outf, " >>>= ");
1587 
      OUTS (outf, uimm5 (src));
1588 
    }
1589 
  else if (opc == 6)
1590 
    {
1591 
      OUTS (outf, dregs (dst));
1592 
      OUTS (outf, " >>= ");
1593 
      OUTS (outf, uimm5 (src));
1594 
    }
1595 
  else if (opc == 7)
1596 
    {
1597 
      OUTS (outf, dregs (dst));
1598 
      OUTS (outf, " <<= ");
1599 
      OUTS (outf, uimm5 (src));
1600 
    }
1601 
  else
1602 
    return 0;
1603 
 
1604 
  return 2;
1605 
}
1606 
 
1607 
static int
1608 
decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1609 
{
1610 
  /* COMP3op
1611 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1612 
     | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1613 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1614 
  int opc  = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1615 
  int dst  = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1616 
  int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1617 
  int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1618 
 
1619 
  if (opc == 5 && src1 == src0)
1620 
    {
1621 
      OUTS (outf, pregs (dst));
1622 
      OUTS (outf, " = ");
1623 
      OUTS (outf, pregs (src0));
1624 
      OUTS (outf, " << 0x1");
1625 
    }
1626 
  else if (opc == 1)
1627 
    {
1628 
      OUTS (outf, dregs (dst));
1629 
      OUTS (outf, " = ");
1630 
      OUTS (outf, dregs (src0));
1631 
      OUTS (outf, " - ");
1632 
      OUTS (outf, dregs (src1));
1633 
    }
1634 
  else if (opc == 2)
1635 
    {
1636 
      OUTS (outf, dregs (dst));
1637 
      OUTS (outf, " = ");
1638 
      OUTS (outf, dregs (src0));
1639 
      OUTS (outf, " & ");
1640 
      OUTS (outf, dregs (src1));
1641 
    }
1642 
  else if (opc == 3)
1643 
    {
1644 
      OUTS (outf, dregs (dst));
1645 
      OUTS (outf, " = ");
1646 
      OUTS (outf, dregs (src0));
1647 
      OUTS (outf, " | ");
1648 
      OUTS (outf, dregs (src1));
1649 
    }
1650 
  else if (opc == 4)
1651 
    {
1652 
      OUTS (outf, dregs (dst));
1653 
      OUTS (outf, " = ");
1654 
      OUTS (outf, dregs (src0));
1655 
      OUTS (outf, " ^ ");
1656 
      OUTS (outf, dregs (src1));
1657 
    }
1658 
  else if (opc == 5)
1659 
    {
1660 
      OUTS (outf, pregs (dst));
1661 
      OUTS (outf, " = ");
1662 
      OUTS (outf, pregs (src0));
1663 
      OUTS (outf, " + ");
1664 
      OUTS (outf, pregs (src1));
1665 
    }
1666 
  else if (opc == 6)
1667 
    {
1668 
      OUTS (outf, pregs (dst));
1669 
      OUTS (outf, " = ");
1670 
      OUTS (outf, pregs (src0));
1671 
      OUTS (outf, " + (");
1672 
      OUTS (outf, pregs (src1));
1673 
      OUTS (outf, " << 0x1)");
1674 
    }
1675 
  else if (opc == 7)
1676 
    {
1677 
      OUTS (outf, pregs (dst));
1678 
      OUTS (outf, " = ");
1679 
      OUTS (outf, pregs (src0));
1680 
      OUTS (outf, " + (");
1681 
      OUTS (outf, pregs (src1));
1682 
      OUTS (outf, " << 0x2)");
1683 
    }
1684 
  else if (opc == 0)
1685 
    {
1686 
      OUTS (outf, dregs (dst));
1687 
      OUTS (outf, " = ");
1688 
      OUTS (outf, dregs (src0));
1689 
      OUTS (outf, " + ");
1690 
      OUTS (outf, dregs (src1));
1691 
    }
1692 
  else
1693 
    return 0;
1694 
 
1695 
  return 2;
1696 
}
1697 
 
1698 
static int
1699 
decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1700 
{
1701 
  /* COMPI2opD
1702 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1703 
     | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1704 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1705 
  int op  = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1706 
  int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1707 
  int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1708 
 
1709 
  bu32 *pval = get_allreg (0, dst);
1710 
 
1711 
  /* Since we don't have 32-bit immediate loads, we allow the disassembler
1712 
     to combine them, so it prints out the right values.
1713 
     Here we keep track of the registers.  */
1714 
  if (op == 0)
1715 
    {
1716 
      *pval = imm7_val (src);
1717 
      if (src & 0x40)
1718 
        *pval |= 0xFFFFFF80;
1719 
      else
1720 
        *pval &= 0x7F;
1721 
    }
1722 
 
1723 
  if (op == 0)
1724 
    {
1725 
      OUTS (outf, dregs (dst));
1726 
      OUTS (outf, " = ");
1727 
      OUTS (outf, imm7 (src));
1728 
      OUTS (outf, " (X);\t\t/*\t\t");
1729 
      OUTS (outf, dregs (dst));
1730 
      OUTS (outf, "=");
1731 
      OUTS (outf, uimm32 (*pval));
1732 
      OUTS (outf, "(");
1733 
      OUTS (outf, imm32 (*pval));
1734 
      OUTS (outf, ") */");
1735 
      comment = 1;
1736 
    }
1737 
  else if (op == 1)
1738 
    {
1739 
      OUTS (outf, dregs (dst));
1740 
      OUTS (outf, " += ");
1741 
      OUTS (outf, imm7 (src));
1742 
      OUTS (outf, ";\t\t/* (");
1743 
      OUTS (outf, imm7d (src));
1744 
      OUTS (outf, ") */");
1745 
      comment = 1;
1746 
    }
1747 
  else
1748 
    return 0;
1749 
 
1750 
  return 2;
1751 
}
1752 
 
1753 
static int
1754 
decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1755 
{
1756 
  /* COMPI2opP
1757 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1758 
     | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1759 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1760 
  int op  = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1761 
  int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1762 
  int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1763 
 
1764 
  bu32 *pval = get_allreg (1, dst);
1765 
 
1766 
  if (op == 0)
1767 
    {
1768 
      *pval = imm7_val (src);
1769 
      if (src & 0x40)
1770 
        *pval |= 0xFFFFFF80;
1771 
      else
1772 
        *pval &= 0x7F;
1773 
    }
1774 
 
1775 
  if (op == 0)
1776 
    {
1777 
      OUTS (outf, pregs (dst));
1778 
      OUTS (outf, " = ");
1779 
      OUTS (outf, imm7 (src));
1780 
      OUTS (outf, " (X);\t\t/*\t\t");
1781 
      OUTS (outf, pregs (dst));
1782 
      OUTS (outf, "=");
1783 
      OUTS (outf, uimm32 (*pval));
1784 
      OUTS (outf, "(");
1785 
      OUTS (outf, imm32 (*pval));
1786 
      OUTS (outf, ") */");
1787 
      comment = 1;
1788 
    }
1789 
  else if (op == 1)
1790 
    {
1791 
      OUTS (outf, pregs (dst));
1792 
      OUTS (outf, " += ");
1793 
      OUTS (outf, imm7 (src));
1794 
      OUTS (outf, ";\t\t/* (");
1795 
      OUTS (outf, imm7d (src));
1796 
      OUTS (outf, ") */");
1797 
      comment = 1;
1798 
    }
1799 
  else
1800 
    return 0;
1801 
 
1802 
  return 2;
1803 
}
1804 
 
1805 
static int
1806 
decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1807 
{
1808 
  /* LDSTpmod
1809 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1810 
     | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1811 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1812 
  int W   = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1813 
  int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1814 
  int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1815 
  int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1816 
  int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1817 
 
1818 
  if (aop == 1 && W == 0 && idx == ptr)
1819 
    {
1820 
      OUTS (outf, dregs_lo (reg));
1821 
      OUTS (outf, " = W[");
1822 
      OUTS (outf, pregs (ptr));
1823 
      OUTS (outf, "]");
1824 
    }
1825 
  else if (aop == 2 && W == 0 && idx == ptr)
1826 
    {
1827 
      OUTS (outf, dregs_hi (reg));
1828 
      OUTS (outf, " = W[");
1829 
      OUTS (outf, pregs (ptr));
1830 
      OUTS (outf, "]");
1831 
    }
1832 
  else if (aop == 1 && W == 1 && idx == ptr)
1833 
    {
1834 
      OUTS (outf, "W[");
1835 
      OUTS (outf, pregs (ptr));
1836 
      OUTS (outf, "] = ");
1837 
      OUTS (outf, dregs_lo (reg));
1838 
    }
1839 
  else if (aop == 2 && W == 1 && idx == ptr)
1840 
    {
1841 
      OUTS (outf, "W[");
1842 
      OUTS (outf, pregs (ptr));
1843 
      OUTS (outf, "] = ");
1844 
      OUTS (outf, dregs_hi (reg));
1845 
    }
1846 
  else if (aop == 0 && W == 0)
1847 
    {
1848 
      OUTS (outf, dregs (reg));
1849 
      OUTS (outf, " = [");
1850 
      OUTS (outf, pregs (ptr));
1851 
      OUTS (outf, " ++ ");
1852 
      OUTS (outf, pregs (idx));
1853 
      OUTS (outf, "]");
1854 
    }
1855 
  else if (aop == 1 && W == 0)
1856 
    {
1857 
      OUTS (outf, dregs_lo (reg));
1858 
      OUTS (outf, " = W[");
1859 
      OUTS (outf, pregs (ptr));
1860 
      OUTS (outf, " ++ ");
1861 
      OUTS (outf, pregs (idx));
1862 
      OUTS (outf, "]");
1863 
    }
1864 
  else if (aop == 2 && W == 0)
1865 
    {
1866 
      OUTS (outf, dregs_hi (reg));
1867 
      OUTS (outf, " = W[");
1868 
      OUTS (outf, pregs (ptr));
1869 
      OUTS (outf, " ++ ");
1870 
      OUTS (outf, pregs (idx));
1871 
      OUTS (outf, "]");
1872 
    }
1873 
  else if (aop == 3 && W == 0)
1874 
    {
1875 
      OUTS (outf, dregs (reg));
1876 
      OUTS (outf, " = W[");
1877 
      OUTS (outf, pregs (ptr));
1878 
      OUTS (outf, " ++ ");
1879 
      OUTS (outf, pregs (idx));
1880 
      OUTS (outf, "] (Z)");
1881 
    }
1882 
  else if (aop == 3 && W == 1)
1883 
    {
1884 
      OUTS (outf, dregs (reg));
1885 
      OUTS (outf, " = W[");
1886 
      OUTS (outf, pregs (ptr));
1887 
      OUTS (outf, " ++ ");
1888 
      OUTS (outf, pregs (idx));
1889 
      OUTS (outf, "] (X)");
1890 
    }
1891 
  else if (aop == 0 && W == 1)
1892 
    {
1893 
      OUTS (outf, "[");
1894 
      OUTS (outf, pregs (ptr));
1895 
      OUTS (outf, " ++ ");
1896 
      OUTS (outf, pregs (idx));
1897 
      OUTS (outf, "] = ");
1898 
      OUTS (outf, dregs (reg));
1899 
    }
1900 
  else if (aop == 1 && W == 1)
1901 
    {
1902 
      OUTS (outf, "W[");
1903 
      OUTS (outf, pregs (ptr));
1904 
      OUTS (outf, " ++ ");
1905 
      OUTS (outf, pregs (idx));
1906 
      OUTS (outf, "] = ");
1907 
      OUTS (outf, dregs_lo (reg));
1908 
    }
1909 
  else if (aop == 2 && W == 1)
1910 
    {
1911 
      OUTS (outf, "W[");
1912 
      OUTS (outf, pregs (ptr));
1913 
      OUTS (outf, " ++ ");
1914 
      OUTS (outf, pregs (idx));
1915 
      OUTS (outf, "] = ");
1916 
      OUTS (outf, dregs_hi (reg));
1917 
    }
1918 
  else
1919 
    return 0;
1920 
 
1921 
  return 2;
1922 
}
1923 
 
1924 
static int
1925 
decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
1926 
{
1927 
  /* dagMODim
1928 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1929 
     | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
1930 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1931 
  int i  = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
1932 
  int m  = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
1933 
  int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
1934 
  int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
1935 
 
1936 
  if (op == 0 && br == 1)
1937 
    {
1938 
      OUTS (outf, iregs (i));
1939 
      OUTS (outf, " += ");
1940 
      OUTS (outf, mregs (m));
1941 
      OUTS (outf, " (BREV)");
1942 
    }
1943 
  else if (op == 0)
1944 
    {
1945 
      OUTS (outf, iregs (i));
1946 
      OUTS (outf, " += ");
1947 
      OUTS (outf, mregs (m));
1948 
    }
1949 
  else if (op == 1)
1950 
    {
1951 
      OUTS (outf, iregs (i));
1952 
      OUTS (outf, " -= ");
1953 
      OUTS (outf, mregs (m));
1954 
    }
1955 
  else
1956 
    return 0;
1957 
 
1958 
  return 2;
1959 
}
1960 
 
1961 
static int
1962 
decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
1963 
{
1964 
  /* dagMODik
1965 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1966 
     | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
1967 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1968 
  int i  = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
1969 
  int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
1970 
 
1971 
  if (op == 0)
1972 
    {
1973 
      OUTS (outf, iregs (i));
1974 
      OUTS (outf, " += 0x2");
1975 
    }
1976 
  else if (op == 1)
1977 
    {
1978 
      OUTS (outf, iregs (i));
1979 
      OUTS (outf, " -= 0x2");
1980 
    }
1981 
  else if (op == 2)
1982 
    {
1983 
      OUTS (outf, iregs (i));
1984 
      OUTS (outf, " += 0x4");
1985 
    }
1986 
  else if (op == 3)
1987 
    {
1988 
      OUTS (outf, iregs (i));
1989 
      OUTS (outf, " -= 0x4");
1990 
    }
1991 
  else
1992 
    return 0;
1993 
 
1994 
 if (! parallel )
1995 
   {
1996 
     OUTS (outf, ";\t\t/* (  ");
1997 
     if (op == 0 || op == 1)
1998 
       OUTS (outf, "2");
1999 
     else if (op == 2 || op == 3)
2000 
        OUTS (outf, "4");
2001 
     OUTS (outf, ") */");
2002 
    comment = 1;
2003 
  }
2004 
 
2005 
  return 2;
2006 
}
2007 
 
2008 
static int
2009 
decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2010 
{
2011 
  /* dspLDST
2012 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2013 
     | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2014 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2015 
  int i   = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2016 
  int m   = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2017 
  int W   = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2018 
  int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2019 
  int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2020 
 
2021 
  if (aop == 0 && W == 0 && m == 0)
2022 
    {
2023 
      OUTS (outf, dregs (reg));
2024 
      OUTS (outf, " = [");
2025 
      OUTS (outf, iregs (i));
2026 
      OUTS (outf, "++]");
2027 
    }
2028 
  else if (aop == 0 && W == 0 && m == 1)
2029 
    {
2030 
      OUTS (outf, dregs_lo (reg));
2031 
      OUTS (outf, " = W[");
2032 
      OUTS (outf, iregs (i));
2033 
      OUTS (outf, "++]");
2034 
    }
2035 
  else if (aop == 0 && W == 0 && m == 2)
2036 
    {
2037 
      OUTS (outf, dregs_hi (reg));
2038 
      OUTS (outf, " = W[");
2039 
      OUTS (outf, iregs (i));
2040 
      OUTS (outf, "++]");
2041 
    }
2042 
  else if (aop == 1 && W == 0 && m == 0)
2043 
    {
2044 
      OUTS (outf, dregs (reg));
2045 
      OUTS (outf, " = [");
2046 
      OUTS (outf, iregs (i));
2047 
      OUTS (outf, "--]");
2048 
    }
2049 
  else if (aop == 1 && W == 0 && m == 1)
2050 
    {
2051 
      OUTS (outf, dregs_lo (reg));
2052 
      OUTS (outf, " = W[");
2053 
      OUTS (outf, iregs (i));
2054 
      OUTS (outf, "--]");
2055 
    }
2056 
  else if (aop == 1 && W == 0 && m == 2)
2057 
    {
2058 
      OUTS (outf, dregs_hi (reg));
2059 
      OUTS (outf, " = W[");
2060 
      OUTS (outf, iregs (i));
2061 
      OUTS (outf, "--]");
2062 
    }
2063 
  else if (aop == 2 && W == 0 && m == 0)
2064 
    {
2065 
      OUTS (outf, dregs (reg));
2066 
      OUTS (outf, " = [");
2067 
      OUTS (outf, iregs (i));
2068 
      OUTS (outf, "]");
2069 
    }
2070 
  else if (aop == 2 && W == 0 && m == 1)
2071 
    {
2072 
      OUTS (outf, dregs_lo (reg));
2073 
      OUTS (outf, " = W[");
2074 
      OUTS (outf, iregs (i));
2075 
      OUTS (outf, "]");
2076 
    }
2077 
  else if (aop == 2 && W == 0 && m == 2)
2078 
    {
2079 
      OUTS (outf, dregs_hi (reg));
2080 
      OUTS (outf, " = W[");
2081 
      OUTS (outf, iregs (i));
2082 
      OUTS (outf, "]");
2083 
    }
2084 
  else if (aop == 0 && W == 1 && m == 0)
2085 
    {
2086 
      OUTS (outf, "[");
2087 
      OUTS (outf, iregs (i));
2088 
      OUTS (outf, "++] = ");
2089 
      OUTS (outf, dregs (reg));
2090 
    }
2091 
  else if (aop == 0 && W == 1 && m == 1)
2092 
    {
2093 
      OUTS (outf, "W[");
2094 
      OUTS (outf, iregs (i));
2095 
      OUTS (outf, "++] = ");
2096 
      OUTS (outf, dregs_lo (reg));
2097 
    }
2098 
  else if (aop == 0 && W == 1 && m == 2)
2099 
    {
2100 
      OUTS (outf, "W[");
2101 
      OUTS (outf, iregs (i));
2102 
      OUTS (outf, "++] = ");
2103 
      OUTS (outf, dregs_hi (reg));
2104 
    }
2105 
  else if (aop == 1 && W == 1 && m == 0)
2106 
    {
2107 
      OUTS (outf, "[");
2108 
      OUTS (outf, iregs (i));
2109 
      OUTS (outf, "--] = ");
2110 
      OUTS (outf, dregs (reg));
2111 
    }
2112 
  else if (aop == 1 && W == 1 && m == 1)
2113 
    {
2114 
      OUTS (outf, "W[");
2115 
      OUTS (outf, iregs (i));
2116 
      OUTS (outf, "--] = ");
2117 
      OUTS (outf, dregs_lo (reg));
2118 
    }
2119 
  else if (aop == 1 && W == 1 && m == 2)
2120 
    {
2121 
      OUTS (outf, "W[");
2122 
      OUTS (outf, iregs (i));
2123 
      OUTS (outf, "--] = ");
2124 
      OUTS (outf, dregs_hi (reg));
2125 
    }
2126 
  else if (aop == 2 && W == 1 && m == 0)
2127 
    {
2128 
      OUTS (outf, "[");
2129 
      OUTS (outf, iregs (i));
2130 
      OUTS (outf, "] = ");
2131 
      OUTS (outf, dregs (reg));
2132 
    }
2133 
  else if (aop == 2 && W == 1 && m == 1)
2134 
    {
2135 
      OUTS (outf, "W[");
2136 
      OUTS (outf, iregs (i));
2137 
      OUTS (outf, "] = ");
2138 
      OUTS (outf, dregs_lo (reg));
2139 
    }
2140 
  else if (aop == 2 && W == 1 && m == 2)
2141 
    {
2142 
      OUTS (outf, "W[");
2143 
      OUTS (outf, iregs (i));
2144 
      OUTS (outf, "] = ");
2145 
      OUTS (outf, dregs_hi (reg));
2146 
    }
2147 
  else if (aop == 3 && W == 0)
2148 
    {
2149 
      OUTS (outf, dregs (reg));
2150 
      OUTS (outf, " = [");
2151 
      OUTS (outf, iregs (i));
2152 
      OUTS (outf, " ++ ");
2153 
      OUTS (outf, mregs (m));
2154 
      OUTS (outf, "]");
2155 
    }
2156 
  else if (aop == 3 && W == 1)
2157 
    {
2158 
      OUTS (outf, "[");
2159 
      OUTS (outf, iregs (i));
2160 
      OUTS (outf, " ++ ");
2161 
      OUTS (outf, mregs (m));
2162 
      OUTS (outf, "] = ");
2163 
      OUTS (outf, dregs (reg));
2164 
    }
2165 
  else
2166 
    return 0;
2167 
 
2168 
  return 2;
2169 
}
2170 
 
2171 
static int
2172 
decode_LDST_0 (TIword iw0, disassemble_info *outf)
2173 
{
2174 
  /* LDST
2175 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2176 
     | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2177 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2178 
  int Z   = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2179 
  int W   = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2180 
  int sz  = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2181 
  int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2182 
  int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2183 
  int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2184 
 
2185 
  if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2186 
    {
2187 
      OUTS (outf, dregs (reg));
2188 
      OUTS (outf, " = [");
2189 
      OUTS (outf, pregs (ptr));
2190 
      OUTS (outf, "++]");
2191 
    }
2192 
  else if (aop == 0 && sz == 0 && Z == 1 && W == 0)
2193 
    {
2194 
      OUTS (outf, pregs (reg));
2195 
      OUTS (outf, " = [");
2196 
      OUTS (outf, pregs (ptr));
2197 
      OUTS (outf, "++]");
2198 
    }
2199 
  else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2200 
    {
2201 
      OUTS (outf, dregs (reg));
2202 
      OUTS (outf, " = W[");
2203 
      OUTS (outf, pregs (ptr));
2204 
      OUTS (outf, "++] (Z)");
2205 
    }
2206 
  else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2207 
    {
2208 
      OUTS (outf, dregs (reg));
2209 
      OUTS (outf, " = W[");
2210 
      OUTS (outf, pregs (ptr));
2211 
      OUTS (outf, "++] (X)");
2212 
    }
2213 
  else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2214 
    {
2215 
      OUTS (outf, dregs (reg));
2216 
      OUTS (outf, " = B[");
2217 
      OUTS (outf, pregs (ptr));
2218 
      OUTS (outf, "++] (Z)");
2219 
    }
2220 
  else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2221 
    {
2222 
      OUTS (outf, dregs (reg));
2223 
      OUTS (outf, " = B[");
2224 
      OUTS (outf, pregs (ptr));
2225 
      OUTS (outf, "++] (X)");
2226 
    }
2227 
  else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2228 
    {
2229 
      OUTS (outf, dregs (reg));
2230 
      OUTS (outf, " = [");
2231 
      OUTS (outf, pregs (ptr));
2232 
      OUTS (outf, "--]");
2233 
    }
2234 
  else if (aop == 1 && sz == 0 && Z == 1 && W == 0)
2235 
    {
2236 
      OUTS (outf, pregs (reg));
2237 
      OUTS (outf, " = [");
2238 
      OUTS (outf, pregs (ptr));
2239 
      OUTS (outf, "--]");
2240 
    }
2241 
  else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2242 
    {
2243 
      OUTS (outf, dregs (reg));
2244 
      OUTS (outf, " = W[");
2245 
      OUTS (outf, pregs (ptr));
2246 
      OUTS (outf, "--] (Z)");
2247 
    }
2248 
  else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2249 
    {
2250 
      OUTS (outf, dregs (reg));
2251 
      OUTS (outf, " = W[");
2252 
      OUTS (outf, pregs (ptr));
2253 
      OUTS (outf, "--] (X)");
2254 
    }
2255 
  else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2256 
    {
2257 
      OUTS (outf, dregs (reg));
2258 
      OUTS (outf, " = B[");
2259 
      OUTS (outf, pregs (ptr));
2260 
      OUTS (outf, "--] (Z)");
2261 
    }
2262 
  else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2263 
    {
2264 
      OUTS (outf, dregs (reg));
2265 
      OUTS (outf, " = B[");
2266 
      OUTS (outf, pregs (ptr));
2267 
      OUTS (outf, "--] (X)");
2268 
    }
2269 
  else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2270 
    {
2271 
      OUTS (outf, dregs (reg));
2272 
      OUTS (outf, " = [");
2273 
      OUTS (outf, pregs (ptr));
2274 
      OUTS (outf, "]");
2275 
    }
2276 
  else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2277 
    {
2278 
      OUTS (outf, pregs (reg));
2279 
      OUTS (outf, " = [");
2280 
      OUTS (outf, pregs (ptr));
2281 
      OUTS (outf, "]");
2282 
    }
2283 
  else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2284 
    {
2285 
      OUTS (outf, dregs (reg));
2286 
      OUTS (outf, " = W[");
2287 
      OUTS (outf, pregs (ptr));
2288 
      OUTS (outf, "] (Z)");
2289 
    }
2290 
  else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2291 
    {
2292 
      OUTS (outf, dregs (reg));
2293 
      OUTS (outf, " = W[");
2294 
      OUTS (outf, pregs (ptr));
2295 
      OUTS (outf, "] (X)");
2296 
    }
2297 
  else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2298 
    {
2299 
      OUTS (outf, dregs (reg));
2300 
      OUTS (outf, " = B[");
2301 
      OUTS (outf, pregs (ptr));
2302 
      OUTS (outf, "] (Z)");
2303 
    }
2304 
  else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2305 
    {
2306 
      OUTS (outf, dregs (reg));
2307 
      OUTS (outf, " = B[");
2308 
      OUTS (outf, pregs (ptr));
2309 
      OUTS (outf, "] (X)");
2310 
    }
2311 
  else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2312 
    {
2313 
      OUTS (outf, "[");
2314 
      OUTS (outf, pregs (ptr));
2315 
      OUTS (outf, "++] = ");
2316 
      OUTS (outf, dregs (reg));
2317 
    }
2318 
  else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2319 
    {
2320 
      OUTS (outf, "[");
2321 
      OUTS (outf, pregs (ptr));
2322 
      OUTS (outf, "++] = ");
2323 
      OUTS (outf, pregs (reg));
2324 
    }
2325 
  else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2326 
    {
2327 
      OUTS (outf, "W[");
2328 
      OUTS (outf, pregs (ptr));
2329 
      OUTS (outf, "++] = ");
2330 
      OUTS (outf, dregs (reg));
2331 
    }
2332 
  else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2333 
    {
2334 
      OUTS (outf, "B[");
2335 
      OUTS (outf, pregs (ptr));
2336 
      OUTS (outf, "++] = ");
2337 
      OUTS (outf, dregs (reg));
2338 
    }
2339 
  else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2340 
    {
2341 
      OUTS (outf, "[");
2342 
      OUTS (outf, pregs (ptr));
2343 
      OUTS (outf, "--] = ");
2344 
      OUTS (outf, dregs (reg));
2345 
    }
2346 
  else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2347 
    {
2348 
      OUTS (outf, "[");
2349 
      OUTS (outf, pregs (ptr));
2350 
      OUTS (outf, "--] = ");
2351 
      OUTS (outf, pregs (reg));
2352 
    }
2353 
  else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2354 
    {
2355 
      OUTS (outf, "W[");
2356 
      OUTS (outf, pregs (ptr));
2357 
      OUTS (outf, "--] = ");
2358 
      OUTS (outf, dregs (reg));
2359 
    }
2360 
  else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2361 
    {
2362 
      OUTS (outf, "B[");
2363 
      OUTS (outf, pregs (ptr));
2364 
      OUTS (outf, "--] = ");
2365 
      OUTS (outf, dregs (reg));
2366 
    }
2367 
  else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2368 
    {
2369 
      OUTS (outf, "[");
2370 
      OUTS (outf, pregs (ptr));
2371 
      OUTS (outf, "] = ");
2372 
      OUTS (outf, dregs (reg));
2373 
    }
2374 
  else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2375 
    {
2376 
      OUTS (outf, "[");
2377 
      OUTS (outf, pregs (ptr));
2378 
      OUTS (outf, "] = ");
2379 
      OUTS (outf, pregs (reg));
2380 
    }
2381 
  else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2382 
    {
2383 
      OUTS (outf, "W[");
2384 
      OUTS (outf, pregs (ptr));
2385 
      OUTS (outf, "] = ");
2386 
      OUTS (outf, dregs (reg));
2387 
    }
2388 
  else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2389 
    {
2390 
      OUTS (outf, "B[");
2391 
      OUTS (outf, pregs (ptr));
2392 
      OUTS (outf, "] = ");
2393 
      OUTS (outf, dregs (reg));
2394 
    }
2395 
  else
2396 
    return 0;
2397 
 
2398 
  return 2;
2399 
}
2400 
 
2401 
static int
2402 
decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2403 
{
2404 
  /* LDSTiiFP
2405 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2406 
     | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2407 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2408 
  int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2409 
  int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2410 
  int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2411 
 
2412 
  if (W == 0)
2413 
    {
2414 
      OUTS (outf, dpregs (reg));
2415 
      OUTS (outf, " = [FP ");
2416 
      OUTS (outf, negimm5s4 (offset));
2417 
      OUTS (outf, "]");
2418 
    }
2419 
  else if (W == 1)
2420 
    {
2421 
      OUTS (outf, "[FP ");
2422 
      OUTS (outf, negimm5s4 (offset));
2423 
      OUTS (outf, "] = ");
2424 
      OUTS (outf, dpregs (reg));
2425 
    }
2426 
  else
2427 
    return 0;
2428 
 
2429 
  return 2;
2430 
}
2431 
 
2432 
static int
2433 
decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2434 
{
2435 
  /* LDSTii
2436 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2437 
     | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2438 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2439 
  int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2440 
  int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2441 
  int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2442 
  int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2443 
  int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2444 
 
2445 
  if (W == 0 && op == 0)
2446 
    {
2447 
      OUTS (outf, dregs (reg));
2448 
      OUTS (outf, " = [");
2449 
      OUTS (outf, pregs (ptr));
2450 
      OUTS (outf, " + ");
2451 
      OUTS (outf, uimm4s4 (offset));
2452 
      OUTS (outf, "]");
2453 
    }
2454 
  else if (W == 0 && op == 1)
2455 
    {
2456 
      OUTS (outf, dregs (reg));
2457 
      OUTS (outf, " = W[");
2458 
      OUTS (outf, pregs (ptr));
2459 
      OUTS (outf, " + ");
2460 
      OUTS (outf, uimm4s2 (offset));
2461 
      OUTS (outf, "] (Z)");
2462 
    }
2463 
  else if (W == 0 && op == 2)
2464 
    {
2465 
      OUTS (outf, dregs (reg));
2466 
      OUTS (outf, " = W[");
2467 
      OUTS (outf, pregs (ptr));
2468 
      OUTS (outf, " + ");
2469 
      OUTS (outf, uimm4s2 (offset));
2470 
      OUTS (outf, "] (X)");
2471 
    }
2472 
  else if (W == 0 && op == 3)
2473 
    {
2474 
      OUTS (outf, pregs (reg));
2475 
      OUTS (outf, " = [");
2476 
      OUTS (outf, pregs (ptr));
2477 
      OUTS (outf, " + ");
2478 
      OUTS (outf, uimm4s4 (offset));
2479 
      OUTS (outf, "]");
2480 
    }
2481 
  else if (W == 1 && op == 0)
2482 
    {
2483 
      OUTS (outf, "[");
2484 
      OUTS (outf, pregs (ptr));
2485 
      OUTS (outf, " + ");
2486 
      OUTS (outf, uimm4s4 (offset));
2487 
      OUTS (outf, "] = ");
2488 
      OUTS (outf, dregs (reg));
2489 
    }
2490 
  else if (W == 1 && op == 1)
2491 
    {
2492 
      OUTS (outf, "W[");
2493 
      OUTS (outf, pregs (ptr));
2494 
      OUTS (outf, " + ");
2495 
      OUTS (outf, uimm4s2 (offset));
2496 
      OUTS (outf, "] = ");
2497 
      OUTS (outf, dregs (reg));
2498 
    }
2499 
  else if (W == 1 && op == 3)
2500 
    {
2501 
      OUTS (outf, "[");
2502 
      OUTS (outf, pregs (ptr));
2503 
      OUTS (outf, " + ");
2504 
      OUTS (outf, uimm4s4 (offset));
2505 
      OUTS (outf, "] = ");
2506 
      OUTS (outf, pregs (reg));
2507 
    }
2508 
  else
2509 
    return 0;
2510 
 
2511 
  return 2;
2512 
}
2513 
 
2514 
static int
2515 
decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2516 
{
2517 
  /* LoopSetup
2518 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2519 
     | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2520 
     |.reg...........| - | - |.eoffset...............................|
2521 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2522 
  int c   = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2523 
  int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2524 
  int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2525 
  int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2526 
  int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2527 
 
2528 
  if (rop == 0)
2529 
    {
2530 
      OUTS (outf, "LSETUP");
2531 
      OUTS (outf, "(0x");
2532 
      OUTS (outf, pcrel4 (soffset));
2533 
      OUTS (outf, ", 0x");
2534 
      OUTS (outf, lppcrel10 (eoffset));
2535 
      OUTS (outf, ") ");
2536 
      OUTS (outf, counters (c));
2537 
    }
2538 
  else if (rop == 1)
2539 
    {
2540 
      OUTS (outf, "LSETUP");
2541 
      OUTS (outf, "(0x");
2542 
      OUTS (outf, pcrel4 (soffset));
2543 
      OUTS (outf, ", 0x");
2544 
      OUTS (outf, lppcrel10 (eoffset));
2545 
      OUTS (outf, ") ");
2546 
      OUTS (outf, counters (c));
2547 
      OUTS (outf, " = ");
2548 
      OUTS (outf, pregs (reg));
2549 
    }
2550 
  else if (rop == 3)
2551 
    {
2552 
      OUTS (outf, "LSETUP");
2553 
      OUTS (outf, "(0x");
2554 
      OUTS (outf, pcrel4 (soffset));
2555 
      OUTS (outf, ", 0x");
2556 
      OUTS (outf, lppcrel10 (eoffset));
2557 
      OUTS (outf, ") ");
2558 
      OUTS (outf, counters (c));
2559 
      OUTS (outf, " = ");
2560 
      OUTS (outf, pregs (reg));
2561 
      OUTS (outf, " >> 0x1");
2562 
    }
2563 
  else
2564 
    return 0;
2565 
 
2566 
  return 4;
2567 
}
2568 
 
2569 
static int
2570 
decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2571 
{
2572 
  /* LDIMMhalf
2573 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2574 
     | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2575 
     |.hword.........................................................|
2576 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2577 
  int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2578 
  int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2579 
  int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2580 
  int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2581 
  int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2582 
  int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2583 
 
2584 
  bu32 *pval = get_allreg (grp, reg);
2585 
 
2586 
  /* Since we don't have 32-bit immediate loads, we allow the disassembler
2587 
     to combine them, so it prints out the right values.
2588 
     Here we keep track of the registers.  */
2589 
  if (H == 0 && S == 1 && Z == 0)
2590 
    {
2591 
      /* regs = imm16 (x) */
2592 
      *pval = imm16_val (hword);
2593 
      if (hword & 0x8000)
2594 
        *pval |= 0xFFFF0000;
2595 
      else
2596 
        *pval &= 0xFFFF;
2597 
    }
2598 
  else if (H == 0 && S == 0 && Z == 1)
2599 
    {
2600 
      /* regs = luimm16 (Z) */
2601 
      *pval = luimm16_val (hword);
2602 
      *pval &= 0xFFFF;
2603 
    }
2604 
  else if (H == 0 && S == 0 && Z == 0)
2605 
    {
2606 
      /* regs_lo = luimm16 */
2607 
      *pval &= 0xFFFF0000;
2608 
      *pval |= luimm16_val (hword);
2609 
    }
2610 
  else if (H == 1 && S == 0 && Z == 0)
2611 
    {
2612 
      /* regs_hi = huimm16 */
2613 
      *pval &= 0xFFFF;
2614 
      *pval |= luimm16_val (hword) << 16;
2615 
    }
2616 
 
2617 
  /* Here we do the disassembly */
2618 
  if (grp == 0 && H == 0 && S == 0 && Z == 0)
2619 
    {
2620 
      OUTS (outf, dregs_lo (reg));
2621 
      OUTS (outf, " = ");
2622 
      OUTS (outf, uimm16 (hword));
2623 
    }
2624 
  else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2625 
    {
2626 
      OUTS (outf, dregs_hi (reg));
2627 
      OUTS (outf, " = ");
2628 
      OUTS (outf, uimm16 (hword));
2629 
    }
2630 
  else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2631 
    {
2632 
      OUTS (outf, dregs (reg));
2633 
      OUTS (outf, " = ");
2634 
      OUTS (outf, imm16 (hword));
2635 
      OUTS (outf, " (X)");
2636 
    }
2637 
  else if (H == 0 && S == 1 && Z == 0)
2638 
   {
2639 
      OUTS (outf, regs (reg, grp));
2640 
      OUTS (outf, " = ");
2641 
      OUTS (outf, imm16 (hword));
2642 
      OUTS (outf, " (X)");
2643 
    }
2644 
  else if (H == 0 && S == 0 && Z == 1)
2645 
    {
2646 
      OUTS (outf, regs (reg, grp));
2647 
      OUTS (outf, " = ");
2648 
      OUTS (outf, uimm16 (hword));
2649 
      OUTS (outf, " (Z)");
2650 
    }
2651 
  else if (H == 0 && S == 0 && Z == 0)
2652 
    {
2653 
      OUTS (outf, regs_lo (reg, grp));
2654 
      OUTS (outf, " = ");
2655 
      OUTS (outf, uimm16 (hword));
2656 
    }
2657 
  else if (H == 1 && S == 0 && Z == 0)
2658 
    {
2659 
      OUTS (outf, regs_hi (reg, grp));
2660 
      OUTS (outf, " = ");
2661 
      OUTS (outf, uimm16 (hword));
2662 
    }
2663 
  else
2664 
    return 0;
2665 
 
2666 
  /* And we print out the 32-bit value if it is a pointer.  */
2667 
  if (S == 0 && Z == 0)
2668 
    {
2669 
      OUTS (outf, ";\t\t/* (");
2670 
      OUTS (outf, imm16d (hword));
2671 
      OUTS (outf, ")\t");
2672 
 
2673 
      /* If it is an MMR, don't print the symbol.  */
2674 
      if (*pval < 0xFFC00000 && grp == 1)
2675 
        {
2676 
          OUTS (outf, regs (reg, grp));
2677 
          OUTS (outf, "=0x");
2678 
          OUTS (outf, huimm32e (*pval));
2679 
        }
2680 
      else
2681 
        {
2682 
          OUTS (outf, regs (reg, grp));
2683 
          OUTS (outf, "=0x");
2684 
          OUTS (outf, huimm32e (*pval));
2685 
          OUTS (outf, "(");
2686 
          OUTS (outf, imm32 (*pval));
2687 
          OUTS (outf, ")");
2688 
        }
2689 
 
2690 
      OUTS (outf, " */");
2691 
      comment = 1;
2692 
    }
2693 
  if (S == 1 || Z == 1)
2694 
    {
2695 
       OUTS (outf, ";\t\t/*\t\t");
2696 
       OUTS (outf, regs (reg, grp));
2697 
       OUTS (outf, "=0x");
2698 
       OUTS (outf, huimm32e (*pval));
2699 
       OUTS (outf, "(");
2700 
       OUTS (outf, imm32 (*pval));
2701 
       OUTS (outf, ") */");
2702 
       comment = 1;
2703 
    }
2704 
  return 4;
2705 
}
2706 
 
2707 
static int
2708 
decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2709 
{
2710 
  /* CALLa
2711 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2712 
     | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2713 
     |.lsw...........................................................|
2714 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2715 
  int S   = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2716 
  int lsw = ((iw1 >> 0) & 0xffff);
2717 
  int msw = ((iw0 >> 0) & 0xff);
2718 
 
2719 
  if (S == 1)
2720 
    OUTS (outf, "CALL 0x");
2721 
  else if (S == 0)
2722 
    OUTS (outf, "JUMP.L 0x");
2723 
  else
2724 
    return 0;
2725 
 
2726 
  OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2727 
  return 4;
2728 
}
2729 
 
2730 
static int
2731 
decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2732 
{
2733 
  /* LDSTidxI
2734 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2735 
     | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2736 
     |.offset........................................................|
2737 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2738 
  int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2739 
  int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2740 
  int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2741 
  int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2742 
  int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2743 
  int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2744 
 
2745 
  if (W == 0 && sz == 0 && Z == 0)
2746 
    {
2747 
      OUTS (outf, dregs (reg));
2748 
      OUTS (outf, " = [");
2749 
      OUTS (outf, pregs (ptr));
2750 
      OUTS (outf, " + ");
2751 
      OUTS (outf, imm16s4 (offset));
2752 
      OUTS (outf, "]");
2753 
    }
2754 
  else if (W == 0 && sz == 0 && Z == 1)
2755 
    {
2756 
      OUTS (outf, pregs (reg));
2757 
      OUTS (outf, " = [");
2758 
      OUTS (outf, pregs (ptr));
2759 
      OUTS (outf, " + ");
2760 
      OUTS (outf, imm16s4 (offset));
2761 
      OUTS (outf, "]");
2762 
    }
2763 
  else if (W == 0 && sz == 1 && Z == 0)
2764 
    {
2765 
      OUTS (outf, dregs (reg));
2766 
      OUTS (outf, " = W[");
2767 
      OUTS (outf, pregs (ptr));
2768 
      OUTS (outf, " + ");
2769 
      OUTS (outf, imm16s2 (offset));
2770 
      OUTS (outf, "] (Z)");
2771 
    }
2772 
  else if (W == 0 && sz == 1 && Z == 1)
2773 
    {
2774 
      OUTS (outf, dregs (reg));
2775 
      OUTS (outf, " = W[");
2776 
      OUTS (outf, pregs (ptr));
2777 
      OUTS (outf, " + ");
2778 
      OUTS (outf, imm16s2 (offset));
2779 
      OUTS (outf, "] (X)");
2780 
    }
2781 
  else if (W == 0 && sz == 2 && Z == 0)
2782 
    {
2783 
      OUTS (outf, dregs (reg));
2784 
      OUTS (outf, " = B[");
2785 
      OUTS (outf, pregs (ptr));
2786 
      OUTS (outf, " + ");
2787 
      OUTS (outf, imm16 (offset));
2788 
      OUTS (outf, "] (Z)");
2789 
    }
2790 
  else if (W == 0 && sz == 2 && Z == 1)
2791 
    {
2792 
      OUTS (outf, dregs (reg));
2793 
      OUTS (outf, " = B[");
2794 
      OUTS (outf, pregs (ptr));
2795 
      OUTS (outf, " + ");
2796 
      OUTS (outf, imm16 (offset));
2797 
      OUTS (outf, "] (X)");
2798 
    }
2799 
  else if (W == 1 && sz == 0 && Z == 0)
2800 
    {
2801 
      OUTS (outf, "[");
2802 
      OUTS (outf, pregs (ptr));
2803 
      OUTS (outf, " + ");
2804 
      OUTS (outf, imm16s4 (offset));
2805 
      OUTS (outf, "] = ");
2806 
      OUTS (outf, dregs (reg));
2807 
    }
2808 
  else if (W == 1 && sz == 0 && Z == 1)
2809 
    {
2810 
      OUTS (outf, "[");
2811 
      OUTS (outf, pregs (ptr));
2812 
      OUTS (outf, " + ");
2813 
      OUTS (outf, imm16s4 (offset));
2814 
      OUTS (outf, "] = ");
2815 
      OUTS (outf, pregs (reg));
2816 
    }
2817 
  else if (W == 1 && sz == 1 && Z == 0)
2818 
    {
2819 
      OUTS (outf, "W[");
2820 
      OUTS (outf, pregs (ptr));
2821 
      OUTS (outf, " + ");
2822 
      OUTS (outf, imm16s2 (offset));
2823 
      OUTS (outf, "] = ");
2824 
      OUTS (outf, dregs (reg));
2825 
    }
2826 
  else if (W == 1 && sz == 2 && Z == 0)
2827 
    {
2828 
      OUTS (outf, "B[");
2829 
      OUTS (outf, pregs (ptr));
2830 
      OUTS (outf, " + ");
2831 
      OUTS (outf, imm16 (offset));
2832 
      OUTS (outf, "] = ");
2833 
      OUTS (outf, dregs (reg));
2834 
    }
2835 
  else
2836 
    return 0;
2837 
 
2838 
  return 4;
2839 
}
2840 
 
2841 
static int
2842 
decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2843 
{
2844 
  /* linkage
2845 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2846 
     | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2847 
     |.framesize.....................................................|
2848 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2849 
  int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2850 
  int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2851 
 
2852 
  if (R == 0)
2853 
    {
2854 
      OUTS (outf, "LINK ");
2855 
      OUTS (outf, uimm16s4 (framesize));
2856 
      OUTS (outf, ";\t\t/* (");
2857 
      OUTS (outf, uimm16s4d (framesize));
2858 
      OUTS (outf, ") */");
2859 
      comment = 1;
2860 
    }
2861 
  else if (R == 1)
2862 
    OUTS (outf, "UNLINK");
2863 
  else
2864 
    return 0;
2865 
 
2866 
  return 4;
2867 
}
2868 
 
2869 
static int
2870 
decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2871 
{
2872 
  /* dsp32mac
2873 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2874 
     | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2875 
     |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2876 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2877 
  int op1  = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2878 
  int w1   = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2879 
  int P    = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2880 
  int MM   = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2881 
  int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2882 
  int w0   = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2883 
  int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2884 
  int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2885 
  int dst  = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2886 
  int h10  = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2887 
  int h00  = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2888 
  int op0  = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2889 
  int h11  = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2890 
  int h01  = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
2891 
 
2892 
  if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2893 
    return 0;
2894 
 
2895 
  if (op1 == 3 && MM)
2896 
    return 0;
2897 
 
2898 
  if ((w1 || w0) && mmod == M_W32)
2899 
    return 0;
2900 
 
2901 
  if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
2902 
    return 0;
2903 
 
2904 
  if (w1 == 1 || op1 != 3)
2905 
    {
2906 
      if (w1)
2907 
        OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
2908 
 
2909 
      if (op1 == 3)
2910 
        OUTS (outf, " = A1");
2911 
      else
2912 
        {
2913 
          if (w1)
2914 
            OUTS (outf, " = (");
2915 
          decode_macfunc (1, op1, h01, h11, src0, src1, outf);
2916 
          if (w1)
2917 
            OUTS (outf, ")");
2918 
        }
2919 
 
2920 
      if (w0 == 1 || op0 != 3)
2921 
        {
2922 
          if (MM)
2923 
            OUTS (outf, " (M)");
2924 
          MM = 0;
2925 
          OUTS (outf, ", ");
2926 
        }
2927 
    }
2928 
 
2929 
  if (w0 == 1 || op0 != 3)
2930 
    {
2931 
      if (w0)
2932 
        OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
2933 
 
2934 
      if (op0 == 3)
2935 
        OUTS (outf, " = A0");
2936 
      else
2937 
        {
2938 
          if (w0)
2939 
            OUTS (outf, " = (");
2940 
          decode_macfunc (0, op0, h00, h10, src0, src1, outf);
2941 
          if (w0)
2942 
            OUTS (outf, ")");
2943 
        }
2944 
    }
2945 
 
2946 
  decode_optmode (mmod, MM, outf);
2947 
 
2948 
  return 4;
2949 
}
2950 
 
2951 
static int
2952 
decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2953 
{
2954 
  /* dsp32mult
2955 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2956 
     | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
2957 
     |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2958 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2959 
  int w1   = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2960 
  int P    = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2961 
  int MM   = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2962 
  int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2963 
  int w0   = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2964 
  int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2965 
  int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2966 
  int dst  = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2967 
  int h10  = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2968 
  int h00  = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2969 
  int h11  = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2970 
  int h01  = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
2971 
 
2972 
  if (w1 == 0 && w0 == 0)
2973 
    return 0;
2974 
 
2975 
  if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
2976 
    return 0;
2977 
 
2978 
  if (w1)
2979 
    {
2980 
      OUTS (outf, P ? dregs (dst | 1) : dregs_hi (dst));
2981 
      OUTS (outf, " = ");
2982 
      decode_multfunc (h01, h11, src0, src1, outf);
2983 
 
2984 
      if (w0)
2985 
        {
2986 
          if (MM)
2987 
            OUTS (outf, " (M)");
2988 
          MM = 0;
2989 
          OUTS (outf, ", ");
2990 
        }
2991 
    }
2992 
 
2993 
  if (w0)
2994 
    {
2995 
      OUTS (outf, dregs (dst));
2996 
      OUTS (outf, " = ");
2997 
      decode_multfunc (h00, h10, src0, src1, outf);
2998 
    }
2999 
 
3000 
  decode_optmode (mmod, MM, outf);
3001 
  return 4;
3002 
}
3003 
 
3004 
static int
3005 
decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3006 
{
3007 
  /* dsp32alu
3008 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3009 
     | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3010 
     |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3011 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
3012 
  int s    = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3013 
  int x    = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3014 
  int aop  = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3015 
  int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3016 
  int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3017 
  int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3018 
  int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3019 
  int HL   = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3020 
  int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3021 
 
3022 
  if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3023 
    {
3024 
      OUTS (outf, "A0.L = ");
3025 
      OUTS (outf, dregs_lo (src0));
3026 
    }
3027 
  else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3028 
    {
3029 
      OUTS (outf, "A1.H = ");
3030 
      OUTS (outf, dregs_hi (src0));
3031 
    }
3032 
  else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3033 
    {
3034 
      OUTS (outf, "A1.L = ");
3035 
      OUTS (outf, dregs_lo (src0));
3036 
    }
3037 
  else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3038 
    {
3039 
      OUTS (outf, "A0.H = ");
3040 
      OUTS (outf, dregs_hi (src0));
3041 
    }
3042 
  else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3043 
    {
3044 
      OUTS (outf, dregs_hi (dst0));
3045 
      OUTS (outf, " = ");
3046 
      OUTS (outf, dregs (src0));
3047 
      OUTS (outf, " - ");
3048 
      OUTS (outf, dregs (src1));
3049 
      OUTS (outf, " (RND20)");
3050 
    }
3051 
  else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3052 
    {
3053 
      OUTS (outf, dregs_hi (dst0));
3054 
      OUTS (outf, " = ");
3055 
      OUTS (outf, dregs (src0));
3056 
      OUTS (outf, " + ");
3057 
      OUTS (outf, dregs (src1));
3058 
      OUTS (outf, " (RND20)");
3059 
    }
3060 
  else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3061 
    {
3062 
      OUTS (outf, dregs_lo (dst0));
3063 
      OUTS (outf, " = ");
3064 
      OUTS (outf, dregs (src0));
3065 
      OUTS (outf, " - ");
3066 
      OUTS (outf, dregs (src1));
3067 
      OUTS (outf, " (RND12)");
3068 
    }
3069 
  else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3070 
    {
3071 
      OUTS (outf, dregs_lo (dst0));
3072 
      OUTS (outf, " = ");
3073 
      OUTS (outf, dregs (src0));
3074 
      OUTS (outf, " + ");
3075 
      OUTS (outf, dregs (src1));
3076 
      OUTS (outf, " (RND12)");
3077 
    }
3078 
  else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3079 
    {
3080 
      OUTS (outf, dregs_lo (dst0));
3081 
      OUTS (outf, " = ");
3082 
      OUTS (outf, dregs (src0));
3083 
      OUTS (outf, " - ");
3084 
      OUTS (outf, dregs (src1));
3085 
      OUTS (outf, " (RND20)");
3086 
    }
3087 
  else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3088 
    {
3089 
      OUTS (outf, dregs_hi (dst0));
3090 
      OUTS (outf, " = ");
3091 
      OUTS (outf, dregs (src0));
3092 
      OUTS (outf, " + ");
3093 
      OUTS (outf, dregs (src1));
3094 
      OUTS (outf, " (RND12)");
3095 
    }
3096 
  else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3097 
    {
3098 
      OUTS (outf, dregs_lo (dst0));
3099 
      OUTS (outf, " = ");
3100 
      OUTS (outf, dregs (src0));
3101 
      OUTS (outf, " + ");
3102 
      OUTS (outf, dregs (src1));
3103 
      OUTS (outf, " (RND20)");
3104 
    }
3105 
  else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3106 
    {
3107 
      OUTS (outf, dregs_hi (dst0));
3108 
      OUTS (outf, " = ");
3109 
      OUTS (outf, dregs (src0));
3110 
      OUTS (outf, " - ");
3111 
      OUTS (outf, dregs (src1));
3112 
      OUTS (outf, " (RND12)");
3113 
    }
3114 
  else if (HL == 1 && aop == 0 && aopcde == 2)
3115 
    {
3116 
      OUTS (outf, dregs_hi (dst0));
3117 
      OUTS (outf, " = ");
3118 
      OUTS (outf, dregs_lo (src0));
3119 
      OUTS (outf, " + ");
3120 
      OUTS (outf, dregs_lo (src1));
3121 
      amod1 (s, x, outf);
3122 
    }
3123 
  else if (HL == 1 && aop == 1 && aopcde == 2)
3124 
    {
3125 
      OUTS (outf, dregs_hi (dst0));
3126 
      OUTS (outf, " = ");
3127 
      OUTS (outf, dregs_lo (src0));
3128 
      OUTS (outf, " + ");
3129 
      OUTS (outf, dregs_hi (src1));
3130 
      amod1 (s, x, outf);
3131 
    }
3132 
  else if (HL == 1 && aop == 2 && aopcde == 2)
3133 
    {
3134 
      OUTS (outf, dregs_hi (dst0));
3135 
      OUTS (outf, " = ");
3136 
      OUTS (outf, dregs_hi (src0));
3137 
      OUTS (outf, " + ");
3138 
      OUTS (outf, dregs_lo (src1));
3139 
      amod1 (s, x, outf);
3140 
    }
3141 
  else if (HL == 1 && aop == 3 && aopcde == 2)
3142 
    {
3143 
      OUTS (outf, dregs_hi (dst0));
3144 
      OUTS (outf, " = ");
3145 
      OUTS (outf, dregs_hi (src0));
3146 
      OUTS (outf, " + ");
3147 
      OUTS (outf, dregs_hi (src1));
3148 
      amod1 (s, x, outf);
3149 
    }
3150 
  else if (HL == 0 && aop == 0 && aopcde == 3)
3151 
    {
3152 
      OUTS (outf, dregs_lo (dst0));
3153 
      OUTS (outf, " = ");
3154 
      OUTS (outf, dregs_lo (src0));
3155 
      OUTS (outf, " - ");
3156 
      OUTS (outf, dregs_lo (src1));
3157 
      amod1 (s, x, outf);
3158 
    }
3159 
  else if (HL == 0 && aop == 1 && aopcde == 3)
3160 
    {
3161 
      OUTS (outf, dregs_lo (dst0));
3162 
      OUTS (outf, " = ");
3163 
      OUTS (outf, dregs_lo (src0));
3164 
      OUTS (outf, " - ");
3165 
      OUTS (outf, dregs_hi (src1));
3166 
      amod1 (s, x, outf);
3167 
    }
3168 
  else if (HL == 0 && aop == 3 && aopcde == 2)
3169 
    {
3170 
      OUTS (outf, dregs_lo (dst0));
3171 
      OUTS (outf, " = ");
3172 
      OUTS (outf, dregs_hi (src0));
3173 
      OUTS (outf, " + ");
3174 
      OUTS (outf, dregs_hi (src1));
3175 
      amod1 (s, x, outf);
3176 
    }
3177 
  else if (HL == 1 && aop == 0 && aopcde == 3)
3178 
    {
3179 
      OUTS (outf, dregs_hi (dst0));
3180 
      OUTS (outf, " = ");
3181 
      OUTS (outf, dregs_lo (src0));
3182 
      OUTS (outf, " - ");
3183 
      OUTS (outf, dregs_lo (src1));
3184 
      amod1 (s, x, outf);
3185 
    }
3186 
  else if (HL == 1 && aop == 1 && aopcde == 3)
3187 
    {
3188 
      OUTS (outf, dregs_hi (dst0));
3189 
      OUTS (outf, " = ");
3190 
      OUTS (outf, dregs_lo (src0));
3191 
      OUTS (outf, " - ");
3192 
      OUTS (outf, dregs_hi (src1));
3193 
      amod1 (s, x, outf);
3194 
    }
3195 
  else if (HL == 1 && aop == 2 && aopcde == 3)
3196 
    {
3197 
      OUTS (outf, dregs_hi (dst0));
3198 
      OUTS (outf, " = ");
3199 
      OUTS (outf, dregs_hi (src0));
3200 
      OUTS (outf, " - ");
3201 
      OUTS (outf, dregs_lo (src1));
3202 
      amod1 (s, x, outf);
3203 
    }
3204 
  else if (HL == 1 && aop == 3 && aopcde == 3)
3205 
    {
3206 
      OUTS (outf, dregs_hi (dst0));
3207 
      OUTS (outf, " = ");
3208 
      OUTS (outf, dregs_hi (src0));
3209 
      OUTS (outf, " - ");
3210 
      OUTS (outf, dregs_hi (src1));
3211 
      amod1 (s, x, outf);
3212 
    }
3213 
  else if (HL == 0 && aop == 2 && aopcde == 2)
3214 
    {
3215 
      OUTS (outf, dregs_lo (dst0));
3216 
      OUTS (outf, " = ");
3217 
      OUTS (outf, dregs_hi (src0));
3218 
      OUTS (outf, " + ");
3219 
      OUTS (outf, dregs_lo (src1));
3220 
      amod1 (s, x, outf);
3221 
    }
3222 
  else if (HL == 0 && aop == 1 && aopcde == 2)
3223 
    {
3224 
      OUTS (outf, dregs_lo (dst0));
3225 
      OUTS (outf, " = ");
3226 
      OUTS (outf, dregs_lo (src0));
3227 
      OUTS (outf, " + ");
3228 
      OUTS (outf, dregs_hi (src1));
3229 
      amod1 (s, x, outf);
3230 
    }
3231 
  else if (HL == 0 && aop == 2 && aopcde == 3)
3232 
    {
3233 
      OUTS (outf, dregs_lo (dst0));
3234 
      OUTS (outf, " = ");
3235 
      OUTS (outf, dregs_hi (src0));
3236 
      OUTS (outf, " - ");
3237 
      OUTS (outf, dregs_lo (src1));
3238 
      amod1 (s, x, outf);
3239 
    }
3240 
  else if (HL == 0 && aop == 3 && aopcde == 3)
3241 
    {
3242 
      OUTS (outf, dregs_lo (dst0));
3243 
      OUTS (outf, " = ");
3244 
      OUTS (outf, dregs_hi (src0));
3245 
      OUTS (outf, " - ");
3246 
      OUTS (outf, dregs_hi (src1));
3247 
      amod1 (s, x, outf);
3248 
    }
3249 
  else if (HL == 0 && aop == 0 && aopcde == 2)
3250 
    {
3251 
      OUTS (outf, dregs_lo (dst0));
3252 
      OUTS (outf, " = ");
3253 
      OUTS (outf, dregs_lo (src0));
3254 
      OUTS (outf, " + ");
3255 
      OUTS (outf, dregs_lo (src1));
3256 
      amod1 (s, x, outf);
3257 
    }
3258 
  else if (aop == 0 && aopcde == 9 && s == 1)
3259 
    {
3260 
      OUTS (outf, "A0 = ");
3261 
      OUTS (outf, dregs (src0));
3262 
    }
3263 
  else if (aop == 3 && aopcde == 11 && s == 0)
3264 
    OUTS (outf, "A0 -= A1");
3265 
 
3266 
  else if (aop == 3 && aopcde == 11 && s == 1)
3267 
    OUTS (outf, "A0 -= A1 (W32)");
3268 
 
3269 
  else if (aop == 3 && aopcde == 22 && HL == 1)
3270 
    {
3271 
      OUTS (outf, dregs (dst0));
3272 
      OUTS (outf, " = BYTEOP2M (");
3273 
      OUTS (outf, dregs (src0 + 1));
3274 
      OUTS (outf, ":");
3275 
      OUTS (outf, imm5 (src0));
3276 
      OUTS (outf, ", ");
3277 
      OUTS (outf, dregs (src1 + 1));
3278 
      OUTS (outf, ":");
3279 
      OUTS (outf, imm5 (src1));
3280 
      OUTS (outf, ") (TH");
3281 
      if (s == 1)
3282 
        OUTS (outf, ", R)");
3283 
      else
3284 
        OUTS (outf, ")");
3285 
    }
3286 
  else if (aop == 3 && aopcde == 22 && HL == 0)
3287 
    {
3288 
      OUTS (outf, dregs (dst0));
3289 
      OUTS (outf, " = BYTEOP2M (");
3290 
      OUTS (outf, dregs (src0 + 1));
3291 
      OUTS (outf, ":");
3292 
      OUTS (outf, imm5 (src0));
3293 
      OUTS (outf, ", ");
3294 
      OUTS (outf, dregs (src1 + 1));
3295 
      OUTS (outf, ":");
3296 
      OUTS (outf, imm5 (src1));
3297 
      OUTS (outf, ") (TL");
3298 
      if (s == 1)
3299 
        OUTS (outf, ", R)");
3300 
      else
3301 
        OUTS (outf, ")");
3302 
    }
3303 
  else if (aop == 2 && aopcde == 22 && HL == 1)
3304 
    {
3305 
      OUTS (outf, dregs (dst0));
3306 
      OUTS (outf, " = BYTEOP2M (");
3307 
      OUTS (outf, dregs (src0 + 1));
3308 
      OUTS (outf, ":");
3309 
      OUTS (outf, imm5 (src0));
3310 
      OUTS (outf, ", ");
3311 
      OUTS (outf, dregs (src1 + 1));
3312 
      OUTS (outf, ":");
3313 
      OUTS (outf, imm5 (src1));
3314 
      OUTS (outf, ") (RNDH");
3315 
      if (s == 1)
3316 
        OUTS (outf, ", R)");
3317 
      else
3318 
        OUTS (outf, ")");
3319 
    }
3320 
  else if (aop == 2 && aopcde == 22 && HL == 0)
3321 
    {
3322 
      OUTS (outf, dregs (dst0));
3323 
      OUTS (outf, " = BYTEOP2M (");
3324 
      OUTS (outf, dregs (src0 + 1));
3325 
      OUTS (outf, ":");
3326 
      OUTS (outf, imm5 (src0));
3327 
      OUTS (outf, ", ");
3328 
      OUTS (outf, dregs (src1 + 1));
3329 
      OUTS (outf, ":");
3330 
      OUTS (outf, imm5 (src1));
3331 
      OUTS (outf, ") (RNDL");
3332 
      if (s == 1)
3333 
        OUTS (outf, ", R)");
3334 
      else
3335 
        OUTS (outf, ")");
3336 
    }
3337 
  else if (aop == 1 && aopcde == 22 && HL == 1)
3338 
    {
3339 
      OUTS (outf, dregs (dst0));
3340 
      OUTS (outf, " = BYTEOP2P (");
3341 
      OUTS (outf, dregs (src0 + 1));
3342 
      OUTS (outf, ":");
3343 
      OUTS (outf, imm5d (src0));
3344 
      OUTS (outf, ", ");
3345 
      OUTS (outf, dregs (src1 + 1));
3346 
      OUTS (outf, ":");
3347 
      OUTS (outf, imm5d (src1));
3348 
      OUTS (outf, ") (TH");
3349 
      if (s == 1)
3350 
        OUTS (outf, ", R)");
3351 
      else
3352 
        OUTS (outf, ")");
3353 
    }
3354 
  else if (aop == 1 && aopcde == 22 && HL == 0)
3355 
    {
3356 
      OUTS (outf, dregs (dst0));
3357 
      OUTS (outf, " = BYTEOP2P (");
3358 
      OUTS (outf, dregs (src0 + 1));
3359 
      OUTS (outf, ":");
3360 
      OUTS (outf, imm5d (src0));
3361 
      OUTS (outf, ", ");
3362 
      OUTS (outf, dregs (src1 + 1));
3363 
      OUTS (outf, ":");
3364 
      OUTS (outf, imm5d (src1));
3365 
      OUTS (outf, ") (TL");
3366 
      if (s == 1)
3367 
        OUTS (outf, ", R)");
3368 
      else
3369 
        OUTS (outf, ")");
3370 
    }
3371 
  else if (aop == 0 && aopcde == 22 && HL == 1)
3372 
    {
3373 
      OUTS (outf, dregs (dst0));
3374 
      OUTS (outf, " = BYTEOP2P (");
3375 
      OUTS (outf, dregs (src0 + 1));
3376 
      OUTS (outf, ":");
3377 
      OUTS (outf, imm5d (src0));
3378 
      OUTS (outf, ", ");
3379 
      OUTS (outf, dregs (src1 + 1));
3380 
      OUTS (outf, ":");
3381 
      OUTS (outf, imm5d (src1));
3382 
      OUTS (outf, ") (RNDH");
3383 
      if (s == 1)
3384 
        OUTS (outf, ", R)");
3385 
      else
3386 
        OUTS (outf, ")");
3387 
    }
3388 
  else if (aop == 0 && aopcde == 22 && HL == 0)
3389 
    {
3390 
      OUTS (outf, dregs (dst0));
3391 
      OUTS (outf, " = BYTEOP2P (");
3392 
      OUTS (outf, dregs (src0 + 1));
3393 
      OUTS (outf, ":");
3394 
      OUTS (outf, imm5d (src0));
3395 
      OUTS (outf, ", ");
3396 
      OUTS (outf, dregs (src1 + 1));
3397 
      OUTS (outf, ":");
3398 
      OUTS (outf, imm5d (src1));
3399 
      OUTS (outf, ") (RNDL");
3400 
      if (s == 1)
3401 
        OUTS (outf, ", R)");
3402 
      else
3403 
        OUTS (outf, ")");
3404 
    }
3405 
  else if (aop == 0 && s == 0 && aopcde == 8)
3406 
    OUTS (outf, "A0 = 0");
3407 
 
3408 
  else if (aop == 0 && s == 1 && aopcde == 8)
3409 
    OUTS (outf, "A0 = A0 (S)");
3410 
 
3411 
  else if (aop == 1 && s == 0 && aopcde == 8)
3412 
    OUTS (outf, "A1 = 0");
3413 
 
3414 
  else if (aop == 1 && s == 1 && aopcde == 8)
3415 
    OUTS (outf, "A1 = A1 (S)");
3416 
 
3417 
  else if (aop == 2 && s == 0 && aopcde == 8)
3418 
    OUTS (outf, "A1 = A0 = 0");
3419 
 
3420 
  else if (aop == 2 && s == 1 && aopcde == 8)
3421 
    OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
3422 
 
3423 
  else if (aop == 3 && s == 0 && aopcde == 8)
3424 
    OUTS (outf, "A0 = A1");
3425 
 
3426 
  else if (aop == 3 && s == 1 && aopcde == 8)
3427 
    OUTS (outf, "A1 = A0");
3428 
 
3429 
  else if (aop == 1 && aopcde == 9 && s == 0)
3430 
    {
3431 
      OUTS (outf, "A0.X = ");
3432 
      OUTS (outf, dregs_lo (src0));
3433 
    }
3434 
  else if (aop == 1 && HL == 0 && aopcde == 11)
3435 
    {
3436 
      OUTS (outf, dregs_lo (dst0));
3437 
      OUTS (outf, " = (A0 += A1)");
3438 
    }
3439 
  else if (aop == 3 && HL == 0 && aopcde == 16)
3440 
    OUTS (outf, "A1 = ABS A0, A0 = ABS A0");
3441 
 
3442 
  else if (aop == 0 && aopcde == 23 && HL == 1)
3443 
    {
3444 
      OUTS (outf, dregs (dst0));
3445 
      OUTS (outf, " = BYTEOP3P (");
3446 
      OUTS (outf, dregs (src0 + 1));
3447 
      OUTS (outf, ":");
3448 
      OUTS (outf, imm5d (src0));
3449 
      OUTS (outf, ", ");
3450 
      OUTS (outf, dregs (src1 + 1));
3451 
      OUTS (outf, ":");
3452 
      OUTS (outf, imm5d (src1));
3453 
      OUTS (outf, ") (HI");
3454 
      if (s == 1)
3455 
        OUTS (outf, ", R)");
3456 
      else
3457 
        OUTS (outf, ")");
3458 
    }
3459 
  else if (aop == 3 && aopcde == 9 && s == 0)
3460 
    {
3461 
      OUTS (outf, "A1.X = ");
3462 
      OUTS (outf, dregs_lo (src0));
3463 
    }
3464 
  else if (aop == 1 && HL == 1 && aopcde == 16)
3465 
    OUTS (outf, "A1 = ABS A1");
3466 
 
3467 
  else if (aop == 0 && HL == 1 && aopcde == 16)
3468 
    OUTS (outf, "A1 = ABS A0");
3469 
 
3470 
  else if (aop == 2 && aopcde == 9 && s == 1)
3471 
    {
3472 
      OUTS (outf, "A1 = ");
3473 
      OUTS (outf, dregs (src0));
3474 
    }
3475 
  else if (HL == 0 && aop == 3 && aopcde == 12)
3476 
    {
3477 
      OUTS (outf, dregs_lo (dst0));
3478 
      OUTS (outf, " = ");
3479 
      OUTS (outf, dregs (src0));
3480 
      OUTS (outf, " (RND)");
3481 
    }
3482 
  else if (aop == 1 && HL == 0 && aopcde == 16)
3483 
    OUTS (outf, "A0 = ABS A1");
3484 
 
3485 
  else if (aop == 0 && HL == 0 && aopcde == 16)
3486 
    OUTS (outf, "A0 = ABS A0");
3487 
 
3488 
  else if (aop == 3 && HL == 0 && aopcde == 15)
3489 
    {
3490 
      OUTS (outf, dregs (dst0));
3491 
      OUTS (outf, " = -");
3492 
      OUTS (outf, dregs (src0));
3493 
      OUTS (outf, " (V)");
3494 
    }
3495 
  else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3496 
    {
3497 
      OUTS (outf, dregs (dst0));
3498 
      OUTS (outf, " = -");
3499 
      OUTS (outf, dregs (src0));
3500 
      OUTS (outf, " (S)");
3501 
    }
3502 
  else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3503 
    {
3504 
      OUTS (outf, dregs (dst0));
3505 
      OUTS (outf, " = -");
3506 
      OUTS (outf, dregs (src0));
3507 
      OUTS (outf, " (NS)");
3508 
    }
3509 
  else if (aop == 1 && HL == 1 && aopcde == 11)
3510 
    {
3511 
      OUTS (outf, dregs_hi (dst0));
3512 
      OUTS (outf, " = (A0 += A1)");
3513 
    }
3514 
  else if (aop == 2 && aopcde == 11 && s == 0)
3515 
    OUTS (outf, "A0 += A1");
3516 
 
3517 
  else if (aop == 2 && aopcde == 11 && s == 1)
3518 
    OUTS (outf, "A0 += A1 (W32)");
3519 
 
3520 
  else if (aop == 3 && HL == 0 && aopcde == 14)
3521 
    OUTS (outf, "A1 = -A1, A0 = -A0");
3522 
 
3523 
  else if (HL == 1 && aop == 3 && aopcde == 12)
3524 
    {
3525 
      OUTS (outf, dregs_hi (dst0));
3526 
      OUTS (outf, " = ");
3527 
      OUTS (outf, dregs (src0));
3528 
      OUTS (outf, " (RND)");
3529 
    }
3530 
  else if (aop == 0 && aopcde == 23 && HL == 0)
3531 
    {
3532 
      OUTS (outf, dregs (dst0));
3533 
      OUTS (outf, " = BYTEOP3P (");
3534 
      OUTS (outf, dregs (src0 + 1));
3535 
      OUTS (outf, ":");
3536 
      OUTS (outf, imm5d (src0));
3537 
      OUTS (outf, ", ");
3538 
      OUTS (outf, dregs (src1 + 1));
3539 
      OUTS (outf, ":");
3540 
      OUTS (outf, imm5d (src1));
3541 
      OUTS (outf, ") (LO");
3542 
      if (s == 1)
3543 
        OUTS (outf, ", R)");
3544 
      else
3545 
        OUTS (outf, ")");
3546 
    }
3547 
  else if (aop == 0 && HL == 0 && aopcde == 14)
3548 
    OUTS (outf, "A0 = -A0");
3549 
 
3550 
  else if (aop == 1 && HL == 0 && aopcde == 14)
3551 
    OUTS (outf, "A0 = -A1");
3552 
 
3553 
  else if (aop == 0 && HL == 1 && aopcde == 14)
3554 
    OUTS (outf, "A1 = -A0");
3555 
 
3556 
  else if (aop == 1 && HL == 1 && aopcde == 14)
3557 
    OUTS (outf, "A1 = -A1");
3558 
 
3559 
  else if (aop == 0 && aopcde == 12)
3560 
    {
3561 
      OUTS (outf, dregs_hi (dst0));
3562 
      OUTS (outf, " = ");
3563 
      OUTS (outf, dregs_lo (dst0));
3564 
      OUTS (outf, " = SIGN (");
3565 
      OUTS (outf, dregs_hi (src0));
3566 
      OUTS (outf, ") * ");
3567 
      OUTS (outf, dregs_hi (src1));
3568 
      OUTS (outf, " + SIGN (");
3569 
      OUTS (outf, dregs_lo (src0));
3570 
      OUTS (outf, ") * ");
3571 
      OUTS (outf, dregs_lo (src1));
3572 
    }
3573 
  else if (aop == 2 && aopcde == 0)
3574 
    {
3575 
      OUTS (outf, dregs (dst0));
3576 
      OUTS (outf, " = ");
3577 
      OUTS (outf, dregs (src0));
3578 
      OUTS (outf, " -|+ ");
3579 
      OUTS (outf, dregs (src1));
3580 
      amod0 (s, x, outf);
3581 
    }
3582 
  else if (aop == 1 && aopcde == 12)
3583 
    {
3584 
      OUTS (outf, dregs (dst1));
3585 
      OUTS (outf, " = A1.L + A1.H, ");
3586 
      OUTS (outf, dregs (dst0));
3587 
      OUTS (outf, " = A0.L + A0.H");
3588 
    }
3589 
  else if (aop == 2 && aopcde == 4)
3590 
    {
3591 
      OUTS (outf, dregs (dst1));
3592 
      OUTS (outf, " = ");
3593 
      OUTS (outf, dregs (src0));
3594 
      OUTS (outf, " + ");
3595 
      OUTS (outf, dregs (src1));
3596 
      OUTS (outf, ", ");
3597 
      OUTS (outf, dregs (dst0));
3598 
      OUTS (outf, " = ");
3599 
      OUTS (outf, dregs (src0));
3600 
      OUTS (outf, " - ");
3601 
      OUTS (outf, dregs (src1));
3602 
      amod1 (s, x, outf);
3603 
    }
3604 
  else if (HL == 0 && aopcde == 1)
3605 
    {
3606 
      OUTS (outf, dregs (dst1));
3607 
      OUTS (outf, " = ");
3608 
      OUTS (outf, dregs (src0));
3609 
      OUTS (outf, " +|+ ");
3610 
      OUTS (outf, dregs (src1));
3611 
      OUTS (outf, ", ");
3612 
      OUTS (outf, dregs (dst0));
3613 
      OUTS (outf, " = ");
3614 
      OUTS (outf, dregs (src0));
3615 
      OUTS (outf, " -|- ");
3616 
      OUTS (outf, dregs (src1));
3617 
      amod0amod2 (s, x, aop, outf);
3618 
    }
3619 
  else if (aop == 0 && aopcde == 11)
3620 
    {
3621 
      OUTS (outf, dregs (dst0));
3622 
      OUTS (outf, " = (A0 += A1)");
3623 
    }
3624 
  else if (aop == 0 && aopcde == 10)
3625 
    {
3626 
      OUTS (outf, dregs_lo (dst0));
3627 
      OUTS (outf, " = A0.X");
3628 
    }
3629 
  else if (aop == 1 && aopcde == 10)
3630 
    {
3631 
      OUTS (outf, dregs_lo (dst0));
3632 
      OUTS (outf, " = A1.X");
3633 
    }
3634 
  else if (aop == 1 && aopcde == 0)
3635 
    {
3636 
      OUTS (outf, dregs (dst0));
3637 
      OUTS (outf, " = ");
3638 
      OUTS (outf, dregs (src0));
3639 
      OUTS (outf, " +|- ");
3640 
      OUTS (outf, dregs (src1));
3641 
      amod0 (s, x, outf);
3642 
    }
3643 
  else if (aop == 3 && aopcde == 0)
3644 
    {
3645 
      OUTS (outf, dregs (dst0));
3646 
      OUTS (outf, " = ");
3647 
      OUTS (outf, dregs (src0));
3648 
      OUTS (outf, " -|- ");
3649 
      OUTS (outf, dregs (src1));
3650 
      amod0 (s, x, outf);
3651 
    }
3652 
  else if (aop == 1 && aopcde == 4)
3653 
    {
3654 
      OUTS (outf, dregs (dst0));
3655 
      OUTS (outf, " = ");
3656 
      OUTS (outf, dregs (src0));
3657 
      OUTS (outf, " - ");
3658 
      OUTS (outf, dregs (src1));
3659 
      amod1 (s, x, outf);
3660 
    }
3661 
  else if (aop == 0 && aopcde == 17)
3662 
    {
3663 
      OUTS (outf, dregs (dst1));
3664 
      OUTS (outf, " = A1 + A0, ");
3665 
      OUTS (outf, dregs (dst0));
3666 
      OUTS (outf, " = A1 - A0");
3667 
      amod1 (s, x, outf);
3668 
    }
3669 
  else if (aop == 1 && aopcde == 17)
3670 
    {
3671 
      OUTS (outf, dregs (dst1));
3672 
      OUTS (outf, " = A0 + A1, ");
3673 
      OUTS (outf, dregs (dst0));
3674 
      OUTS (outf, " = A0 - A1");
3675 
      amod1 (s, x, outf);
3676 
    }
3677 
  else if (aop == 0 && aopcde == 18)
3678 
    {
3679 
      OUTS (outf, "SAA (");
3680 
      OUTS (outf, dregs (src0 + 1));
3681 
      OUTS (outf, ":");
3682 
      OUTS (outf, imm5d (src0));
3683 
      OUTS (outf, ", ");
3684 
      OUTS (outf, dregs (src1 + 1));
3685 
      OUTS (outf, ":");
3686 
      OUTS (outf, imm5d (src1));
3687 
      OUTS (outf, ")");
3688 
      aligndir (s, outf);
3689 
    }
3690 
  else if (aop == 3 && aopcde == 18)
3691 
    OUTS (outf, "DISALGNEXCPT");
3692 
 
3693 
  else if (aop == 0 && aopcde == 20)
3694 
    {
3695 
      OUTS (outf, dregs (dst0));
3696 
      OUTS (outf, " = BYTEOP1P (");
3697 
      OUTS (outf, dregs (src0 + 1));
3698 
      OUTS (outf, ":");
3699 
      OUTS (outf, imm5d (src0));
3700 
      OUTS (outf, ", ");
3701 
      OUTS (outf, dregs (src1 + 1));
3702 
      OUTS (outf, ":");
3703 
      OUTS (outf, imm5d (src1));
3704 
      OUTS (outf, ")");
3705 
      aligndir (s, outf);
3706 
    }
3707 
  else if (aop == 1 && aopcde == 20)
3708 
    {
3709 
      OUTS (outf, dregs (dst0));
3710 
      OUTS (outf, " = BYTEOP1P (");
3711 
      OUTS (outf, dregs (src0 + 1));
3712 
      OUTS (outf, ":");
3713 
      OUTS (outf, imm5d (src0));
3714 
      OUTS (outf, ", ");
3715 
      OUTS (outf, dregs (src1 + 1));
3716 
      OUTS (outf, ":");
3717 
      OUTS (outf, imm5d (src1));
3718 
      OUTS (outf, ") (T");
3719 
      if (s == 1)
3720 
        OUTS (outf, ", R)");
3721 
      else
3722 
        OUTS (outf, ")");
3723 
    }
3724 
  else if (aop == 0 && aopcde == 21)
3725 
    {
3726 
      OUTS (outf, "(");
3727 
      OUTS (outf, dregs (dst1));
3728 
      OUTS (outf, ", ");
3729 
      OUTS (outf, dregs (dst0));
3730 
      OUTS (outf, ") = BYTEOP16P (");
3731 
      OUTS (outf, dregs (src0 + 1));
3732 
      OUTS (outf, ":");
3733 
      OUTS (outf, imm5d (src0));
3734 
      OUTS (outf, ", ");
3735 
      OUTS (outf, dregs (src1 + 1));
3736 
      OUTS (outf, ":");
3737 
      OUTS (outf, imm5d (src1));
3738 
      OUTS (outf, ")");
3739 
      aligndir (s, outf);
3740 
    }
3741 
  else if (aop == 1 && aopcde == 21)
3742 
    {
3743 
      OUTS (outf, "(");
3744 
      OUTS (outf, dregs (dst1));
3745 
      OUTS (outf, ", ");
3746 
      OUTS (outf, dregs (dst0));
3747 
      OUTS (outf, ") = BYTEOP16M (");
3748 
      OUTS (outf, dregs (src0 + 1));
3749 
      OUTS (outf, ":");
3750 
      OUTS (outf, imm5d (src0));
3751 
      OUTS (outf, ", ");
3752 
      OUTS (outf, dregs (src1 + 1));
3753 
      OUTS (outf, ":");
3754 
      OUTS (outf, imm5d (src1));
3755 
      OUTS (outf, ")");
3756 
      aligndir (s, outf);
3757 
    }
3758 
  else if (aop == 2 && aopcde == 7)
3759 
    {
3760 
      OUTS (outf, dregs (dst0));
3761 
      OUTS (outf, " = ABS ");
3762 
      OUTS (outf, dregs (src0));
3763 
    }
3764 
  else if (aop == 1 && aopcde == 7)
3765 
    {
3766 
      OUTS (outf, dregs (dst0));
3767 
      OUTS (outf, " = MIN (");
3768 
      OUTS (outf, dregs (src0));
3769 
      OUTS (outf, ", ");
3770 
      OUTS (outf, dregs (src1));
3771 
      OUTS (outf, ")");
3772 
    }
3773 
  else if (aop == 0 && aopcde == 7)
3774 
    {
3775 
      OUTS (outf, dregs (dst0));
3776 
      OUTS (outf, " = MAX (");
3777 
      OUTS (outf, dregs (src0));
3778 
      OUTS (outf, ", ");
3779 
      OUTS (outf, dregs (src1));
3780 
      OUTS (outf, ")");
3781 
    }
3782 
  else if (aop == 2 && aopcde == 6)
3783 
    {
3784 
      OUTS (outf, dregs (dst0));
3785 
      OUTS (outf, " = ABS ");
3786 
      OUTS (outf, dregs (src0));
3787 
      OUTS (outf, " (V)");
3788 
    }
3789 
  else if (aop == 1 && aopcde == 6)
3790 
    {
3791 
      OUTS (outf, dregs (dst0));
3792 
      OUTS (outf, " = MIN (");
3793 
      OUTS (outf, dregs (src0));
3794 
      OUTS (outf, ", ");
3795 
      OUTS (outf, dregs (src1));
3796 
      OUTS (outf, ") (V)");
3797 
    }
3798 
  else if (aop == 0 && aopcde == 6)
3799 
    {
3800 
      OUTS (outf, dregs (dst0));
3801 
      OUTS (outf, " = MAX (");
3802 
      OUTS (outf, dregs (src0));
3803 
      OUTS (outf, ", ");
3804 
      OUTS (outf, dregs (src1));
3805 
      OUTS (outf, ") (V)");
3806 
    }
3807 
  else if (HL == 1 && aopcde == 1)
3808 
    {
3809 
      OUTS (outf, dregs (dst1));
3810 
      OUTS (outf, " = ");
3811 
      OUTS (outf, dregs (src0));
3812 
      OUTS (outf, " +|- ");
3813 
      OUTS (outf, dregs (src1));
3814 
      OUTS (outf, ", ");
3815 
      OUTS (outf, dregs (dst0));
3816 
      OUTS (outf, " = ");
3817 
      OUTS (outf, dregs (src0));
3818 
      OUTS (outf, " -|+ ");
3819 
      OUTS (outf, dregs (src1));
3820 
      amod0amod2 (s, x, aop, outf);
3821 
    }
3822 
  else if (aop == 0 && aopcde == 4)
3823 
    {
3824 
      OUTS (outf, dregs (dst0));
3825 
      OUTS (outf, " = ");
3826 
      OUTS (outf, dregs (src0));
3827 
      OUTS (outf, " + ");
3828 
      OUTS (outf, dregs (src1));
3829 
      amod1 (s, x, outf);
3830 
    }
3831 
  else if (aop == 0 && aopcde == 0)
3832 
    {
3833 
      OUTS (outf, dregs (dst0));
3834 
      OUTS (outf, " = ");
3835 
      OUTS (outf, dregs (src0));
3836 
      OUTS (outf, " +|+ ");
3837 
      OUTS (outf, dregs (src1));
3838 
      amod0 (s, x, outf);
3839 
    }
3840 
  else if (aop == 0 && aopcde == 24)
3841 
    {
3842 
      OUTS (outf, dregs (dst0));
3843 
      OUTS (outf, " = BYTEPACK (");
3844 
      OUTS (outf, dregs (src0));
3845 
      OUTS (outf, ", ");
3846 
      OUTS (outf, dregs (src1));
3847 
      OUTS (outf, ")");
3848 
    }
3849 
  else if (aop == 1 && aopcde == 24)
3850 
    {
3851 
      OUTS (outf, "(");
3852 
      OUTS (outf, dregs (dst1));
3853 
      OUTS (outf, ", ");
3854 
      OUTS (outf, dregs (dst0));
3855 
      OUTS (outf, ") = BYTEUNPACK ");
3856 
      OUTS (outf, dregs (src0 + 1));
3857 
      OUTS (outf, ":");
3858 
      OUTS (outf, imm5d (src0));
3859 
      aligndir (s, outf);
3860 
    }
3861 
  else if (aopcde == 13)
3862 
    {
3863 
      OUTS (outf, "(");
3864 
      OUTS (outf, dregs (dst1));
3865 
      OUTS (outf, ", ");
3866 
      OUTS (outf, dregs (dst0));
3867 
      OUTS (outf, ") = SEARCH ");
3868 
      OUTS (outf, dregs (src0));
3869 
      OUTS (outf, " (");
3870 
      searchmod (aop, outf);
3871 
      OUTS (outf, ")");
3872 
    }
3873 
  else
3874 
    return 0;
3875 
 
3876 
  return 4;
3877 
}
3878 
 
3879 
static int
3880 
decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3881 
{
3882 
  /* dsp32shift
3883 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3884 
     | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3885 
     |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3886 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
3887 
  int HLs  = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3888 
  int sop  = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3889 
  int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3890 
  int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3891 
  int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3892 
  int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3893 
  const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3894 
 
3895 
  if (HLs == 0 && sop == 0 && sopcde == 0)
3896 
    {
3897 
      OUTS (outf, dregs_lo (dst0));
3898 
      OUTS (outf, " = ASHIFT ");
3899 
      OUTS (outf, dregs_lo (src1));
3900 
      OUTS (outf, " BY ");
3901 
      OUTS (outf, dregs_lo (src0));
3902 
    }
3903 
  else if (HLs == 1 && sop == 0 && sopcde == 0)
3904 
    {
3905 
      OUTS (outf, dregs_lo (dst0));
3906 
      OUTS (outf, " = ASHIFT ");
3907 
      OUTS (outf, dregs_hi (src1));
3908 
      OUTS (outf, " BY ");
3909 
      OUTS (outf, dregs_lo (src0));
3910 
    }
3911 
  else if (HLs == 2 && sop == 0 && sopcde == 0)
3912 
    {
3913 
      OUTS (outf, dregs_hi (dst0));
3914 
      OUTS (outf, " = ASHIFT ");
3915 
      OUTS (outf, dregs_lo (src1));
3916 
      OUTS (outf, " BY ");
3917 
      OUTS (outf, dregs_lo (src0));
3918 
    }
3919 
  else if (HLs == 3 && sop == 0 && sopcde == 0)
3920 
    {
3921 
      OUTS (outf, dregs_hi (dst0));
3922 
      OUTS (outf, " = ASHIFT ");
3923 
      OUTS (outf, dregs_hi (src1));
3924 
      OUTS (outf, " BY ");
3925 
      OUTS (outf, dregs_lo (src0));
3926 
    }
3927 
  else if (HLs == 0 && sop == 1 && sopcde == 0)
3928 
    {
3929 
      OUTS (outf, dregs_lo (dst0));
3930 
      OUTS (outf, " = ASHIFT ");
3931 
      OUTS (outf, dregs_lo (src1));
3932 
      OUTS (outf, " BY ");
3933 
      OUTS (outf, dregs_lo (src0));
3934 
      OUTS (outf, " (S)");
3935 
    }
3936 
  else if (HLs == 1 && sop == 1 && sopcde == 0)
3937 
    {
3938 
      OUTS (outf, dregs_lo (dst0));
3939 
      OUTS (outf, " = ASHIFT ");
3940 
      OUTS (outf, dregs_hi (src1));
3941 
      OUTS (outf, " BY ");
3942 
      OUTS (outf, dregs_lo (src0));
3943 
      OUTS (outf, " (S)");
3944 
    }
3945 
  else if (HLs == 2 && sop == 1 && sopcde == 0)
3946 
    {
3947 
      OUTS (outf, dregs_hi (dst0));
3948 
      OUTS (outf, " = ASHIFT ");
3949 
      OUTS (outf, dregs_lo (src1));
3950 
      OUTS (outf, " BY ");
3951 
      OUTS (outf, dregs_lo (src0));
3952 
      OUTS (outf, " (S)");
3953 
    }
3954 
  else if (HLs == 3 && sop == 1 && sopcde == 0)
3955 
    {
3956 
      OUTS (outf, dregs_hi (dst0));
3957 
      OUTS (outf, " = ASHIFT ");
3958 
      OUTS (outf, dregs_hi (src1));
3959 
      OUTS (outf, " BY ");
3960 
      OUTS (outf, dregs_lo (src0));
3961 
      OUTS (outf, " (S)");
3962 
    }
3963 
  else if (sop == 2 && sopcde == 0)
3964 
    {
3965 
      OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
3966 
      OUTS (outf, " = LSHIFT ");
3967 
      OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
3968 
      OUTS (outf, " BY ");
3969 
      OUTS (outf, dregs_lo (src0));
3970 
    }
3971 
  else if (sop == 0 && sopcde == 3)
3972 
    {
3973 
      OUTS (outf, acc01);
3974 
      OUTS (outf, " = ASHIFT ");
3975 
      OUTS (outf, acc01);
3976 
      OUTS (outf, " BY ");
3977 
      OUTS (outf, dregs_lo (src0));
3978 
    }
3979 
  else if (sop == 1 && sopcde == 3)
3980 
    {
3981 
      OUTS (outf, acc01);
3982 
      OUTS (outf, " = LSHIFT ");
3983 
      OUTS (outf, acc01);
3984 
      OUTS (outf, " BY ");
3985 
      OUTS (outf, dregs_lo (src0));
3986 
    }
3987 
  else if (sop == 2 && sopcde == 3)
3988 
    {
3989 
      OUTS (outf, acc01);
3990 
      OUTS (outf, " = ROT ");
3991 
      OUTS (outf, acc01);
3992 
      OUTS (outf, " BY ");
3993 
      OUTS (outf, dregs_lo (src0));
3994 
    }
3995 
  else if (sop == 3 && sopcde == 3)
3996 
    {
3997 
      OUTS (outf, dregs (dst0));
3998 
      OUTS (outf, " = ROT ");
3999 
      OUTS (outf, dregs (src1));
4000 
      OUTS (outf, " BY ");
4001 
      OUTS (outf, dregs_lo (src0));
4002 
    }
4003 
  else if (sop == 1 && sopcde == 1)
4004 
    {
4005 
      OUTS (outf, dregs (dst0));
4006 
      OUTS (outf, " = ASHIFT ");
4007 
      OUTS (outf, dregs (src1));
4008 
      OUTS (outf, " BY ");
4009 
      OUTS (outf, dregs_lo (src0));
4010 
      OUTS (outf, " (V, S)");
4011 
    }
4012 
  else if (sop == 0 && sopcde == 1)
4013 
    {
4014 
      OUTS (outf, dregs (dst0));
4015 
      OUTS (outf, " = ASHIFT ");
4016 
      OUTS (outf, dregs (src1));
4017 
      OUTS (outf, " BY ");
4018 
      OUTS (outf, dregs_lo (src0));
4019 
      OUTS (outf, " (V)");
4020 
    }
4021 
  else if (sop == 0 && sopcde == 2)
4022 
    {
4023 
      OUTS (outf, dregs (dst0));
4024 
      OUTS (outf, " = ASHIFT ");
4025 
      OUTS (outf, dregs (src1));
4026 
      OUTS (outf, " BY ");
4027 
      OUTS (outf, dregs_lo (src0));
4028 
    }
4029 
  else if (sop == 1 && sopcde == 2)
4030 
    {
4031 
      OUTS (outf, dregs (dst0));
4032 
      OUTS (outf, " = ASHIFT ");
4033 
      OUTS (outf, dregs (src1));
4034 
      OUTS (outf, " BY ");
4035 
      OUTS (outf, dregs_lo (src0));
4036 
      OUTS (outf, " (S)");
4037 
    }
4038 
  else if (sop == 2 && sopcde == 2)
4039 
    {
4040 
      OUTS (outf, dregs (dst0));
4041 
      OUTS (outf, " = SHIFT ");
4042 
      OUTS (outf, dregs (src1));
4043 
      OUTS (outf, " BY ");
4044 
      OUTS (outf, dregs_lo (src0));
4045 
    }
4046 
  else if (sop == 3 && sopcde == 2)
4047 
    {
4048 
      OUTS (outf, dregs (dst0));
4049 
      OUTS (outf, " = ROT ");
4050 
      OUTS (outf, dregs (src1));
4051 
      OUTS (outf, " BY ");
4052 
      OUTS (outf, dregs_lo (src0));
4053 
    }
4054 
  else if (sop == 2 && sopcde == 1)
4055 
    {
4056 
      OUTS (outf, dregs (dst0));
4057 
      OUTS (outf, " = SHIFT ");
4058 
      OUTS (outf, dregs (src1));
4059 
      OUTS (outf, " BY ");
4060 
      OUTS (outf, dregs_lo (src0));
4061 
      OUTS (outf, " (V)");
4062 
    }
4063 
  else if (sop == 0 && sopcde == 4)
4064 
    {
4065 
      OUTS (outf, dregs (dst0));
4066 
      OUTS (outf, " = PACK (");
4067 
      OUTS (outf, dregs_lo (src1));
4068 
      OUTS (outf, ", ");
4069 
      OUTS (outf, dregs_lo (src0));
4070 
      OUTS (outf, ")");
4071 
    }
4072 
  else if (sop == 1 && sopcde == 4)
4073 
    {
4074 
      OUTS (outf, dregs (dst0));
4075 
      OUTS (outf, " = PACK (");
4076 
      OUTS (outf, dregs_lo (src1));
4077 
      OUTS (outf, ", ");
4078 
      OUTS (outf, dregs_hi (src0));
4079 
      OUTS (outf, ")");
4080 
    }
4081 
  else if (sop == 2 && sopcde == 4)
4082 
    {
4083 
      OUTS (outf, dregs (dst0));
4084 
      OUTS (outf, " = PACK (");
4085 
      OUTS (outf, dregs_hi (src1));
4086 
      OUTS (outf, ", ");
4087 
      OUTS (outf, dregs_lo (src0));
4088 
      OUTS (outf, ")");
4089 
    }
4090 
  else if (sop == 3 && sopcde == 4)
4091 
    {
4092 
      OUTS (outf, dregs (dst0));
4093 
      OUTS (outf, " = PACK (");
4094 
      OUTS (outf, dregs_hi (src1));
4095 
      OUTS (outf, ", ");
4096 
      OUTS (outf, dregs_hi (src0));
4097 
      OUTS (outf, ")");
4098 
    }
4099 
  else if (sop == 0 && sopcde == 5)
4100 
    {
4101 
      OUTS (outf, dregs_lo (dst0));
4102 
      OUTS (outf, " = SIGNBITS ");
4103 
      OUTS (outf, dregs (src1));
4104 
    }
4105 
  else if (sop == 1 && sopcde == 5)
4106 
    {
4107 
      OUTS (outf, dregs_lo (dst0));
4108 
      OUTS (outf, " = SIGNBITS ");
4109 
      OUTS (outf, dregs_lo (src1));
4110 
    }
4111 
  else if (sop == 2 && sopcde == 5)
4112 
    {
4113 
      OUTS (outf, dregs_lo (dst0));
4114 
      OUTS (outf, " = SIGNBITS ");
4115 
      OUTS (outf, dregs_hi (src1));
4116 
    }
4117 
  else if (sop == 0 && sopcde == 6)
4118 
    {
4119 
      OUTS (outf, dregs_lo (dst0));
4120 
      OUTS (outf, " = SIGNBITS A0");
4121 
    }
4122 
  else if (sop == 1 && sopcde == 6)
4123 
    {
4124 
      OUTS (outf, dregs_lo (dst0));
4125 
      OUTS (outf, " = SIGNBITS A1");
4126 
    }
4127 
  else if (sop == 3 && sopcde == 6)
4128 
    {
4129 
      OUTS (outf, dregs_lo (dst0));
4130 
      OUTS (outf, " = ONES ");
4131 
      OUTS (outf, dregs (src1));
4132 
    }
4133 
  else if (sop == 0 && sopcde == 7)
4134 
    {
4135 
      OUTS (outf, dregs_lo (dst0));
4136 
      OUTS (outf, " = EXPADJ (");
4137 
      OUTS (outf, dregs (src1));
4138 
      OUTS (outf, ", ");
4139 
      OUTS (outf, dregs_lo (src0));
4140 
      OUTS (outf, ")");
4141 
    }
4142 
  else if (sop == 1 && sopcde == 7)
4143 
    {
4144 
      OUTS (outf, dregs_lo (dst0));
4145 
      OUTS (outf, " = EXPADJ (");
4146 
      OUTS (outf, dregs (src1));
4147 
      OUTS (outf, ", ");
4148 
      OUTS (outf, dregs_lo (src0));
4149 
      OUTS (outf, ") (V)");
4150 
    }
4151 
  else if (sop == 2 && sopcde == 7)
4152 
    {
4153 
      OUTS (outf, dregs_lo (dst0));
4154 
      OUTS (outf, " = EXPADJ (");
4155 
      OUTS (outf, dregs_lo (src1));
4156 
      OUTS (outf, ", ");
4157 
      OUTS (outf, dregs_lo (src0));
4158 
      OUTS (outf, ")");
4159 
    }
4160 
  else if (sop == 3 && sopcde == 7)
4161 
    {
4162 
      OUTS (outf, dregs_lo (dst0));
4163 
      OUTS (outf, " = EXPADJ (");
4164 
      OUTS (outf, dregs_hi (src1));
4165 
      OUTS (outf, ", ");
4166 
      OUTS (outf, dregs_lo (src0));
4167 
      OUTS (outf, ")");
4168 
    }
4169 
  else if (sop == 0 && sopcde == 8)
4170 
    {
4171 
      OUTS (outf, "BITMUX (");
4172 
      OUTS (outf, dregs (src0));
4173 
      OUTS (outf, ", ");
4174 
      OUTS (outf, dregs (src1));
4175 
      OUTS (outf, ", A0) (ASR)");
4176 
    }
4177 
  else if (sop == 1 && sopcde == 8)
4178 
    {
4179 
      OUTS (outf, "BITMUX (");
4180 
      OUTS (outf, dregs (src0));
4181 
      OUTS (outf, ", ");
4182 
      OUTS (outf, dregs (src1));
4183 
      OUTS (outf, ", A0) (ASL)");
4184 
    }
4185 
  else if (sop == 0 && sopcde == 9)
4186 
    {
4187 
      OUTS (outf, dregs_lo (dst0));
4188 
      OUTS (outf, " = VIT_MAX (");
4189 
      OUTS (outf, dregs (src1));
4190 
      OUTS (outf, ") (ASL)");
4191 
    }
4192 
  else if (sop == 1 && sopcde == 9)
4193 
    {
4194 
      OUTS (outf, dregs_lo (dst0));
4195 
      OUTS (outf, " = VIT_MAX (");
4196 
      OUTS (outf, dregs (src1));
4197 
      OUTS (outf, ") (ASR)");
4198 
    }
4199 
  else if (sop == 2 && sopcde == 9)
4200 
    {
4201 
      OUTS (outf, dregs (dst0));
4202 
      OUTS (outf, " = VIT_MAX (");
4203 
      OUTS (outf, dregs (src1));
4204 
      OUTS (outf, ", ");
4205 
      OUTS (outf, dregs (src0));
4206 
      OUTS (outf, ") (ASL)");
4207 
    }
4208 
  else if (sop == 3 && sopcde == 9)
4209 
    {
4210 
      OUTS (outf, dregs (dst0));
4211 
      OUTS (outf, " = VIT_MAX (");
4212 
      OUTS (outf, dregs (src1));
4213 
      OUTS (outf, ", ");
4214 
      OUTS (outf, dregs (src0));
4215 
      OUTS (outf, ") (ASR)");
4216 
    }
4217 
  else if (sop == 0 && sopcde == 10)
4218 
    {
4219 
      OUTS (outf, dregs (dst0));
4220 
      OUTS (outf, " = EXTRACT (");
4221 
      OUTS (outf, dregs (src1));
4222 
      OUTS (outf, ", ");
4223 
      OUTS (outf, dregs_lo (src0));
4224 
      OUTS (outf, ") (Z)");
4225 
    }
4226 
  else if (sop == 1 && sopcde == 10)
4227 
    {
4228 
      OUTS (outf, dregs (dst0));
4229 
      OUTS (outf, " = EXTRACT (");
4230 
      OUTS (outf, dregs (src1));
4231 
      OUTS (outf, ", ");
4232 
      OUTS (outf, dregs_lo (src0));
4233 
      OUTS (outf, ") (X)");
4234 
    }
4235 
  else if (sop == 2 && sopcde == 10)
4236 
    {
4237 
      OUTS (outf, dregs (dst0));
4238 
      OUTS (outf, " = DEPOSIT (");
4239 
      OUTS (outf, dregs (src1));
4240 
      OUTS (outf, ", ");
4241 
      OUTS (outf, dregs (src0));
4242 
      OUTS (outf, ")");
4243 
    }
4244 
  else if (sop == 3 && sopcde == 10)
4245 
    {
4246 
      OUTS (outf, dregs (dst0));
4247 
      OUTS (outf, " = DEPOSIT (");
4248 
      OUTS (outf, dregs (src1));
4249 
      OUTS (outf, ", ");
4250 
      OUTS (outf, dregs (src0));
4251 
      OUTS (outf, ") (X)");
4252 
    }
4253 
  else if (sop == 0 && sopcde == 11)
4254 
    {
4255 
      OUTS (outf, dregs_lo (dst0));
4256 
      OUTS (outf, " = CC = BXORSHIFT (A0, ");
4257 
      OUTS (outf, dregs (src0));
4258 
      OUTS (outf, ")");
4259 
    }
4260 
  else if (sop == 1 && sopcde == 11)
4261 
    {
4262 
      OUTS (outf, dregs_lo (dst0));
4263 
      OUTS (outf, " = CC = BXOR (A0, ");
4264 
      OUTS (outf, dregs (src0));
4265 
      OUTS (outf, ")");
4266 
    }
4267 
  else if (sop == 0 && sopcde == 12)
4268 
    OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
4269 
 
4270 
  else if (sop == 1 && sopcde == 12)
4271 
    {
4272 
      OUTS (outf, dregs_lo (dst0));
4273 
      OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4274 
    }
4275 
  else if (sop == 0 && sopcde == 13)
4276 
    {
4277 
      OUTS (outf, dregs (dst0));
4278 
      OUTS (outf, " = ALIGN8 (");
4279 
      OUTS (outf, dregs (src1));
4280 
      OUTS (outf, ", ");
4281 
      OUTS (outf, dregs (src0));
4282 
      OUTS (outf, ")");
4283 
    }
4284 
  else if (sop == 1 && sopcde == 13)
4285 
    {
4286 
      OUTS (outf, dregs (dst0));
4287 
      OUTS (outf, " = ALIGN16 (");
4288 
      OUTS (outf, dregs (src1));
4289 
      OUTS (outf, ", ");
4290 
      OUTS (outf, dregs (src0));
4291 
      OUTS (outf, ")");
4292 
    }
4293 
  else if (sop == 2 && sopcde == 13)
4294 
    {
4295 
      OUTS (outf, dregs (dst0));
4296 
      OUTS (outf, " = ALIGN24 (");
4297 
      OUTS (outf, dregs (src1));
4298 
      OUTS (outf, ", ");
4299 
      OUTS (outf, dregs (src0));
4300 
      OUTS (outf, ")");
4301 
    }
4302 
  else
4303 
    return 0;
4304 
 
4305 
  return 4;
4306 
}
4307 
 
4308 
static int
4309 
decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4310 
{
4311 
  /* dsp32shiftimm
4312 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4313 
     | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4314 
     |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4315 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
4316 
  int src1     = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4317 
  int sop      = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4318 
  int bit8     = ((iw1 >> 8) & 0x1);
4319 
  int immag    = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4320 
  int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4321 
  int dst0     = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4322 
  int sopcde   = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4323 
  int HLs      = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4324 
 
4325 
 
4326 
  if (sop == 0 && sopcde == 0)
4327 
    {
4328 
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4329 
      OUTS (outf, " = ");
4330 
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4331 
      OUTS (outf, " >>> ");
4332 
      OUTS (outf, uimm4 (newimmag));
4333 
    }
4334 
  else if (sop == 1 && sopcde == 0 && bit8 == 0)
4335 
    {
4336 
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4337 
      OUTS (outf, " = ");
4338 
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4339 
      OUTS (outf, " << ");
4340 
      OUTS (outf, uimm4 (immag));
4341 
      OUTS (outf, " (S)");
4342 
    }
4343 
  else if (sop == 1 && sopcde == 0 && bit8 == 1)
4344 
    {
4345 
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4346 
      OUTS (outf, " = ");
4347 
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4348 
      OUTS (outf, " >>> ");
4349 
      OUTS (outf, uimm4 (newimmag));
4350 
      OUTS (outf, " (S)");
4351 
    }
4352 
  else if (sop == 2 && sopcde == 0 && bit8 == 0)
4353 
    {
4354 
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4355 
      OUTS (outf, " = ");
4356 
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4357 
      OUTS (outf, " << ");
4358 
      OUTS (outf, uimm4 (immag));
4359 
    }
4360 
  else if (sop == 2 && sopcde == 0 && bit8 == 1)
4361 
    {
4362 
      OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4363 
      OUTS (outf, " = ");
4364 
      OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4365 
      OUTS (outf, " >> ");
4366 
      OUTS (outf, uimm4 (newimmag));
4367 
    }
4368 
  else if (sop == 2 && sopcde == 3 && HLs == 1)
4369 
    {
4370 
      OUTS (outf, "A1 = ROT A1 BY ");
4371 
      OUTS (outf, imm6 (immag));
4372 
    }
4373 
  else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4374 
    {
4375 
      OUTS (outf, "A0 = A0 << ");
4376 
      OUTS (outf, uimm5 (immag));
4377 
    }
4378 
  else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4379 
    {
4380 
      OUTS (outf, "A0 = A0 >>> ");
4381 
      OUTS (outf, uimm5 (newimmag));
4382 
    }
4383 
  else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4384 
    {
4385 
      OUTS (outf, "A1 = A1 << ");
4386 
      OUTS (outf, uimm5 (immag));
4387 
    }
4388 
  else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4389 
    {
4390 
      OUTS (outf, "A1 = A1 >>> ");
4391 
      OUTS (outf, uimm5 (newimmag));
4392 
    }
4393 
  else if (sop == 1 && sopcde == 3 && HLs == 0)
4394 
    {
4395 
      OUTS (outf, "A0 = A0 >> ");
4396 
      OUTS (outf, uimm5 (newimmag));
4397 
    }
4398 
  else if (sop == 1 && sopcde == 3 && HLs == 1)
4399 
    {
4400 
      OUTS (outf, "A1 = A1 >> ");
4401 
      OUTS (outf, uimm5 (newimmag));
4402 
    }
4403 
  else if (sop == 2 && sopcde == 3 && HLs == 0)
4404 
    {
4405 
      OUTS (outf, "A0 = ROT A0 BY ");
4406 
      OUTS (outf, imm6 (immag));
4407 
    }
4408 
  else if (sop == 1 && sopcde == 1 && bit8 == 0)
4409 
    {
4410 
      OUTS (outf, dregs (dst0));
4411 
      OUTS (outf, " = ");
4412 
      OUTS (outf, dregs (src1));
4413 
      OUTS (outf, " << ");
4414 
      OUTS (outf, uimm5 (immag));
4415 
      OUTS (outf, " (V, S)");
4416 
    }
4417 
  else if (sop == 1 && sopcde == 1 && bit8 == 1)
4418 
    {
4419 
      OUTS (outf, dregs (dst0));
4420 
      OUTS (outf, " = ");
4421 
      OUTS (outf, dregs (src1));
4422 
      OUTS (outf, " >>> ");
4423 
      OUTS (outf, imm5 (-immag));
4424 
      OUTS (outf, " (V)");
4425 
    }
4426 
  else if (sop == 2 && sopcde == 1 && bit8 == 1)
4427 
    {
4428 
      OUTS (outf, dregs (dst0));
4429 
      OUTS (outf, " = ");
4430 
      OUTS (outf, dregs (src1));
4431 
      OUTS (outf, " >> ");
4432 
      OUTS (outf, uimm5 (newimmag));
4433 
      OUTS (outf, " (V)");
4434 
    }
4435 
  else if (sop == 2 && sopcde == 1 && bit8 == 0)
4436 
    {
4437 
      OUTS (outf, dregs (dst0));
4438 
      OUTS (outf, " = ");
4439 
      OUTS (outf, dregs (src1));
4440 
      OUTS (outf, " << ");
4441 
      OUTS (outf, imm5 (immag));
4442 
      OUTS (outf, " (V)");
4443 
    }
4444 
  else if (sop == 0 && sopcde == 1)
4445 
    {
4446 
      OUTS (outf, dregs (dst0));
4447 
      OUTS (outf, " = ");
4448 
      OUTS (outf, dregs (src1));
4449 
      OUTS (outf, " >>> ");
4450 
      OUTS (outf, uimm5 (newimmag));
4451 
      OUTS (outf, " (V)");
4452 
    }
4453 
  else if (sop == 1 && sopcde == 2)
4454 
    {
4455 
      OUTS (outf, dregs (dst0));
4456 
      OUTS (outf, " = ");
4457 
      OUTS (outf, dregs (src1));
4458 
      OUTS (outf, " << ");
4459 
      OUTS (outf, uimm5 (immag));
4460 
      OUTS (outf, " (S)");
4461 
    }
4462 
  else if (sop == 2 && sopcde == 2 && bit8 == 1)
4463 
    {
4464 
      OUTS (outf, dregs (dst0));
4465 
      OUTS (outf, " = ");
4466 
      OUTS (outf, dregs (src1));
4467 
      OUTS (outf, " >> ");
4468 
      OUTS (outf, uimm5 (newimmag));
4469 
    }
4470 
  else if (sop == 2 && sopcde == 2 && bit8 == 0)
4471 
    {
4472 
      OUTS (outf, dregs (dst0));
4473 
      OUTS (outf, " = ");
4474 
      OUTS (outf, dregs (src1));
4475 
      OUTS (outf, " << ");
4476 
      OUTS (outf, uimm5 (immag));
4477 
    }
4478 
  else if (sop == 3 && sopcde == 2)
4479 
    {
4480 
      OUTS (outf, dregs (dst0));
4481 
      OUTS (outf, " = ROT ");
4482 
      OUTS (outf, dregs (src1));
4483 
      OUTS (outf, " BY ");
4484 
      OUTS (outf, imm6 (immag));
4485 
    }
4486 
  else if (sop == 0 && sopcde == 2)
4487 
    {
4488 
      OUTS (outf, dregs (dst0));
4489 
      OUTS (outf, " = ");
4490 
      OUTS (outf, dregs (src1));
4491 
      OUTS (outf, " >>> ");
4492 
      OUTS (outf, uimm5 (newimmag));
4493 
    }
4494 
  else
4495 
    return 0;
4496 
 
4497 
  return 4;
4498 
}
4499 
 
4500 
static int
4501 
decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4502 
{
4503 
  /* pseudoDEBUG
4504 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4505 
     | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4506 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
4507 
  int fn  = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4508 
  int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4509 
  int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4510 
 
4511 
  if (reg == 0 && fn == 3)
4512 
    OUTS (outf, "DBG A0");
4513 
 
4514 
  else if (reg == 1 && fn == 3)
4515 
    OUTS (outf, "DBG A1");
4516 
 
4517 
  else if (reg == 3 && fn == 3)
4518 
    OUTS (outf, "ABORT");
4519 
 
4520 
  else if (reg == 4 && fn == 3)
4521 
    OUTS (outf, "HLT");
4522 
 
4523 
  else if (reg == 5 && fn == 3)
4524 
    OUTS (outf, "DBGHALT");
4525 
 
4526 
  else if (reg == 6 && fn == 3)
4527 
    {
4528 
      OUTS (outf, "DBGCMPLX (");
4529 
      OUTS (outf, dregs (grp));
4530 
      OUTS (outf, ")");
4531 
    }
4532 
  else if (reg == 7 && fn == 3)
4533 
    OUTS (outf, "DBG");
4534 
 
4535 
  else if (grp == 0 && fn == 2)
4536 
    {
4537 
      OUTS (outf, "OUTC");
4538 
      OUTS (outf, dregs (reg));
4539 
    }
4540 
  else if (fn == 0)
4541 
    {
4542 
      OUTS (outf, "DBG");
4543 
      OUTS (outf, allregs (reg, grp));
4544 
    }
4545 
  else if (fn == 1)
4546 
    {
4547 
      OUTS (outf, "PRNT");
4548 
      OUTS (outf, allregs (reg, grp));
4549 
    }
4550 
  else
4551 
    return 0;
4552 
 
4553 
  return 2;
4554 
}
4555 
 
4556 
static int
4557 
decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4558 
{
4559 
  /* pseudodbg_assert
4560 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4561 
     | 1 | 1 | 1 | 1 | 0 | - | - | - | - | - |.dbgop.....|.regtest...|
4562 
     |.expected......................................................|
4563 
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
4564 
  int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
4565 
  int dbgop    = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
4566 
  int regtest  = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4567 
 
4568 
  if (dbgop == 0)
4569 
    {
4570 
      OUTS (outf, "DBGA (");
4571 
      OUTS (outf, dregs_lo (regtest));
4572 
      OUTS (outf, ", ");
4573 
      OUTS (outf, uimm16 (expected));
4574 
      OUTS (outf, ")");
4575 
    }
4576 
  else if (dbgop == 1)
4577 
    {
4578 
      OUTS (outf, "DBGA (");
4579 
      OUTS (outf, dregs_hi (regtest));
4580 
      OUTS (outf, ", ");
4581 
      OUTS (outf, uimm16 (expected));
4582 
      OUTS (outf, ")");
4583 
    }
4584 
  else if (dbgop == 2)
4585 
    {
4586 
      OUTS (outf, "DBGAL (");
4587 
      OUTS (outf, dregs (regtest));
4588 
      OUTS (outf, ", ");
4589 
      OUTS (outf, uimm16 (expected));
4590 
      OUTS (outf, ")");
4591 
    }
4592 
  else if (dbgop == 3)
4593 
    {
4594 
      OUTS (outf, "DBGAH (");
4595 
      OUTS (outf, dregs (regtest));
4596 
      OUTS (outf, ", ");
4597 
      OUTS (outf, uimm16 (expected));
4598 
      OUTS (outf, ")");
4599 
    }
4600 
  else
4601 
    return 0;
4602 
  return 4;
4603 
}
4604 
 
4605 
int
4606 
_print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4607 
{
4608 
  bfd_byte buf[4];
4609 
  TIword iw0;
4610 
  TIword iw1;
4611 
  int status;
4612 
  int rv = 0;
4613 
 
4614 
  status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf);
4615 
  status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf);
4616 
 
4617 
  iw0 = bfd_getl16 (buf);
4618 
  iw1 = bfd_getl16 (buf + 2);
4619 
 
4620 
  if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4621 
    {
4622 
      OUTS (outf, "MNOP");
4623 
      return 4;
4624 
    }
4625 
  else if ((iw0 & 0xff00) == 0x0000)
4626 
    rv = decode_ProgCtrl_0 (iw0, outf);
4627 
  else if ((iw0 & 0xffc0) == 0x0240)
4628 
    rv = decode_CaCTRL_0 (iw0, outf);
4629 
  else if ((iw0 & 0xff80) == 0x0100)
4630 
    rv = decode_PushPopReg_0 (iw0, outf);
4631 
  else if ((iw0 & 0xfe00) == 0x0400)
4632 
    rv = decode_PushPopMultiple_0 (iw0, outf);
4633 
  else if ((iw0 & 0xfe00) == 0x0600)
4634 
    rv = decode_ccMV_0 (iw0, outf);
4635 
  else if ((iw0 & 0xf800) == 0x0800)
4636 
    rv = decode_CCflag_0 (iw0, outf);
4637 
  else if ((iw0 & 0xffe0) == 0x0200)
4638 
    rv = decode_CC2dreg_0 (iw0, outf);
4639 
  else if ((iw0 & 0xff00) == 0x0300)
4640 
    rv = decode_CC2stat_0 (iw0, outf);
4641 
  else if ((iw0 & 0xf000) == 0x1000)
4642 
    rv = decode_BRCC_0 (iw0, pc, outf);
4643 
  else if ((iw0 & 0xf000) == 0x2000)
4644 
    rv = decode_UJUMP_0 (iw0, pc, outf);
4645 
  else if ((iw0 & 0xf000) == 0x3000)
4646 
    rv = decode_REGMV_0 (iw0, outf);
4647 
  else if ((iw0 & 0xfc00) == 0x4000)
4648 
    rv = decode_ALU2op_0 (iw0, outf);
4649 
  else if ((iw0 & 0xfe00) == 0x4400)
4650 
    rv = decode_PTR2op_0 (iw0, outf);
4651 
  else if ((iw0 & 0xf800) == 0x4800)
4652 
    rv = decode_LOGI2op_0 (iw0, outf);
4653 
  else if ((iw0 & 0xf000) == 0x5000)
4654 
    rv = decode_COMP3op_0 (iw0, outf);
4655 
  else if ((iw0 & 0xf800) == 0x6000)
4656 
    rv = decode_COMPI2opD_0 (iw0, outf);
4657 
  else if ((iw0 & 0xf800) == 0x6800)
4658 
    rv = decode_COMPI2opP_0 (iw0, outf);
4659 
  else if ((iw0 & 0xf000) == 0x8000)
4660 
    rv = decode_LDSTpmod_0 (iw0, outf);
4661 
  else if ((iw0 & 0xff60) == 0x9e60)
4662 
    rv = decode_dagMODim_0 (iw0, outf);
4663 
  else if ((iw0 & 0xfff0) == 0x9f60)
4664 
    rv = decode_dagMODik_0 (iw0, outf);
4665 
  else if ((iw0 & 0xfc00) == 0x9c00)
4666 
    rv = decode_dspLDST_0 (iw0, outf);
4667 
  else if ((iw0 & 0xf000) == 0x9000)
4668 
    rv = decode_LDST_0 (iw0, outf);
4669 
  else if ((iw0 & 0xfc00) == 0xb800)
4670 
    rv = decode_LDSTiiFP_0 (iw0, outf);
4671 
  else if ((iw0 & 0xe000) == 0xA000)
4672 
    rv = decode_LDSTii_0 (iw0, outf);
4673 
  else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
4674 
    rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4675 
  else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
4676 
    rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4677 
  else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
4678 
    rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4679 
  else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
4680 
    rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4681 
  else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
4682 
    rv = decode_linkage_0 (iw0, iw1, outf);
4683 
  else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
4684 
    rv = decode_dsp32mac_0 (iw0, iw1, outf);
4685 
  else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
4686 
    rv = decode_dsp32mult_0 (iw0, iw1, outf);
4687 
  else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
4688 
    rv = decode_dsp32alu_0 (iw0, iw1, outf);
4689 
  else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
4690 
    rv = decode_dsp32shift_0 (iw0, iw1, outf);
4691 
  else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
4692 
    rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4693 
  else if ((iw0 & 0xff00) == 0xf800)
4694 
    rv = decode_pseudoDEBUG_0 (iw0, outf);
4695 
#if 0
4696 
  else if ((iw0 & 0xFF00) == 0xF900)
4697 
    rv = decode_pseudoOChar_0 (iw0, iw1, pc, outf);
4698 
#endif
4699 
  else if ((iw0 & 0xFFC0) == 0xf000 && (iw1 & 0x0000) == 0x0000)
4700 
    rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4701 
 
4702 
  return rv;
4703 
}
4704 
 
4705 
 
4706 
int
4707 
print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4708 
{
4709 
  bfd_byte buf[2];
4710 
  unsigned short iw0;
4711 
  int status;
4712 
  int count = 0;
4713 
 
4714 
  status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf);
4715 
  iw0 = bfd_getl16 (buf);
4716 
 
4717 
  count += _print_insn_bfin (pc, outf);
4718 
 
4719 
  /* Proper display of multiple issue instructions.  */
4720 
 
4721 
  if ((iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
4722 
      && ((iw0 & 0xe800) != 0xe800 /* Not Linkage.  */ ))
4723 
    {
4724 
      parallel = 1;
4725 
      outf->fprintf_func (outf->stream, " || ");
4726 
      count += _print_insn_bfin (pc + 4, outf);
4727 
      outf->fprintf_func (outf->stream, " || ");
4728 
      count += _print_insn_bfin (pc + 6, outf);
4729 
      parallel = 0;
4730 
    }
4731 
  if (count == 0)
4732 
    {
4733 
      outf->fprintf_func (outf->stream, "ILLEGAL");
4734 
      return 2;
4735 
    }
4736 
  if (!comment)
4737 
    outf->fprintf_func (outf->stream, ";");
4738 
 
4739 
  comment = 0;
4740 
 
4741 
  return count;
4742 
}

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