OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [opcodes/] [mt-opc.h] - Blame information for rev 252

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius 
/* Instruction opcode header for mt.
2 
 
3 
THIS FILE IS MACHINE GENERATED WITH CGEN.
4 
 
5 
Copyright 1996-2007 Free Software Foundation, Inc.
6 
 
7 
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8 
 
9 
   This file is free software; you can redistribute it and/or modify
10 
   it under the terms of the GNU General Public License as published by
11 
   the Free Software Foundation; either version 3, or (at your option)
12 
   any later version.
13 
 
14 
   It is distributed in the hope that it will be useful, but WITHOUT
15 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17 
   License for more details.
18 
 
19 
   You should have received a copy of the GNU General Public License along
20 
   with this program; if not, write to the Free Software Foundation, Inc.,
21 
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22 
 
23 
*/
24 
 
25 
#ifndef MT_OPC_H
26 
#define MT_OPC_H
27 
 
28 
/* -- opc.h */
29 
 
30 
/* Check applicability of instructions against machines.  */
31 
#define CGEN_VALIDATE_INSN_SUPPORTED
32 
 
33 
/* Allows reason codes to be output when assembler errors occur.  */
34 
#define CGEN_VERBOSE_ASSEMBLER_ERRORS
35 
 
36 
/* Override disassembly hashing - there are variable bits in the top
37 
   byte of these instructions.  */
38 
#define CGEN_DIS_HASH_SIZE 8
39 
#define CGEN_DIS_HASH(buf, value) (((* (unsigned char *) (buf)) >> 5) % CGEN_DIS_HASH_SIZE)
40 
 
41 
#define CGEN_ASM_HASH_SIZE 127
42 
#define CGEN_ASM_HASH(insn) mt_asm_hash (insn)
43 
 
44 
extern unsigned int mt_asm_hash (const char *);
45 
 
46 
extern int mt_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
47 
 
48 
 
49 
/* -- opc.c */
50 
/* Enum declaration for mt instruction types.  */
51 
typedef enum cgen_insn_type {
52 
  MT_INSN_INVALID, MT_INSN_ADD, MT_INSN_ADDU, MT_INSN_ADDI
53 
 , MT_INSN_ADDUI, MT_INSN_SUB, MT_INSN_SUBU, MT_INSN_SUBI
54 
 , MT_INSN_SUBUI, MT_INSN_MUL, MT_INSN_MULI, MT_INSN_AND
55 
 , MT_INSN_ANDI, MT_INSN_OR, MT_INSN_NOP, MT_INSN_ORI
56 
 , MT_INSN_XOR, MT_INSN_XORI, MT_INSN_NAND, MT_INSN_NANDI
57 
 , MT_INSN_NOR, MT_INSN_NORI, MT_INSN_XNOR, MT_INSN_XNORI
58 
 , MT_INSN_LDUI, MT_INSN_LSL, MT_INSN_LSLI, MT_INSN_LSR
59 
 , MT_INSN_LSRI, MT_INSN_ASR, MT_INSN_ASRI, MT_INSN_BRLT
60 
 , MT_INSN_BRLE, MT_INSN_BREQ, MT_INSN_BRNE, MT_INSN_JMP
61 
 , MT_INSN_JAL, MT_INSN_DBNZ, MT_INSN_EI, MT_INSN_DI
62 
 , MT_INSN_SI, MT_INSN_RETI, MT_INSN_LDW, MT_INSN_STW
63 
 , MT_INSN_BREAK, MT_INSN_IFLUSH, MT_INSN_LDCTXT, MT_INSN_LDFB
64 
 , MT_INSN_STFB, MT_INSN_FBCB, MT_INSN_MFBCB, MT_INSN_FBCCI
65 
 , MT_INSN_FBRCI, MT_INSN_FBCRI, MT_INSN_FBRRI, MT_INSN_MFBCCI
66 
 , MT_INSN_MFBRCI, MT_INSN_MFBCRI, MT_INSN_MFBRRI, MT_INSN_FBCBDR
67 
 , MT_INSN_RCFBCB, MT_INSN_MRCFBCB, MT_INSN_CBCAST, MT_INSN_DUPCBCAST
68 
 , MT_INSN_WFBI, MT_INSN_WFB, MT_INSN_RCRISC, MT_INSN_FBCBINC
69 
 , MT_INSN_RCXMODE, MT_INSN_INTERLEAVER, MT_INSN_WFBINC, MT_INSN_MWFBINC
70 
 , MT_INSN_WFBINCR, MT_INSN_MWFBINCR, MT_INSN_FBCBINCS, MT_INSN_MFBCBINCS
71 
 , MT_INSN_FBCBINCRS, MT_INSN_MFBCBINCRS, MT_INSN_LOOP, MT_INSN_LOOPI
72 
 , MT_INSN_DFBC, MT_INSN_DWFB, MT_INSN_FBWFB, MT_INSN_DFBR
73 
} CGEN_INSN_TYPE;
74 
 
75 
/* Index of `invalid' insn place holder.  */
76 
#define CGEN_INSN_INVALID MT_INSN_INVALID
77 
 
78 
/* Total number of insns in table.  */
79 
#define MAX_INSNS ((int) MT_INSN_DFBR + 1)
80 
 
81 
/* This struct records data prior to insertion or after extraction.  */
82 
struct cgen_fields
83 
{
84 
  int length;
85 
  long f_nil;
86 
  long f_anyof;
87 
  long f_msys;
88 
  long f_opc;
89 
  long f_imm;
90 
  long f_uu24;
91 
  long f_sr1;
92 
  long f_sr2;
93 
  long f_dr;
94 
  long f_drrr;
95 
  long f_imm16u;
96 
  long f_imm16s;
97 
  long f_imm16a;
98 
  long f_uu4a;
99 
  long f_uu4b;
100 
  long f_uu12;
101 
  long f_uu8;
102 
  long f_uu16;
103 
  long f_uu1;
104 
  long f_msopc;
105 
  long f_uu_26_25;
106 
  long f_mask;
107 
  long f_bankaddr;
108 
  long f_rda;
109 
  long f_uu_2_25;
110 
  long f_rbbc;
111 
  long f_perm;
112 
  long f_mode;
113 
  long f_uu_1_24;
114 
  long f_wr;
115 
  long f_fbincr;
116 
  long f_uu_2_23;
117 
  long f_xmode;
118 
  long f_a23;
119 
  long f_mask1;
120 
  long f_cr;
121 
  long f_type;
122 
  long f_incamt;
123 
  long f_cbs;
124 
  long f_uu_1_19;
125 
  long f_ball;
126 
  long f_colnum;
127 
  long f_brc;
128 
  long f_incr;
129 
  long f_fbdisp;
130 
  long f_uu_4_15;
131 
  long f_length;
132 
  long f_uu_1_15;
133 
  long f_rc;
134 
  long f_rcnum;
135 
  long f_rownum;
136 
  long f_cbx;
137 
  long f_id;
138 
  long f_size;
139 
  long f_rownum1;
140 
  long f_uu_3_11;
141 
  long f_rc1;
142 
  long f_ccb;
143 
  long f_cbrb;
144 
  long f_cdb;
145 
  long f_rownum2;
146 
  long f_cell;
147 
  long f_uu_3_9;
148 
  long f_contnum;
149 
  long f_uu_1_6;
150 
  long f_dup;
151 
  long f_rc2;
152 
  long f_ctxdisp;
153 
  long f_imm16l;
154 
  long f_loopo;
155 
  long f_cb1sel;
156 
  long f_cb2sel;
157 
  long f_cb1incr;
158 
  long f_cb2incr;
159 
  long f_rc3;
160 
  long f_msysfrsr2;
161 
  long f_brc2;
162 
  long f_ball2;
163 
};
164 
 
165 
#define CGEN_INIT_PARSE(od) \
166 
{\
167 
}
168 
#define CGEN_INIT_INSERT(od) \
169 
{\
170 
}
171 
#define CGEN_INIT_EXTRACT(od) \
172 
{\
173 
}
174 
#define CGEN_INIT_PRINT(od) \
175 
{\
176 
}
177 
 
178 
 
179 
#endif /* MT_OPC_H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.