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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [opcodes/] [or32-opc.c] - Blame information for rev 156

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1 38 julius
/* Table of opcodes for the OpenRISC 1000 ISA.
2
   Copyright 2002, 2004, 2005, 2007 Free Software Foundation, Inc.
3
   Contributed by Damjan Lampret (lampret@opencores.org).
4
 
5
   This file is part of the GNU opcodes library.
6
 
7
   This library is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
 
12
   It is distributed in the hope that it will be useful, but WITHOUT
13
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
   License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with this program; if not, write to the Free Software
19
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20
   MA 02110-1301, USA.  */
21
 
22
/* We treat all letters the same in encode/decode routines so
23
   we need to assign some characteristics to them like signess etc.  */
24
#include <string.h>
25
#include <stdio.h>
26
#include <stdlib.h>
27
#include "safe-ctype.h"
28
#include "ansidecl.h"
29
#ifdef HAVE_CONFIG_H
30
# include "config.h"
31
#endif
32
#ifdef HAS_EXECUTION
33
# ifdef HAVE_INTTYPES_H
34
#  include <inttypes.h> /* ...but to get arch.h we need uint{8,16,32}_t... */
35
# endif
36
# include "port.h"
37
# include "arch.h" /* ...but to get abstract.h, we need oraddr_t... */
38
# include "abstract.h" /* To get struct iqueue_entry... */
39
# include "debug.h" /* To get debug() */
40
#endif
41
#include "opcode/or32.h"
42
 
43
const struct or32_letter or32_letters[] =
44
{
45
  { 'A', NUM_UNSIGNED },
46
  { 'B', NUM_UNSIGNED },
47
  { 'D', NUM_UNSIGNED },
48
  { 'I', NUM_SIGNED },
49
  { 'K', NUM_UNSIGNED },
50
  { 'L', NUM_UNSIGNED },
51
  { 'N', NUM_SIGNED },
52
  { '0', NUM_UNSIGNED },
53
  { '\0', 0 }     /* Dummy entry.  */
54
};
55
 
56
/* Opcode encoding:
57
   machine[31:30]: first two bits of opcode
58
                   00 - neither of source operands is GPR
59
                   01 - second source operand is GPR (rB)
60
                   10 - first source operand is GPR (rA)
61
                   11 - both source operands are GPRs (rA and rB)
62
   machine[29:26]: next four bits of opcode
63
   machine[25:00]: instruction operands (specific to individual instruction)
64
 
65
  Recommendation: irrelevant instruction bits should be set with a value of
66
  bits in same positions of instruction preceding current instruction in the
67
  code (when assembling).  */
68
 
69
#ifdef HAS_EXECUTION
70
# if SIMPLE_EXECUTION
71
#  define EFN &l_none
72
#  define EF(func) &(func)
73
#  define EFI &l_invalid
74
# elif COMPLEX_EXECUTION
75
#  define EFN "l_none"
76
#  define EFI "l_invalid"
77
#  ifdef __GNUC__
78
#   define EF(func) #func
79
#  else
80
#   define EF(func) "func"
81
#  endif
82
# else /* DYNAMIC_EXECUTION */
83
#  define EFN &l_none
84
#  define EF(func) &(gen_ ##func)
85
#  define EFI &gen_l_invalid
86
# endif
87
#else /* HAS_EXECUTION */
88
# define EFN &l_none
89
# define EF(func) EFN
90
# define EFI EFN
91
#endif /* HAS_EXECUTION */
92
 
93
const struct or32_opcode or32_opcodes[] = {
94
  { "l.j",        "N",           "00 0x0  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_j), OR32_IF_DELAY, it_jump },
95
  { "l.jal",      "N",           "00 0x1  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_jal), OR32_IF_DELAY, it_jump },
96
  { "l.bnf",      "N",           "00 0x3  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bnf), OR32_IF_DELAY | OR32_R_FLAG, it_branch },
97
  { "l.bf",       "N",           "00 0x4  NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bf), OR32_IF_DELAY | OR32_R_FLAG, it_branch },
98
  { "l.nop",      "K",           "00 0x5  01--- ----- KKKK KKKK KKKK KKKK", EF(l_nop), 0, it_nop },
99
  { "l.movhi",    "rD,K",        "00 0x6  DDDDD ----0 KKKK KKKK KKKK KKKK", EF(l_movhi), 0, it_movimm },
100
  { "l.macrc",    "rD",          "00 0x6  DDDDD ----1 0000 0000 0000 0000", EF(l_macrc), 0, it_mac },
101
  { "l.sys",      "K",           "00 0x8  00000 00000 KKKK KKKK KKKK KKKK", EF(l_sys), 0, it_exception },
102
  { "l.trap",     "K",           "00 0x8  01000 00000 KKKK KKKK KKKK KKKK", EF(l_trap), 0, it_exception },
103
  { "l.msync",    "",            "00 0x8  10000 00000 0000 0000 0000 0000", EFN, 0, it_unknown },
104
  { "l.psync",    "",            "00 0x8  10100 00000 0000 0000 0000 0000", EFN, 0, it_unknown },
105
  { "l.csync",    "",            "00 0x8  11000 00000 0000 0000 0000 0000", EFN, 0, it_unknown },
106
  { "l.rfe",      "",            "00 0x9  ----- ----- ---- ---- ---- ----", EF(l_rfe), 0, it_exception },
107
  { "lv.all_eq.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x0",   EFI, 0, it_unknown },
108
  { "lv.all_eq.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x1",   EFI, 0, it_unknown },
109
  { "lv.all_ge.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x2",   EFI, 0, it_unknown },
110
  { "lv.all_ge.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x3",   EFI, 0, it_unknown },
111
  { "lv.all_gt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x4",   EFI, 0, it_unknown },
112
  { "lv.all_gt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x5",   EFI, 0, it_unknown },
113
  { "lv.all_le.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x6",   EFI, 0, it_unknown },
114
  { "lv.all_le.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x7",   EFI, 0, it_unknown },
115
  { "lv.all_lt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x8",   EFI, 0, it_unknown },
116
  { "lv.all_lt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0x9",   EFI, 0, it_unknown },
117
  { "lv.all_ne.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0xA",   EFI, 0, it_unknown },
118
  { "lv.all_ne.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x1 0xB",   EFI, 0, it_unknown },
119
  { "lv.any_eq.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x0",   EFI, 0, it_unknown },
120
  { "lv.any_eq.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x1",   EFI, 0, it_unknown },
121
  { "lv.any_ge.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x2",   EFI, 0, it_unknown },
122
  { "lv.any_ge.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x3",   EFI, 0, it_unknown },
123
  { "lv.any_gt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x4",   EFI, 0, it_unknown },
124
  { "lv.any_gt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x5",   EFI, 0, it_unknown },
125
  { "lv.any_le.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x6",   EFI, 0, it_unknown },
126
  { "lv.any_le.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x7",   EFI, 0, it_unknown },
127
  { "lv.any_lt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x8",   EFI, 0, it_unknown },
128
  { "lv.any_lt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0x9",   EFI, 0, it_unknown },
129
  { "lv.any_ne.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0xA",   EFI, 0, it_unknown },
130
  { "lv.any_ne.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x2 0xB",   EFI, 0, it_unknown },
131
  { "lv.add.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x0",   EFI, 0, it_unknown },
132
  { "lv.add.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x1",   EFI, 0, it_unknown },
133
  { "lv.adds.b",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x2",   EFI, 0, it_unknown },
134
  { "lv.adds.h",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x3",   EFI, 0, it_unknown },
135
  { "lv.addu.b",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x4",   EFI, 0, it_unknown },
136
  { "lv.addu.h",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x5",   EFI, 0, it_unknown },
137
  { "lv.addus.b", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x6",   EFI, 0, it_unknown },
138
  { "lv.addus.h", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x7",   EFI, 0, it_unknown },
139
  { "lv.and",     "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x8",   EFI, 0, it_unknown },
140
  { "lv.avg.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0x9",   EFI, 0, it_unknown },
141
  { "lv.avg.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x3 0xA",   EFI, 0, it_unknown },
142
  { "lv.cmp_eq.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x0",   EFI, 0, it_unknown },
143
  { "lv.cmp_eq.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x1",   EFI, 0, it_unknown },
144
  { "lv.cmp_ge.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x2",   EFI, 0, it_unknown },
145
  { "lv.cmp_ge.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x3",   EFI, 0, it_unknown },
146
  { "lv.cmp_gt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x4",   EFI, 0, it_unknown },
147
  { "lv.cmp_gt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x5",   EFI, 0, it_unknown },
148
  { "lv.cmp_le.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x6",   EFI, 0, it_unknown },
149
  { "lv.cmp_le.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x7",   EFI, 0, it_unknown },
150
  { "lv.cmp_lt.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x8",   EFI, 0, it_unknown },
151
  { "lv.cmp_lt.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0x9",   EFI, 0, it_unknown },
152
  { "lv.cmp_ne.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0xA",   EFI, 0, it_unknown },
153
  { "lv.cmp_ne.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x4 0xB",   EFI, 0, it_unknown },
154
  { "lv.madds.h", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x4",   EFI, 0, it_unknown },
155
  { "lv.max.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x5",   EFI, 0, it_unknown },
156
  { "lv.max.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x6",   EFI, 0, it_unknown },
157
  { "lv.merge.b", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x7",   EFI, 0, it_unknown },
158
  { "lv.merge.h", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x8",   EFI, 0, it_unknown },
159
  { "lv.min.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0x9",   EFI, 0, it_unknown },
160
  { "lv.min.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xA",   EFI, 0, it_unknown },
161
  { "lv.msubs.h", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xB",   EFI, 0, it_unknown },
162
  { "lv.muls.h",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xC",   EFI, 0, it_unknown },
163
  { "lv.nand",    "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xD",   EFI, 0, it_unknown },
164
  { "lv.nor",     "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xE",   EFI, 0, it_unknown },
165
  { "lv.or",      "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x5 0xF",   EFI, 0, it_unknown },
166
  { "lv.pack.b",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x0",   EFI, 0, it_unknown },
167
  { "lv.pack.h",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x1",   EFI, 0, it_unknown },
168
  { "lv.packs.b", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x2",   EFI, 0, it_unknown },
169
  { "lv.packs.h", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x3",   EFI, 0, it_unknown },
170
  { "lv.packus.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x4",   EFI, 0, it_unknown },
171
  { "lv.packus.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x5",   EFI, 0, it_unknown },
172
  { "lv.perm.n",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x6",   EFI, 0, it_unknown },
173
  { "lv.rl.b",    "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x7",   EFI, 0, it_unknown },
174
  { "lv.rl.h",    "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x8",   EFI, 0, it_unknown },
175
  { "lv.sll.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0x9",   EFI, 0, it_unknown },
176
  { "lv.sll.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xA",   EFI, 0, it_unknown },
177
  { "lv.sll",     "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xB",   EFI, 0, it_unknown },
178
  { "lv.srl.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xC",   EFI, 0, it_unknown },
179
  { "lv.srl.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xD",   EFI, 0, it_unknown },
180
  { "lv.sra.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xE",   EFI, 0, it_unknown },
181
  { "lv.sra.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x6 0xF",   EFI, 0, it_unknown },
182
  { "lv.srl",     "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x0",   EFI, 0, it_unknown },
183
  { "lv.sub.b",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x1",   EFI, 0, it_unknown },
184
  { "lv.sub.h",   "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x2",   EFI, 0, it_unknown },
185
  { "lv.subs.b",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x3",   EFI, 0, it_unknown },
186
  { "lv.subs.h",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x4",   EFI, 0, it_unknown },
187
  { "lv.subu.b",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x5",   EFI, 0, it_unknown },
188
  { "lv.subu.h",  "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x6",   EFI, 0, it_unknown },
189
  { "lv.subus.b", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x7",   EFI, 0, it_unknown },
190
  { "lv.subus.h", "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x8",   EFI, 0, it_unknown },
191
  { "lv.unpack.b","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0x9",   EFI, 0, it_unknown },
192
  { "lv.unpack.h","rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0xA",   EFI, 0, it_unknown },
193
  { "lv.xor",     "rD,rA,rB",    "00 0xA  DDDDD AAAAA BBBB B--- 0x7 0xB",   EFI, 0, it_unknown },
194
  { "lv.cust1",   "",            "00 0xA  ----- ----- ---- ---- 0xC ----",  EFI, 0, it_unknown },
195
  { "lv.cust2",   "",            "00 0xA  ----- ----- ---- ---- 0xD ----",  EFI, 0, it_unknown },
196
  { "lv.cust3",   "",            "00 0xA  ----- ----- ---- ---- 0xE ----",  EFI, 0, it_unknown },
197
  { "lv.cust4",   "",            "00 0xA  ----- ----- ---- ---- 0xF ----",  EFI, 0, it_unknown },
198
 
199
  { "l.jr",       "rB",          "01 0x1  ----- ----- BBBB B--- ---- ----", EF(l_jr), OR32_IF_DELAY, it_jump },
200
  { "l.jalr",     "rB",          "01 0x2  ----- ----- BBBB B--- ---- ----", EF(l_jalr), OR32_IF_DELAY, it_jump },
201
  { "l.maci",     "rA,I",        "01 0x3  IIIII AAAAA ---- -III IIII IIII", EF(l_mac), 0, it_mac },
202
  { "l.cust1",    "",            "01 0xC  ----- ----- ---- ---- ---- ----", EF(l_cust1), 0, it_unknown },
203
  { "l.cust2",    "",            "01 0xD  ----- ----- ---- ---- ---- ----", EF(l_cust2), 0, it_unknown },
204
  { "l.cust3",    "",            "01 0xE  ----- ----- ---- ---- ---- ----", EF(l_cust3), 0, it_unknown },
205
  { "l.cust4",    "",            "01 0xF  ----- ----- ---- ---- ---- ----", EF(l_cust4), 0, it_unknown },
206
 
207
  { "l.ld",       "rD,I(rA)",    "10 0x0  DDDDD AAAAA IIII IIII IIII IIII", EFI, 0, it_load },
208
  { "l.lwz",      "rD,I(rA)",    "10 0x1  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lwz), 0, it_load },
209
  { "l.lws",      "rD,I(rA)",    "10 0x2  DDDDD AAAAA IIII IIII IIII IIII", EFI, 0, it_load },
210
  { "l.lbz",      "rD,I(rA)",    "10 0x3  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbz), 0, it_load },
211
  { "l.lbs",      "rD,I(rA)",    "10 0x4  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbs), 0, it_load },
212
  { "l.lhz",      "rD,I(rA)",    "10 0x5  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhz), 0, it_load },
213
  { "l.lhs",      "rD,I(rA)",    "10 0x6  DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhs), 0, it_load },
214
 
215
  { "l.addi",     "rD,rA,I",     "10 0x7  DDDDD AAAAA IIII IIII IIII IIII", EF(l_add), OR32_W_FLAG, it_arith },
216
  { "l.addic",    "rD,rA,I",     "10 0x8  DDDDD AAAAA IIII IIII IIII IIII", EFI, 0, it_arith },
217
  { "l.andi",     "rD,rA,K",     "10 0x9  DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_and), OR32_W_FLAG, it_arith },
218
  { "l.ori",      "rD,rA,K",     "10 0xA  DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_or), 0, it_arith },
219
  { "l.xori",     "rD,rA,I",     "10 0xB  DDDDD AAAAA IIII IIII IIII IIII", EF(l_xor), 0, it_arith },
220
  { "l.muli",     "rD,rA,I",     "10 0xC  DDDDD AAAAA IIII IIII IIII IIII", EF(l_mul), 0, it_arith },
221
  { "l.mfspr",    "rD,rA,K",     "10 0xD  DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_mfspr), 0, it_move },
222
  { "l.slli",     "rD,rA,L",     "10 0xE  DDDDD AAAAA ---- ---- 00LL LLLL", EF(l_sll), 0, it_shift },
223
  { "l.srli",     "rD,rA,L",     "10 0xE  DDDDD AAAAA ---- ---- 01LL LLLL", EF(l_srl), 0, it_shift },
224
  { "l.srai",     "rD,rA,L",     "10 0xE  DDDDD AAAAA ---- ---- 10LL LLLL", EF(l_sra), 0, it_shift },
225
  { "l.rori",     "rD,rA,L",     "10 0xE  DDDDD AAAAA ---- ---- 11LL LLLL", EFI, 0, it_shift },
226
 
227
  { "l.sfeqi",    "rA,I",        "10 0xF  00000 AAAAA IIII IIII IIII IIII", EF(l_sfeq), OR32_W_FLAG, it_compare },
228
  { "l.sfnei",    "rA,I",        "10 0xF  00001 AAAAA IIII IIII IIII IIII", EF(l_sfne), OR32_W_FLAG, it_compare },
229
  { "l.sfgtui",   "rA,I",        "10 0xF  00010 AAAAA IIII IIII IIII IIII", EF(l_sfgtu), OR32_W_FLAG, it_compare },
230
  { "l.sfgeui",   "rA,I",        "10 0xF  00011 AAAAA IIII IIII IIII IIII", EF(l_sfgeu), OR32_W_FLAG, it_compare },
231
  { "l.sfltui",   "rA,I",        "10 0xF  00100 AAAAA IIII IIII IIII IIII", EF(l_sfltu), OR32_W_FLAG, it_compare },
232
  { "l.sfleui",   "rA,I",        "10 0xF  00101 AAAAA IIII IIII IIII IIII", EF(l_sfleu), OR32_W_FLAG, it_compare },
233
  { "l.sfgtsi",   "rA,I",        "10 0xF  01010 AAAAA IIII IIII IIII IIII", EF(l_sfgts), OR32_W_FLAG, it_compare },
234
  { "l.sfgesi",   "rA,I",        "10 0xF  01011 AAAAA IIII IIII IIII IIII", EF(l_sfges), OR32_W_FLAG, it_compare },
235
  { "l.sfltsi",   "rA,I",        "10 0xF  01100 AAAAA IIII IIII IIII IIII", EF(l_sflts), OR32_W_FLAG, it_compare },
236
  { "l.sflesi",   "rA,I",        "10 0xF  01101 AAAAA IIII IIII IIII IIII", EF(l_sfles), OR32_W_FLAG, it_compare },
237
 
238
  { "l.mtspr",    "rA,rB,K",     "11 0x0  KKKKK AAAAA BBBB BKKK KKKK KKKK", EF(l_mtspr), 0, it_move },
239
  { "l.mac",      "rA,rB",       "11 0x1  ----- AAAAA BBBB B--- ---- 0x1",  EF(l_mac), 0, it_mac },
240
  { "l.msb",      "rA,rB",       "11 0x1  ----- AAAAA BBBB B--- ---- 0x2",  EF(l_msb), 0, it_mac },
241
 
242
  { "lf.add.s",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x0",   EF(lf_add_s), 0, it_float },
243
  { "lf.sub.s",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x1",   EF(lf_sub_s), 0, it_float },
244
  { "lf.mul.s",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x2",   EF(lf_mul_s), 0, it_float },
245
  { "lf.div.s",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x3",   EF(lf_div_s), 0, it_float },
246
  { "lf.itof.s",  "rD,rA",       "11 0x2  DDDDD AAAAA 0000 0--- 0x0 0x4",   EF(lf_itof_s), 0, it_float },
247
  { "lf.ftoi.s",  "rD,rA",       "11 0x2  DDDDD AAAAA 0000 0--- 0x0 0x5",   EF(lf_ftoi_s), 0, it_float },
248
  { "lf.rem.s",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x6",   EF(lf_rem_s), 0, it_float },
249
  { "lf.madd.s",  "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x0 0x7",   EF(lf_madd_s), 0, it_float },
250
  { "lf.sfeq.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0x8",   EF(lf_sfeq_s), 0, it_float },
251
  { "lf.sfne.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0x9",   EF(lf_sfne_s), 0, it_float },
252
  { "lf.sfgt.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0xA",   EF(lf_sfgt_s), 0, it_float },
253
  { "lf.sfge.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0xB",   EF(lf_sfge_s), 0, it_float },
254
  { "lf.sflt.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0xC",   EF(lf_sflt_s), 0, it_float },
255
  { "lf.sfle.s",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x0 0xD",   EF(lf_sfle_s), 0, it_float },
256
  { "lf.cust1.s", "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0xD ----",  EFI, 0, it_float },
257
 
258
  { "lf.add.d",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x0",   EFI, 0, it_float },
259
  { "lf.sub.d",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x1",   EFI, 0, it_float },
260
  { "lf.mul.d",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x2",   EFI, 0, it_float },
261
  { "lf.div.d",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x3",   EFI, 0, it_float },
262
  { "lf.itof.d",  "rD,rA",       "11 0x2  DDDDD AAAAA 0000 0--- 0x1 0x4",   EFI, 0, it_float },
263
  { "lf.ftoi.d",  "rD,rA",       "11 0x2  DDDDD AAAAA 0000 0--- 0x1 0x5",   EFI, 0, it_float },
264
  { "lf.rem.d",   "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x6",   EFI, 0, it_float },
265
  { "lf.madd.d",  "rD,rA,rB",    "11 0x2  DDDDD AAAAA BBBB B--- 0x1 0x7",   EFI, 0, it_float },
266
  { "lf.sfeq.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0x8",   EFI, 0, it_float },
267
  { "lf.sfne.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0x9",   EFI, 0, it_float },
268
  { "lf.sfgt.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0xA",   EFI, 0, it_float },
269
  { "lf.sfge.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0xB",   EFI, 0, it_float },
270
  { "lf.sflt.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0xC",   EFI, 0, it_float },
271
  { "lf.sfle.d",  "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0x1 0xD",   EFI, 0, it_float },
272
  { "lf.cust1.d", "rA,rB",       "11 0x2  ----- AAAAA BBBB B--- 0xE ----",  EFI, 0, it_float },
273
 
274
  { "l.sd",       "I(rD),rB",    "11 0x4  IIIII DDDDD BBBB BIII IIII IIII", EFI, 0, it_store },
275
  { "l.sw",       "I(rD),rB",    "11 0x5  IIIII DDDDD BBBB BIII IIII IIII", EF(l_sw), 0, it_store },
276
  { "l.sb",       "I(rD),rB",    "11 0x6  IIIII DDDDD BBBB BIII IIII IIII", EF(l_sb), 0, it_store },
277
  { "l.sh",       "I(rD),rB",    "11 0x7  IIIII DDDDD BBBB BIII IIII IIII", EF(l_sh), 0, it_store },
278
 
279
  { "l.add",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x0",  EF(l_add), OR32_W_FLAG, it_arith },
280
  { "l.addc",     "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x1",  EF(l_addc), OR32_W_FLAG, it_arith },
281
  { "l.sub",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x2",  EF(l_sub), 0, it_arith },
282
  { "l.and",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x3",  EF(l_and), OR32_W_FLAG, it_arith },
283
  { "l.or",       "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x4",  EF(l_or), 0, it_arith },
284
  { "l.xor",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0x5",  EF(l_xor), 0, it_arith },
285
  { "l.mul",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0x6",  EF(l_mul), 0, it_arith },
286
 
287
  { "l.sll",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 00-- 0x8",  EF(l_sll), 0, it_shift },
288
  { "l.srl",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 01-- 0x8",  EF(l_srl), 0, it_shift },
289
  { "l.sra",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 10-- 0x8",  EF(l_sra), 0, it_shift },
290
  { "l.ror",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 11-- 0x8",  EFI, 0, it_shift },
291
  { "l.div",      "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0x9",  EF(l_div), 0, it_arith },
292
  { "l.divu",     "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0xA",  EF(l_divu), 0, it_arith },
293
  { "l.mulu",     "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-11 ---- 0xB",  EFI, 0, it_arith },
294
  { "l.extbs",    "rD,rA",       "11 0x8  DDDDD AAAAA ---- --00 01-- 0xC",  EF(l_extbs), 0, it_move },
295
  { "l.exths",    "rD,rA",       "11 0x8  DDDDD AAAAA ---- --00 00-- 0xC",  EF(l_exths), 0, it_move },
296
  { "l.extws",    "rD,rA",       "11 0x8  DDDDD AAAAA ---- --00 00-- 0xD",  EF(l_extws), 0, it_move },
297
  { "l.extbz",    "rD,rA",       "11 0x8  DDDDD AAAAA ---- --00 11-- 0xC",  EF(l_extbz), 0, it_move },
298
  { "l.exthz",    "rD,rA",       "11 0x8  DDDDD AAAAA ---- --00 10-- 0xC",  EF(l_exthz), 0, it_move },
299
  { "l.extwz",    "rD,rA",       "11 0x8  DDDDD AAAAA ---- --00 01-- 0xD",  EF(l_extwz), 0, it_move },
300
  { "l.cmov",     "rD,rA,rB",    "11 0x8  DDDDD AAAAA BBBB B-00 ---- 0xE",  EF(l_cmov), OR32_R_FLAG, it_move },
301
  { "l.ff1",      "rD,rA",       "11 0x8  DDDDD AAAAA ---- --00 ---- 0xF",  EF(l_ff1), 0, it_arith },
302
  { "l.fl1",      "rD,rA",       "11 0x8  DDDDD AAAAA ---- --01 ---- 0xF",  EFI, 0, it_arith },
303
 
304
  { "l.sfeq",     "rA,rB",       "11 0x9  00000 AAAAA BBBB B--- ---- ----", EF(l_sfeq), OR32_W_FLAG, it_compare },
305
  { "l.sfne",     "rA,rB",       "11 0x9  00001 AAAAA BBBB B--- ---- ----", EF(l_sfne), OR32_W_FLAG, it_compare },
306
  { "l.sfgtu",    "rA,rB",       "11 0x9  00010 AAAAA BBBB B--- ---- ----", EF(l_sfgtu), OR32_W_FLAG, it_compare },
307
  { "l.sfgeu",    "rA,rB",       "11 0x9  00011 AAAAA BBBB B--- ---- ----", EF(l_sfgeu), OR32_W_FLAG, it_compare },
308
  { "l.sfltu",    "rA,rB",       "11 0x9  00100 AAAAA BBBB B--- ---- ----", EF(l_sfltu), OR32_W_FLAG, it_compare },
309
  { "l.sfleu",    "rA,rB",       "11 0x9  00101 AAAAA BBBB B--- ---- ----", EF(l_sfleu), OR32_W_FLAG, it_compare },
310
  { "l.sfgts",    "rA,rB",       "11 0x9  01010 AAAAA BBBB B--- ---- ----", EF(l_sfgts), OR32_W_FLAG, it_compare },
311
  { "l.sfges",    "rA,rB",       "11 0x9  01011 AAAAA BBBB B--- ---- ----", EF(l_sfges), OR32_W_FLAG, it_compare },
312
  { "l.sflts",    "rA,rB",       "11 0x9  01100 AAAAA BBBB B--- ---- ----", EF(l_sflts), OR32_W_FLAG, it_compare },
313
  { "l.sfles",    "rA,rB",       "11 0x9  01101 AAAAA BBBB B--- ---- ----", EF(l_sfles), OR32_W_FLAG, it_compare },
314
 
315
  { "l.cust5",    "rD,rA,rB,L,K","11 0xC  DDDDD AAAAA BBBB BLLL LLLK KKKK", EFI, 0, it_unknown },
316
  { "l.cust6",    "",            "11 0xD  ----- ----- ---- ---- ---- ----", EFI, 0, it_unknown },
317
  { "l.cust7",    "",            "11 0xE  ----- ----- ---- ---- ---- ----", EFI, 0, it_unknown },
318
  { "l.cust8",    "",            "11 0xF  ----- ----- ---- ---- ---- ----", EFI, 0, it_unknown },
319
 
320
  /* This section should not be defined in or1ksim, since it contains duplicates,
321
     which would cause machine builder to complain.  */
322
#ifdef HAS_CUST
323
  { "l.cust5_1",  "rD",          "11 0xC  DDDDD ----- ---- ---- ---- ----", EFI, 0, it_unknown },
324
  { "l.cust5_2",  "rD,rA"   ,    "11 0xC  DDDDD AAAAA ---- ---- ---- ----", EFI, 0, it_unknown },
325
  { "l.cust5_3",  "rD,rA,rB",    "11 0xC  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0, it_unknown },
326
 
327
  { "l.cust6_1",  "rD",          "11 0xD  DDDDD ----- ---- ---- ---- ----", EFI, 0, it_unknown },
328
  { "l.cust6_2",  "rD,rA"   ,    "11 0xD  DDDDD AAAAA ---- ---- ---- ----", EFI, 0, it_unknown },
329
  { "l.cust6_3",  "rD,rA,rB",    "11 0xD  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0, it_unknown },
330
 
331
  { "l.cust7_1",  "rD",          "11 0xE  DDDDD ----- ---- ---- ---- ----", EFI, 0, it_unknown },
332
  { "l.cust7_2",  "rD,rA"   ,    "11 0xE  DDDDD AAAAA ---- ---- ---- ----", EFI, 0, it_unknown },
333
  { "l.cust7_3",  "rD,rA,rB",    "11 0xE  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0, it_unknown },
334
 
335
  { "l.cust8_1",  "rD",          "11 0xF  DDDDD ----- ---- ---- ---- ----", EFI, 0, it_unknown },
336
  { "l.cust8_2",  "rD,rA"   ,    "11 0xF  DDDDD AAAAA ---- ---- ---- ----", EFI, 0, it_unknown },
337
  { "l.cust8_3",  "rD,rA,rB",    "11 0xF  DDDDD AAAAA BBBB B--- ---- ----", EFI, 0, it_unknown },
338
#endif
339
 
340
  /* Dummy entry, not included in num_opcodes.  This
341
     lets code examine entry i+1 without checking
342
     if we've run off the end of the table.  */
343
  { "", "", "", EFI, 0, 0 }
344
};
345
 
346
#undef EFI
347
#undef EFN
348
#undef EF 
349
 
350
/* Define dummy, if debug is not defined.  */
351
#ifndef HAS_DEBUG
352
#define debug(l, fmt...) ;
353
#endif
354
 
355
const unsigned int or32_num_opcodes = ((sizeof(or32_opcodes)) / (sizeof(struct or32_opcode))) - 1;
356
 
357
/* Calculates instruction length in bytes. Always 4 for OR32.  */
358
 
359
int
360
insn_len (int insn_index ATTRIBUTE_UNUSED)
361
{
362
  insn_index = 0; /* Just to get rid that warning.  */
363
  return 4;
364
}
365
 
366
/* Is individual insn's operand signed or unsigned?  */
367
 
368
int
369
letter_signed (char l)
370
{
371
  const struct or32_letter *pletter;
372
 
373
  for (pletter = or32_letters; pletter->letter != '\0'; pletter++)
374
    if (pletter->letter == l)
375
      return pletter->sign;
376
 
377
  printf ("letter_signed(%c): Unknown letter.\n", l);
378
  return 0;
379
}
380
 
381
/* Simple cache for letter ranges */
382
static int range_cache[256] = {0};
383
 
384
/* Number of letters in the individual lettered operand.  */
385
int
386
letter_range (char l)
387
{
388
  const struct or32_opcode *pinsn;
389
  char *enc;
390
  int range = 0;
391
 
392
  /* Is value cached? */
393
  if ((range = range_cache[(unsigned char)l])) return range;
394
 
395
  for (pinsn = or32_opcodes; strlen (pinsn->name); pinsn ++)
396
    {
397
      if (strchr (pinsn->encoding,l))
398
        {
399
          for (enc = pinsn->encoding; *enc != '\0'; enc ++)
400
            if ((*enc == '0') && (*(enc + 1) == 'x'))
401
              enc += 2;
402
            else if (*enc == l)
403
              range++;
404
          return range_cache[(unsigned char)l] = range;
405
        }
406
    }
407
 
408
  printf ("\nABORT: letter_range(%c): Never used letter.\n", l);
409
  exit (1);
410
}
411
 
412
/* MM: Returns index of given instruction name.  */
413
 
414
int
415
insn_index (char *insn)
416
{
417
  unsigned int i;
418
  int found = -1;
419
 
420
  for (i = 0; i < or32_num_opcodes; i++)
421
    if (!strcmp (or32_opcodes[i].name, insn))
422
      {
423
        found = i;
424
        break;
425
      }
426
  return found;
427
}
428
 
429
const char *
430
insn_name (int index)
431
{
432
  if (index >= 0 && index < (int) or32_num_opcodes)
433
    return or32_opcodes[index].name;
434
  else
435
    return "???";
436
}
437
 
438
#if defined(HAS_EXECUTION) && SIMPLE_EXECUTION
439
void
440
l_none(struct iqueue_entry *current)
441
{
442
}
443
#elif defined(HAS_EXECUTION) && DYNAMIC_EXECUTION
444
void
445
l_none(struct op_queue *opq, int *param_t, orreg_t *param, int delay_slot)
446
{
447
}
448
#else
449
void
450
l_none (void)
451
{
452
}
453
#endif
454
 
455
/* Finite automata for instruction decoding building code.  */
456
 
457
/* Find simbols in encoding.  */
458
 
459
unsigned long
460
insn_extract (char param_ch, char *enc_initial)
461
{
462
  char *enc;
463
  unsigned long ret = 0;
464
  unsigned opc_pos = 32;
465
 
466
  for (enc = enc_initial; *enc != '\0'; )
467
    if ((*enc == '0') && (*(enc + 1) == 'x'))
468
      {
469
        unsigned long tmp = strtol (enc+2, NULL, 16);
470
 
471
        opc_pos -= 4;
472
        if (param_ch == '0' || param_ch == '1')
473
          {
474
            if (param_ch == '0')
475
              tmp = 15 - tmp;
476
            ret |= tmp << opc_pos;
477
          }
478
        enc += 3;
479
      }
480
    else
481
      {
482
        if (*enc == '0' || *enc == '1' || *enc == '-' || ISALPHA (*enc))
483
          {
484
            opc_pos--;
485
            if (param_ch == *enc)
486
              ret |= 1 << opc_pos;
487
          }
488
        enc++;
489
      }
490
  return ret;
491
}
492
 
493
#define MAX_AUTOMATA_SIZE  1200
494
#define MAX_OP_TABLE_SIZE  1200
495
#define MAX_LEN            8
496
 
497
#ifndef MIN
498
#define MIN(x, y)          ((x) < (y) ? (x) : (y))
499
#endif
500
 
501
unsigned long *automata;
502
int nuncovered;
503
int curpass = 0;
504
 
505
/* MM: Struct that hold runtime build information about instructions.  */
506
struct temp_insn_struct *ti;
507
 
508
struct insn_op_struct *op_data, **op_start;
509
 
510
/* Recursive utility function used to find best match and to build automata.  */
511
 
512
static unsigned long *
513
cover_insn (unsigned long * cur, int pass, unsigned int mask)
514
{
515
  int best_first = 0, last_match = -1, ninstr = 0;
516
  unsigned int best_len = 0;
517
  unsigned int i;
518
  unsigned long cur_mask = mask;
519
  unsigned long *next;
520
 
521
  for (i = 0; i < or32_num_opcodes; i++)
522
    if (ti[i].in_pass == pass)
523
      {
524
        cur_mask &= ti[i].insn_mask;
525
        ninstr++;
526
        last_match = i;
527
      }
528
 
529
  debug (8, "%08X %08lX\n", mask, cur_mask);
530
 
531
  if (ninstr == 0)
532
    return 0;
533
 
534
  if (ninstr == 1)
535
    {
536
      /* Leaf holds instruction index.  */
537
      debug (8, "%li>I%i %s\n",
538
             (long)(cur - automata), last_match, or32_opcodes[last_match].name);
539
 
540
      *cur = LEAF_FLAG | last_match;
541
      cur++;
542
      nuncovered--;
543
    }
544
  else
545
    {
546
      /* Find longest match.  */
547
      for (i = 0; i < 32; i++)
548
        {
549
          unsigned int len;
550
 
551
          for (len = best_len + 1; len < MIN (MAX_LEN, 33 - i); len++)
552
            {
553
              unsigned long m = (1UL << ((unsigned long) len)) - 1;
554
 
555
              debug (9, " (%i(%08lX & %08lX>>%i = %08lX, %08lX)",
556
                     len,m, cur_mask, i, (cur_mask >> (unsigned)i),
557
                     (cur_mask >> (unsigned) i) & m);
558
 
559
              if ((m & (cur_mask >> (unsigned) i)) == m)
560
                {
561
                  best_len = len;
562
                  best_first = i;
563
                  debug (9, "!");
564
                }
565
              else
566
                break;
567
            }
568
        }
569
 
570
      debug (9, "\n");
571
 
572
      if (!best_len)
573
        {
574
          fprintf (stderr, "%i instructions match mask 0x%08X:\n", ninstr, mask);
575
 
576
          for (i = 0; i < or32_num_opcodes; i++)
577
            if (ti[i].in_pass == pass)
578
              fprintf (stderr, "%s ", or32_opcodes[i].name);
579
 
580
          fprintf (stderr, "\n");
581
          exit (1);
582
        }
583
 
584
      debug (8, "%li> #### %i << %i (%i) ####\n",
585
             (long)(cur - automata), best_len, best_first, ninstr);
586
 
587
      *cur = best_first;
588
      cur++;
589
      *cur = (1 << best_len) - 1;
590
      cur++;
591
      next = cur;
592
 
593
      /* Allocate space for pointers.  */
594
      cur += 1 << best_len;
595
      cur_mask = (1 << (unsigned long) best_len) - 1;
596
 
597
      for (i = 0; i < ((unsigned) 1 << best_len); i++)
598
        {
599
          unsigned int j;
600
          unsigned long *c;
601
 
602
          curpass++;
603
          for (j = 0; j < or32_num_opcodes; j++)
604
            if (ti[j].in_pass == pass
605
                && ((ti[j].insn >> best_first) & cur_mask) == (unsigned long) i
606
                && ((ti[j].insn_mask >> best_first) & cur_mask) == cur_mask)
607
              ti[j].in_pass = curpass;
608
 
609
          debug (9, "%08X %08lX %i\n", mask, cur_mask, best_first);
610
          c = cover_insn (cur, curpass, mask & (~(cur_mask << best_first)));
611
          if (c)
612
            {
613
              debug (8, "%li> #%X -> %lu\n", (long)(next - automata), i, (long)(cur - automata));
614
              *next = cur - automata;
615
              cur = c;
616
            }
617
          else
618
            {
619
              debug (8, "%li> N/A\n", (long)(next - automata));
620
              *next = 0;
621
            }
622
          next++;
623
        }
624
    }
625
  return cur;
626
}
627
 
628
/* Returns number of nonzero bits.  */
629
 
630
static int
631
num_ones (unsigned long value)
632
{
633
  int c = 0;
634
 
635
  while (value)
636
    {
637
      if (value & 1)
638
        c++;
639
      value >>= 1;
640
    }
641
  return c;
642
}
643
 
644
/* Utility function, which converts parameters from or32_opcode
645
   format to more binary form.  Parameters are stored in ti struct.  */
646
 
647
static struct insn_op_struct *
648
parse_params (const struct or32_opcode * opcode,
649
              struct insn_op_struct * cur)
650
{
651
  char *args = opcode->args;
652
  int i, type;
653
  int num_cur_op = 0;
654
 
655
  i = 0;
656
  type = 0;
657
  /* In case we don't have any parameters, we add dummy read from r0.  */
658
 
659
  if (!(*args))
660
    {
661
      cur->type = OPTYPE_REG | OPTYPE_OP | OPTYPE_LAST;
662
      cur->data = 0;
663
      debug (9, "#%08lX %08lX\n", cur->type, cur->data);
664
      cur++;
665
      return cur;
666
  }
667
 
668
  while (*args != '\0')
669
    {
670
      if (*args == 'r')
671
        {
672
          args++;
673
          type |= OPTYPE_REG;
674
    if (*args == 'D')
675
      type |= OPTYPE_DST;
676
        }
677
      else if (ISALPHA (*args))
678
        {
679
          unsigned long arg;
680
 
681
          arg = insn_extract (*args, opcode->encoding);
682
          debug (9, "%s : %08lX ------\n", opcode->name, arg);
683
          if (letter_signed (*args))
684
            {
685
              type |= OPTYPE_SIG;
686
              type |= ((num_ones (arg) - 1) << OPTYPE_SBIT_SHR) & OPTYPE_SBIT;
687
            }
688
 
689
    num_cur_op = 0;
690
          /* Split argument to sequences of consecutive ones.  */
691
          while (arg)
692
            {
693
              int shr = 0;
694
              unsigned long tmp = arg, mask = 0;
695
 
696
              while ((tmp & 1) == 0)
697
                {
698
                  shr++;
699
                  tmp >>= 1;
700
                }
701
              while (tmp & 1)
702
                {
703
                  mask++;
704
                  tmp >>= 1;
705
                }
706
              cur->type = type | shr;
707
              cur->data = mask;
708
              arg &= ~(((1 << mask) - 1) << shr);
709
              debug (6, "|%08lX %08lX\n", cur->type, cur->data);
710
              cur++;
711
        num_cur_op++;
712
            }
713
          args++;
714
        }
715
      else if (*args == '(')
716
        {
717
          /* Next param is displacement.
718
             Later we will treat them as one operand.  */
719
    /* Set the OPTYPE_DIS flag on all insn_op_structs that belong to this
720
     * operand */
721
    while(num_cur_op > 0) {
722
            cur[-num_cur_op].type |= type | OPTYPE_DIS;
723
      num_cur_op--;
724
    }
725
    cur[-1].type |= OPTYPE_OP;
726
          debug(9, ">%08X %08X\n", cur->type, cur->data);
727
          type = 0;
728
          i++;
729
          args++;
730
        }
731
      else if (*args == OPERAND_DELIM)
732
        {
733
          cur--;
734
          cur->type = type | cur->type | OPTYPE_OP;
735
          debug (9, ">%08lX %08lX\n", cur->type, cur->data);
736
          cur++;
737
          type = 0;
738
          i++;
739
          args++;
740
        }
741
      else if (*args == '0')
742
        {
743
          cur->type = type;
744
          cur->data = 0;
745
          debug (9, ">%08lX %08lX\n", cur->type, cur->data);
746
          cur++;
747
          type = 0;
748
          i++;
749
          args++;
750
        }
751
      else if (*args == ')')
752
        args++;
753
      else
754
        {
755
          fprintf (stderr, "%s : parse error in args.\n", opcode->name);
756
          exit (1);
757
        }
758
    }
759
 
760
  cur--;
761
  cur->type = type | cur->type | OPTYPE_OP | OPTYPE_LAST;
762
  debug (9, "#%08lX %08lX\n", cur->type, cur->data);
763
  cur++;
764
 
765
  return cur;
766
}
767
 
768
/* Constructs new automata based on or32_opcodes array.  */
769
 
770
void
771
build_automata (void)
772
{
773
  unsigned int i;
774
  unsigned long *end;
775
  struct insn_op_struct *cur;
776
 
777
  automata = malloc (MAX_AUTOMATA_SIZE * sizeof (unsigned long));
778
  ti = malloc (sizeof (struct temp_insn_struct) * or32_num_opcodes);
779
 
780
  nuncovered = or32_num_opcodes;
781
  printf ("Building automata... ");
782
  /* Build temporary information about instructions.  */
783
  for (i = 0; i < or32_num_opcodes; i++)
784
    {
785
      unsigned long ones, zeros;
786
      char *encoding = or32_opcodes[i].encoding;
787
 
788
      ones  = insn_extract('1', encoding);
789
      zeros = insn_extract('0', encoding);
790
 
791
      ti[i].insn_mask = ones | zeros;
792
      ti[i].insn = ones;
793
      ti[i].in_pass = curpass = 0;
794
 
795
      /*debug(9, "%s: %s %08X %08X\n", or32_opcodes[i].name,
796
        or32_opcodes[i].encoding, ti[i].insn_mask, ti[i].insn);*/
797
    }
798
 
799
  /* Until all are covered search for best criteria to separate them.  */
800
  end = cover_insn (automata, curpass, 0xFFFFFFFF);
801
 
802
  if (end - automata > MAX_AUTOMATA_SIZE)
803
    {
804
      fprintf (stderr, "Automata too large. Increase MAX_AUTOMATA_SIZE.");
805
      exit (1);
806
    }
807
 
808
  printf ("done, num uncovered: %i/%i.\n", nuncovered, or32_num_opcodes);
809
  printf ("Parsing operands data... ");
810
 
811
  op_data = malloc (MAX_OP_TABLE_SIZE * sizeof (struct insn_op_struct));
812
  op_start = malloc (or32_num_opcodes * sizeof (struct insn_op_struct *));
813
  cur = op_data;
814
 
815
  for (i = 0; i < or32_num_opcodes; i++)
816
    {
817
      op_start[i] = cur;
818
      cur = parse_params (&or32_opcodes[i], cur);
819
 
820
      if (cur - op_data > MAX_OP_TABLE_SIZE)
821
        {
822
          fprintf (stderr, "Operands table too small, increase MAX_OP_TABLE_SIZE.\n");
823
          exit (1);
824
        }
825
    }
826
  printf ("done.\n");
827
}
828
 
829
void
830
destruct_automata (void)
831
{
832
  free (ti);
833
  free (automata);
834
  free (op_data);
835
  free (op_start);
836
}
837
 
838
/* Decodes instruction and returns instruction index.  */
839
 
840
int
841
insn_decode (unsigned int insn)
842
{
843
  unsigned long *a = automata;
844
  int i;
845
 
846
  while (!(*a & LEAF_FLAG))
847
    {
848
      unsigned int first = *a;
849
 
850
      debug (9, "%li ", (long)(a - automata));
851
 
852
      a++;
853
      i = (insn >> first) & *a;
854
      a++;
855
      if (!*(a + i))
856
        {
857
          /* Invalid instruction found?  */
858
          debug (9, "XXX\n");
859
          return -1;
860
        }
861
      a = automata + *(a + i);
862
    }
863
 
864
  i = *a & ~LEAF_FLAG;
865
 
866
  debug (9, "%i\n", i);
867
 
868
  /* Final check - do we have direct match?
869
     (based on or32_opcodes this should be the only possibility,
870
     but in case of invalid/missing instruction we must perform a check)  */
871
  if ((ti[i].insn_mask & insn) == ti[i].insn)
872
    return i;
873
  else
874
    return -1;
875
}
876
 
877
static char disassembled_str[50];
878
char *disassembled = &disassembled_str[0];
879
 
880
/* Automagically does zero- or sign- extension and also finds correct
881
   sign bit position if sign extension is correct extension. Which extension
882
   is proper is figured out from letter description.  */
883
 
884
unsigned long
885
extend_imm (unsigned long imm, char l)
886
{
887
  unsigned long mask;
888
  int letter_bits;
889
 
890
  /* First truncate all bits above valid range for this letter
891
     in case it is zero extend.  */
892
  letter_bits = letter_range (l);
893
  mask = (1 << letter_bits) - 1;
894
  imm &= mask;
895
 
896
  /* Do sign extend if this is the right one.  */
897
  if (letter_signed(l) && (imm >> (letter_bits - 1)))
898
    imm |= (~mask);
899
 
900
  return imm;
901
}
902
 
903
static unsigned long
904
or32_extract (char param_ch, char *enc_initial, unsigned long insn)
905
{
906
  char *enc;
907
  unsigned long ret = 0;
908
  int opc_pos = 0;
909
  int param_pos = 0;
910
 
911
  for (enc = enc_initial; *enc != '\0'; enc++)
912
    if (*enc == param_ch)
913
      {
914
        if (enc - 2 >= enc_initial && (*(enc - 2) == '0') && (*(enc - 1) == 'x'))
915
          continue;
916
        else
917
          param_pos++;
918
      }
919
 
920
#if DEBUG
921
  printf ("or32_extract: %x ", param_pos);
922
#endif
923
  opc_pos = 32;
924
 
925
  for (enc = enc_initial; *enc != '\0'; )
926
    if ((*enc == '0') && (*(enc + 1) == 'x'))
927
      {
928
        opc_pos -= 4;
929
        if ((param_ch == '0') || (param_ch == '1'))
930
          {
931
            unsigned long tmp = strtol (enc, NULL, 16);
932
#if DEBUG
933
            printf (" enc=%s, tmp=%x ", enc, tmp);
934
#endif
935
            if (param_ch == '0')
936
              tmp = 15 - tmp;
937
            ret |= tmp << opc_pos;
938
          }
939
        enc += 3;
940
      }
941
    else if ((*enc == '0') || (*enc == '1'))
942
      {
943
        opc_pos--;
944
        if (param_ch == *enc)
945
          ret |= 1 << opc_pos;
946
        enc++;
947
      }
948
    else if (*enc == param_ch)
949
      {
950
        opc_pos--;
951
        param_pos--;
952
#if DEBUG
953
        printf ("\n  ret=%x opc_pos=%x, param_pos=%x\n", ret, opc_pos, param_pos);
954
#endif  
955
        if (ISLOWER (param_ch))
956
          ret -= ((insn >> opc_pos) & 0x1) << param_pos;
957
        else
958
          ret += ((insn >> opc_pos) & 0x1) << param_pos;
959
        enc++;
960
      }
961
    else if (ISALPHA (*enc))
962
      {
963
        opc_pos--;
964
        enc++;
965
      }
966
    else if (*enc == '-')
967
      {
968
        opc_pos--;
969
        enc++;
970
      }
971
    else
972
      enc++;
973
 
974
#if DEBUG
975
  printf ("ret=%x\n", ret);
976
#endif
977
  return ret;
978
}
979
 
980
/* Print register. Used only by print_insn.  */
981
 
982
static char *
983
or32_print_register (char *dest, char param_ch, char *encoding, unsigned long insn)
984
{
985
  int regnum = or32_extract(param_ch, encoding, insn);
986
 
987
  sprintf (dest, "r%d", regnum);
988
  while (*dest) dest++;
989
  return dest;
990
}
991
 
992
/* Print immediate. Used only by print_insn.  */
993
 
994
static char *
995
or32_print_immediate (char *dest, char param_ch, char *encoding, unsigned long insn)
996
{
997
  int imm = or32_extract (param_ch, encoding, insn);
998
 
999
  imm = extend_imm (imm, param_ch);
1000
 
1001
  if (letter_signed (param_ch))
1002
    {
1003
      if (imm < 0)
1004
        sprintf (dest, "%d", imm);
1005
      else
1006
        sprintf (dest, "0x%x", imm);
1007
    }
1008
  else
1009
    sprintf (dest, "%#x", imm);
1010
  while (*dest) dest++;
1011
  return dest;
1012
}
1013
 
1014
/* Disassemble one instruction from insn index.
1015
   Return the size of the instruction.  */
1016
 
1017
int
1018
disassemble_index (insn, index)
1019
     unsigned long insn;
1020
     int index;
1021
{
1022
  char *dest = disassembled;
1023
 
1024
  if (index >= 0)
1025
    {
1026
      struct or32_opcode const *opcode = &or32_opcodes[index];
1027
      char *s;
1028
 
1029
      strcpy (dest, opcode->name);
1030
      while (*dest) dest++;
1031
      *dest++ = ' ';
1032
      *dest = 0;
1033
 
1034
      for (s = opcode->args; *s != '\0'; ++s)
1035
        {
1036
          switch (*s)
1037
            {
1038
            case '\0':
1039
              return insn_len (insn);
1040
 
1041
            case 'r':
1042
              dest = or32_print_register(dest, *++s, opcode->encoding, insn);
1043
              break;
1044
 
1045
            default:
1046
              if (strchr (opcode->encoding, *s))
1047
                dest = or32_print_immediate (dest, *s, opcode->encoding, insn);
1048
              else {
1049
                *dest++ = *s;
1050
                *dest = 0;
1051
              }
1052
            }
1053
        }
1054
    }
1055
  else
1056
    {
1057
      /* This used to be %8x for binutils.  */
1058
      sprintf(dest, ".word 0x%08lx", insn);
1059
      while (*dest) dest++;
1060
    }
1061
 
1062
  return insn_len (insn);
1063
}
1064
 
1065
/* Disassemble one instruction from insn to disassemble.
1066
   Return the size of the instruction.  */
1067
 
1068
int
1069
disassemble_insn (unsigned long insn)
1070
{
1071
  return disassemble_index (insn, insn_decode (insn));
1072
}
1073
 

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