OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.18.50/] [opcodes/] [s390-opc.c] - Blame information for rev 300

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius 
/* s390-opc.c -- S390 opcode list
2 
   Copyright 2000, 2001, 2003, 2007 Free Software Foundation, Inc.
3 
   Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
4 
 
5 
   This file is part of the GNU opcodes library.
6 
 
7 
   This library is free software; you can redistribute it and/or modify
8 
   it under the terms of the GNU General Public License as published by
9 
   the Free Software Foundation; either version 3, or (at your option)
10 
   any later version.
11 
 
12 
   It is distributed in the hope that it will be useful, but WITHOUT
13 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15 
   License for more details.
16 
 
17 
   You should have received a copy of the GNU General Public License
18 
   along with this file; see the file COPYING.  If not, write to the
19 
   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 
   MA 02110-1301, USA.  */
21 
 
22 
#include <stdio.h>
23 
#include "ansidecl.h"
24 
#include "opcode/s390.h"
25 
 
26 
/* This file holds the S390 opcode table.  The opcode table
27 
   includes almost all of the extended instruction mnemonics.  This
28 
   permits the disassembler to use them, and simplifies the assembler
29 
   logic, at the cost of increasing the table size.  The table is
30 
   strictly constant data, so the compiler should be able to put it in
31 
   the .text section.
32 
 
33 
   This file also holds the operand table.  All knowledge about
34 
   inserting operands into instructions and vice-versa is kept in this
35 
   file.  */
36 
 
37 
/* The operands table.
38 
   The fields are bits, shift, insert, extract, flags.  */
39 
 
40 
const struct s390_operand s390_operands[] =
41 
{
42 
#define UNUSED 0
43 
  { 0, 0, 0 },                    /* Indicates the end of the operand list */
44 
 
45 
/* General purpose register operands.  */
46 
 
47 
#define R_8    1                  /* GPR starting at position 8 */
48 
  { 4, 8, S390_OPERAND_GPR },
49 
#define R_12   2                  /* GPR starting at position 12 */
50 
  { 4, 12, S390_OPERAND_GPR },
51 
#define R_16   3                  /* GPR starting at position 16 */
52 
  { 4, 16, S390_OPERAND_GPR },
53 
#define R_20   4                  /* GPR starting at position 20 */
54 
  { 4, 20, S390_OPERAND_GPR },
55 
#define R_24   5                  /* GPR starting at position 24 */
56 
  { 4, 24, S390_OPERAND_GPR },
57 
#define R_28   6                  /* GPR starting at position 28 */
58 
  { 4, 28, S390_OPERAND_GPR },
59 
#define RO_28  7                  /* optional GPR starting at position 28 */
60 
  { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) },
61 
#define R_32   8                  /* GPR starting at position 32 */
62 
  { 4, 32, S390_OPERAND_GPR },
63 
 
64 
/* Floating point register operands.  */
65 
 
66 
#define F_8    9                  /* FPR starting at position 8 */
67 
  { 4, 8, S390_OPERAND_FPR },
68 
#define F_12   10                 /* FPR starting at position 12 */
69 
  { 4, 12, S390_OPERAND_FPR },
70 
#define F_16   11                 /* FPR starting at position 16 */
71 
  { 4, 16, S390_OPERAND_FPR },
72 
#define F_20   12                 /* FPR starting at position 16 */
73 
  { 4, 16, S390_OPERAND_FPR },
74 
#define F_24   13                 /* FPR starting at position 24 */
75 
  { 4, 24, S390_OPERAND_FPR },
76 
#define F_28   14                 /* FPR starting at position 28 */
77 
  { 4, 28, S390_OPERAND_FPR },
78 
#define F_32   15                 /* FPR starting at position 32 */
79 
  { 4, 32, S390_OPERAND_FPR },
80 
 
81 
/* Access register operands.  */
82 
 
83 
#define A_8    16                 /* Access reg. starting at position 8 */
84 
  { 4, 8, S390_OPERAND_AR },
85 
#define A_12   17                 /* Access reg. starting at position 12 */
86 
  { 4, 12, S390_OPERAND_AR },
87 
#define A_24   18                 /* Access reg. starting at position 24 */
88 
  { 4, 24, S390_OPERAND_AR },
89 
#define A_28   19                 /* Access reg. starting at position 28 */
90 
  { 4, 28, S390_OPERAND_AR },
91 
 
92 
/* Control register operands.  */
93 
 
94 
#define C_8    20                 /* Control reg. starting at position 8 */
95 
  { 4, 8, S390_OPERAND_CR },
96 
#define C_12   21                 /* Control reg. starting at position 12 */
97 
  { 4, 12, S390_OPERAND_CR },
98 
 
99 
/* Base register operands.  */
100 
 
101 
#define B_16   22                 /* Base register starting at position 16 */
102 
  { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR },
103 
#define B_32   23                 /* Base register starting at position 32 */
104 
  { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR },
105 
 
106 
#define X_12   24                 /* Index register starting at position 12 */
107 
  { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR },
108 
 
109 
/* Address displacement operands.  */
110 
 
111 
#define D_20   25                 /* Displacement starting at position 20 */
112 
  { 12, 20, S390_OPERAND_DISP },
113 
#define D_36   26                 /* Displacement starting at position 36 */
114 
  { 12, 36, S390_OPERAND_DISP },
115 
#define D20_20 27                 /* 20 bit displacement starting at 20 */
116 
  { 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED },
117 
 
118 
/* Length operands.  */
119 
 
120 
#define L4_8   28                 /* 4 bit length starting at position 8 */
121 
  { 4, 8, S390_OPERAND_LENGTH },
122 
#define L4_12  29                 /* 4 bit length starting at position 12 */
123 
  { 4, 12, S390_OPERAND_LENGTH },
124 
#define L8_8   30                 /* 8 bit length starting at position 8 */
125 
  { 8, 8, S390_OPERAND_LENGTH },
126 
 
127 
/* Signed immediate operands.  */
128 
 
129 
#define I8_8   31                 /* 8 bit signed value starting at 8 */
130 
  { 8, 8, S390_OPERAND_SIGNED },
131 
#define I8_32  32                 /* 8 bit signed value starting at 32 */
132 
  { 8, 32, S390_OPERAND_SIGNED },
133 
#define I16_16 33                 /* 16 bit signed value starting at 16 */
134 
  { 16, 16, S390_OPERAND_SIGNED },
135 
#define I16_32 34                 /* 16 bit signed value starting at 32 */
136 
  { 16, 32, S390_OPERAND_SIGNED },
137 
#define I32_16 35                 /* 32 bit signed value starting at 16 */
138 
  { 32, 16, S390_OPERAND_SIGNED },
139 
 
140 
/* Unsigned immediate operands.  */
141 
 
142 
#define U4_8   36                 /* 4 bit unsigned value starting at 8 */
143 
  { 4, 8, 0 },
144 
#define U4_12  37                 /* 4 bit unsigned value starting at 12 */
145 
  { 4, 12, 0 },
146 
#define U4_16  38                 /* 4 bit unsigned value starting at 16 */
147 
  { 4, 16, 0 },
148 
#define U4_20  39                 /* 4 bit unsigned value starting at 20 */
149 
  { 4, 20, 0 },
150 
#define U4_32  40                 /* 4 bit unsigned value starting at 32 */
151 
  { 4, 32, 0 },
152 
#define U8_8   41                 /* 8 bit unsigned value starting at 8 */
153 
  { 8, 8, 0 },
154 
#define U8_16  42                 /* 8 bit unsigned value starting at 16 */
155 
  { 8, 16, 0 },
156 
#define U8_24  43                 /* 8 bit unsigned value starting at 24 */
157 
  { 8, 24, 0 },
158 
#define U8_32  44                 /* 8 bit unsigned value starting at 32 */
159 
  { 8, 32, 0 },
160 
#define U16_16 45                 /* 16 bit unsigned value starting at 16 */
161 
  { 16, 16, 0 },
162 
#define U16_32 46                 /* 16 bit unsigned value starting at 32 */
163 
  { 16, 32, 0 },
164 
#define U32_16 47                 /* 32 bit unsigned value starting at 16 */
165 
  { 32, 16, 0 },
166 
 
167 
/* PC-relative address operands.  */
168 
 
169 
#define J16_16 48                 /* PC relative jump offset at 16 */
170 
  { 16, 16, S390_OPERAND_PCREL },
171 
#define J32_16 49                 /* PC relative long offset at 16 */
172 
  { 32, 16, S390_OPERAND_PCREL },
173 
 
174 
/* Conditional mask operands.  */
175 
 
176 
#define M_16   50                 /* 4 bit optional mask starting at 16 */
177 
  { 4, 16, S390_OPERAND_OPTIONAL },
178 
 
179 
};
180 
 
181 
 
182 
/* Macros used to form opcodes.  */
183 
 
184 
/* 8/16/48 bit opcodes.  */
185 
#define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 }
186 
#define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 }
187 
#define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \
188 
                  (x >> 16) & 255, (x >> 8) & 255, x & 255}
189 
 
190 
/* The new format of the INSTR_x_y and MASK_x_y defines is based
191 
   on the following rules:
192 
   1) the middle part of the definition (x in INSTR_x_y) is the official
193 
      names of the instruction format that you can find in the principals
194 
      of operation.
195 
   2) the last part of the definition (y in INSTR_x_y) gives you an idea
196 
      which operands the binary represenation of the instruction has.
197 
      The meanings of the letters in y are:
198 
      a - access register
199 
      c - control register
200 
      d - displacement, 12 bit
201 
      f - floating pointer register
202 
      i - signed integer, 4, 8, 16 or 32 bit
203 
      l - length, 4 or 8 bit
204 
      p - pc relative
205 
      r - general purpose register
206 
      u - unsigned integer, 4, 8, 16 or 32 bit
207 
      m - mode field, 4 bit
208 
 
209 
      The order of the letters reflects the layout of the format in
210 
      storage and not the order of the paramaters of the instructions.
211 
      The use of the letters is not a 100% match with the PoP but it is
212 
      quite close.
213 
 
214 
      For example the instruction "mvo" is defined in the PoP as follows:
215 
 
216 
      MVO  D1(L1,B1),D2(L2,B2)   [SS]
217 
 
218 
      --------------------------------------
219 
      | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 |
220 
      --------------------------------------
221 
 
222 
 
223 
      The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD.  */
224 
 
225 
#define INSTR_E          2, { 0,0,0,0,0,0 }                    /* e.g. pr    */
226 
#define INSTR_RIE_RRP    6, { R_8,R_12,J16_16,0,0,0 }          /* e.g. brxhg */
227 
#define INSTR_RIE_RRPU   6, { R_8,R_12,U4_32,J16_16,0,0 }      /* e.g. crj   */
228 
#define INSTR_RIE_RRP0   6, { R_8,R_12,J16_16,0,0,0 }          /* e.g. crjne */
229 
#define INSTR_RIE_RUPI   6, { R_8,I8_32,U4_12,J16_16,0,0 }     /* e.g. cij   */
230 
#define INSTR_RIE_R0PI   6, { R_8,I8_32,J16_16,0,0,0 }         /* e.g. cijne */
231 
#define INSTR_RIE_RUPU   6, { R_8,U8_32,U4_12,J16_16,0,0 }     /* e.g. clij  */
232 
#define INSTR_RIE_R0PU   6, { R_8,U8_32,J16_16,0,0,0 }         /* e.g. clijne */
233 
#define INSTR_RIE_R0IU   6, { R_8,I16_16,U4_32,0,0,0 }         /* e.g. cit   */
234 
#define INSTR_RIE_R0I0   6, { R_8,I16_16,0,0,0,0 }             /* e.g. citne */
235 
#define INSTR_RIE_R0UU   6, { R_8,U16_16,U4_32,0,0,0 }         /* e.g. clfit */
236 
#define INSTR_RIE_R0U0   6, { R_8,U16_16,0,0,0,0 }             /* e.g. clfitne */
237 
#define INSTR_RIE_RRUUU  6, { R_8,R_12,U8_16,U8_24,U8_32,0 }   /* e.g. rnsbg */
238 
#define INSTR_RIL_0P     6, { J32_16,0,0,0,0 }                 /* e.g. jg    */
239 
#define INSTR_RIL_RP     6, { R_8,J32_16,0,0,0,0 }             /* e.g. brasl */
240 
#define INSTR_RIL_UP     6, { U4_8,J32_16,0,0,0,0 }            /* e.g. brcl  */
241 
#define INSTR_RIL_RI     6, { R_8,I32_16,0,0,0,0 }             /* e.g. afi   */
242 
#define INSTR_RIL_RU     6, { R_8,U32_16,0,0,0,0 }             /* e.g. alfi  */
243 
#define INSTR_RI_0P      4, { J16_16,0,0,0,0,0 }               /* e.g. j     */
244 
#define INSTR_RI_RI      4, { R_8,I16_16,0,0,0,0 }             /* e.g. ahi   */
245 
#define INSTR_RI_RP      4, { R_8,J16_16,0,0,0,0 }             /* e.g. brct  */
246 
#define INSTR_RI_RU      4, { R_8,U16_16,0,0,0,0 }             /* e.g. tml   */
247 
#define INSTR_RI_UP      4, { U4_8,J16_16,0,0,0,0 }            /* e.g. brc   */
248 
#define INSTR_RIS_RURDI  6, { R_8,I8_32,U4_12,D_20,B_16,0 }    /* e.g. cib   */
249 
#define INSTR_RIS_R0RDI  6, { R_8,I8_32,D_20,B_16,0,0 }        /* e.g. cibne */
250 
#define INSTR_RIS_RURDU  6, { R_8,U8_32,U4_12,D_20,B_16,0 }    /* e.g. clib  */
251 
#define INSTR_RIS_R0RDU  6, { R_8,U8_32,D_20,B_16,0,0 }        /* e.g. clibne*/
252 
#define INSTR_RRE_00     4, { 0,0,0,0,0,0 }                    /* e.g. palb  */
253 
#define INSTR_RRE_0R     4, { R_28,0,0,0,0,0 }                 /* e.g. tb    */
254 
#define INSTR_RRE_AA     4, { A_24,A_28,0,0,0,0 }              /* e.g. cpya  */
255 
#define INSTR_RRE_AR     4, { A_24,R_28,0,0,0,0 }              /* e.g. sar   */
256 
#define INSTR_RRE_F0     4, { F_24,0,0,0,0,0 }                 /* e.g. sqer  */
257 
#define INSTR_RRE_FF     4, { F_24,F_28,0,0,0,0 }              /* e.g. debr  */
258 
#define INSTR_RRE_R0     4, { R_24,0,0,0,0,0 }                 /* e.g. ipm   */
259 
#define INSTR_RRE_RA     4, { R_24,A_28,0,0,0,0 }              /* e.g. ear   */
260 
#define INSTR_RRE_RF     4, { R_24,F_28,0,0,0,0 }              /* e.g. cefbr */
261 
#define INSTR_RRE_RR     4, { R_24,R_28,0,0,0,0 }              /* e.g. lura  */
262 
#define INSTR_RRE_FR     4, { F_24,R_28,0,0,0,0 }              /* e.g. ldgr  */
263 
/* Actually efpc and sfpc do not take an optional operand.
264 
   This is just a workaround for existing code e.g. glibc.  */
265 
#define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 }             /* efpc, sfpc */
266 
#define INSTR_RRF_F0FF   4, { F_16,F_24,F_28,0,0,0 }           /* e.g. madbr */
267 
#define INSTR_RRF_F0FF2  4, { F_24,F_16,F_28,0,0,0 }           /* e.g. cpsdr */
268 
#define INSTR_RRF_F0FR   4, { F_24,F_16,R_28,0,0,0 }           /* e.g. iedtr */
269 
#define INSTR_RRF_FUFF   4, { F_24,F_16,F_28,U4_20,0,0 }       /* e.g. didbr */
270 
#define INSTR_RRF_RURR   4, { R_24,R_28,R_16,U4_20,0,0 }       /* e.g. .insn */
271 
#define INSTR_RRF_R0RR   4, { R_24,R_28,R_16,0,0,0 }           /* e.g. idte  */
272 
#define INSTR_RRF_U0FF   4, { F_24,U4_16,F_28,0,0,0 }          /* e.g. fixr  */
273 
#define INSTR_RRF_U0RF   4, { R_24,U4_16,F_28,0,0,0 }          /* e.g. cfebr */
274 
#define INSTR_RRF_UUFF   4, { F_24,U4_16,F_28,U4_20,0,0 }      /* e.g. fidtr */
275 
#define INSTR_RRF_0UFF   4, { F_24,F_28,U4_20,0,0,0 }          /* e.g. ldetr */
276 
#define INSTR_RRF_FFFU   4, { F_24,F_16,F_28,U4_20,0,0 }       /* e.g. qadtr */
277 
#define INSTR_RRF_M0RR   4, { R_24,R_28,M_16,0,0,0 }           /* e.g. sske  */
278 
#define INSTR_RRF_U0RR   4, { R_24,R_28,U4_16,0,0,0 }          /* e.g. clrt  */
279 
#define INSTR_RRF_00RR   4, { R_24,R_28,0,0,0,0 }              /* e.g. clrtne */
280 
#define INSTR_RR_0R      2, { R_12, 0,0,0,0,0 }                /* e.g. br    */
281 
#define INSTR_RR_FF      2, { F_8,F_12,0,0,0,0 }               /* e.g. adr   */
282 
#define INSTR_RR_R0      2, { R_8, 0,0,0,0,0 }                 /* e.g. spm   */
283 
#define INSTR_RR_RR      2, { R_8,R_12,0,0,0,0 }               /* e.g. lr    */
284 
#define INSTR_RR_U0      2, { U8_8, 0,0,0,0,0 }                /* e.g. svc   */
285 
#define INSTR_RR_UR      2, { U4_8,R_12,0,0,0,0 }              /* e.g. bcr   */
286 
#define INSTR_RRR_F0FF   4, { F_24,F_28,F_16,0,0,0 }           /* e.g. ddtr  */
287 
#define INSTR_RRS_RRRDU  6, { R_8,R_12,U4_32,D_20,B_16 }       /* e.g. crb   */
288 
#define INSTR_RRS_RRRD0  6, { R_8,R_12,D_20,B_16,0 }           /* e.g. crbne */
289 
#define INSTR_RSE_RRRD   6, { R_8,R_12,D_20,B_16,0,0 }         /* e.g. lmh   */
290 
#define INSTR_RSE_CCRD   6, { C_8,C_12,D_20,B_16,0,0 }         /* e.g. lmh   */
291 
#define INSTR_RSE_RURD   6, { R_8,U4_12,D_20,B_16,0,0 }        /* e.g. icmh  */
292 
#define INSTR_RSL_R0RD   6, { D_20,L4_8,B_16,0,0,0 }           /* e.g. tp    */
293 
#define INSTR_RSI_RRP    4, { R_8,R_12,J16_16,0,0,0 }          /* e.g. brxh  */
294 
#define INSTR_RSY_RRRD   6, { R_8,R_12,D20_20,B_16,0,0 }       /* e.g. stmy  */
295 
#define INSTR_RSY_RURD   6, { R_8,U4_12,D20_20,B_16,0,0 }      /* e.g. icmh  */
296 
#define INSTR_RSY_AARD   6, { A_8,A_12,D20_20,B_16,0,0 }       /* e.g. lamy  */
297 
#define INSTR_RSY_CCRD   6, { C_8,C_12,D20_20,B_16,0,0 }       /* e.g. lamy  */
298 
#define INSTR_RS_AARD    4, { A_8,A_12,D_20,B_16,0,0 }         /* e.g. lam   */
299 
#define INSTR_RS_CCRD    4, { C_8,C_12,D_20,B_16,0,0 }         /* e.g. lctl  */
300 
#define INSTR_RS_R0RD    4, { R_8,D_20,B_16,0,0,0 }            /* e.g. sll   */
301 
#define INSTR_RS_RRRD    4, { R_8,R_12,D_20,B_16,0,0 }         /* e.g. cs    */
302 
#define INSTR_RS_RURD    4, { R_8,U4_12,D_20,B_16,0,0 }        /* e.g. icm   */
303 
#define INSTR_RXE_FRRD   6, { F_8,D_20,X_12,B_16,0,0 }         /* e.g. axbr  */
304 
#define INSTR_RXE_RRRD   6, { R_8,D_20,X_12,B_16,0,0 }         /* e.g. lg    */
305 
#define INSTR_RXF_FRRDF  6, { F_32,F_8,D_20,X_12,B_16,0 }      /* e.g. madb  */
306 
#define INSTR_RXF_RRRDR  6, { R_32,R_8,D_20,X_12,B_16,0 }      /* e.g. .insn */
307 
#define INSTR_RXY_RRRD   6, { R_8,D20_20,X_12,B_16,0,0 }       /* e.g. ly    */
308 
#define INSTR_RXY_FRRD   6, { F_8,D20_20,X_12,B_16,0,0 }       /* e.g. ley   */
309 
#define INSTR_RXY_URRD   6, { U4_8,D20_20,X_12,B_16,0,0 }      /* e.g. pfd   */
310 
#define INSTR_RX_0RRD    4, { D_20,X_12,B_16,0,0,0 }           /* e.g. be    */
311 
#define INSTR_RX_FRRD    4, { F_8,D_20,X_12,B_16,0,0 }         /* e.g. ae    */
312 
#define INSTR_RX_RRRD    4, { R_8,D_20,X_12,B_16,0,0 }         /* e.g. l     */
313 
#define INSTR_RX_URRD    4, { U4_8,D_20,X_12,B_16,0,0 }        /* e.g. bc    */
314 
#define INSTR_SI_URD     4, { D_20,B_16,U8_8,0,0,0 }           /* e.g. cli   */
315 
#define INSTR_SIY_URD    6, { D20_20,B_16,U8_8,0,0,0 }         /* e.g. tmy   */
316 
#define INSTR_SIY_IRD    6, { D20_20,B_16,I8_8,0,0,0 }         /* e.g. asi   */
317 
#define INSTR_SIL_RDI    6, { D_20,B_16,I16_32,0,0,0 }         /* e.g. chhsi */
318 
#define INSTR_SIL_RDU    6, { D_20,B_16,U16_32,0,0,0 }         /* e.g. clfhsi */
319 
#define INSTR_SSE_RDRD   6, { D_20,B_16,D_36,B_32,0,0 }        /* e.g. mvsdk */
320 
#define INSTR_SS_L0RDRD  6, { D_20,L8_8,B_16,D_36,B_32,0     } /* e.g. mvc   */
321 
#define INSTR_SS_L2RDRD  6, { D_20,B_16,D_36,L8_8,B_32,0     } /* e.g. pka   */
322 
#define INSTR_SS_LIRDRD  6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp   */
323 
#define INSTR_SS_LLRDRD  6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack  */
324 
#define INSTR_SS_RRRDRD  6, { D_20,R_8,B_16,D_36,B_32,R_12 }   /* e.g. mvck  */
325 
#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 }   /* e.g. plo   */
326 
#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 }   /* e.g. lmd   */
327 
#define INSTR_SSF_RRDRD  6, { D_20,B_16,D_36,B_32,R_8,0 }      /* e.g. mvcos */
328 
#define INSTR_S_00       4, { 0,0,0,0,0,0 }                    /* e.g. hsch  */
329 
#define INSTR_S_RD       4, { D_20,B_16,0,0,0,0 }              /* e.g. lpsw  */
330 
 
331 
#define MASK_E           { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
332 
#define MASK_RIE_RRP     { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
333 
#define MASK_RIE_RRPU    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
334 
#define MASK_RIE_RRP0    { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
335 
#define MASK_RIE_RUPI    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
336 
#define MASK_RIE_R0PI    { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
337 
#define MASK_RIE_RUPU    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
338 
#define MASK_RIE_R0PU    { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
339 
#define MASK_RIE_R0IU    { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff }
340 
#define MASK_RIE_R0I0    { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
341 
#define MASK_RIE_R0UU    { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff }
342 
#define MASK_RIE_R0U0    { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
343 
#define MASK_RIE_RRUUU   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
344 
#define MASK_RIL_0P      { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
345 
#define MASK_RIL_RP      { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
346 
#define MASK_RIL_UP      { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
347 
#define MASK_RIL_RI      { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
348 
#define MASK_RIL_RU      { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
349 
#define MASK_RI_0P       { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
350 
#define MASK_RI_RI       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
351 
#define MASK_RI_RP       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
352 
#define MASK_RI_RU       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
353 
#define MASK_RI_UP       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
354 
#define MASK_RIS_RURDI   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
355 
#define MASK_RIS_R0RDI   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff }
356 
#define MASK_RIS_RURDU   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
357 
#define MASK_RIS_R0RDU   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff }
358 
#define MASK_RRE_00      { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
359 
#define MASK_RRE_0R      { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 }
360 
#define MASK_RRE_AA      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
361 
#define MASK_RRE_AR      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
362 
#define MASK_RRE_F0      { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
363 
#define MASK_RRE_FF      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
364 
#define MASK_RRE_R0      { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
365 
#define MASK_RRE_RA      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
366 
#define MASK_RRE_RF      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
367 
#define MASK_RRE_RR      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
368 
#define MASK_RRE_FR      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
369 
#define MASK_RRE_RR_OPT  { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
370 
#define MASK_RRF_F0FF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
371 
#define MASK_RRF_F0FF2   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
372 
#define MASK_RRF_F0FR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
373 
#define MASK_RRF_FUFF    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
374 
#define MASK_RRF_RURR    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
375 
#define MASK_RRF_R0RR    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
376 
#define MASK_RRF_U0FF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
377 
#define MASK_RRF_U0RF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
378 
#define MASK_RRF_UUFF    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
379 
#define MASK_RRF_0UFF    { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 }
380 
#define MASK_RRF_FFFU    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
381 
#define MASK_RRF_M0RR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
382 
#define MASK_RRF_U0RR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
383 
#define MASK_RRF_00RR    { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
384 
#define MASK_RR_0R       { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
385 
#define MASK_RR_FF       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
386 
#define MASK_RR_R0       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
387 
#define MASK_RR_RR       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
388 
#define MASK_RR_U0       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
389 
#define MASK_RR_UR       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
390 
#define MASK_RRR_F0FF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
391 
#define MASK_RRS_RRRDU   { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
392 
#define MASK_RRS_RRRD0   { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
393 
#define MASK_RSE_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
394 
#define MASK_RSE_CCRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
395 
#define MASK_RSE_RURD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
396 
#define MASK_RSL_R0RD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
397 
#define MASK_RSI_RRP     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
398 
#define MASK_RS_AARD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
399 
#define MASK_RS_CCRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
400 
#define MASK_RS_R0RD     { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
401 
#define MASK_RS_RRRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
402 
#define MASK_RS_RURD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
403 
#define MASK_RSY_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
404 
#define MASK_RSY_RURD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
405 
#define MASK_RSY_AARD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
406 
#define MASK_RSY_CCRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
407 
#define MASK_RXE_FRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
408 
#define MASK_RXE_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
409 
#define MASK_RXF_FRRDF   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
410 
#define MASK_RXF_RRRDR   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
411 
#define MASK_RXY_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
412 
#define MASK_RXY_FRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
413 
#define MASK_RXY_URRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
414 
#define MASK_RX_0RRD     { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
415 
#define MASK_RX_FRRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
416 
#define MASK_RX_RRRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
417 
#define MASK_RX_URRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
418 
#define MASK_SI_URD      { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
419 
#define MASK_SIY_URD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
420 
#define MASK_SIY_IRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
421 
#define MASK_SIL_RDI     { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
422 
#define MASK_SIL_RDU     { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
423 
#define MASK_SSE_RDRD    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
424 
#define MASK_SS_L0RDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
425 
#define MASK_SS_L2RDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
426 
#define MASK_SS_LIRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
427 
#define MASK_SS_LLRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
428 
#define MASK_SS_RRRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
429 
#define MASK_SS_RRRDRD2  { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
430 
#define MASK_SS_RRRDRD3  { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
431 
#define MASK_SSF_RRDRD   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
432 
#define MASK_S_00        { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
433 
#define MASK_S_RD        { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
434 
 
435 
 
436 
/* The opcode formats table (blueprints for .insn pseudo mnemonic).  */
437 
 
438 
const struct s390_opcode s390_opformats[] =
439 
  {
440 
  { "e",        OP8(0x00LL),    MASK_E,         INSTR_E,        3, 0 },
441 
  { "ri",       OP8(0x00LL),    MASK_RI_RI,     INSTR_RI_RI,    3, 0 },
442 
  { "rie",      OP8(0x00LL),    MASK_RIE_RRP,   INSTR_RIE_RRP,  3, 0 },
443 
  { "ril",      OP8(0x00LL),    MASK_RIL_RP,    INSTR_RIL_RP,   3, 0 },
444 
  { "rilu",     OP8(0x00LL),    MASK_RIL_RU,    INSTR_RIL_RU,   3, 0 },
445 
  { "ris",      OP8(0x00LL),    MASK_RIS_RURDI, INSTR_RIS_RURDI,3, 6 },
446 
  { "rr",       OP8(0x00LL),    MASK_RR_RR,     INSTR_RR_RR,    3, 0 },
447 
  { "rre",      OP8(0x00LL),    MASK_RRE_RR,    INSTR_RRE_RR,   3, 0 },
448 
  { "rrf",      OP8(0x00LL),    MASK_RRF_RURR,  INSTR_RRF_RURR, 3, 0 },
449 
  { "rrs",      OP8(0x00LL),    MASK_RRS_RRRDU, INSTR_RRS_RRRDU,3, 6 },
450 
  { "rs",       OP8(0x00LL),    MASK_RS_RRRD,   INSTR_RS_RRRD,  3, 0 },
451 
  { "rse",      OP8(0x00LL),    MASK_RSE_RRRD,  INSTR_RSE_RRRD, 3, 0 },
452 
  { "rsi",      OP8(0x00LL),    MASK_RSI_RRP,   INSTR_RSI_RRP,  3, 0 },
453 
  { "rsy",      OP8(0x00LL),    MASK_RSY_RRRD,  INSTR_RSY_RRRD, 3, 3 },
454 
  { "rx",       OP8(0x00LL),    MASK_RX_RRRD,   INSTR_RX_RRRD,  3, 0 },
455 
  { "rxe",      OP8(0x00LL),    MASK_RXE_RRRD,  INSTR_RXE_RRRD, 3, 0 },
456 
  { "rxf",      OP8(0x00LL),    MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 },
457 
  { "rxy",      OP8(0x00LL),    MASK_RXY_RRRD,  INSTR_RXY_RRRD, 3, 3 },
458 
  { "s",        OP8(0x00LL),    MASK_S_RD,      INSTR_S_RD,     3, 0 },
459 
  { "si",       OP8(0x00LL),    MASK_SI_URD,    INSTR_SI_URD,   3, 0 },
460 
  { "siy",      OP8(0x00LL),    MASK_SIY_URD,   INSTR_SIY_URD,  3, 3 },
461 
  { "sil",      OP8(0x00LL),    MASK_SIL_RDI,   INSTR_SIL_RDI,  3, 6 },
462 
  { "ss",       OP8(0x00LL),    MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 },
463 
  { "sse",      OP8(0x00LL),    MASK_SSE_RDRD,  INSTR_SSE_RDRD, 3, 0 },
464 
  { "ssf",      OP8(0x00LL),    MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 },
465 
};
466 
 
467 
const int s390_num_opformats =
468 
  sizeof (s390_opformats) / sizeof (s390_opformats[0]);
469 
 
470 
#include "s390-opc.tab"

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.