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@section Relocations
2
BFD maintains relocations in much the same way it maintains
3
symbols: they are left alone until required, then read in
4
en-masse and translated into an internal form.  A common
5
routine @code{bfd_perform_relocation} acts upon the
6
canonical form to do the fixup.
7
 
8
Relocations are maintained on a per section basis,
9
while symbols are maintained on a per BFD basis.
10
 
11
All that a back end has to do to fit the BFD interface is to create
12
a @code{struct reloc_cache_entry} for each relocation
13
in a particular section, and fill in the right bits of the structures.
14
 
15
@menu
16
* typedef arelent::
17
* howto manager::
18
@end menu
19
 
20
 
21
@node typedef arelent, howto manager, Relocations, Relocations
22
@subsection typedef arelent
23
This is the structure of a relocation entry:
24
 
25
 
26
@example
27
 
28
typedef enum bfd_reloc_status
29
@{
30
  /* No errors detected.  */
31
  bfd_reloc_ok,
32
 
33
  /* The relocation was performed, but there was an overflow.  */
34
  bfd_reloc_overflow,
35
 
36
  /* The address to relocate was not within the section supplied.  */
37
  bfd_reloc_outofrange,
38
 
39
  /* Used by special functions.  */
40
  bfd_reloc_continue,
41
 
42
  /* Unsupported relocation size requested.  */
43
  bfd_reloc_notsupported,
44
 
45
  /* Unused.  */
46
  bfd_reloc_other,
47
 
48
  /* The symbol to relocate against was undefined.  */
49
  bfd_reloc_undefined,
50
 
51
  /* The relocation was performed, but may not be ok - presently
52
     generated only when linking i960 coff files with i960 b.out
53
     symbols.  If this type is returned, the error_message argument
54
     to bfd_perform_relocation will be set.  */
55
  bfd_reloc_dangerous
56
 @}
57
 bfd_reloc_status_type;
58
 
59
 
60
typedef struct reloc_cache_entry
61
@{
62
  /* A pointer into the canonical table of pointers.  */
63
  struct bfd_symbol **sym_ptr_ptr;
64
 
65
  /* offset in section.  */
66
  bfd_size_type address;
67
 
68
  /* addend for relocation value.  */
69
  bfd_vma addend;
70
 
71
  /* Pointer to how to perform the required relocation.  */
72
  reloc_howto_type *howto;
73
 
74
@}
75
arelent;
76
 
77
@end example
78
@strong{Description}@*
79
Here is a description of each of the fields within an @code{arelent}:
80
 
81
@itemize @bullet
82
 
83
@item
84
@code{sym_ptr_ptr}
85
@end itemize
86
The symbol table pointer points to a pointer to the symbol
87
associated with the relocation request.  It is the pointer
88
into the table returned by the back end's
89
@code{canonicalize_symtab} action. @xref{Symbols}. The symbol is
90
referenced through a pointer to a pointer so that tools like
91
the linker can fix up all the symbols of the same name by
92
modifying only one pointer. The relocation routine looks in
93
the symbol and uses the base of the section the symbol is
94
attached to and the value of the symbol as the initial
95
relocation offset. If the symbol pointer is zero, then the
96
section provided is looked up.
97
 
98
@itemize @bullet
99
 
100
@item
101
@code{address}
102
@end itemize
103
The @code{address} field gives the offset in bytes from the base of
104
the section data which owns the relocation record to the first
105
byte of relocatable information. The actual data relocated
106
will be relative to this point; for example, a relocation
107
type which modifies the bottom two bytes of a four byte word
108
would not touch the first byte pointed to in a big endian
109
world.
110
 
111
@itemize @bullet
112
 
113
@item
114
@code{addend}
115
@end itemize
116
The @code{addend} is a value provided by the back end to be added (!)
117
to the relocation offset. Its interpretation is dependent upon
118
the howto. For example, on the 68k the code:
119
 
120
@example
121
        char foo[];
122
        main()
123
                @{
124
                return foo[0x12345678];
125
                @}
126
@end example
127
 
128
Could be compiled into:
129
 
130
@example
131
        linkw fp,#-4
132
        moveb @@#12345678,d0
133
        extbl d0
134
        unlk fp
135
        rts
136
@end example
137
 
138
This could create a reloc pointing to @code{foo}, but leave the
139
offset in the data, something like:
140
 
141
@example
142
RELOCATION RECORDS FOR [.text]:
143
offset   type      value
144
00000006 32        _foo
145
 
146
00000000 4e56 fffc          ; linkw fp,#-4
147
00000004 1039 1234 5678     ; moveb @@#12345678,d0
148
0000000a 49c0               ; extbl d0
149
0000000c 4e5e               ; unlk fp
150
0000000e 4e75               ; rts
151
@end example
152
 
153
Using coff and an 88k, some instructions don't have enough
154
space in them to represent the full address range, and
155
pointers have to be loaded in two parts. So you'd get something like:
156
 
157
@example
158
        or.u     r13,r0,hi16(_foo+0x12345678)
159
        ld.b     r2,r13,lo16(_foo+0x12345678)
160
        jmp      r1
161
@end example
162
 
163
This should create two relocs, both pointing to @code{_foo}, and with
164
0x12340000 in their addend field. The data would consist of:
165
 
166
@example
167
RELOCATION RECORDS FOR [.text]:
168
offset   type      value
169
00000002 HVRT16    _foo+0x12340000
170
00000006 LVRT16    _foo+0x12340000
171
 
172
00000000 5da05678           ; or.u r13,r0,0x5678
173
00000004 1c4d5678           ; ld.b r2,r13,0x5678
174
00000008 f400c001           ; jmp r1
175
@end example
176
 
177
The relocation routine digs out the value from the data, adds
178
it to the addend to get the original offset, and then adds the
179
value of @code{_foo}. Note that all 32 bits have to be kept around
180
somewhere, to cope with carry from bit 15 to bit 16.
181
 
182
One further example is the sparc and the a.out format. The
183
sparc has a similar problem to the 88k, in that some
184
instructions don't have room for an entire offset, but on the
185
sparc the parts are created in odd sized lumps. The designers of
186
the a.out format chose to not use the data within the section
187
for storing part of the offset; all the offset is kept within
188
the reloc. Anything in the data should be ignored.
189
 
190
@example
191
        save %sp,-112,%sp
192
        sethi %hi(_foo+0x12345678),%g2
193
        ldsb [%g2+%lo(_foo+0x12345678)],%i0
194
        ret
195
        restore
196
@end example
197
 
198
Both relocs contain a pointer to @code{foo}, and the offsets
199
contain junk.
200
 
201
@example
202
RELOCATION RECORDS FOR [.text]:
203
offset   type      value
204
00000004 HI22      _foo+0x12345678
205
00000008 LO10      _foo+0x12345678
206
 
207
00000000 9de3bf90     ; save %sp,-112,%sp
208
00000004 05000000     ; sethi %hi(_foo+0),%g2
209
00000008 f048a000     ; ldsb [%g2+%lo(_foo+0)],%i0
210
0000000c 81c7e008     ; ret
211
00000010 81e80000     ; restore
212
@end example
213
 
214
@itemize @bullet
215
 
216
@item
217
@code{howto}
218
@end itemize
219
The @code{howto} field can be imagined as a
220
relocation instruction. It is a pointer to a structure which
221
contains information on what to do with all of the other
222
information in the reloc record and data section. A back end
223
would normally have a relocation instruction set and turn
224
relocations into pointers to the correct structure on input -
225
but it would be possible to create each howto field on demand.
226
 
227
@subsubsection @code{enum complain_overflow}
228
Indicates what sort of overflow checking should be done when
229
performing a relocation.
230
 
231
 
232
@example
233
 
234
enum complain_overflow
235
@{
236
  /* Do not complain on overflow.  */
237
  complain_overflow_dont,
238
 
239
  /* Complain if the value overflows when considered as a signed
240
     number one bit larger than the field.  ie. A bitfield of N bits
241
     is allowed to represent -2**n to 2**n-1.  */
242
  complain_overflow_bitfield,
243
 
244
  /* Complain if the value overflows when considered as a signed
245
     number.  */
246
  complain_overflow_signed,
247
 
248
  /* Complain if the value overflows when considered as an
249
     unsigned number.  */
250
  complain_overflow_unsigned
251
@};
252
@end example
253
@subsubsection @code{reloc_howto_type}
254
The @code{reloc_howto_type} is a structure which contains all the
255
information that libbfd needs to know to tie up a back end's data.
256
 
257
 
258
@example
259
struct bfd_symbol;             /* Forward declaration.  */
260
 
261
struct reloc_howto_struct
262
@{
263
  /*  The type field has mainly a documentary use - the back end can
264
      do what it wants with it, though normally the back end's
265
      external idea of what a reloc number is stored
266
      in this field.  For example, a PC relative word relocation
267
      in a coff environment has the type 023 - because that's
268
      what the outside world calls a R_PCRWORD reloc.  */
269
  unsigned int type;
270
 
271
  /*  The value the final relocation is shifted right by.  This drops
272
      unwanted data from the relocation.  */
273
  unsigned int rightshift;
274
 
275
  /*  The size of the item to be relocated.  This is *not* a
276
      power-of-two measure.  To get the number of bytes operated
277
      on by a type of relocation, use bfd_get_reloc_size.  */
278
  int size;
279
 
280
  /*  The number of bits in the item to be relocated.  This is used
281
      when doing overflow checking.  */
282
  unsigned int bitsize;
283
 
284
  /*  Notes that the relocation is relative to the location in the
285
      data section of the addend.  The relocation function will
286
      subtract from the relocation value the address of the location
287
      being relocated.  */
288
  bfd_boolean pc_relative;
289
 
290
  /*  The bit position of the reloc value in the destination.
291
      The relocated value is left shifted by this amount.  */
292
  unsigned int bitpos;
293
 
294
  /* What type of overflow error should be checked for when
295
     relocating.  */
296
  enum complain_overflow complain_on_overflow;
297
 
298
  /* If this field is non null, then the supplied function is
299
     called rather than the normal function.  This allows really
300
     strange relocation methods to be accommodated (e.g., i960 callj
301
     instructions).  */
302
  bfd_reloc_status_type (*special_function)
303
    (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
304
     bfd *, char **);
305
 
306
  /* The textual name of the relocation type.  */
307
  char *name;
308
 
309
  /* Some formats record a relocation addend in the section contents
310
     rather than with the relocation.  For ELF formats this is the
311
     distinction between USE_REL and USE_RELA (though the code checks
312
     for USE_REL == 1/0).  The value of this field is TRUE if the
313
     addend is recorded with the section contents; when performing a
314
     partial link (ld -r) the section contents (the data) will be
315
     modified.  The value of this field is FALSE if addends are
316
     recorded with the relocation (in arelent.addend); when performing
317
     a partial link the relocation will be modified.
318
     All relocations for all ELF USE_RELA targets should set this field
319
     to FALSE (values of TRUE should be looked on with suspicion).
320
     However, the converse is not true: not all relocations of all ELF
321
     USE_REL targets set this field to TRUE.  Why this is so is peculiar
322
     to each particular target.  For relocs that aren't used in partial
323
     links (e.g. GOT stuff) it doesn't matter what this is set to.  */
324
  bfd_boolean partial_inplace;
325
 
326
  /* src_mask selects the part of the instruction (or data) to be used
327
     in the relocation sum.  If the target relocations don't have an
328
     addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
329
     dst_mask to extract the addend from the section contents.  If
330
     relocations do have an addend in the reloc, eg. ELF USE_RELA, this
331
     field should be zero.  Non-zero values for ELF USE_RELA targets are
332
     bogus as in those cases the value in the dst_mask part of the
333
     section contents should be treated as garbage.  */
334
  bfd_vma src_mask;
335
 
336
  /* dst_mask selects which parts of the instruction (or data) are
337
     replaced with a relocated value.  */
338
  bfd_vma dst_mask;
339
 
340
  /* When some formats create PC relative instructions, they leave
341
     the value of the pc of the place being relocated in the offset
342
     slot of the instruction, so that a PC relative relocation can
343
     be made just by adding in an ordinary offset (e.g., sun3 a.out).
344
     Some formats leave the displacement part of an instruction
345
     empty (e.g., m88k bcs); this flag signals the fact.  */
346
  bfd_boolean pcrel_offset;
347
@};
348
 
349
@end example
350
@findex The HOWTO Macro
351
@subsubsection @code{The HOWTO Macro}
352
@strong{Description}@*
353
The HOWTO define is horrible and will go away.
354
@example
355
#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
356
  @{ (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC @}
357
@end example
358
 
359
@strong{Description}@*
360
And will be replaced with the totally magic way. But for the
361
moment, we are compatible, so do it this way.
362
@example
363
#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
364
  HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
365
         NAME, FALSE, 0, 0, IN)
366
 
367
@end example
368
 
369
@strong{Description}@*
370
This is used to fill in an empty howto entry in an array.
371
@example
372
#define EMPTY_HOWTO(C) \
373
  HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
374
         NULL, FALSE, 0, 0, FALSE)
375
 
376
@end example
377
 
378
@strong{Description}@*
379
Helper routine to turn a symbol into a relocation value.
380
@example
381
#define HOWTO_PREPARE(relocation, symbol)               \
382
  @{                                                     \
383
    if (symbol != NULL)                                 \
384
      @{                                                 \
385
        if (bfd_is_com_section (symbol->section))       \
386
          @{                                             \
387
            relocation = 0;                             \
388
          @}                                             \
389
        else                                            \
390
          @{                                             \
391
            relocation = symbol->value;                 \
392
          @}                                             \
393
      @}                                                 \
394
  @}
395
 
396
@end example
397
 
398
@findex bfd_get_reloc_size
399
@subsubsection @code{bfd_get_reloc_size}
400
@strong{Synopsis}
401
@example
402
unsigned int bfd_get_reloc_size (reloc_howto_type *);
403
@end example
404
@strong{Description}@*
405
For a reloc_howto_type that operates on a fixed number of bytes,
406
this returns the number of bytes operated on.
407
 
408
@findex arelent_chain
409
@subsubsection @code{arelent_chain}
410
@strong{Description}@*
411
How relocs are tied together in an @code{asection}:
412
@example
413
typedef struct relent_chain
414
@{
415
  arelent relent;
416
  struct relent_chain *next;
417
@}
418
arelent_chain;
419
 
420
@end example
421
 
422
@findex bfd_check_overflow
423
@subsubsection @code{bfd_check_overflow}
424
@strong{Synopsis}
425
@example
426
bfd_reloc_status_type bfd_check_overflow
427
   (enum complain_overflow how,
428
    unsigned int bitsize,
429
    unsigned int rightshift,
430
    unsigned int addrsize,
431
    bfd_vma relocation);
432
@end example
433
@strong{Description}@*
434
Perform overflow checking on @var{relocation} which has
435
@var{bitsize} significant bits and will be shifted right by
436
@var{rightshift} bits, on a machine with addresses containing
437
@var{addrsize} significant bits.  The result is either of
438
@code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
439
 
440
@findex bfd_perform_relocation
441
@subsubsection @code{bfd_perform_relocation}
442
@strong{Synopsis}
443
@example
444
bfd_reloc_status_type bfd_perform_relocation
445
   (bfd *abfd,
446
    arelent *reloc_entry,
447
    void *data,
448
    asection *input_section,
449
    bfd *output_bfd,
450
    char **error_message);
451
@end example
452
@strong{Description}@*
453
If @var{output_bfd} is supplied to this function, the
454
generated image will be relocatable; the relocations are
455
copied to the output file after they have been changed to
456
reflect the new state of the world. There are two ways of
457
reflecting the results of partial linkage in an output file:
458
by modifying the output data in place, and by modifying the
459
relocation record.  Some native formats (e.g., basic a.out and
460
basic coff) have no way of specifying an addend in the
461
relocation type, so the addend has to go in the output data.
462
This is no big deal since in these formats the output data
463
slot will always be big enough for the addend. Complex reloc
464
types with addends were invented to solve just this problem.
465
The @var{error_message} argument is set to an error message if
466
this return @code{bfd_reloc_dangerous}.
467
 
468
@findex bfd_install_relocation
469
@subsubsection @code{bfd_install_relocation}
470
@strong{Synopsis}
471
@example
472
bfd_reloc_status_type bfd_install_relocation
473
   (bfd *abfd,
474
    arelent *reloc_entry,
475
    void *data, bfd_vma data_start,
476
    asection *input_section,
477
    char **error_message);
478
@end example
479
@strong{Description}@*
480
This looks remarkably like @code{bfd_perform_relocation}, except it
481
does not expect that the section contents have been filled in.
482
I.e., it's suitable for use when creating, rather than applying
483
a relocation.
484
 
485
For now, this function should be considered reserved for the
486
assembler.
487
 
488
 
489
@node howto manager,  , typedef arelent, Relocations
490
@subsection The howto manager
491
When an application wants to create a relocation, but doesn't
492
know what the target machine might call it, it can find out by
493
using this bit of code.
494
 
495
@findex bfd_reloc_code_type
496
@subsubsection @code{bfd_reloc_code_type}
497
@strong{Description}@*
498
The insides of a reloc code.  The idea is that, eventually, there
499
will be one enumerator for every type of relocation we ever do.
500
Pass one of these values to @code{bfd_reloc_type_lookup}, and it'll
501
return a howto pointer.
502
 
503
This does mean that the application must determine the correct
504
enumerator value; you can't get a howto pointer from a random set
505
of attributes.
506
 
507
Here are the possible values for @code{enum bfd_reloc_code_real}:
508
 
509
@deffn {} BFD_RELOC_64
510
@deffnx {} BFD_RELOC_32
511
@deffnx {} BFD_RELOC_26
512
@deffnx {} BFD_RELOC_24
513
@deffnx {} BFD_RELOC_16
514
@deffnx {} BFD_RELOC_14
515
@deffnx {} BFD_RELOC_8
516
Basic absolute relocations of N bits.
517
@end deffn
518
@deffn {} BFD_RELOC_64_PCREL
519
@deffnx {} BFD_RELOC_32_PCREL
520
@deffnx {} BFD_RELOC_24_PCREL
521
@deffnx {} BFD_RELOC_16_PCREL
522
@deffnx {} BFD_RELOC_12_PCREL
523
@deffnx {} BFD_RELOC_8_PCREL
524
PC-relative relocations.  Sometimes these are relative to the address
525
of the relocation itself; sometimes they are relative to the start of
526
the section containing the relocation.  It depends on the specific target.
527
 
528
The 24-bit relocation is used in some Intel 960 configurations.
529
@end deffn
530
@deffn {} BFD_RELOC_32_SECREL
531
Section relative relocations.  Some targets need this for DWARF2.
532
@end deffn
533
@deffn {} BFD_RELOC_32_GOT_PCREL
534
@deffnx {} BFD_RELOC_16_GOT_PCREL
535
@deffnx {} BFD_RELOC_8_GOT_PCREL
536
@deffnx {} BFD_RELOC_32_GOTOFF
537
@deffnx {} BFD_RELOC_16_GOTOFF
538
@deffnx {} BFD_RELOC_LO16_GOTOFF
539
@deffnx {} BFD_RELOC_HI16_GOTOFF
540
@deffnx {} BFD_RELOC_HI16_S_GOTOFF
541
@deffnx {} BFD_RELOC_8_GOTOFF
542
@deffnx {} BFD_RELOC_64_PLT_PCREL
543
@deffnx {} BFD_RELOC_32_PLT_PCREL
544
@deffnx {} BFD_RELOC_24_PLT_PCREL
545
@deffnx {} BFD_RELOC_16_PLT_PCREL
546
@deffnx {} BFD_RELOC_8_PLT_PCREL
547
@deffnx {} BFD_RELOC_64_PLTOFF
548
@deffnx {} BFD_RELOC_32_PLTOFF
549
@deffnx {} BFD_RELOC_16_PLTOFF
550
@deffnx {} BFD_RELOC_LO16_PLTOFF
551
@deffnx {} BFD_RELOC_HI16_PLTOFF
552
@deffnx {} BFD_RELOC_HI16_S_PLTOFF
553
@deffnx {} BFD_RELOC_8_PLTOFF
554
For ELF.
555
@end deffn
556
@deffn {} BFD_RELOC_68K_GLOB_DAT
557
@deffnx {} BFD_RELOC_68K_JMP_SLOT
558
@deffnx {} BFD_RELOC_68K_RELATIVE
559
@deffnx {} BFD_RELOC_68K_TLS_GD32
560
@deffnx {} BFD_RELOC_68K_TLS_GD16
561
@deffnx {} BFD_RELOC_68K_TLS_GD8
562
@deffnx {} BFD_RELOC_68K_TLS_LDM32
563
@deffnx {} BFD_RELOC_68K_TLS_LDM16
564
@deffnx {} BFD_RELOC_68K_TLS_LDM8
565
@deffnx {} BFD_RELOC_68K_TLS_LDO32
566
@deffnx {} BFD_RELOC_68K_TLS_LDO16
567
@deffnx {} BFD_RELOC_68K_TLS_LDO8
568
@deffnx {} BFD_RELOC_68K_TLS_IE32
569
@deffnx {} BFD_RELOC_68K_TLS_IE16
570
@deffnx {} BFD_RELOC_68K_TLS_IE8
571
@deffnx {} BFD_RELOC_68K_TLS_LE32
572
@deffnx {} BFD_RELOC_68K_TLS_LE16
573
@deffnx {} BFD_RELOC_68K_TLS_LE8
574
Relocations used by 68K ELF.
575
@end deffn
576
@deffn {} BFD_RELOC_32_BASEREL
577
@deffnx {} BFD_RELOC_16_BASEREL
578
@deffnx {} BFD_RELOC_LO16_BASEREL
579
@deffnx {} BFD_RELOC_HI16_BASEREL
580
@deffnx {} BFD_RELOC_HI16_S_BASEREL
581
@deffnx {} BFD_RELOC_8_BASEREL
582
@deffnx {} BFD_RELOC_RVA
583
Linkage-table relative.
584
@end deffn
585
@deffn {} BFD_RELOC_8_FFnn
586
Absolute 8-bit relocation, but used to form an address like 0xFFnn.
587
@end deffn
588
@deffn {} BFD_RELOC_32_PCREL_S2
589
@deffnx {} BFD_RELOC_16_PCREL_S2
590
@deffnx {} BFD_RELOC_23_PCREL_S2
591
These PC-relative relocations are stored as word displacements --
592
i.e., byte displacements shifted right two bits.  The 30-bit word
593
displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
594
SPARC.  (SPARC tools generally refer to this as <<WDISP30>>.)  The
595
signed 16-bit displacement is used on the MIPS, and the 23-bit
596
displacement is used on the Alpha.
597
@end deffn
598
@deffn {} BFD_RELOC_HI22
599
@deffnx {} BFD_RELOC_LO10
600
High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
601
the target word.  These are used on the SPARC.
602
@end deffn
603
@deffn {} BFD_RELOC_GPREL16
604
@deffnx {} BFD_RELOC_GPREL32
605
For systems that allocate a Global Pointer register, these are
606
displacements off that register.  These relocation types are
607
handled specially, because the value the register will have is
608
decided relatively late.
609
@end deffn
610
@deffn {} BFD_RELOC_I960_CALLJ
611
Reloc types used for i960/b.out.
612
@end deffn
613
@deffn {} BFD_RELOC_NONE
614
@deffnx {} BFD_RELOC_SPARC_WDISP22
615
@deffnx {} BFD_RELOC_SPARC22
616
@deffnx {} BFD_RELOC_SPARC13
617
@deffnx {} BFD_RELOC_SPARC_GOT10
618
@deffnx {} BFD_RELOC_SPARC_GOT13
619
@deffnx {} BFD_RELOC_SPARC_GOT22
620
@deffnx {} BFD_RELOC_SPARC_PC10
621
@deffnx {} BFD_RELOC_SPARC_PC22
622
@deffnx {} BFD_RELOC_SPARC_WPLT30
623
@deffnx {} BFD_RELOC_SPARC_COPY
624
@deffnx {} BFD_RELOC_SPARC_GLOB_DAT
625
@deffnx {} BFD_RELOC_SPARC_JMP_SLOT
626
@deffnx {} BFD_RELOC_SPARC_RELATIVE
627
@deffnx {} BFD_RELOC_SPARC_UA16
628
@deffnx {} BFD_RELOC_SPARC_UA32
629
@deffnx {} BFD_RELOC_SPARC_UA64
630
@deffnx {} BFD_RELOC_SPARC_GOTDATA_HIX22
631
@deffnx {} BFD_RELOC_SPARC_GOTDATA_LOX10
632
@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_HIX22
633
@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_LOX10
634
@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP
635
SPARC ELF relocations.  There is probably some overlap with other
636
relocation types already defined.
637
@end deffn
638
@deffn {} BFD_RELOC_SPARC_BASE13
639
@deffnx {} BFD_RELOC_SPARC_BASE22
640
I think these are specific to SPARC a.out (e.g., Sun 4).
641
@end deffn
642
@deffn {} BFD_RELOC_SPARC_64
643
@deffnx {} BFD_RELOC_SPARC_10
644
@deffnx {} BFD_RELOC_SPARC_11
645
@deffnx {} BFD_RELOC_SPARC_OLO10
646
@deffnx {} BFD_RELOC_SPARC_HH22
647
@deffnx {} BFD_RELOC_SPARC_HM10
648
@deffnx {} BFD_RELOC_SPARC_LM22
649
@deffnx {} BFD_RELOC_SPARC_PC_HH22
650
@deffnx {} BFD_RELOC_SPARC_PC_HM10
651
@deffnx {} BFD_RELOC_SPARC_PC_LM22
652
@deffnx {} BFD_RELOC_SPARC_WDISP16
653
@deffnx {} BFD_RELOC_SPARC_WDISP19
654
@deffnx {} BFD_RELOC_SPARC_7
655
@deffnx {} BFD_RELOC_SPARC_6
656
@deffnx {} BFD_RELOC_SPARC_5
657
@deffnx {} BFD_RELOC_SPARC_DISP64
658
@deffnx {} BFD_RELOC_SPARC_PLT32
659
@deffnx {} BFD_RELOC_SPARC_PLT64
660
@deffnx {} BFD_RELOC_SPARC_HIX22
661
@deffnx {} BFD_RELOC_SPARC_LOX10
662
@deffnx {} BFD_RELOC_SPARC_H44
663
@deffnx {} BFD_RELOC_SPARC_M44
664
@deffnx {} BFD_RELOC_SPARC_L44
665
@deffnx {} BFD_RELOC_SPARC_REGISTER
666
SPARC64 relocations
667
@end deffn
668
@deffn {} BFD_RELOC_SPARC_REV32
669
SPARC little endian relocation
670
@end deffn
671
@deffn {} BFD_RELOC_SPARC_TLS_GD_HI22
672
@deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10
673
@deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD
674
@deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL
675
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22
676
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_LO10
677
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_ADD
678
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_CALL
679
@deffnx {} BFD_RELOC_SPARC_TLS_LDO_HIX22
680
@deffnx {} BFD_RELOC_SPARC_TLS_LDO_LOX10
681
@deffnx {} BFD_RELOC_SPARC_TLS_LDO_ADD
682
@deffnx {} BFD_RELOC_SPARC_TLS_IE_HI22
683
@deffnx {} BFD_RELOC_SPARC_TLS_IE_LO10
684
@deffnx {} BFD_RELOC_SPARC_TLS_IE_LD
685
@deffnx {} BFD_RELOC_SPARC_TLS_IE_LDX
686
@deffnx {} BFD_RELOC_SPARC_TLS_IE_ADD
687
@deffnx {} BFD_RELOC_SPARC_TLS_LE_HIX22
688
@deffnx {} BFD_RELOC_SPARC_TLS_LE_LOX10
689
@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD32
690
@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD64
691
@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF32
692
@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF64
693
@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF32
694
@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF64
695
SPARC TLS relocations
696
@end deffn
697
@deffn {} BFD_RELOC_SPU_IMM7
698
@deffnx {} BFD_RELOC_SPU_IMM8
699
@deffnx {} BFD_RELOC_SPU_IMM10
700
@deffnx {} BFD_RELOC_SPU_IMM10W
701
@deffnx {} BFD_RELOC_SPU_IMM16
702
@deffnx {} BFD_RELOC_SPU_IMM16W
703
@deffnx {} BFD_RELOC_SPU_IMM18
704
@deffnx {} BFD_RELOC_SPU_PCREL9a
705
@deffnx {} BFD_RELOC_SPU_PCREL9b
706
@deffnx {} BFD_RELOC_SPU_PCREL16
707
@deffnx {} BFD_RELOC_SPU_LO16
708
@deffnx {} BFD_RELOC_SPU_HI16
709
@deffnx {} BFD_RELOC_SPU_PPU32
710
@deffnx {} BFD_RELOC_SPU_PPU64
711
@deffnx {} BFD_RELOC_SPU_ADD_PIC
712
SPU Relocations.
713
@end deffn
714
@deffn {} BFD_RELOC_ALPHA_GPDISP_HI16
715
Alpha ECOFF and ELF relocations.  Some of these treat the symbol or
716
"addend" in some special way.
717
For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
718
writing; when reading, it will be the absolute section symbol.  The
719
addend is the displacement in bytes of the "lda" instruction from
720
the "ldah" instruction (which is at the address of this reloc).
721
@end deffn
722
@deffn {} BFD_RELOC_ALPHA_GPDISP_LO16
723
For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
724
with GPDISP_HI16 relocs.  The addend is ignored when writing the
725
relocations out, and is filled in with the file's GP value on
726
reading, for convenience.
727
@end deffn
728
@deffn {} BFD_RELOC_ALPHA_GPDISP
729
The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
730
relocation except that there is no accompanying GPDISP_LO16
731
relocation.
732
@end deffn
733
@deffn {} BFD_RELOC_ALPHA_LITERAL
734
@deffnx {} BFD_RELOC_ALPHA_ELF_LITERAL
735
@deffnx {} BFD_RELOC_ALPHA_LITUSE
736
The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
737
the assembler turns it into a LDQ instruction to load the address of
738
the symbol, and then fills in a register in the real instruction.
739
 
740
The LITERAL reloc, at the LDQ instruction, refers to the .lita
741
section symbol.  The addend is ignored when writing, but is filled
742
in with the file's GP value on reading, for convenience, as with the
743
GPDISP_LO16 reloc.
744
 
745
The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
746
It should refer to the symbol to be referenced, as with 16_GOTOFF,
747
but it generates output not based on the position within the .got
748
section, but relative to the GP value chosen for the file during the
749
final link stage.
750
 
751
The LITUSE reloc, on the instruction using the loaded address, gives
752
information to the linker that it might be able to use to optimize
753
away some literal section references.  The symbol is ignored (read
754
as the absolute section symbol), and the "addend" indicates the type
755
of instruction using the register:
756
1 - "memory" fmt insn
757
2 - byte-manipulation (byte offset reg)
758
3 - jsr (target of branch)
759
@end deffn
760
@deffn {} BFD_RELOC_ALPHA_HINT
761
The HINT relocation indicates a value that should be filled into the
762
"hint" field of a jmp/jsr/ret instruction, for possible branch-
763
prediction logic which may be provided on some processors.
764
@end deffn
765
@deffn {} BFD_RELOC_ALPHA_LINKAGE
766
The LINKAGE relocation outputs a linkage pair in the object file,
767
which is filled by the linker.
768
@end deffn
769
@deffn {} BFD_RELOC_ALPHA_CODEADDR
770
The CODEADDR relocation outputs a STO_CA in the object file,
771
which is filled by the linker.
772
@end deffn
773
@deffn {} BFD_RELOC_ALPHA_GPREL_HI16
774
@deffnx {} BFD_RELOC_ALPHA_GPREL_LO16
775
The GPREL_HI/LO relocations together form a 32-bit offset from the
776
GP register.
777
@end deffn
778
@deffn {} BFD_RELOC_ALPHA_BRSGP
779
Like BFD_RELOC_23_PCREL_S2, except that the source and target must
780
share a common GP, and the target address is adjusted for
781
STO_ALPHA_STD_GPLOAD.
782
@end deffn
783
@deffn {} BFD_RELOC_ALPHA_NOP
784
The NOP relocation outputs a NOP if the longword displacement
785
between two procedure entry points is < 2^21.
786
@end deffn
787
@deffn {} BFD_RELOC_ALPHA_BSR
788
The BSR relocation outputs a BSR if the longword displacement
789
between two procedure entry points is < 2^21.
790
@end deffn
791
@deffn {} BFD_RELOC_ALPHA_LDA
792
The LDA relocation outputs a LDA if the longword displacement
793
between two procedure entry points is < 2^16.
794
@end deffn
795
@deffn {} BFD_RELOC_ALPHA_BOH
796
The BOH relocation outputs a BSR if the longword displacement
797
between two procedure entry points is < 2^21, or else a hint.
798
@end deffn
799
@deffn {} BFD_RELOC_ALPHA_TLSGD
800
@deffnx {} BFD_RELOC_ALPHA_TLSLDM
801
@deffnx {} BFD_RELOC_ALPHA_DTPMOD64
802
@deffnx {} BFD_RELOC_ALPHA_GOTDTPREL16
803
@deffnx {} BFD_RELOC_ALPHA_DTPREL64
804
@deffnx {} BFD_RELOC_ALPHA_DTPREL_HI16
805
@deffnx {} BFD_RELOC_ALPHA_DTPREL_LO16
806
@deffnx {} BFD_RELOC_ALPHA_DTPREL16
807
@deffnx {} BFD_RELOC_ALPHA_GOTTPREL16
808
@deffnx {} BFD_RELOC_ALPHA_TPREL64
809
@deffnx {} BFD_RELOC_ALPHA_TPREL_HI16
810
@deffnx {} BFD_RELOC_ALPHA_TPREL_LO16
811
@deffnx {} BFD_RELOC_ALPHA_TPREL16
812
Alpha thread-local storage relocations.
813
@end deffn
814
@deffn {} BFD_RELOC_MIPS_JMP
815
Bits 27..2 of the relocation address shifted right 2 bits;
816
simple reloc otherwise.
817
@end deffn
818
@deffn {} BFD_RELOC_MIPS16_JMP
819
The MIPS16 jump instruction.
820
@end deffn
821
@deffn {} BFD_RELOC_MIPS16_GPREL
822
MIPS16 GP relative reloc.
823
@end deffn
824
@deffn {} BFD_RELOC_HI16
825
High 16 bits of 32-bit value; simple reloc.
826
@end deffn
827
@deffn {} BFD_RELOC_HI16_S
828
High 16 bits of 32-bit value but the low 16 bits will be sign
829
extended and added to form the final result.  If the low 16
830
bits form a negative number, we need to add one to the high value
831
to compensate for the borrow when the low bits are added.
832
@end deffn
833
@deffn {} BFD_RELOC_LO16
834
Low 16 bits.
835
@end deffn
836
@deffn {} BFD_RELOC_HI16_PCREL
837
High 16 bits of 32-bit pc-relative value
838
@end deffn
839
@deffn {} BFD_RELOC_HI16_S_PCREL
840
High 16 bits of 32-bit pc-relative value, adjusted
841
@end deffn
842
@deffn {} BFD_RELOC_LO16_PCREL
843
Low 16 bits of pc-relative value
844
@end deffn
845
@deffn {} BFD_RELOC_MIPS16_GOT16
846
@deffnx {} BFD_RELOC_MIPS16_CALL16
847
Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
848
16-bit immediate fields
849
@end deffn
850
@deffn {} BFD_RELOC_MIPS16_HI16
851
MIPS16 high 16 bits of 32-bit value.
852
@end deffn
853
@deffn {} BFD_RELOC_MIPS16_HI16_S
854
MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
855
extended and added to form the final result.  If the low 16
856
bits form a negative number, we need to add one to the high value
857
to compensate for the borrow when the low bits are added.
858
@end deffn
859
@deffn {} BFD_RELOC_MIPS16_LO16
860
MIPS16 low 16 bits.
861
@end deffn
862
@deffn {} BFD_RELOC_MIPS_LITERAL
863
Relocation against a MIPS literal section.
864
@end deffn
865
@deffn {} BFD_RELOC_MIPS_GOT16
866
@deffnx {} BFD_RELOC_MIPS_CALL16
867
@deffnx {} BFD_RELOC_MIPS_GOT_HI16
868
@deffnx {} BFD_RELOC_MIPS_GOT_LO16
869
@deffnx {} BFD_RELOC_MIPS_CALL_HI16
870
@deffnx {} BFD_RELOC_MIPS_CALL_LO16
871
@deffnx {} BFD_RELOC_MIPS_SUB
872
@deffnx {} BFD_RELOC_MIPS_GOT_PAGE
873
@deffnx {} BFD_RELOC_MIPS_GOT_OFST
874
@deffnx {} BFD_RELOC_MIPS_GOT_DISP
875
@deffnx {} BFD_RELOC_MIPS_SHIFT5
876
@deffnx {} BFD_RELOC_MIPS_SHIFT6
877
@deffnx {} BFD_RELOC_MIPS_INSERT_A
878
@deffnx {} BFD_RELOC_MIPS_INSERT_B
879
@deffnx {} BFD_RELOC_MIPS_DELETE
880
@deffnx {} BFD_RELOC_MIPS_HIGHEST
881
@deffnx {} BFD_RELOC_MIPS_HIGHER
882
@deffnx {} BFD_RELOC_MIPS_SCN_DISP
883
@deffnx {} BFD_RELOC_MIPS_REL16
884
@deffnx {} BFD_RELOC_MIPS_RELGOT
885
@deffnx {} BFD_RELOC_MIPS_JALR
886
@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD32
887
@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL32
888
@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD64
889
@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL64
890
@deffnx {} BFD_RELOC_MIPS_TLS_GD
891
@deffnx {} BFD_RELOC_MIPS_TLS_LDM
892
@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_HI16
893
@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_LO16
894
@deffnx {} BFD_RELOC_MIPS_TLS_GOTTPREL
895
@deffnx {} BFD_RELOC_MIPS_TLS_TPREL32
896
@deffnx {} BFD_RELOC_MIPS_TLS_TPREL64
897
@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_HI16
898
@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_LO16
899
MIPS ELF relocations.
900
@end deffn
901
@deffn {} BFD_RELOC_MIPS_COPY
902
@deffnx {} BFD_RELOC_MIPS_JUMP_SLOT
903
MIPS ELF relocations (VxWorks and PLT extensions).
904
@end deffn
905
@deffn {} BFD_RELOC_MOXIE_10_PCREL
906
Moxie ELF relocations.
907
@end deffn
908
@deffn {} BFD_RELOC_FRV_LABEL16
909
@deffnx {} BFD_RELOC_FRV_LABEL24
910
@deffnx {} BFD_RELOC_FRV_LO16
911
@deffnx {} BFD_RELOC_FRV_HI16
912
@deffnx {} BFD_RELOC_FRV_GPREL12
913
@deffnx {} BFD_RELOC_FRV_GPRELU12
914
@deffnx {} BFD_RELOC_FRV_GPREL32
915
@deffnx {} BFD_RELOC_FRV_GPRELHI
916
@deffnx {} BFD_RELOC_FRV_GPRELLO
917
@deffnx {} BFD_RELOC_FRV_GOT12
918
@deffnx {} BFD_RELOC_FRV_GOTHI
919
@deffnx {} BFD_RELOC_FRV_GOTLO
920
@deffnx {} BFD_RELOC_FRV_FUNCDESC
921
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOT12
922
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTHI
923
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTLO
924
@deffnx {} BFD_RELOC_FRV_FUNCDESC_VALUE
925
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFF12
926
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
927
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
928
@deffnx {} BFD_RELOC_FRV_GOTOFF12
929
@deffnx {} BFD_RELOC_FRV_GOTOFFHI
930
@deffnx {} BFD_RELOC_FRV_GOTOFFLO
931
@deffnx {} BFD_RELOC_FRV_GETTLSOFF
932
@deffnx {} BFD_RELOC_FRV_TLSDESC_VALUE
933
@deffnx {} BFD_RELOC_FRV_GOTTLSDESC12
934
@deffnx {} BFD_RELOC_FRV_GOTTLSDESCHI
935
@deffnx {} BFD_RELOC_FRV_GOTTLSDESCLO
936
@deffnx {} BFD_RELOC_FRV_TLSMOFF12
937
@deffnx {} BFD_RELOC_FRV_TLSMOFFHI
938
@deffnx {} BFD_RELOC_FRV_TLSMOFFLO
939
@deffnx {} BFD_RELOC_FRV_GOTTLSOFF12
940
@deffnx {} BFD_RELOC_FRV_GOTTLSOFFHI
941
@deffnx {} BFD_RELOC_FRV_GOTTLSOFFLO
942
@deffnx {} BFD_RELOC_FRV_TLSOFF
943
@deffnx {} BFD_RELOC_FRV_TLSDESC_RELAX
944
@deffnx {} BFD_RELOC_FRV_GETTLSOFF_RELAX
945
@deffnx {} BFD_RELOC_FRV_TLSOFF_RELAX
946
@deffnx {} BFD_RELOC_FRV_TLSMOFF
947
Fujitsu Frv Relocations.
948
@end deffn
949
@deffn {} BFD_RELOC_MN10300_GOTOFF24
950
This is a 24bit GOT-relative reloc for the mn10300.
951
@end deffn
952
@deffn {} BFD_RELOC_MN10300_GOT32
953
This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
954
in the instruction.
955
@end deffn
956
@deffn {} BFD_RELOC_MN10300_GOT24
957
This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
958
in the instruction.
959
@end deffn
960
@deffn {} BFD_RELOC_MN10300_GOT16
961
This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
962
in the instruction.
963
@end deffn
964
@deffn {} BFD_RELOC_MN10300_COPY
965
Copy symbol at runtime.
966
@end deffn
967
@deffn {} BFD_RELOC_MN10300_GLOB_DAT
968
Create GOT entry.
969
@end deffn
970
@deffn {} BFD_RELOC_MN10300_JMP_SLOT
971
Create PLT entry.
972
@end deffn
973
@deffn {} BFD_RELOC_MN10300_RELATIVE
974
Adjust by program base.
975
@end deffn
976
@deffn {} BFD_RELOC_MN10300_SYM_DIFF
977
Together with another reloc targeted at the same location,
978
allows for a value that is the difference of two symbols
979
in the same section.
980
@end deffn
981
@deffn {} BFD_RELOC_MN10300_ALIGN
982
The addend of this reloc is an alignment power that must
983
be honoured at the offset's location, regardless of linker
984
relaxation.
985
@end deffn
986
@deffn {} BFD_RELOC_386_GOT32
987
@deffnx {} BFD_RELOC_386_PLT32
988
@deffnx {} BFD_RELOC_386_COPY
989
@deffnx {} BFD_RELOC_386_GLOB_DAT
990
@deffnx {} BFD_RELOC_386_JUMP_SLOT
991
@deffnx {} BFD_RELOC_386_RELATIVE
992
@deffnx {} BFD_RELOC_386_GOTOFF
993
@deffnx {} BFD_RELOC_386_GOTPC
994
@deffnx {} BFD_RELOC_386_TLS_TPOFF
995
@deffnx {} BFD_RELOC_386_TLS_IE
996
@deffnx {} BFD_RELOC_386_TLS_GOTIE
997
@deffnx {} BFD_RELOC_386_TLS_LE
998
@deffnx {} BFD_RELOC_386_TLS_GD
999
@deffnx {} BFD_RELOC_386_TLS_LDM
1000
@deffnx {} BFD_RELOC_386_TLS_LDO_32
1001
@deffnx {} BFD_RELOC_386_TLS_IE_32
1002
@deffnx {} BFD_RELOC_386_TLS_LE_32
1003
@deffnx {} BFD_RELOC_386_TLS_DTPMOD32
1004
@deffnx {} BFD_RELOC_386_TLS_DTPOFF32
1005
@deffnx {} BFD_RELOC_386_TLS_TPOFF32
1006
@deffnx {} BFD_RELOC_386_TLS_GOTDESC
1007
@deffnx {} BFD_RELOC_386_TLS_DESC_CALL
1008
@deffnx {} BFD_RELOC_386_TLS_DESC
1009
@deffnx {} BFD_RELOC_386_IRELATIVE
1010
i386/elf relocations
1011
@end deffn
1012
@deffn {} BFD_RELOC_X86_64_GOT32
1013
@deffnx {} BFD_RELOC_X86_64_PLT32
1014
@deffnx {} BFD_RELOC_X86_64_COPY
1015
@deffnx {} BFD_RELOC_X86_64_GLOB_DAT
1016
@deffnx {} BFD_RELOC_X86_64_JUMP_SLOT
1017
@deffnx {} BFD_RELOC_X86_64_RELATIVE
1018
@deffnx {} BFD_RELOC_X86_64_GOTPCREL
1019
@deffnx {} BFD_RELOC_X86_64_32S
1020
@deffnx {} BFD_RELOC_X86_64_DTPMOD64
1021
@deffnx {} BFD_RELOC_X86_64_DTPOFF64
1022
@deffnx {} BFD_RELOC_X86_64_TPOFF64
1023
@deffnx {} BFD_RELOC_X86_64_TLSGD
1024
@deffnx {} BFD_RELOC_X86_64_TLSLD
1025
@deffnx {} BFD_RELOC_X86_64_DTPOFF32
1026
@deffnx {} BFD_RELOC_X86_64_GOTTPOFF
1027
@deffnx {} BFD_RELOC_X86_64_TPOFF32
1028
@deffnx {} BFD_RELOC_X86_64_GOTOFF64
1029
@deffnx {} BFD_RELOC_X86_64_GOTPC32
1030
@deffnx {} BFD_RELOC_X86_64_GOT64
1031
@deffnx {} BFD_RELOC_X86_64_GOTPCREL64
1032
@deffnx {} BFD_RELOC_X86_64_GOTPC64
1033
@deffnx {} BFD_RELOC_X86_64_GOTPLT64
1034
@deffnx {} BFD_RELOC_X86_64_PLTOFF64
1035
@deffnx {} BFD_RELOC_X86_64_GOTPC32_TLSDESC
1036
@deffnx {} BFD_RELOC_X86_64_TLSDESC_CALL
1037
@deffnx {} BFD_RELOC_X86_64_TLSDESC
1038
@deffnx {} BFD_RELOC_X86_64_IRELATIVE
1039
x86-64/elf relocations
1040
@end deffn
1041
@deffn {} BFD_RELOC_NS32K_IMM_8
1042
@deffnx {} BFD_RELOC_NS32K_IMM_16
1043
@deffnx {} BFD_RELOC_NS32K_IMM_32
1044
@deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL
1045
@deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL
1046
@deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL
1047
@deffnx {} BFD_RELOC_NS32K_DISP_8
1048
@deffnx {} BFD_RELOC_NS32K_DISP_16
1049
@deffnx {} BFD_RELOC_NS32K_DISP_32
1050
@deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL
1051
@deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL
1052
@deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL
1053
ns32k relocations
1054
@end deffn
1055
@deffn {} BFD_RELOC_PDP11_DISP_8_PCREL
1056
@deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL
1057
PDP11 relocations
1058
@end deffn
1059
@deffn {} BFD_RELOC_PJ_CODE_HI16
1060
@deffnx {} BFD_RELOC_PJ_CODE_LO16
1061
@deffnx {} BFD_RELOC_PJ_CODE_DIR16
1062
@deffnx {} BFD_RELOC_PJ_CODE_DIR32
1063
@deffnx {} BFD_RELOC_PJ_CODE_REL16
1064
@deffnx {} BFD_RELOC_PJ_CODE_REL32
1065
Picojava relocs.  Not all of these appear in object files.
1066
@end deffn
1067
@deffn {} BFD_RELOC_PPC_B26
1068
@deffnx {} BFD_RELOC_PPC_BA26
1069
@deffnx {} BFD_RELOC_PPC_TOC16
1070
@deffnx {} BFD_RELOC_PPC_B16
1071
@deffnx {} BFD_RELOC_PPC_B16_BRTAKEN
1072
@deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN
1073
@deffnx {} BFD_RELOC_PPC_BA16
1074
@deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN
1075
@deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN
1076
@deffnx {} BFD_RELOC_PPC_COPY
1077
@deffnx {} BFD_RELOC_PPC_GLOB_DAT
1078
@deffnx {} BFD_RELOC_PPC_JMP_SLOT
1079
@deffnx {} BFD_RELOC_PPC_RELATIVE
1080
@deffnx {} BFD_RELOC_PPC_LOCAL24PC
1081
@deffnx {} BFD_RELOC_PPC_EMB_NADDR32
1082
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16
1083
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO
1084
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI
1085
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA
1086
@deffnx {} BFD_RELOC_PPC_EMB_SDAI16
1087
@deffnx {} BFD_RELOC_PPC_EMB_SDA2I16
1088
@deffnx {} BFD_RELOC_PPC_EMB_SDA2REL
1089
@deffnx {} BFD_RELOC_PPC_EMB_SDA21
1090
@deffnx {} BFD_RELOC_PPC_EMB_MRKREF
1091
@deffnx {} BFD_RELOC_PPC_EMB_RELSEC16
1092
@deffnx {} BFD_RELOC_PPC_EMB_RELST_LO
1093
@deffnx {} BFD_RELOC_PPC_EMB_RELST_HI
1094
@deffnx {} BFD_RELOC_PPC_EMB_RELST_HA
1095
@deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD
1096
@deffnx {} BFD_RELOC_PPC_EMB_RELSDA
1097
@deffnx {} BFD_RELOC_PPC64_HIGHER
1098
@deffnx {} BFD_RELOC_PPC64_HIGHER_S
1099
@deffnx {} BFD_RELOC_PPC64_HIGHEST
1100
@deffnx {} BFD_RELOC_PPC64_HIGHEST_S
1101
@deffnx {} BFD_RELOC_PPC64_TOC16_LO
1102
@deffnx {} BFD_RELOC_PPC64_TOC16_HI
1103
@deffnx {} BFD_RELOC_PPC64_TOC16_HA
1104
@deffnx {} BFD_RELOC_PPC64_TOC
1105
@deffnx {} BFD_RELOC_PPC64_PLTGOT16
1106
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO
1107
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI
1108
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA
1109
@deffnx {} BFD_RELOC_PPC64_ADDR16_DS
1110
@deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS
1111
@deffnx {} BFD_RELOC_PPC64_GOT16_DS
1112
@deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS
1113
@deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS
1114
@deffnx {} BFD_RELOC_PPC64_SECTOFF_DS
1115
@deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS
1116
@deffnx {} BFD_RELOC_PPC64_TOC16_DS
1117
@deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS
1118
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS
1119
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS
1120
Power(rs6000) and PowerPC relocations.
1121
@end deffn
1122
@deffn {} BFD_RELOC_PPC_TLS
1123
@deffnx {} BFD_RELOC_PPC_TLSGD
1124
@deffnx {} BFD_RELOC_PPC_TLSLD
1125
@deffnx {} BFD_RELOC_PPC_DTPMOD
1126
@deffnx {} BFD_RELOC_PPC_TPREL16
1127
@deffnx {} BFD_RELOC_PPC_TPREL16_LO
1128
@deffnx {} BFD_RELOC_PPC_TPREL16_HI
1129
@deffnx {} BFD_RELOC_PPC_TPREL16_HA
1130
@deffnx {} BFD_RELOC_PPC_TPREL
1131
@deffnx {} BFD_RELOC_PPC_DTPREL16
1132
@deffnx {} BFD_RELOC_PPC_DTPREL16_LO
1133
@deffnx {} BFD_RELOC_PPC_DTPREL16_HI
1134
@deffnx {} BFD_RELOC_PPC_DTPREL16_HA
1135
@deffnx {} BFD_RELOC_PPC_DTPREL
1136
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16
1137
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_LO
1138
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HI
1139
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HA
1140
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16
1141
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_LO
1142
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HI
1143
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HA
1144
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16
1145
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_LO
1146
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HI
1147
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HA
1148
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16
1149
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_LO
1150
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HI
1151
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HA
1152
@deffnx {} BFD_RELOC_PPC64_TPREL16_DS
1153
@deffnx {} BFD_RELOC_PPC64_TPREL16_LO_DS
1154
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHER
1155
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHERA
1156
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHEST
1157
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHESTA
1158
@deffnx {} BFD_RELOC_PPC64_DTPREL16_DS
1159
@deffnx {} BFD_RELOC_PPC64_DTPREL16_LO_DS
1160
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHER
1161
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHERA
1162
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHEST
1163
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHESTA
1164
PowerPC and PowerPC64 thread-local storage relocations.
1165
@end deffn
1166
@deffn {} BFD_RELOC_I370_D12
1167
IBM 370/390 relocations
1168
@end deffn
1169
@deffn {} BFD_RELOC_CTOR
1170
The type of reloc used to build a constructor table - at the moment
1171
probably a 32 bit wide absolute relocation, but the target can choose.
1172
It generally does map to one of the other relocation types.
1173
@end deffn
1174
@deffn {} BFD_RELOC_ARM_PCREL_BRANCH
1175
ARM 26 bit pc-relative branch.  The lowest two bits must be zero and are
1176
not stored in the instruction.
1177
@end deffn
1178
@deffn {} BFD_RELOC_ARM_PCREL_BLX
1179
ARM 26 bit pc-relative branch.  The lowest bit must be zero and is
1180
not stored in the instruction.  The 2nd lowest bit comes from a 1 bit
1181
field in the instruction.
1182
@end deffn
1183
@deffn {} BFD_RELOC_THUMB_PCREL_BLX
1184
Thumb 22 bit pc-relative branch.  The lowest bit must be zero and is
1185
not stored in the instruction.  The 2nd lowest bit comes from a 1 bit
1186
field in the instruction.
1187
@end deffn
1188
@deffn {} BFD_RELOC_ARM_PCREL_CALL
1189
ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
1190
@end deffn
1191
@deffn {} BFD_RELOC_ARM_PCREL_JUMP
1192
ARM 26-bit pc-relative branch for B or conditional BL instruction.
1193
@end deffn
1194
@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH7
1195
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH9
1196
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12
1197
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH20
1198
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23
1199
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH25
1200
Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
1201
The lowest bit must be zero and is not stored in the instruction.
1202
Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
1203
"nn" one smaller in all cases.  Note further that BRANCH23
1204
corresponds to R_ARM_THM_CALL.
1205
@end deffn
1206
@deffn {} BFD_RELOC_ARM_OFFSET_IMM
1207
12-bit immediate offset, used in ARM-format ldr and str instructions.
1208
@end deffn
1209
@deffn {} BFD_RELOC_ARM_THUMB_OFFSET
1210
5-bit immediate offset, used in Thumb-format ldr and str instructions.
1211
@end deffn
1212
@deffn {} BFD_RELOC_ARM_TARGET1
1213
Pc-relative or absolute relocation depending on target.  Used for
1214
entries in .init_array sections.
1215
@end deffn
1216
@deffn {} BFD_RELOC_ARM_ROSEGREL32
1217
Read-only segment base relative address.
1218
@end deffn
1219
@deffn {} BFD_RELOC_ARM_SBREL32
1220
Data segment base relative address.
1221
@end deffn
1222
@deffn {} BFD_RELOC_ARM_TARGET2
1223
This reloc is used for references to RTTI data from exception handling
1224
tables.  The actual definition depends on the target.  It may be a
1225
pc-relative or some form of GOT-indirect relocation.
1226
@end deffn
1227
@deffn {} BFD_RELOC_ARM_PREL31
1228
31-bit PC relative address.
1229
@end deffn
1230
@deffn {} BFD_RELOC_ARM_MOVW
1231
@deffnx {} BFD_RELOC_ARM_MOVT
1232
@deffnx {} BFD_RELOC_ARM_MOVW_PCREL
1233
@deffnx {} BFD_RELOC_ARM_MOVT_PCREL
1234
@deffnx {} BFD_RELOC_ARM_THUMB_MOVW
1235
@deffnx {} BFD_RELOC_ARM_THUMB_MOVT
1236
@deffnx {} BFD_RELOC_ARM_THUMB_MOVW_PCREL
1237
@deffnx {} BFD_RELOC_ARM_THUMB_MOVT_PCREL
1238
Low and High halfword relocations for MOVW and MOVT instructions.
1239
@end deffn
1240
@deffn {} BFD_RELOC_ARM_JUMP_SLOT
1241
@deffnx {} BFD_RELOC_ARM_GLOB_DAT
1242
@deffnx {} BFD_RELOC_ARM_GOT32
1243
@deffnx {} BFD_RELOC_ARM_PLT32
1244
@deffnx {} BFD_RELOC_ARM_RELATIVE
1245
@deffnx {} BFD_RELOC_ARM_GOTOFF
1246
@deffnx {} BFD_RELOC_ARM_GOTPC
1247
Relocations for setting up GOTs and PLTs for shared libraries.
1248
@end deffn
1249
@deffn {} BFD_RELOC_ARM_TLS_GD32
1250
@deffnx {} BFD_RELOC_ARM_TLS_LDO32
1251
@deffnx {} BFD_RELOC_ARM_TLS_LDM32
1252
@deffnx {} BFD_RELOC_ARM_TLS_DTPOFF32
1253
@deffnx {} BFD_RELOC_ARM_TLS_DTPMOD32
1254
@deffnx {} BFD_RELOC_ARM_TLS_TPOFF32
1255
@deffnx {} BFD_RELOC_ARM_TLS_IE32
1256
@deffnx {} BFD_RELOC_ARM_TLS_LE32
1257
ARM thread-local storage relocations.
1258
@end deffn
1259
@deffn {} BFD_RELOC_ARM_ALU_PC_G0_NC
1260
@deffnx {} BFD_RELOC_ARM_ALU_PC_G0
1261
@deffnx {} BFD_RELOC_ARM_ALU_PC_G1_NC
1262
@deffnx {} BFD_RELOC_ARM_ALU_PC_G1
1263
@deffnx {} BFD_RELOC_ARM_ALU_PC_G2
1264
@deffnx {} BFD_RELOC_ARM_LDR_PC_G0
1265
@deffnx {} BFD_RELOC_ARM_LDR_PC_G1
1266
@deffnx {} BFD_RELOC_ARM_LDR_PC_G2
1267
@deffnx {} BFD_RELOC_ARM_LDRS_PC_G0
1268
@deffnx {} BFD_RELOC_ARM_LDRS_PC_G1
1269
@deffnx {} BFD_RELOC_ARM_LDRS_PC_G2
1270
@deffnx {} BFD_RELOC_ARM_LDC_PC_G0
1271
@deffnx {} BFD_RELOC_ARM_LDC_PC_G1
1272
@deffnx {} BFD_RELOC_ARM_LDC_PC_G2
1273
@deffnx {} BFD_RELOC_ARM_ALU_SB_G0_NC
1274
@deffnx {} BFD_RELOC_ARM_ALU_SB_G0
1275
@deffnx {} BFD_RELOC_ARM_ALU_SB_G1_NC
1276
@deffnx {} BFD_RELOC_ARM_ALU_SB_G1
1277
@deffnx {} BFD_RELOC_ARM_ALU_SB_G2
1278
@deffnx {} BFD_RELOC_ARM_LDR_SB_G0
1279
@deffnx {} BFD_RELOC_ARM_LDR_SB_G1
1280
@deffnx {} BFD_RELOC_ARM_LDR_SB_G2
1281
@deffnx {} BFD_RELOC_ARM_LDRS_SB_G0
1282
@deffnx {} BFD_RELOC_ARM_LDRS_SB_G1
1283
@deffnx {} BFD_RELOC_ARM_LDRS_SB_G2
1284
@deffnx {} BFD_RELOC_ARM_LDC_SB_G0
1285
@deffnx {} BFD_RELOC_ARM_LDC_SB_G1
1286
@deffnx {} BFD_RELOC_ARM_LDC_SB_G2
1287
ARM group relocations.
1288
@end deffn
1289
@deffn {} BFD_RELOC_ARM_V4BX
1290
Annotation of BX instructions.
1291
@end deffn
1292
@deffn {} BFD_RELOC_ARM_IMMEDIATE
1293
@deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE
1294
@deffnx {} BFD_RELOC_ARM_T32_IMMEDIATE
1295
@deffnx {} BFD_RELOC_ARM_T32_ADD_IMM
1296
@deffnx {} BFD_RELOC_ARM_T32_IMM12
1297
@deffnx {} BFD_RELOC_ARM_T32_ADD_PC12
1298
@deffnx {} BFD_RELOC_ARM_SHIFT_IMM
1299
@deffnx {} BFD_RELOC_ARM_SMC
1300
@deffnx {} BFD_RELOC_ARM_SWI
1301
@deffnx {} BFD_RELOC_ARM_MULTI
1302
@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM
1303
@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM_S2
1304
@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM
1305
@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
1306
@deffnx {} BFD_RELOC_ARM_ADR_IMM
1307
@deffnx {} BFD_RELOC_ARM_LDR_IMM
1308
@deffnx {} BFD_RELOC_ARM_LITERAL
1309
@deffnx {} BFD_RELOC_ARM_IN_POOL
1310
@deffnx {} BFD_RELOC_ARM_OFFSET_IMM8
1311
@deffnx {} BFD_RELOC_ARM_T32_OFFSET_U8
1312
@deffnx {} BFD_RELOC_ARM_T32_OFFSET_IMM
1313
@deffnx {} BFD_RELOC_ARM_HWLITERAL
1314
@deffnx {} BFD_RELOC_ARM_THUMB_ADD
1315
@deffnx {} BFD_RELOC_ARM_THUMB_IMM
1316
@deffnx {} BFD_RELOC_ARM_THUMB_SHIFT
1317
These relocs are only used within the ARM assembler.  They are not
1318
(at present) written to any object files.
1319
@end deffn
1320
@deffn {} BFD_RELOC_SH_PCDISP8BY2
1321
@deffnx {} BFD_RELOC_SH_PCDISP12BY2
1322
@deffnx {} BFD_RELOC_SH_IMM3
1323
@deffnx {} BFD_RELOC_SH_IMM3U
1324
@deffnx {} BFD_RELOC_SH_DISP12
1325
@deffnx {} BFD_RELOC_SH_DISP12BY2
1326
@deffnx {} BFD_RELOC_SH_DISP12BY4
1327
@deffnx {} BFD_RELOC_SH_DISP12BY8
1328
@deffnx {} BFD_RELOC_SH_DISP20
1329
@deffnx {} BFD_RELOC_SH_DISP20BY8
1330
@deffnx {} BFD_RELOC_SH_IMM4
1331
@deffnx {} BFD_RELOC_SH_IMM4BY2
1332
@deffnx {} BFD_RELOC_SH_IMM4BY4
1333
@deffnx {} BFD_RELOC_SH_IMM8
1334
@deffnx {} BFD_RELOC_SH_IMM8BY2
1335
@deffnx {} BFD_RELOC_SH_IMM8BY4
1336
@deffnx {} BFD_RELOC_SH_PCRELIMM8BY2
1337
@deffnx {} BFD_RELOC_SH_PCRELIMM8BY4
1338
@deffnx {} BFD_RELOC_SH_SWITCH16
1339
@deffnx {} BFD_RELOC_SH_SWITCH32
1340
@deffnx {} BFD_RELOC_SH_USES
1341
@deffnx {} BFD_RELOC_SH_COUNT
1342
@deffnx {} BFD_RELOC_SH_ALIGN
1343
@deffnx {} BFD_RELOC_SH_CODE
1344
@deffnx {} BFD_RELOC_SH_DATA
1345
@deffnx {} BFD_RELOC_SH_LABEL
1346
@deffnx {} BFD_RELOC_SH_LOOP_START
1347
@deffnx {} BFD_RELOC_SH_LOOP_END
1348
@deffnx {} BFD_RELOC_SH_COPY
1349
@deffnx {} BFD_RELOC_SH_GLOB_DAT
1350
@deffnx {} BFD_RELOC_SH_JMP_SLOT
1351
@deffnx {} BFD_RELOC_SH_RELATIVE
1352
@deffnx {} BFD_RELOC_SH_GOTPC
1353
@deffnx {} BFD_RELOC_SH_GOT_LOW16
1354
@deffnx {} BFD_RELOC_SH_GOT_MEDLOW16
1355
@deffnx {} BFD_RELOC_SH_GOT_MEDHI16
1356
@deffnx {} BFD_RELOC_SH_GOT_HI16
1357
@deffnx {} BFD_RELOC_SH_GOTPLT_LOW16
1358
@deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16
1359
@deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16
1360
@deffnx {} BFD_RELOC_SH_GOTPLT_HI16
1361
@deffnx {} BFD_RELOC_SH_PLT_LOW16
1362
@deffnx {} BFD_RELOC_SH_PLT_MEDLOW16
1363
@deffnx {} BFD_RELOC_SH_PLT_MEDHI16
1364
@deffnx {} BFD_RELOC_SH_PLT_HI16
1365
@deffnx {} BFD_RELOC_SH_GOTOFF_LOW16
1366
@deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16
1367
@deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16
1368
@deffnx {} BFD_RELOC_SH_GOTOFF_HI16
1369
@deffnx {} BFD_RELOC_SH_GOTPC_LOW16
1370
@deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16
1371
@deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16
1372
@deffnx {} BFD_RELOC_SH_GOTPC_HI16
1373
@deffnx {} BFD_RELOC_SH_COPY64
1374
@deffnx {} BFD_RELOC_SH_GLOB_DAT64
1375
@deffnx {} BFD_RELOC_SH_JMP_SLOT64
1376
@deffnx {} BFD_RELOC_SH_RELATIVE64
1377
@deffnx {} BFD_RELOC_SH_GOT10BY4
1378
@deffnx {} BFD_RELOC_SH_GOT10BY8
1379
@deffnx {} BFD_RELOC_SH_GOTPLT10BY4
1380
@deffnx {} BFD_RELOC_SH_GOTPLT10BY8
1381
@deffnx {} BFD_RELOC_SH_GOTPLT32
1382
@deffnx {} BFD_RELOC_SH_SHMEDIA_CODE
1383
@deffnx {} BFD_RELOC_SH_IMMU5
1384
@deffnx {} BFD_RELOC_SH_IMMS6
1385
@deffnx {} BFD_RELOC_SH_IMMS6BY32
1386
@deffnx {} BFD_RELOC_SH_IMMU6
1387
@deffnx {} BFD_RELOC_SH_IMMS10
1388
@deffnx {} BFD_RELOC_SH_IMMS10BY2
1389
@deffnx {} BFD_RELOC_SH_IMMS10BY4
1390
@deffnx {} BFD_RELOC_SH_IMMS10BY8
1391
@deffnx {} BFD_RELOC_SH_IMMS16
1392
@deffnx {} BFD_RELOC_SH_IMMU16
1393
@deffnx {} BFD_RELOC_SH_IMM_LOW16
1394
@deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL
1395
@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16
1396
@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL
1397
@deffnx {} BFD_RELOC_SH_IMM_MEDHI16
1398
@deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL
1399
@deffnx {} BFD_RELOC_SH_IMM_HI16
1400
@deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL
1401
@deffnx {} BFD_RELOC_SH_PT_16
1402
@deffnx {} BFD_RELOC_SH_TLS_GD_32
1403
@deffnx {} BFD_RELOC_SH_TLS_LD_32
1404
@deffnx {} BFD_RELOC_SH_TLS_LDO_32
1405
@deffnx {} BFD_RELOC_SH_TLS_IE_32
1406
@deffnx {} BFD_RELOC_SH_TLS_LE_32
1407
@deffnx {} BFD_RELOC_SH_TLS_DTPMOD32
1408
@deffnx {} BFD_RELOC_SH_TLS_DTPOFF32
1409
@deffnx {} BFD_RELOC_SH_TLS_TPOFF32
1410
Renesas / SuperH SH relocs.  Not all of these appear in object files.
1411
@end deffn
1412
@deffn {} BFD_RELOC_ARC_B22_PCREL
1413
ARC Cores relocs.
1414
ARC 22 bit pc-relative branch.  The lowest two bits must be zero and are
1415
not stored in the instruction.  The high 20 bits are installed in bits 26
1416
through 7 of the instruction.
1417
@end deffn
1418
@deffn {} BFD_RELOC_ARC_B26
1419
ARC 26 bit absolute branch.  The lowest two bits must be zero and are not
1420
stored in the instruction.  The high 24 bits are installed in bits 23
1421
through 0.
1422
@end deffn
1423
@deffn {} BFD_RELOC_BFIN_16_IMM
1424
ADI Blackfin 16 bit immediate absolute reloc.
1425
@end deffn
1426
@deffn {} BFD_RELOC_BFIN_16_HIGH
1427
ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
1428
@end deffn
1429
@deffn {} BFD_RELOC_BFIN_4_PCREL
1430
ADI Blackfin 'a' part of LSETUP.
1431
@end deffn
1432
@deffn {} BFD_RELOC_BFIN_5_PCREL
1433
ADI Blackfin.
1434
@end deffn
1435
@deffn {} BFD_RELOC_BFIN_16_LOW
1436
ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
1437
@end deffn
1438
@deffn {} BFD_RELOC_BFIN_10_PCREL
1439
ADI Blackfin.
1440
@end deffn
1441
@deffn {} BFD_RELOC_BFIN_11_PCREL
1442
ADI Blackfin 'b' part of LSETUP.
1443
@end deffn
1444
@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP
1445
ADI Blackfin.
1446
@end deffn
1447
@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP_S
1448
ADI Blackfin Short jump, pcrel.
1449
@end deffn
1450
@deffn {} BFD_RELOC_BFIN_24_PCREL_CALL_X
1451
ADI Blackfin Call.x not implemented.
1452
@end deffn
1453
@deffn {} BFD_RELOC_BFIN_24_PCREL_JUMP_L
1454
ADI Blackfin Long Jump pcrel.
1455
@end deffn
1456
@deffn {} BFD_RELOC_BFIN_GOT17M4
1457
@deffnx {} BFD_RELOC_BFIN_GOTHI
1458
@deffnx {} BFD_RELOC_BFIN_GOTLO
1459
@deffnx {} BFD_RELOC_BFIN_FUNCDESC
1460
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOT17M4
1461
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTHI
1462
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTLO
1463
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_VALUE
1464
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
1465
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
1466
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
1467
@deffnx {} BFD_RELOC_BFIN_GOTOFF17M4
1468
@deffnx {} BFD_RELOC_BFIN_GOTOFFHI
1469
@deffnx {} BFD_RELOC_BFIN_GOTOFFLO
1470
ADI Blackfin FD-PIC relocations.
1471
@end deffn
1472
@deffn {} BFD_RELOC_BFIN_GOT
1473
ADI Blackfin GOT relocation.
1474
@end deffn
1475
@deffn {} BFD_RELOC_BFIN_PLTPC
1476
ADI Blackfin PLTPC relocation.
1477
@end deffn
1478
@deffn {} BFD_ARELOC_BFIN_PUSH
1479
ADI Blackfin arithmetic relocation.
1480
@end deffn
1481
@deffn {} BFD_ARELOC_BFIN_CONST
1482
ADI Blackfin arithmetic relocation.
1483
@end deffn
1484
@deffn {} BFD_ARELOC_BFIN_ADD
1485
ADI Blackfin arithmetic relocation.
1486
@end deffn
1487
@deffn {} BFD_ARELOC_BFIN_SUB
1488
ADI Blackfin arithmetic relocation.
1489
@end deffn
1490
@deffn {} BFD_ARELOC_BFIN_MULT
1491
ADI Blackfin arithmetic relocation.
1492
@end deffn
1493
@deffn {} BFD_ARELOC_BFIN_DIV
1494
ADI Blackfin arithmetic relocation.
1495
@end deffn
1496
@deffn {} BFD_ARELOC_BFIN_MOD
1497
ADI Blackfin arithmetic relocation.
1498
@end deffn
1499
@deffn {} BFD_ARELOC_BFIN_LSHIFT
1500
ADI Blackfin arithmetic relocation.
1501
@end deffn
1502
@deffn {} BFD_ARELOC_BFIN_RSHIFT
1503
ADI Blackfin arithmetic relocation.
1504
@end deffn
1505
@deffn {} BFD_ARELOC_BFIN_AND
1506
ADI Blackfin arithmetic relocation.
1507
@end deffn
1508
@deffn {} BFD_ARELOC_BFIN_OR
1509
ADI Blackfin arithmetic relocation.
1510
@end deffn
1511
@deffn {} BFD_ARELOC_BFIN_XOR
1512
ADI Blackfin arithmetic relocation.
1513
@end deffn
1514
@deffn {} BFD_ARELOC_BFIN_LAND
1515
ADI Blackfin arithmetic relocation.
1516
@end deffn
1517
@deffn {} BFD_ARELOC_BFIN_LOR
1518
ADI Blackfin arithmetic relocation.
1519
@end deffn
1520
@deffn {} BFD_ARELOC_BFIN_LEN
1521
ADI Blackfin arithmetic relocation.
1522
@end deffn
1523
@deffn {} BFD_ARELOC_BFIN_NEG
1524
ADI Blackfin arithmetic relocation.
1525
@end deffn
1526
@deffn {} BFD_ARELOC_BFIN_COMP
1527
ADI Blackfin arithmetic relocation.
1528
@end deffn
1529
@deffn {} BFD_ARELOC_BFIN_PAGE
1530
ADI Blackfin arithmetic relocation.
1531
@end deffn
1532
@deffn {} BFD_ARELOC_BFIN_HWPAGE
1533
ADI Blackfin arithmetic relocation.
1534
@end deffn
1535
@deffn {} BFD_ARELOC_BFIN_ADDR
1536
ADI Blackfin arithmetic relocation.
1537
@end deffn
1538
@deffn {} BFD_RELOC_D10V_10_PCREL_R
1539
Mitsubishi D10V relocs.
1540
This is a 10-bit reloc with the right 2 bits
1541
assumed to be 0.
1542
@end deffn
1543
@deffn {} BFD_RELOC_D10V_10_PCREL_L
1544
Mitsubishi D10V relocs.
1545
This is a 10-bit reloc with the right 2 bits
1546
assumed to be 0.  This is the same as the previous reloc
1547
except it is in the left container, i.e.,
1548
shifted left 15 bits.
1549
@end deffn
1550
@deffn {} BFD_RELOC_D10V_18
1551
This is an 18-bit reloc with the right 2 bits
1552
assumed to be 0.
1553
@end deffn
1554
@deffn {} BFD_RELOC_D10V_18_PCREL
1555
This is an 18-bit reloc with the right 2 bits
1556
assumed to be 0.
1557
@end deffn
1558
@deffn {} BFD_RELOC_D30V_6
1559
Mitsubishi D30V relocs.
1560
This is a 6-bit absolute reloc.
1561
@end deffn
1562
@deffn {} BFD_RELOC_D30V_9_PCREL
1563
This is a 6-bit pc-relative reloc with
1564
the right 3 bits assumed to be 0.
1565
@end deffn
1566
@deffn {} BFD_RELOC_D30V_9_PCREL_R
1567
This is a 6-bit pc-relative reloc with
1568
the right 3 bits assumed to be 0. Same
1569
as the previous reloc but on the right side
1570
of the container.
1571
@end deffn
1572
@deffn {} BFD_RELOC_D30V_15
1573
This is a 12-bit absolute reloc with the
1574
right 3 bitsassumed to be 0.
1575
@end deffn
1576
@deffn {} BFD_RELOC_D30V_15_PCREL
1577
This is a 12-bit pc-relative reloc with
1578
the right 3 bits assumed to be 0.
1579
@end deffn
1580
@deffn {} BFD_RELOC_D30V_15_PCREL_R
1581
This is a 12-bit pc-relative reloc with
1582
the right 3 bits assumed to be 0. Same
1583
as the previous reloc but on the right side
1584
of the container.
1585
@end deffn
1586
@deffn {} BFD_RELOC_D30V_21
1587
This is an 18-bit absolute reloc with
1588
the right 3 bits assumed to be 0.
1589
@end deffn
1590
@deffn {} BFD_RELOC_D30V_21_PCREL
1591
This is an 18-bit pc-relative reloc with
1592
the right 3 bits assumed to be 0.
1593
@end deffn
1594
@deffn {} BFD_RELOC_D30V_21_PCREL_R
1595
This is an 18-bit pc-relative reloc with
1596
the right 3 bits assumed to be 0. Same
1597
as the previous reloc but on the right side
1598
of the container.
1599
@end deffn
1600
@deffn {} BFD_RELOC_D30V_32
1601
This is a 32-bit absolute reloc.
1602
@end deffn
1603
@deffn {} BFD_RELOC_D30V_32_PCREL
1604
This is a 32-bit pc-relative reloc.
1605
@end deffn
1606
@deffn {} BFD_RELOC_DLX_HI16_S
1607
DLX relocs
1608
@end deffn
1609
@deffn {} BFD_RELOC_DLX_LO16
1610
DLX relocs
1611
@end deffn
1612
@deffn {} BFD_RELOC_DLX_JMP26
1613
DLX relocs
1614
@end deffn
1615
@deffn {} BFD_RELOC_M32C_HI8
1616
@deffnx {} BFD_RELOC_M32C_RL_JUMP
1617
@deffnx {} BFD_RELOC_M32C_RL_1ADDR
1618
@deffnx {} BFD_RELOC_M32C_RL_2ADDR
1619
Renesas M16C/M32C Relocations.
1620
@end deffn
1621
@deffn {} BFD_RELOC_M32R_24
1622
Renesas M32R (formerly Mitsubishi M32R) relocs.
1623
This is a 24 bit absolute address.
1624
@end deffn
1625
@deffn {} BFD_RELOC_M32R_10_PCREL
1626
This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
1627
@end deffn
1628
@deffn {} BFD_RELOC_M32R_18_PCREL
1629
This is an 18-bit reloc with the right 2 bits assumed to be 0.
1630
@end deffn
1631
@deffn {} BFD_RELOC_M32R_26_PCREL
1632
This is a 26-bit reloc with the right 2 bits assumed to be 0.
1633
@end deffn
1634
@deffn {} BFD_RELOC_M32R_HI16_ULO
1635
This is a 16-bit reloc containing the high 16 bits of an address
1636
used when the lower 16 bits are treated as unsigned.
1637
@end deffn
1638
@deffn {} BFD_RELOC_M32R_HI16_SLO
1639
This is a 16-bit reloc containing the high 16 bits of an address
1640
used when the lower 16 bits are treated as signed.
1641
@end deffn
1642
@deffn {} BFD_RELOC_M32R_LO16
1643
This is a 16-bit reloc containing the lower 16 bits of an address.
1644
@end deffn
1645
@deffn {} BFD_RELOC_M32R_SDA16
1646
This is a 16-bit reloc containing the small data area offset for use in
1647
add3, load, and store instructions.
1648
@end deffn
1649
@deffn {} BFD_RELOC_M32R_GOT24
1650
@deffnx {} BFD_RELOC_M32R_26_PLTREL
1651
@deffnx {} BFD_RELOC_M32R_COPY
1652
@deffnx {} BFD_RELOC_M32R_GLOB_DAT
1653
@deffnx {} BFD_RELOC_M32R_JMP_SLOT
1654
@deffnx {} BFD_RELOC_M32R_RELATIVE
1655
@deffnx {} BFD_RELOC_M32R_GOTOFF
1656
@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_ULO
1657
@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_SLO
1658
@deffnx {} BFD_RELOC_M32R_GOTOFF_LO
1659
@deffnx {} BFD_RELOC_M32R_GOTPC24
1660
@deffnx {} BFD_RELOC_M32R_GOT16_HI_ULO
1661
@deffnx {} BFD_RELOC_M32R_GOT16_HI_SLO
1662
@deffnx {} BFD_RELOC_M32R_GOT16_LO
1663
@deffnx {} BFD_RELOC_M32R_GOTPC_HI_ULO
1664
@deffnx {} BFD_RELOC_M32R_GOTPC_HI_SLO
1665
@deffnx {} BFD_RELOC_M32R_GOTPC_LO
1666
For PIC.
1667
@end deffn
1668
@deffn {} BFD_RELOC_V850_9_PCREL
1669
This is a 9-bit reloc
1670
@end deffn
1671
@deffn {} BFD_RELOC_V850_22_PCREL
1672
This is a 22-bit reloc
1673
@end deffn
1674
@deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET
1675
This is a 16 bit offset from the short data area pointer.
1676
@end deffn
1677
@deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET
1678
This is a 16 bit offset (of which only 15 bits are used) from the
1679
short data area pointer.
1680
@end deffn
1681
@deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET
1682
This is a 16 bit offset from the zero data area pointer.
1683
@end deffn
1684
@deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET
1685
This is a 16 bit offset (of which only 15 bits are used) from the
1686
zero data area pointer.
1687
@end deffn
1688
@deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET
1689
This is an 8 bit offset (of which only 6 bits are used) from the
1690
tiny data area pointer.
1691
@end deffn
1692
@deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET
1693
This is an 8bit offset (of which only 7 bits are used) from the tiny
1694
data area pointer.
1695
@end deffn
1696
@deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET
1697
This is a 7 bit offset from the tiny data area pointer.
1698
@end deffn
1699
@deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET
1700
This is a 16 bit offset from the tiny data area pointer.
1701
@end deffn
1702
@deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET
1703
This is a 5 bit offset (of which only 4 bits are used) from the tiny
1704
data area pointer.
1705
@end deffn
1706
@deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET
1707
This is a 4 bit offset from the tiny data area pointer.
1708
@end deffn
1709
@deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
1710
This is a 16 bit offset from the short data area pointer, with the
1711
bits placed non-contiguously in the instruction.
1712
@end deffn
1713
@deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
1714
This is a 16 bit offset from the zero data area pointer, with the
1715
bits placed non-contiguously in the instruction.
1716
@end deffn
1717
@deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET
1718
This is a 6 bit offset from the call table base pointer.
1719
@end deffn
1720
@deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET
1721
This is a 16 bit offset from the call table base pointer.
1722
@end deffn
1723
@deffn {} BFD_RELOC_V850_LONGCALL
1724
Used for relaxing indirect function calls.
1725
@end deffn
1726
@deffn {} BFD_RELOC_V850_LONGJUMP
1727
Used for relaxing indirect jumps.
1728
@end deffn
1729
@deffn {} BFD_RELOC_V850_ALIGN
1730
Used to maintain alignment whilst relaxing.
1731
@end deffn
1732
@deffn {} BFD_RELOC_V850_LO16_SPLIT_OFFSET
1733
This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
1734
instructions.
1735
@end deffn
1736
@deffn {} BFD_RELOC_MN10300_32_PCREL
1737
This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
1738
instruction.
1739
@end deffn
1740
@deffn {} BFD_RELOC_MN10300_16_PCREL
1741
This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
1742
instruction.
1743
@end deffn
1744
@deffn {} BFD_RELOC_TIC30_LDP
1745
This is a 8bit DP reloc for the tms320c30, where the most
1746
significant 8 bits of a 24 bit word are placed into the least
1747
significant 8 bits of the opcode.
1748
@end deffn
1749
@deffn {} BFD_RELOC_TIC54X_PARTLS7
1750
This is a 7bit reloc for the tms320c54x, where the least
1751
significant 7 bits of a 16 bit word are placed into the least
1752
significant 7 bits of the opcode.
1753
@end deffn
1754
@deffn {} BFD_RELOC_TIC54X_PARTMS9
1755
This is a 9bit DP reloc for the tms320c54x, where the most
1756
significant 9 bits of a 16 bit word are placed into the least
1757
significant 9 bits of the opcode.
1758
@end deffn
1759
@deffn {} BFD_RELOC_TIC54X_23
1760
This is an extended address 23-bit reloc for the tms320c54x.
1761
@end deffn
1762
@deffn {} BFD_RELOC_TIC54X_16_OF_23
1763
This is a 16-bit reloc for the tms320c54x, where the least
1764
significant 16 bits of a 23-bit extended address are placed into
1765
the opcode.
1766
@end deffn
1767
@deffn {} BFD_RELOC_TIC54X_MS7_OF_23
1768
This is a reloc for the tms320c54x, where the most
1769
significant 7 bits of a 23-bit extended address are placed into
1770
the opcode.
1771
@end deffn
1772
@deffn {} BFD_RELOC_FR30_48
1773
This is a 48 bit reloc for the FR30 that stores 32 bits.
1774
@end deffn
1775
@deffn {} BFD_RELOC_FR30_20
1776
This is a 32 bit reloc for the FR30 that stores 20 bits split up into
1777
two sections.
1778
@end deffn
1779
@deffn {} BFD_RELOC_FR30_6_IN_4
1780
This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
1781
4 bits.
1782
@end deffn
1783
@deffn {} BFD_RELOC_FR30_8_IN_8
1784
This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
1785
into 8 bits.
1786
@end deffn
1787
@deffn {} BFD_RELOC_FR30_9_IN_8
1788
This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
1789
into 8 bits.
1790
@end deffn
1791
@deffn {} BFD_RELOC_FR30_10_IN_8
1792
This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
1793
into 8 bits.
1794
@end deffn
1795
@deffn {} BFD_RELOC_FR30_9_PCREL
1796
This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
1797
short offset into 8 bits.
1798
@end deffn
1799
@deffn {} BFD_RELOC_FR30_12_PCREL
1800
This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
1801
short offset into 11 bits.
1802
@end deffn
1803
@deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4
1804
@deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2
1805
@deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2
1806
@deffnx {} BFD_RELOC_MCORE_PCREL_32
1807
@deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
1808
@deffnx {} BFD_RELOC_MCORE_RVA
1809
Motorola Mcore relocations.
1810
@end deffn
1811
@deffn {} BFD_RELOC_MEP_8
1812
@deffnx {} BFD_RELOC_MEP_16
1813
@deffnx {} BFD_RELOC_MEP_32
1814
@deffnx {} BFD_RELOC_MEP_PCREL8A2
1815
@deffnx {} BFD_RELOC_MEP_PCREL12A2
1816
@deffnx {} BFD_RELOC_MEP_PCREL17A2
1817
@deffnx {} BFD_RELOC_MEP_PCREL24A2
1818
@deffnx {} BFD_RELOC_MEP_PCABS24A2
1819
@deffnx {} BFD_RELOC_MEP_LOW16
1820
@deffnx {} BFD_RELOC_MEP_HI16U
1821
@deffnx {} BFD_RELOC_MEP_HI16S
1822
@deffnx {} BFD_RELOC_MEP_GPREL
1823
@deffnx {} BFD_RELOC_MEP_TPREL
1824
@deffnx {} BFD_RELOC_MEP_TPREL7
1825
@deffnx {} BFD_RELOC_MEP_TPREL7A2
1826
@deffnx {} BFD_RELOC_MEP_TPREL7A4
1827
@deffnx {} BFD_RELOC_MEP_UIMM24
1828
@deffnx {} BFD_RELOC_MEP_ADDR24A4
1829
@deffnx {} BFD_RELOC_MEP_GNU_VTINHERIT
1830
@deffnx {} BFD_RELOC_MEP_GNU_VTENTRY
1831
Toshiba Media Processor Relocations.
1832
@end deffn
1833
@deffn {} BFD_RELOC_MMIX_GETA
1834
@deffnx {} BFD_RELOC_MMIX_GETA_1
1835
@deffnx {} BFD_RELOC_MMIX_GETA_2
1836
@deffnx {} BFD_RELOC_MMIX_GETA_3
1837
These are relocations for the GETA instruction.
1838
@end deffn
1839
@deffn {} BFD_RELOC_MMIX_CBRANCH
1840
@deffnx {} BFD_RELOC_MMIX_CBRANCH_J
1841
@deffnx {} BFD_RELOC_MMIX_CBRANCH_1
1842
@deffnx {} BFD_RELOC_MMIX_CBRANCH_2
1843
@deffnx {} BFD_RELOC_MMIX_CBRANCH_3
1844
These are relocations for a conditional branch instruction.
1845
@end deffn
1846
@deffn {} BFD_RELOC_MMIX_PUSHJ
1847
@deffnx {} BFD_RELOC_MMIX_PUSHJ_1
1848
@deffnx {} BFD_RELOC_MMIX_PUSHJ_2
1849
@deffnx {} BFD_RELOC_MMIX_PUSHJ_3
1850
@deffnx {} BFD_RELOC_MMIX_PUSHJ_STUBBABLE
1851
These are relocations for the PUSHJ instruction.
1852
@end deffn
1853
@deffn {} BFD_RELOC_MMIX_JMP
1854
@deffnx {} BFD_RELOC_MMIX_JMP_1
1855
@deffnx {} BFD_RELOC_MMIX_JMP_2
1856
@deffnx {} BFD_RELOC_MMIX_JMP_3
1857
These are relocations for the JMP instruction.
1858
@end deffn
1859
@deffn {} BFD_RELOC_MMIX_ADDR19
1860
This is a relocation for a relative address as in a GETA instruction or
1861
a branch.
1862
@end deffn
1863
@deffn {} BFD_RELOC_MMIX_ADDR27
1864
This is a relocation for a relative address as in a JMP instruction.
1865
@end deffn
1866
@deffn {} BFD_RELOC_MMIX_REG_OR_BYTE
1867
This is a relocation for an instruction field that may be a general
1868
register or a value 0..255.
1869
@end deffn
1870
@deffn {} BFD_RELOC_MMIX_REG
1871
This is a relocation for an instruction field that may be a general
1872
register.
1873
@end deffn
1874
@deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET
1875
This is a relocation for two instruction fields holding a register and
1876
an offset, the equivalent of the relocation.
1877
@end deffn
1878
@deffn {} BFD_RELOC_MMIX_LOCAL
1879
This relocation is an assertion that the expression is not allocated as
1880
a global register.  It does not modify contents.
1881
@end deffn
1882
@deffn {} BFD_RELOC_AVR_7_PCREL
1883
This is a 16 bit reloc for the AVR that stores 8 bit pc relative
1884
short offset into 7 bits.
1885
@end deffn
1886
@deffn {} BFD_RELOC_AVR_13_PCREL
1887
This is a 16 bit reloc for the AVR that stores 13 bit pc relative
1888
short offset into 12 bits.
1889
@end deffn
1890
@deffn {} BFD_RELOC_AVR_16_PM
1891
This is a 16 bit reloc for the AVR that stores 17 bit value (usually
1892
program memory address) into 16 bits.
1893
@end deffn
1894
@deffn {} BFD_RELOC_AVR_LO8_LDI
1895
This is a 16 bit reloc for the AVR that stores 8 bit value (usually
1896
data memory address) into 8 bit immediate value of LDI insn.
1897
@end deffn
1898
@deffn {} BFD_RELOC_AVR_HI8_LDI
1899
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1900
of data memory address) into 8 bit immediate value of LDI insn.
1901
@end deffn
1902
@deffn {} BFD_RELOC_AVR_HH8_LDI
1903
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1904
of program memory address) into 8 bit immediate value of LDI insn.
1905
@end deffn
1906
@deffn {} BFD_RELOC_AVR_MS8_LDI
1907
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1908
of 32 bit value) into 8 bit immediate value of LDI insn.
1909
@end deffn
1910
@deffn {} BFD_RELOC_AVR_LO8_LDI_NEG
1911
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1912
(usually data memory address) into 8 bit immediate value of SUBI insn.
1913
@end deffn
1914
@deffn {} BFD_RELOC_AVR_HI8_LDI_NEG
1915
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1916
(high 8 bit of data memory address) into 8 bit immediate value of
1917
SUBI insn.
1918
@end deffn
1919
@deffn {} BFD_RELOC_AVR_HH8_LDI_NEG
1920
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1921
(most high 8 bit of program memory address) into 8 bit immediate value
1922
of LDI or SUBI insn.
1923
@end deffn
1924
@deffn {} BFD_RELOC_AVR_MS8_LDI_NEG
1925
This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
1926
of 32 bit value) into 8 bit immediate value of LDI insn.
1927
@end deffn
1928
@deffn {} BFD_RELOC_AVR_LO8_LDI_PM
1929
This is a 16 bit reloc for the AVR that stores 8 bit value (usually
1930
command address) into 8 bit immediate value of LDI insn.
1931
@end deffn
1932
@deffn {} BFD_RELOC_AVR_LO8_LDI_GS
1933
This is a 16 bit reloc for the AVR that stores 8 bit value
1934
(command address) into 8 bit immediate value of LDI insn. If the address
1935
is beyond the 128k boundary, the linker inserts a jump stub for this reloc
1936
in the lower 128k.
1937
@end deffn
1938
@deffn {} BFD_RELOC_AVR_HI8_LDI_PM
1939
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1940
of command address) into 8 bit immediate value of LDI insn.
1941
@end deffn
1942
@deffn {} BFD_RELOC_AVR_HI8_LDI_GS
1943
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1944
of command address) into 8 bit immediate value of LDI insn.  If the address
1945
is beyond the 128k boundary, the linker inserts a jump stub for this reloc
1946
below 128k.
1947
@end deffn
1948
@deffn {} BFD_RELOC_AVR_HH8_LDI_PM
1949
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1950
of command address) into 8 bit immediate value of LDI insn.
1951
@end deffn
1952
@deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG
1953
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1954
(usually command address) into 8 bit immediate value of SUBI insn.
1955
@end deffn
1956
@deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG
1957
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1958
(high 8 bit of 16 bit command address) into 8 bit immediate value
1959
of SUBI insn.
1960
@end deffn
1961
@deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG
1962
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1963
(high 6 bit of 22 bit command address) into 8 bit immediate
1964
value of SUBI insn.
1965
@end deffn
1966
@deffn {} BFD_RELOC_AVR_CALL
1967
This is a 32 bit reloc for the AVR that stores 23 bit value
1968
into 22 bits.
1969
@end deffn
1970
@deffn {} BFD_RELOC_AVR_LDI
1971
This is a 16 bit reloc for the AVR that stores all needed bits
1972
for absolute addressing with ldi with overflow check to linktime
1973
@end deffn
1974
@deffn {} BFD_RELOC_AVR_6
1975
This is a 6 bit reloc for the AVR that stores offset for ldd/std
1976
instructions
1977
@end deffn
1978
@deffn {} BFD_RELOC_AVR_6_ADIW
1979
This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
1980
instructions
1981
@end deffn
1982
@deffn {} BFD_RELOC_390_12
1983
Direct 12 bit.
1984
@end deffn
1985
@deffn {} BFD_RELOC_390_GOT12
1986
12 bit GOT offset.
1987
@end deffn
1988
@deffn {} BFD_RELOC_390_PLT32
1989
32 bit PC relative PLT address.
1990
@end deffn
1991
@deffn {} BFD_RELOC_390_COPY
1992
Copy symbol at runtime.
1993
@end deffn
1994
@deffn {} BFD_RELOC_390_GLOB_DAT
1995
Create GOT entry.
1996
@end deffn
1997
@deffn {} BFD_RELOC_390_JMP_SLOT
1998
Create PLT entry.
1999
@end deffn
2000
@deffn {} BFD_RELOC_390_RELATIVE
2001
Adjust by program base.
2002
@end deffn
2003
@deffn {} BFD_RELOC_390_GOTPC
2004
32 bit PC relative offset to GOT.
2005
@end deffn
2006
@deffn {} BFD_RELOC_390_GOT16
2007
16 bit GOT offset.
2008
@end deffn
2009
@deffn {} BFD_RELOC_390_PC16DBL
2010
PC relative 16 bit shifted by 1.
2011
@end deffn
2012
@deffn {} BFD_RELOC_390_PLT16DBL
2013
16 bit PC rel. PLT shifted by 1.
2014
@end deffn
2015
@deffn {} BFD_RELOC_390_PC32DBL
2016
PC relative 32 bit shifted by 1.
2017
@end deffn
2018
@deffn {} BFD_RELOC_390_PLT32DBL
2019
32 bit PC rel. PLT shifted by 1.
2020
@end deffn
2021
@deffn {} BFD_RELOC_390_GOTPCDBL
2022
32 bit PC rel. GOT shifted by 1.
2023
@end deffn
2024
@deffn {} BFD_RELOC_390_GOT64
2025
64 bit GOT offset.
2026
@end deffn
2027
@deffn {} BFD_RELOC_390_PLT64
2028
64 bit PC relative PLT address.
2029
@end deffn
2030
@deffn {} BFD_RELOC_390_GOTENT
2031
32 bit rel. offset to GOT entry.
2032
@end deffn
2033
@deffn {} BFD_RELOC_390_GOTOFF64
2034
64 bit offset to GOT.
2035
@end deffn
2036
@deffn {} BFD_RELOC_390_GOTPLT12
2037
12-bit offset to symbol-entry within GOT, with PLT handling.
2038
@end deffn
2039
@deffn {} BFD_RELOC_390_GOTPLT16
2040
16-bit offset to symbol-entry within GOT, with PLT handling.
2041
@end deffn
2042
@deffn {} BFD_RELOC_390_GOTPLT32
2043
32-bit offset to symbol-entry within GOT, with PLT handling.
2044
@end deffn
2045
@deffn {} BFD_RELOC_390_GOTPLT64
2046
64-bit offset to symbol-entry within GOT, with PLT handling.
2047
@end deffn
2048
@deffn {} BFD_RELOC_390_GOTPLTENT
2049
32-bit rel. offset to symbol-entry within GOT, with PLT handling.
2050
@end deffn
2051
@deffn {} BFD_RELOC_390_PLTOFF16
2052
16-bit rel. offset from the GOT to a PLT entry.
2053
@end deffn
2054
@deffn {} BFD_RELOC_390_PLTOFF32
2055
32-bit rel. offset from the GOT to a PLT entry.
2056
@end deffn
2057
@deffn {} BFD_RELOC_390_PLTOFF64
2058
64-bit rel. offset from the GOT to a PLT entry.
2059
@end deffn
2060
@deffn {} BFD_RELOC_390_TLS_LOAD
2061
@deffnx {} BFD_RELOC_390_TLS_GDCALL
2062
@deffnx {} BFD_RELOC_390_TLS_LDCALL
2063
@deffnx {} BFD_RELOC_390_TLS_GD32
2064
@deffnx {} BFD_RELOC_390_TLS_GD64
2065
@deffnx {} BFD_RELOC_390_TLS_GOTIE12
2066
@deffnx {} BFD_RELOC_390_TLS_GOTIE32
2067
@deffnx {} BFD_RELOC_390_TLS_GOTIE64
2068
@deffnx {} BFD_RELOC_390_TLS_LDM32
2069
@deffnx {} BFD_RELOC_390_TLS_LDM64
2070
@deffnx {} BFD_RELOC_390_TLS_IE32
2071
@deffnx {} BFD_RELOC_390_TLS_IE64
2072
@deffnx {} BFD_RELOC_390_TLS_IEENT
2073
@deffnx {} BFD_RELOC_390_TLS_LE32
2074
@deffnx {} BFD_RELOC_390_TLS_LE64
2075
@deffnx {} BFD_RELOC_390_TLS_LDO32
2076
@deffnx {} BFD_RELOC_390_TLS_LDO64
2077
@deffnx {} BFD_RELOC_390_TLS_DTPMOD
2078
@deffnx {} BFD_RELOC_390_TLS_DTPOFF
2079
@deffnx {} BFD_RELOC_390_TLS_TPOFF
2080
s390 tls relocations.
2081
@end deffn
2082
@deffn {} BFD_RELOC_390_20
2083
@deffnx {} BFD_RELOC_390_GOT20
2084
@deffnx {} BFD_RELOC_390_GOTPLT20
2085
@deffnx {} BFD_RELOC_390_TLS_GOTIE20
2086
Long displacement extension.
2087
@end deffn
2088
@deffn {} BFD_RELOC_SCORE_GPREL15
2089
Score relocations
2090
Low 16 bit for load/store
2091
@end deffn
2092
@deffn {} BFD_RELOC_SCORE_DUMMY2
2093
@deffnx {} BFD_RELOC_SCORE_JMP
2094
This is a 24-bit reloc with the right 1 bit assumed to be 0
2095
@end deffn
2096
@deffn {} BFD_RELOC_SCORE_BRANCH
2097
This is a 19-bit reloc with the right 1 bit assumed to be 0
2098
@end deffn
2099
@deffn {} BFD_RELOC_SCORE_IMM30
2100
This is a 32-bit reloc for 48-bit instructions.
2101
@end deffn
2102
@deffn {} BFD_RELOC_SCORE_IMM32
2103
This is a 32-bit reloc for 48-bit instructions.
2104
@end deffn
2105
@deffn {} BFD_RELOC_SCORE16_JMP
2106
This is a 11-bit reloc with the right 1 bit assumed to be 0
2107
@end deffn
2108
@deffn {} BFD_RELOC_SCORE16_BRANCH
2109
This is a 8-bit reloc with the right 1 bit assumed to be 0
2110
@end deffn
2111
@deffn {} BFD_RELOC_SCORE_BCMP
2112
This is a 9-bit reloc with the right 1 bit assumed to be 0
2113
@end deffn
2114
@deffn {} BFD_RELOC_SCORE_GOT15
2115
@deffnx {} BFD_RELOC_SCORE_GOT_LO16
2116
@deffnx {} BFD_RELOC_SCORE_CALL15
2117
@deffnx {} BFD_RELOC_SCORE_DUMMY_HI16
2118
Undocumented Score relocs
2119
@end deffn
2120
@deffn {} BFD_RELOC_IP2K_FR9
2121
Scenix IP2K - 9-bit register number / data address
2122
@end deffn
2123
@deffn {} BFD_RELOC_IP2K_BANK
2124
Scenix IP2K - 4-bit register/data bank number
2125
@end deffn
2126
@deffn {} BFD_RELOC_IP2K_ADDR16CJP
2127
Scenix IP2K - low 13 bits of instruction word address
2128
@end deffn
2129
@deffn {} BFD_RELOC_IP2K_PAGE3
2130
Scenix IP2K - high 3 bits of instruction word address
2131
@end deffn
2132
@deffn {} BFD_RELOC_IP2K_LO8DATA
2133
@deffnx {} BFD_RELOC_IP2K_HI8DATA
2134
@deffnx {} BFD_RELOC_IP2K_EX8DATA
2135
Scenix IP2K - ext/low/high 8 bits of data address
2136
@end deffn
2137
@deffn {} BFD_RELOC_IP2K_LO8INSN
2138
@deffnx {} BFD_RELOC_IP2K_HI8INSN
2139
Scenix IP2K - low/high 8 bits of instruction word address
2140
@end deffn
2141
@deffn {} BFD_RELOC_IP2K_PC_SKIP
2142
Scenix IP2K - even/odd PC modifier to modify snb pcl.0
2143
@end deffn
2144
@deffn {} BFD_RELOC_IP2K_TEXT
2145
Scenix IP2K - 16 bit word address in text section.
2146
@end deffn
2147
@deffn {} BFD_RELOC_IP2K_FR_OFFSET
2148
Scenix IP2K - 7-bit sp or dp offset
2149
@end deffn
2150
@deffn {} BFD_RELOC_VPE4KMATH_DATA
2151
@deffnx {} BFD_RELOC_VPE4KMATH_INSN
2152
Scenix VPE4K coprocessor - data/insn-space addressing
2153
@end deffn
2154
@deffn {} BFD_RELOC_VTABLE_INHERIT
2155
@deffnx {} BFD_RELOC_VTABLE_ENTRY
2156
These two relocations are used by the linker to determine which of
2157
the entries in a C++ virtual function table are actually used.  When
2158
the --gc-sections option is given, the linker will zero out the entries
2159
that are not used, so that the code for those functions need not be
2160
included in the output.
2161
 
2162
VTABLE_INHERIT is a zero-space relocation used to describe to the
2163
linker the inheritance tree of a C++ virtual function table.  The
2164
relocation's symbol should be the parent class' vtable, and the
2165
relocation should be located at the child vtable.
2166
 
2167
VTABLE_ENTRY is a zero-space relocation that describes the use of a
2168
virtual function table entry.  The reloc's symbol should refer to the
2169
table of the class mentioned in the code.  Off of that base, an offset
2170
describes the entry that is being used.  For Rela hosts, this offset
2171
is stored in the reloc's addend.  For Rel hosts, we are forced to put
2172
this offset in the reloc's section offset.
2173
@end deffn
2174
@deffn {} BFD_RELOC_IA64_IMM14
2175
@deffnx {} BFD_RELOC_IA64_IMM22
2176
@deffnx {} BFD_RELOC_IA64_IMM64
2177
@deffnx {} BFD_RELOC_IA64_DIR32MSB
2178
@deffnx {} BFD_RELOC_IA64_DIR32LSB
2179
@deffnx {} BFD_RELOC_IA64_DIR64MSB
2180
@deffnx {} BFD_RELOC_IA64_DIR64LSB
2181
@deffnx {} BFD_RELOC_IA64_GPREL22
2182
@deffnx {} BFD_RELOC_IA64_GPREL64I
2183
@deffnx {} BFD_RELOC_IA64_GPREL32MSB
2184
@deffnx {} BFD_RELOC_IA64_GPREL32LSB
2185
@deffnx {} BFD_RELOC_IA64_GPREL64MSB
2186
@deffnx {} BFD_RELOC_IA64_GPREL64LSB
2187
@deffnx {} BFD_RELOC_IA64_LTOFF22
2188
@deffnx {} BFD_RELOC_IA64_LTOFF64I
2189
@deffnx {} BFD_RELOC_IA64_PLTOFF22
2190
@deffnx {} BFD_RELOC_IA64_PLTOFF64I
2191
@deffnx {} BFD_RELOC_IA64_PLTOFF64MSB
2192
@deffnx {} BFD_RELOC_IA64_PLTOFF64LSB
2193
@deffnx {} BFD_RELOC_IA64_FPTR64I
2194
@deffnx {} BFD_RELOC_IA64_FPTR32MSB
2195
@deffnx {} BFD_RELOC_IA64_FPTR32LSB
2196
@deffnx {} BFD_RELOC_IA64_FPTR64MSB
2197
@deffnx {} BFD_RELOC_IA64_FPTR64LSB
2198
@deffnx {} BFD_RELOC_IA64_PCREL21B
2199
@deffnx {} BFD_RELOC_IA64_PCREL21BI
2200
@deffnx {} BFD_RELOC_IA64_PCREL21M
2201
@deffnx {} BFD_RELOC_IA64_PCREL21F
2202
@deffnx {} BFD_RELOC_IA64_PCREL22
2203
@deffnx {} BFD_RELOC_IA64_PCREL60B
2204
@deffnx {} BFD_RELOC_IA64_PCREL64I
2205
@deffnx {} BFD_RELOC_IA64_PCREL32MSB
2206
@deffnx {} BFD_RELOC_IA64_PCREL32LSB
2207
@deffnx {} BFD_RELOC_IA64_PCREL64MSB
2208
@deffnx {} BFD_RELOC_IA64_PCREL64LSB
2209
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22
2210
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I
2211
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB
2212
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB
2213
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB
2214
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB
2215
@deffnx {} BFD_RELOC_IA64_SEGREL32MSB
2216
@deffnx {} BFD_RELOC_IA64_SEGREL32LSB
2217
@deffnx {} BFD_RELOC_IA64_SEGREL64MSB
2218
@deffnx {} BFD_RELOC_IA64_SEGREL64LSB
2219
@deffnx {} BFD_RELOC_IA64_SECREL32MSB
2220
@deffnx {} BFD_RELOC_IA64_SECREL32LSB
2221
@deffnx {} BFD_RELOC_IA64_SECREL64MSB
2222
@deffnx {} BFD_RELOC_IA64_SECREL64LSB
2223
@deffnx {} BFD_RELOC_IA64_REL32MSB
2224
@deffnx {} BFD_RELOC_IA64_REL32LSB
2225
@deffnx {} BFD_RELOC_IA64_REL64MSB
2226
@deffnx {} BFD_RELOC_IA64_REL64LSB
2227
@deffnx {} BFD_RELOC_IA64_LTV32MSB
2228
@deffnx {} BFD_RELOC_IA64_LTV32LSB
2229
@deffnx {} BFD_RELOC_IA64_LTV64MSB
2230
@deffnx {} BFD_RELOC_IA64_LTV64LSB
2231
@deffnx {} BFD_RELOC_IA64_IPLTMSB
2232
@deffnx {} BFD_RELOC_IA64_IPLTLSB
2233
@deffnx {} BFD_RELOC_IA64_COPY
2234
@deffnx {} BFD_RELOC_IA64_LTOFF22X
2235
@deffnx {} BFD_RELOC_IA64_LDXMOV
2236
@deffnx {} BFD_RELOC_IA64_TPREL14
2237
@deffnx {} BFD_RELOC_IA64_TPREL22
2238
@deffnx {} BFD_RELOC_IA64_TPREL64I
2239
@deffnx {} BFD_RELOC_IA64_TPREL64MSB
2240
@deffnx {} BFD_RELOC_IA64_TPREL64LSB
2241
@deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22
2242
@deffnx {} BFD_RELOC_IA64_DTPMOD64MSB
2243
@deffnx {} BFD_RELOC_IA64_DTPMOD64LSB
2244
@deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22
2245
@deffnx {} BFD_RELOC_IA64_DTPREL14
2246
@deffnx {} BFD_RELOC_IA64_DTPREL22
2247
@deffnx {} BFD_RELOC_IA64_DTPREL64I
2248
@deffnx {} BFD_RELOC_IA64_DTPREL32MSB
2249
@deffnx {} BFD_RELOC_IA64_DTPREL32LSB
2250
@deffnx {} BFD_RELOC_IA64_DTPREL64MSB
2251
@deffnx {} BFD_RELOC_IA64_DTPREL64LSB
2252
@deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22
2253
Intel IA64 Relocations.
2254
@end deffn
2255
@deffn {} BFD_RELOC_M68HC11_HI8
2256
Motorola 68HC11 reloc.
2257
This is the 8 bit high part of an absolute address.
2258
@end deffn
2259
@deffn {} BFD_RELOC_M68HC11_LO8
2260
Motorola 68HC11 reloc.
2261
This is the 8 bit low part of an absolute address.
2262
@end deffn
2263
@deffn {} BFD_RELOC_M68HC11_3B
2264
Motorola 68HC11 reloc.
2265
This is the 3 bit of a value.
2266
@end deffn
2267
@deffn {} BFD_RELOC_M68HC11_RL_JUMP
2268
Motorola 68HC11 reloc.
2269
This reloc marks the beginning of a jump/call instruction.
2270
It is used for linker relaxation to correctly identify beginning
2271
of instruction and change some branches to use PC-relative
2272
addressing mode.
2273
@end deffn
2274
@deffn {} BFD_RELOC_M68HC11_RL_GROUP
2275
Motorola 68HC11 reloc.
2276
This reloc marks a group of several instructions that gcc generates
2277
and for which the linker relaxation pass can modify and/or remove
2278
some of them.
2279
@end deffn
2280
@deffn {} BFD_RELOC_M68HC11_LO16
2281
Motorola 68HC11 reloc.
2282
This is the 16-bit lower part of an address.  It is used for 'call'
2283
instruction to specify the symbol address without any special
2284
transformation (due to memory bank window).
2285
@end deffn
2286
@deffn {} BFD_RELOC_M68HC11_PAGE
2287
Motorola 68HC11 reloc.
2288
This is a 8-bit reloc that specifies the page number of an address.
2289
It is used by 'call' instruction to specify the page number of
2290
the symbol.
2291
@end deffn
2292
@deffn {} BFD_RELOC_M68HC11_24
2293
Motorola 68HC11 reloc.
2294
This is a 24-bit reloc that represents the address with a 16-bit
2295
value and a 8-bit page number.  The symbol address is transformed
2296
to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
2297
@end deffn
2298
@deffn {} BFD_RELOC_M68HC12_5B
2299
Motorola 68HC12 reloc.
2300
This is the 5 bits of a value.
2301
@end deffn
2302
@deffn {} BFD_RELOC_16C_NUM08
2303
@deffnx {} BFD_RELOC_16C_NUM08_C
2304
@deffnx {} BFD_RELOC_16C_NUM16
2305
@deffnx {} BFD_RELOC_16C_NUM16_C
2306
@deffnx {} BFD_RELOC_16C_NUM32
2307
@deffnx {} BFD_RELOC_16C_NUM32_C
2308
@deffnx {} BFD_RELOC_16C_DISP04
2309
@deffnx {} BFD_RELOC_16C_DISP04_C
2310
@deffnx {} BFD_RELOC_16C_DISP08
2311
@deffnx {} BFD_RELOC_16C_DISP08_C
2312
@deffnx {} BFD_RELOC_16C_DISP16
2313
@deffnx {} BFD_RELOC_16C_DISP16_C
2314
@deffnx {} BFD_RELOC_16C_DISP24
2315
@deffnx {} BFD_RELOC_16C_DISP24_C
2316
@deffnx {} BFD_RELOC_16C_DISP24a
2317
@deffnx {} BFD_RELOC_16C_DISP24a_C
2318
@deffnx {} BFD_RELOC_16C_REG04
2319
@deffnx {} BFD_RELOC_16C_REG04_C
2320
@deffnx {} BFD_RELOC_16C_REG04a
2321
@deffnx {} BFD_RELOC_16C_REG04a_C
2322
@deffnx {} BFD_RELOC_16C_REG14
2323
@deffnx {} BFD_RELOC_16C_REG14_C
2324
@deffnx {} BFD_RELOC_16C_REG16
2325
@deffnx {} BFD_RELOC_16C_REG16_C
2326
@deffnx {} BFD_RELOC_16C_REG20
2327
@deffnx {} BFD_RELOC_16C_REG20_C
2328
@deffnx {} BFD_RELOC_16C_ABS20
2329
@deffnx {} BFD_RELOC_16C_ABS20_C
2330
@deffnx {} BFD_RELOC_16C_ABS24
2331
@deffnx {} BFD_RELOC_16C_ABS24_C
2332
@deffnx {} BFD_RELOC_16C_IMM04
2333
@deffnx {} BFD_RELOC_16C_IMM04_C
2334
@deffnx {} BFD_RELOC_16C_IMM16
2335
@deffnx {} BFD_RELOC_16C_IMM16_C
2336
@deffnx {} BFD_RELOC_16C_IMM20
2337
@deffnx {} BFD_RELOC_16C_IMM20_C
2338
@deffnx {} BFD_RELOC_16C_IMM24
2339
@deffnx {} BFD_RELOC_16C_IMM24_C
2340
@deffnx {} BFD_RELOC_16C_IMM32
2341
@deffnx {} BFD_RELOC_16C_IMM32_C
2342
NS CR16C Relocations.
2343
@end deffn
2344
@deffn {} BFD_RELOC_CR16_NUM8
2345
@deffnx {} BFD_RELOC_CR16_NUM16
2346
@deffnx {} BFD_RELOC_CR16_NUM32
2347
@deffnx {} BFD_RELOC_CR16_NUM32a
2348
@deffnx {} BFD_RELOC_CR16_REGREL0
2349
@deffnx {} BFD_RELOC_CR16_REGREL4
2350
@deffnx {} BFD_RELOC_CR16_REGREL4a
2351
@deffnx {} BFD_RELOC_CR16_REGREL14
2352
@deffnx {} BFD_RELOC_CR16_REGREL14a
2353
@deffnx {} BFD_RELOC_CR16_REGREL16
2354
@deffnx {} BFD_RELOC_CR16_REGREL20
2355
@deffnx {} BFD_RELOC_CR16_REGREL20a
2356
@deffnx {} BFD_RELOC_CR16_ABS20
2357
@deffnx {} BFD_RELOC_CR16_ABS24
2358
@deffnx {} BFD_RELOC_CR16_IMM4
2359
@deffnx {} BFD_RELOC_CR16_IMM8
2360
@deffnx {} BFD_RELOC_CR16_IMM16
2361
@deffnx {} BFD_RELOC_CR16_IMM20
2362
@deffnx {} BFD_RELOC_CR16_IMM24
2363
@deffnx {} BFD_RELOC_CR16_IMM32
2364
@deffnx {} BFD_RELOC_CR16_IMM32a
2365
@deffnx {} BFD_RELOC_CR16_DISP4
2366
@deffnx {} BFD_RELOC_CR16_DISP8
2367
@deffnx {} BFD_RELOC_CR16_DISP16
2368
@deffnx {} BFD_RELOC_CR16_DISP20
2369
@deffnx {} BFD_RELOC_CR16_DISP24
2370
@deffnx {} BFD_RELOC_CR16_DISP24a
2371
@deffnx {} BFD_RELOC_CR16_SWITCH8
2372
@deffnx {} BFD_RELOC_CR16_SWITCH16
2373
@deffnx {} BFD_RELOC_CR16_SWITCH32
2374
@deffnx {} BFD_RELOC_CR16_GOT_REGREL20
2375
@deffnx {} BFD_RELOC_CR16_GOTC_REGREL20
2376
@deffnx {} BFD_RELOC_CR16_GLOB_DAT
2377
NS CR16 Relocations.
2378
@end deffn
2379
@deffn {} BFD_RELOC_CRX_REL4
2380
@deffnx {} BFD_RELOC_CRX_REL8
2381
@deffnx {} BFD_RELOC_CRX_REL8_CMP
2382
@deffnx {} BFD_RELOC_CRX_REL16
2383
@deffnx {} BFD_RELOC_CRX_REL24
2384
@deffnx {} BFD_RELOC_CRX_REL32
2385
@deffnx {} BFD_RELOC_CRX_REGREL12
2386
@deffnx {} BFD_RELOC_CRX_REGREL22
2387
@deffnx {} BFD_RELOC_CRX_REGREL28
2388
@deffnx {} BFD_RELOC_CRX_REGREL32
2389
@deffnx {} BFD_RELOC_CRX_ABS16
2390
@deffnx {} BFD_RELOC_CRX_ABS32
2391
@deffnx {} BFD_RELOC_CRX_NUM8
2392
@deffnx {} BFD_RELOC_CRX_NUM16
2393
@deffnx {} BFD_RELOC_CRX_NUM32
2394
@deffnx {} BFD_RELOC_CRX_IMM16
2395
@deffnx {} BFD_RELOC_CRX_IMM32
2396
@deffnx {} BFD_RELOC_CRX_SWITCH8
2397
@deffnx {} BFD_RELOC_CRX_SWITCH16
2398
@deffnx {} BFD_RELOC_CRX_SWITCH32
2399
NS CRX Relocations.
2400
@end deffn
2401
@deffn {} BFD_RELOC_CRIS_BDISP8
2402
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_5
2403
@deffnx {} BFD_RELOC_CRIS_SIGNED_6
2404
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_6
2405
@deffnx {} BFD_RELOC_CRIS_SIGNED_8
2406
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_8
2407
@deffnx {} BFD_RELOC_CRIS_SIGNED_16
2408
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_16
2409
@deffnx {} BFD_RELOC_CRIS_LAPCQ_OFFSET
2410
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_4
2411
These relocs are only used within the CRIS assembler.  They are not
2412
(at present) written to any object files.
2413
@end deffn
2414
@deffn {} BFD_RELOC_CRIS_COPY
2415
@deffnx {} BFD_RELOC_CRIS_GLOB_DAT
2416
@deffnx {} BFD_RELOC_CRIS_JUMP_SLOT
2417
@deffnx {} BFD_RELOC_CRIS_RELATIVE
2418
Relocs used in ELF shared libraries for CRIS.
2419
@end deffn
2420
@deffn {} BFD_RELOC_CRIS_32_GOT
2421
32-bit offset to symbol-entry within GOT.
2422
@end deffn
2423
@deffn {} BFD_RELOC_CRIS_16_GOT
2424
16-bit offset to symbol-entry within GOT.
2425
@end deffn
2426
@deffn {} BFD_RELOC_CRIS_32_GOTPLT
2427
32-bit offset to symbol-entry within GOT, with PLT handling.
2428
@end deffn
2429
@deffn {} BFD_RELOC_CRIS_16_GOTPLT
2430
16-bit offset to symbol-entry within GOT, with PLT handling.
2431
@end deffn
2432
@deffn {} BFD_RELOC_CRIS_32_GOTREL
2433
32-bit offset to symbol, relative to GOT.
2434
@end deffn
2435
@deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL
2436
32-bit offset to symbol with PLT entry, relative to GOT.
2437
@end deffn
2438
@deffn {} BFD_RELOC_CRIS_32_PLT_PCREL
2439
32-bit offset to symbol with PLT entry, relative to this relocation.
2440
@end deffn
2441
@deffn {} BFD_RELOC_CRIS_32_GOT_GD
2442
@deffnx {} BFD_RELOC_CRIS_16_GOT_GD
2443
@deffnx {} BFD_RELOC_CRIS_32_GD
2444
@deffnx {} BFD_RELOC_CRIS_DTP
2445
@deffnx {} BFD_RELOC_CRIS_32_DTPREL
2446
@deffnx {} BFD_RELOC_CRIS_16_DTPREL
2447
@deffnx {} BFD_RELOC_CRIS_32_GOT_TPREL
2448
@deffnx {} BFD_RELOC_CRIS_16_GOT_TPREL
2449
@deffnx {} BFD_RELOC_CRIS_32_TPREL
2450
@deffnx {} BFD_RELOC_CRIS_16_TPREL
2451
@deffnx {} BFD_RELOC_CRIS_DTPMOD
2452
@deffnx {} BFD_RELOC_CRIS_32_IE
2453
Relocs used in TLS code for CRIS.
2454
@end deffn
2455
@deffn {} BFD_RELOC_860_COPY
2456
@deffnx {} BFD_RELOC_860_GLOB_DAT
2457
@deffnx {} BFD_RELOC_860_JUMP_SLOT
2458
@deffnx {} BFD_RELOC_860_RELATIVE
2459
@deffnx {} BFD_RELOC_860_PC26
2460
@deffnx {} BFD_RELOC_860_PLT26
2461
@deffnx {} BFD_RELOC_860_PC16
2462
@deffnx {} BFD_RELOC_860_LOW0
2463
@deffnx {} BFD_RELOC_860_SPLIT0
2464
@deffnx {} BFD_RELOC_860_LOW1
2465
@deffnx {} BFD_RELOC_860_SPLIT1
2466
@deffnx {} BFD_RELOC_860_LOW2
2467
@deffnx {} BFD_RELOC_860_SPLIT2
2468
@deffnx {} BFD_RELOC_860_LOW3
2469
@deffnx {} BFD_RELOC_860_LOGOT0
2470
@deffnx {} BFD_RELOC_860_SPGOT0
2471
@deffnx {} BFD_RELOC_860_LOGOT1
2472
@deffnx {} BFD_RELOC_860_SPGOT1
2473
@deffnx {} BFD_RELOC_860_LOGOTOFF0
2474
@deffnx {} BFD_RELOC_860_SPGOTOFF0
2475
@deffnx {} BFD_RELOC_860_LOGOTOFF1
2476
@deffnx {} BFD_RELOC_860_SPGOTOFF1
2477
@deffnx {} BFD_RELOC_860_LOGOTOFF2
2478
@deffnx {} BFD_RELOC_860_LOGOTOFF3
2479
@deffnx {} BFD_RELOC_860_LOPC
2480
@deffnx {} BFD_RELOC_860_HIGHADJ
2481
@deffnx {} BFD_RELOC_860_HAGOT
2482
@deffnx {} BFD_RELOC_860_HAGOTOFF
2483
@deffnx {} BFD_RELOC_860_HAPC
2484
@deffnx {} BFD_RELOC_860_HIGH
2485
@deffnx {} BFD_RELOC_860_HIGOT
2486
@deffnx {} BFD_RELOC_860_HIGOTOFF
2487
Intel i860 Relocations.
2488
@end deffn
2489
@deffn {} BFD_RELOC_OPENRISC_ABS_26
2490
@deffnx {} BFD_RELOC_OPENRISC_REL_26
2491
OpenRISC Relocations.
2492
@end deffn
2493
@deffn {} BFD_RELOC_H8_DIR16A8
2494
@deffnx {} BFD_RELOC_H8_DIR16R8
2495
@deffnx {} BFD_RELOC_H8_DIR24A8
2496
@deffnx {} BFD_RELOC_H8_DIR24R8
2497
@deffnx {} BFD_RELOC_H8_DIR32A16
2498
H8 elf Relocations.
2499
@end deffn
2500
@deffn {} BFD_RELOC_XSTORMY16_REL_12
2501
@deffnx {} BFD_RELOC_XSTORMY16_12
2502
@deffnx {} BFD_RELOC_XSTORMY16_24
2503
@deffnx {} BFD_RELOC_XSTORMY16_FPTR16
2504
Sony Xstormy16 Relocations.
2505
@end deffn
2506
@deffn {} BFD_RELOC_RELC
2507
Self-describing complex relocations.
2508
@end deffn
2509
@deffn {} BFD_RELOC_XC16X_PAG
2510
@deffnx {} BFD_RELOC_XC16X_POF
2511
@deffnx {} BFD_RELOC_XC16X_SEG
2512
@deffnx {} BFD_RELOC_XC16X_SOF
2513
Infineon Relocations.
2514
@end deffn
2515
@deffn {} BFD_RELOC_VAX_GLOB_DAT
2516
@deffnx {} BFD_RELOC_VAX_JMP_SLOT
2517
@deffnx {} BFD_RELOC_VAX_RELATIVE
2518
Relocations used by VAX ELF.
2519
@end deffn
2520
@deffn {} BFD_RELOC_MT_PC16
2521
Morpho MT - 16 bit immediate relocation.
2522
@end deffn
2523
@deffn {} BFD_RELOC_MT_HI16
2524
Morpho MT - Hi 16 bits of an address.
2525
@end deffn
2526
@deffn {} BFD_RELOC_MT_LO16
2527
Morpho MT - Low 16 bits of an address.
2528
@end deffn
2529
@deffn {} BFD_RELOC_MT_GNU_VTINHERIT
2530
Morpho MT - Used to tell the linker which vtable entries are used.
2531
@end deffn
2532
@deffn {} BFD_RELOC_MT_GNU_VTENTRY
2533
Morpho MT - Used to tell the linker which vtable entries are used.
2534
@end deffn
2535
@deffn {} BFD_RELOC_MT_PCINSN8
2536
Morpho MT - 8 bit immediate relocation.
2537
@end deffn
2538
@deffn {} BFD_RELOC_MSP430_10_PCREL
2539
@deffnx {} BFD_RELOC_MSP430_16_PCREL
2540
@deffnx {} BFD_RELOC_MSP430_16
2541
@deffnx {} BFD_RELOC_MSP430_16_PCREL_BYTE
2542
@deffnx {} BFD_RELOC_MSP430_16_BYTE
2543
@deffnx {} BFD_RELOC_MSP430_2X_PCREL
2544
@deffnx {} BFD_RELOC_MSP430_RL_PCREL
2545
msp430 specific relocation codes
2546
@end deffn
2547
@deffn {} BFD_RELOC_IQ2000_OFFSET_16
2548
@deffnx {} BFD_RELOC_IQ2000_OFFSET_21
2549
@deffnx {} BFD_RELOC_IQ2000_UHI16
2550
IQ2000 Relocations.
2551
@end deffn
2552
@deffn {} BFD_RELOC_XTENSA_RTLD
2553
Special Xtensa relocation used only by PLT entries in ELF shared
2554
objects to indicate that the runtime linker should set the value
2555
to one of its own internal functions or data structures.
2556
@end deffn
2557
@deffn {} BFD_RELOC_XTENSA_GLOB_DAT
2558
@deffnx {} BFD_RELOC_XTENSA_JMP_SLOT
2559
@deffnx {} BFD_RELOC_XTENSA_RELATIVE
2560
Xtensa relocations for ELF shared objects.
2561
@end deffn
2562
@deffn {} BFD_RELOC_XTENSA_PLT
2563
Xtensa relocation used in ELF object files for symbols that may require
2564
PLT entries.  Otherwise, this is just a generic 32-bit relocation.
2565
@end deffn
2566
@deffn {} BFD_RELOC_XTENSA_DIFF8
2567
@deffnx {} BFD_RELOC_XTENSA_DIFF16
2568
@deffnx {} BFD_RELOC_XTENSA_DIFF32
2569
Xtensa relocations to mark the difference of two local symbols.
2570
These are only needed to support linker relaxation and can be ignored
2571
when not relaxing.  The field is set to the value of the difference
2572
assuming no relaxation.  The relocation encodes the position of the
2573
first symbol so the linker can determine whether to adjust the field
2574
value.
2575
@end deffn
2576
@deffn {} BFD_RELOC_XTENSA_SLOT0_OP
2577
@deffnx {} BFD_RELOC_XTENSA_SLOT1_OP
2578
@deffnx {} BFD_RELOC_XTENSA_SLOT2_OP
2579
@deffnx {} BFD_RELOC_XTENSA_SLOT3_OP
2580
@deffnx {} BFD_RELOC_XTENSA_SLOT4_OP
2581
@deffnx {} BFD_RELOC_XTENSA_SLOT5_OP
2582
@deffnx {} BFD_RELOC_XTENSA_SLOT6_OP
2583
@deffnx {} BFD_RELOC_XTENSA_SLOT7_OP
2584
@deffnx {} BFD_RELOC_XTENSA_SLOT8_OP
2585
@deffnx {} BFD_RELOC_XTENSA_SLOT9_OP
2586
@deffnx {} BFD_RELOC_XTENSA_SLOT10_OP
2587
@deffnx {} BFD_RELOC_XTENSA_SLOT11_OP
2588
@deffnx {} BFD_RELOC_XTENSA_SLOT12_OP
2589
@deffnx {} BFD_RELOC_XTENSA_SLOT13_OP
2590
@deffnx {} BFD_RELOC_XTENSA_SLOT14_OP
2591
Generic Xtensa relocations for instruction operands.  Only the slot
2592
number is encoded in the relocation.  The relocation applies to the
2593
last PC-relative immediate operand, or if there are no PC-relative
2594
immediates, to the last immediate operand.
2595
@end deffn
2596
@deffn {} BFD_RELOC_XTENSA_SLOT0_ALT
2597
@deffnx {} BFD_RELOC_XTENSA_SLOT1_ALT
2598
@deffnx {} BFD_RELOC_XTENSA_SLOT2_ALT
2599
@deffnx {} BFD_RELOC_XTENSA_SLOT3_ALT
2600
@deffnx {} BFD_RELOC_XTENSA_SLOT4_ALT
2601
@deffnx {} BFD_RELOC_XTENSA_SLOT5_ALT
2602
@deffnx {} BFD_RELOC_XTENSA_SLOT6_ALT
2603
@deffnx {} BFD_RELOC_XTENSA_SLOT7_ALT
2604
@deffnx {} BFD_RELOC_XTENSA_SLOT8_ALT
2605
@deffnx {} BFD_RELOC_XTENSA_SLOT9_ALT
2606
@deffnx {} BFD_RELOC_XTENSA_SLOT10_ALT
2607
@deffnx {} BFD_RELOC_XTENSA_SLOT11_ALT
2608
@deffnx {} BFD_RELOC_XTENSA_SLOT12_ALT
2609
@deffnx {} BFD_RELOC_XTENSA_SLOT13_ALT
2610
@deffnx {} BFD_RELOC_XTENSA_SLOT14_ALT
2611
Alternate Xtensa relocations.  Only the slot is encoded in the
2612
relocation.  The meaning of these relocations is opcode-specific.
2613
@end deffn
2614
@deffn {} BFD_RELOC_XTENSA_OP0
2615
@deffnx {} BFD_RELOC_XTENSA_OP1
2616
@deffnx {} BFD_RELOC_XTENSA_OP2
2617
Xtensa relocations for backward compatibility.  These have all been
2618
replaced by BFD_RELOC_XTENSA_SLOT0_OP.
2619
@end deffn
2620
@deffn {} BFD_RELOC_XTENSA_ASM_EXPAND
2621
Xtensa relocation to mark that the assembler expanded the
2622
instructions from an original target.  The expansion size is
2623
encoded in the reloc size.
2624
@end deffn
2625
@deffn {} BFD_RELOC_XTENSA_ASM_SIMPLIFY
2626
Xtensa relocation to mark that the linker should simplify
2627
assembler-expanded instructions.  This is commonly used
2628
internally by the linker after analysis of a
2629
BFD_RELOC_XTENSA_ASM_EXPAND.
2630
@end deffn
2631
@deffn {} BFD_RELOC_XTENSA_TLSDESC_FN
2632
@deffnx {} BFD_RELOC_XTENSA_TLSDESC_ARG
2633
@deffnx {} BFD_RELOC_XTENSA_TLS_DTPOFF
2634
@deffnx {} BFD_RELOC_XTENSA_TLS_TPOFF
2635
@deffnx {} BFD_RELOC_XTENSA_TLS_FUNC
2636
@deffnx {} BFD_RELOC_XTENSA_TLS_ARG
2637
@deffnx {} BFD_RELOC_XTENSA_TLS_CALL
2638
Xtensa TLS relocations.
2639
@end deffn
2640
@deffn {} BFD_RELOC_Z80_DISP8
2641
8 bit signed offset in (ix+d) or (iy+d).
2642
@end deffn
2643
@deffn {} BFD_RELOC_Z8K_DISP7
2644
DJNZ offset.
2645
@end deffn
2646
@deffn {} BFD_RELOC_Z8K_CALLR
2647
CALR offset.
2648
@end deffn
2649
@deffn {} BFD_RELOC_Z8K_IMM4L
2650
4 bit value.
2651
@end deffn
2652
@deffn {} BFD_RELOC_LM32_CALL
2653
@deffnx {} BFD_RELOC_LM32_BRANCH
2654
@deffnx {} BFD_RELOC_LM32_16_GOT
2655
@deffnx {} BFD_RELOC_LM32_GOTOFF_HI16
2656
@deffnx {} BFD_RELOC_LM32_GOTOFF_LO16
2657
@deffnx {} BFD_RELOC_LM32_COPY
2658
@deffnx {} BFD_RELOC_LM32_GLOB_DAT
2659
@deffnx {} BFD_RELOC_LM32_JMP_SLOT
2660
@deffnx {} BFD_RELOC_LM32_RELATIVE
2661
Lattice Mico32 relocations.
2662
@end deffn
2663
@deffn {} BFD_RELOC_MACH_O_SECTDIFF
2664
Difference between two section addreses.  Must be followed by a
2665
BFD_RELOC_MACH_O_PAIR.
2666
@end deffn
2667
@deffn {} BFD_RELOC_MACH_O_PAIR
2668
Mach-O generic relocations.
2669
@end deffn
2670
@deffn {} BFD_RELOC_MICROBLAZE_32_LO
2671
This is a 32 bit reloc for the microblaze that stores the
2672
low 16 bits of a value
2673
@end deffn
2674
@deffn {} BFD_RELOC_MICROBLAZE_32_LO_PCREL
2675
This is a 32 bit pc-relative reloc for the microblaze that
2676
stores the low 16 bits of a value
2677
@end deffn
2678
@deffn {} BFD_RELOC_MICROBLAZE_32_ROSDA
2679
This is a 32 bit reloc for the microblaze that stores a
2680
value relative to the read-only small data area anchor
2681
@end deffn
2682
@deffn {} BFD_RELOC_MICROBLAZE_32_RWSDA
2683
This is a 32 bit reloc for the microblaze that stores a
2684
value relative to the read-write small data area anchor
2685
@end deffn
2686
@deffn {} BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
2687
This is a 32 bit reloc for the microblaze to handle
2688
expressions of the form "Symbol Op Symbol"
2689
@end deffn
2690
@deffn {} BFD_RELOC_MICROBLAZE_64_NONE
2691
This is a 64 bit reloc that stores the 32 bit pc relative
2692
value in two words (with an imm instruction).  No relocation is
2693
done here - only used for relaxing
2694
@end deffn
2695
@deffn {} BFD_RELOC_MICROBLAZE_64_GOTPC
2696
This is a 64 bit reloc that stores the 32 bit pc relative
2697
value in two words (with an imm instruction).  The relocation is
2698
PC-relative GOT offset
2699
@end deffn
2700
@deffn {} BFD_RELOC_MICROBLAZE_64_GOT
2701
This is a 64 bit reloc that stores the 32 bit pc relative
2702
value in two words (with an imm instruction).  The relocation is
2703
GOT offset
2704
@end deffn
2705
@deffn {} BFD_RELOC_MICROBLAZE_64_PLT
2706
This is a 64 bit reloc that stores the 32 bit pc relative
2707
value in two words (with an imm instruction).  The relocation is
2708
PC-relative offset into PLT
2709
@end deffn
2710
@deffn {} BFD_RELOC_MICROBLAZE_64_GOTOFF
2711
This is a 64 bit reloc that stores the 32 bit GOT relative
2712
value in two words (with an imm instruction).  The relocation is
2713
relative offset from _GLOBAL_OFFSET_TABLE_
2714
@end deffn
2715
@deffn {} BFD_RELOC_MICROBLAZE_32_GOTOFF
2716
This is a 32 bit reloc that stores the 32 bit GOT relative
2717
value in a word.  The relocation is relative offset from
2718
@end deffn
2719
@deffn {} BFD_RELOC_MICROBLAZE_COPY
2720
This is used to tell the dynamic linker to copy the value out of
2721
the dynamic object into the runtime process image.
2722
@end deffn
2723
 
2724
@example
2725
 
2726
typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
2727
@end example
2728
@findex bfd_reloc_type_lookup
2729
@subsubsection @code{bfd_reloc_type_lookup}
2730
@strong{Synopsis}
2731
@example
2732
reloc_howto_type *bfd_reloc_type_lookup
2733
   (bfd *abfd, bfd_reloc_code_real_type code);
2734
reloc_howto_type *bfd_reloc_name_lookup
2735
   (bfd *abfd, const char *reloc_name);
2736
@end example
2737
@strong{Description}@*
2738
Return a pointer to a howto structure which, when
2739
invoked, will perform the relocation @var{code} on data from the
2740
architecture noted.
2741
 
2742
@findex bfd_default_reloc_type_lookup
2743
@subsubsection @code{bfd_default_reloc_type_lookup}
2744
@strong{Synopsis}
2745
@example
2746
reloc_howto_type *bfd_default_reloc_type_lookup
2747
   (bfd *abfd, bfd_reloc_code_real_type  code);
2748
@end example
2749
@strong{Description}@*
2750
Provides a default relocation lookup routine for any architecture.
2751
 
2752
@findex bfd_get_reloc_code_name
2753
@subsubsection @code{bfd_get_reloc_code_name}
2754
@strong{Synopsis}
2755
@example
2756
const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
2757
@end example
2758
@strong{Description}@*
2759
Provides a printable name for the supplied relocation code.
2760
Useful mainly for printing error messages.
2761
 
2762
@findex bfd_generic_relax_section
2763
@subsubsection @code{bfd_generic_relax_section}
2764
@strong{Synopsis}
2765
@example
2766
bfd_boolean bfd_generic_relax_section
2767
   (bfd *abfd,
2768
    asection *section,
2769
    struct bfd_link_info *,
2770
    bfd_boolean *);
2771
@end example
2772
@strong{Description}@*
2773
Provides default handling for relaxing for back ends which
2774
don't do relaxing.
2775
 
2776
@findex bfd_generic_gc_sections
2777
@subsubsection @code{bfd_generic_gc_sections}
2778
@strong{Synopsis}
2779
@example
2780
bfd_boolean bfd_generic_gc_sections
2781
   (bfd *, struct bfd_link_info *);
2782
@end example
2783
@strong{Description}@*
2784
Provides default handling for relaxing for back ends which
2785
don't do section gc -- i.e., does nothing.
2786
 
2787
@findex bfd_generic_merge_sections
2788
@subsubsection @code{bfd_generic_merge_sections}
2789
@strong{Synopsis}
2790
@example
2791
bfd_boolean bfd_generic_merge_sections
2792
   (bfd *, struct bfd_link_info *);
2793
@end example
2794
@strong{Description}@*
2795
Provides default handling for SEC_MERGE section merging for back ends
2796
which don't have SEC_MERGE support -- i.e., does nothing.
2797
 
2798
@findex bfd_generic_get_relocated_section_contents
2799
@subsubsection @code{bfd_generic_get_relocated_section_contents}
2800
@strong{Synopsis}
2801
@example
2802
bfd_byte *bfd_generic_get_relocated_section_contents
2803
   (bfd *abfd,
2804
    struct bfd_link_info *link_info,
2805
    struct bfd_link_order *link_order,
2806
    bfd_byte *data,
2807
    bfd_boolean relocatable,
2808
    asymbol **symbols);
2809
@end example
2810
@strong{Description}@*
2811
Provides default handling of relocation effort for back ends
2812
which can't be bothered to do it efficiently.
2813
 

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