OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [cpu/] [m32r.cpu] - Blame information for rev 283

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 205 julius
; Renesas M32R CPU description.  -*- Scheme -*-
2
;
3
; Copyright 1998, 1999, 2000, 2001, 2003, 2007, 2009
4
; Free Software Foundation, Inc.
5
;
6
; Contributed by Red Hat Inc; developed under contract from Mitsubishi
7
; Electric Corporation.
8
;
9
; This file is part of the GNU Binutils.
10
;
11
; This program is free software; you can redistribute it and/or modify
12
; it under the terms of the GNU General Public License as published by
13
; the Free Software Foundation; either version 3 of the License, or
14
; (at your option) any later version.
15
;
16
; This program is distributed in the hope that it will be useful,
17
; but WITHOUT ANY WARRANTY; without even the implied warranty of
18
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19
; GNU General Public License for more details.
20
;
21
; You should have received a copy of the GNU General Public License
22
; along with this program; if not, write to the Free Software
23
; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
24
; MA 02110-1301, USA.
25
 
26
(include "simplify.inc")
27
 
28
; FIXME: Delete sign extension of accumulator results.
29
; Sign extension is done when accumulator is read.
30
 
31
; define-arch must appear first
32
 
33
(define-arch
34
  (name m32r) ; name of cpu family
35
  (comment "Renesas M32R")
36
  (default-alignment aligned)
37
  (insn-lsb0? #f)
38
  (machs m32r m32rx m32r2)
39
  (isas m32r)
40
)
41
 
42
; Attributes.
43
 
44
; An attribute to describe which pipeline an insn runs in.
45
; O_OS is a special attribute for sll, sra, sla, slli, srai, slai.
46
; These instructions have O attribute for m32rx and OS attribute for m32r2.
47
 
48
(define-attr
49
  (for insn)
50
  (type enum)
51
  (name PIPE)
52
  (comment "parallel execution pipeline selection")
53
  (values NONE O S OS O_OS)
54
)
55
 
56
; A derived attribute that says which insns can be executed in parallel
57
; with others.  This is a required attribute for architectures with
58
; parallel execution.
59
 
60
(define-attr
61
  (for insn)
62
  (type enum)
63
  (name PARALLEL)
64
  (attrs META) ; do not define in any generated file for now
65
  (values NO YES)
66
  (default (if (eq-attr (current-insn) PIPE NONE) (symbol NO) (symbol YES)))
67
)
68
 
69
; Instruction set parameters.
70
 
71
(define-isa
72
  (name m32r)
73
 
74
  ; This is 32 because 16 bit insns always appear as pairs.
75
  ; ??? See if this can go away.  It's only used by the disassembler (right?)
76
  ; to decide how long an unknown insn is.  One value isn't sufficient (e.g. if
77
  ; on a 16 bit (and not 32 bit) boundary, will only want to advance pc by 16.)
78
  (default-insn-bitsize 32)
79
 
80
  ; Number of bytes of insn we can initially fetch.
81
  ; The M32R is tricky in that insns are either two 16-bit insns
82
  ; (executed sequentially or in parallel) or one 32-bit insn.
83
  ; So on one hand the base insn size is 16 bits, but on another it's 32.
84
  ; 32 is chosen because:
85
  ; - if the chip were ever bi-endian it is believed that the byte order would
86
  ;   be based on 32 bit quantities
87
  ; - 32 bit insns are always aligned on 32 bit boundaries
88
  ; - the pc will never stop on a 16 bit (and not 32 bit) boundary
89
  ;   [well actually it can, but there are no branches to such places]
90
  (base-insn-bitsize 32)
91
 
92
  ; Used in computing bit numbers.
93
  (default-insn-word-bitsize 32)
94
 
95
  ; The m32r fetches 2 insns at a time.
96
  (liw-insns 2)
97
 
98
  ; While the m32r can execute insns in parallel, the base mach can't
99
  ; (other than nop).  The base mach is greatly handicapped by this, but
100
  ; we still need to cleanly handle it.
101
  (parallel-insns 2)
102
 
103
  ; Initial bitnumbers to decode insns by.
104
  (decode-assist (0 1 2 3 8 9 10 11))
105
 
106
  ; Classification of instructions that fit in the various frames.
107
  ; wip, not currently used
108
  (insn-types (long ; name
109
               31 ; length
110
               (eq-attr (current-insn) LENGTH 31) ; matching insns
111
               (0 1 2 7 8 9 10) ; decode-assist
112
               )
113
              (short
114
               15
115
               (eq-attr (current-insn) LENGTH 15) ; matching insns
116
               (0 1 2 7 8 9 10)
117
               )
118
              )
119
 
120
  ; Instruction framing.
121
  ; Each m32r insn is either one 32 bit insn, two 16 bit insns executed
122
  ; serially (left->right), or two 16 bit insns executed parallelly.
123
  ; wip, not currently used
124
  (frame long32 ; name
125
         ((long)) ; list of insns in frame, plus constraint
126
         "$0"   ; assembler
127
         (+ (1 1) (31 $0)) ; value
128
         (sequence () (execute $0)) ; action
129
         )
130
  (frame serial2x16
131
         ((short)
132
          (short))
133
         "$0 -> $1"
134
         (+ (1 0) (15 $0) (1 0) (15 $1))
135
         (sequence ()
136
                   (execute $0)
137
                   (execute $1))
138
         )
139
  (frame parallel2x16
140
         ((short (eq-attr (current-insn) PIPE "O,BOTH"))
141
          (short (eq-attr (current-insn) PIPE "S,BOTH")))
142
         "$0 || $1"
143
         (+ (1 0) (15 $0) (1 1) (15 $1))
144
         (parallel ()
145
                   (execute $0)
146
                   (execute $1))
147
         )
148
)
149
 
150
; Cpu family definitions.
151
 
152
; ??? define-cpu-family [and in general "cpu-family"] might be clearer than
153
; define-cpu.
154
; ??? Have define-arch provide defaults for architecture that define-cpu can
155
; then override [reduces duplication in define-cpu].
156
; ??? Another way to go is to delete cpu-families entirely and have one mach
157
; able to inherit things from another mach (would also need the ability to
158
; not only override specific inherited things but also disable some,
159
; e.g. if an insn wasn't supported).
160
 
161
(define-cpu
162
  ; cpu names must be distinct from the architecture name and machine names.
163
  ; The "b" suffix stands for "base" and is the convention.
164
  ; The "f" suffix stands for "family" and is the convention.
165
  (name m32rbf)
166
  (comment "Renesas M32R base family")
167
  (endian either)
168
  (word-bitsize 32)
169
  ; Override isa spec (??? keeps things simpler, though it was more true
170
  ; in the early days and not so much now).
171
  (parallel-insns 1)
172
)
173
 
174
(define-cpu
175
  (name m32rxf)
176
  (comment "Renesas M32Rx family")
177
  (endian either)
178
  (word-bitsize 32)
179
  ; Generated files have an "x" suffix.
180
  (file-transform "x")
181
)
182
 
183
(define-cpu
184
  (name m32r2f)
185
  (comment "Renesas M32R2 family")
186
  (endian either)
187
  (word-bitsize 32)
188
  ; Generated files have an "2" suffix.
189
  (file-transform "2")
190
)
191
 
192
(define-mach
193
  (name m32r)
194
  (comment "Generic M32R cpu")
195
  (cpu m32rbf)
196
)
197
 
198
(define-mach
199
  (name m32rx)
200
  (comment "M32RX cpu")
201
  (cpu m32rxf)
202
)
203
 
204
(define-mach
205
  (name m32r2)
206
  (comment "M32R2 cpu")
207
  (cpu m32r2f)
208
)
209
 
210
; Model descriptions.
211
 
212
; The meaning of this value is wip but at the moment it's intended to describe
213
; the implementation (i.e. what -mtune=foo does in sparc gcc).
214
;
215
; Notes while wip:
216
; - format of pipeline entry:
217
;   (pipeline name (stage1-name ...) (stage2-name ...) ...)
218
;   The contents of a stage description is wip.
219
; - each mach must have at least one model
220
; - the default model must be the first one
221
;- maybe have `retire' support update total cycle count to handle current
222
;  parallel insn cycle counting problems
223
 
224
(define-model
225
  (name m32r/d) (comment "m32r/d") (attrs)
226
  (mach m32r)
227
 
228
  ;(prefetch)
229
  ;(retire)
230
 
231
  (pipeline p-non-mem "" () ((fetch) (decode) (execute) (writeback)))
232
  (pipeline p-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
233
 
234
  ; `state' is a list of variables for recording model state
235
  (state
236
   ; bit mask of h-gr registers, =1 means value being loaded from memory
237
   (h-gr UINT)
238
   )
239
 
240
  (unit u-exec "Execution Unit" ()
241
        1 1 ; issue done
242
        () ; state
243
        ((sr INT -1) (dr INT -1)) ; inputs
244
        ((dr INT -1)) ; outputs
245
        () ; profile action (default)
246
        )
247
  (unit u-cmp "Compare Unit" ()
248
        1 1 ; issue done
249
        () ; state
250
        ((src1 INT -1) (src2 INT -1)) ; inputs
251
        () ; outputs
252
        () ; profile action (default)
253
        )
254
  (unit u-mac "Multiply/Accumulate Unit" ()
255
        1 1 ; issue done
256
        () ; state
257
        ((src1 INT -1) (src2 INT -1)) ; inputs
258
        () ; outputs
259
        () ; profile action (default)
260
        )
261
  (unit u-cti "Branch Unit" ()
262
        1 1 ; issue done
263
        () ; state
264
        ((sr INT -1)) ; inputs
265
        ((pc)) ; outputs
266
        () ; profile action (default)
267
        )
268
  (unit u-load "Memory Load Unit" ()
269
        1 1 ; issue done
270
        () ; state
271
        ((sr INT)
272
         ;(ld-mem AI)
273
         ) ; inputs
274
        ((dr INT)) ; outputs
275
        () ; profile action (default)
276
        )
277
  (unit u-store "Memory Store Unit" ()
278
        1 1 ; issue done
279
        () ; state
280
        ((src1 INT) (src2 INT)) ; inputs
281
        () ; ((st-mem AI)) ; outputs
282
        () ; profile action (default)
283
        )
284
)
285
 
286
(define-model
287
  (name test) (comment "test") (attrs)
288
  (mach m32r)
289
  (pipeline all "" () ((fetch) (decode) (execute) (writeback)))
290
  (unit u-exec "Execution Unit" ()
291
        1 1 ; issue done
292
        () () () ())
293
)
294
 
295
; Each mach must have at least one model.
296
 
297
(define-model
298
  (name m32rx) (comment "m32rx") (attrs)
299
  (mach m32rx)
300
 
301
  ; ??? It's 6 stages but I forget the details right now.
302
  (pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))
303
  (pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))
304
  (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
305
 
306
  (unit u-exec "Execution Unit" ()
307
        1 1 ; issue done
308
        () ; state
309
        ((sr INT -1) (dr INT -1)) ; inputs
310
        ((dr INT -1)) ; outputs
311
        () ; profile action (default)
312
        )
313
  (unit u-cmp "Compare Unit" ()
314
        1 1 ; issue done
315
        () ; state
316
        ((src1 INT -1) (src2 INT -1)) ; inputs
317
        () ; outputs
318
        () ; profile action (default)
319
        )
320
  (unit u-mac "Multiply/Accumulate Unit" ()
321
        1 1 ; issue done
322
        () ; state
323
        ((src1 INT -1) (src2 INT -1)) ; inputs
324
        () ; outputs
325
        () ; profile action (default)
326
        )
327
  (unit u-cti "Branch Unit" ()
328
        1 1 ; issue done
329
        () ; state
330
        ((sr INT -1)) ; inputs
331
        ((pc)) ; outputs
332
        () ; profile action (default)
333
        )
334
  (unit u-load "Memory Load Unit" ()
335
        1 1 ; issue done
336
        () ; state
337
        ((sr INT)) ; inputs
338
        ((dr INT)) ; outputs
339
        () ; profile action (default)
340
        )
341
  (unit u-store "Memory Store Unit" ()
342
        1 1 ; issue done
343
        () ; state
344
        ((src1 INT) (src2 INT)) ; inputs
345
        () ; outputs
346
        () ; profile action (default)
347
        )
348
)
349
 
350
(define-model
351
  (name m32r2) (comment "m32r2") (attrs)
352
  (mach m32r2)
353
 
354
  ; ??? It's 6 stages but I forget the details right now.
355
  (pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))
356
  (pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))
357
  (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
358
 
359
  (unit u-exec "Execution Unit" ()
360
        1 1 ; issue done
361
        () ; state
362
        ((sr INT -1) (dr INT -1)) ; inputs
363
        ((dr INT -1)) ; outputs
364
        () ; profile action (default)
365
        )
366
  (unit u-cmp "Compare Unit" ()
367
        1 1 ; issue done
368
        () ; state
369
        ((src1 INT -1) (src2 INT -1)) ; inputs
370
        () ; outputs
371
        () ; profile action (default)
372
        )
373
  (unit u-mac "Multiply/Accumulate Unit" ()
374
        1 1 ; issue done
375
        () ; state
376
        ((src1 INT -1) (src2 INT -1)) ; inputs
377
        () ; outputs
378
        () ; profile action (default)
379
        )
380
  (unit u-cti "Branch Unit" ()
381
        1 1 ; issue done
382
        () ; state
383
        ((sr INT -1)) ; inputs
384
        ((pc)) ; outputs
385
        () ; profile action (default)
386
        )
387
  (unit u-load "Memory Load Unit" ()
388
        1 1 ; issue done
389
        () ; state
390
        ((sr INT)) ; inputs
391
        ((dr INT)) ; outputs
392
        () ; profile action (default)
393
        )
394
  (unit u-store "Memory Store Unit" ()
395
        1 1 ; issue done
396
        () ; state
397
        ((src1 INT) (src2 INT)) ; inputs
398
        () ; outputs
399
        () ; profile action (default)
400
        )
401
)
402
 
403
; The instruction fetch/execute cycle.
404
; This is split into two parts as sometimes more than one instruction is
405
; decoded at once.
406
; The `const SI' argument to decode/execute is used to distinguish
407
; multiple instructions processed at the same time (e.g. m32r).
408
;
409
; ??? This is wip, and not currently used.
410
; ??? Needs to be moved to define-isa.
411
 
412
; This is how to fetch and decode an instruction.
413
 
414
;(define-extract
415
;  (sequence VOID
416
;           (if VOID (ne AI (and AI pc (const AI 3)) (const AI 0))
417
;               (sequence VOID
418
;                         (set-quiet USI (scratch UHI insn1) (ifetch UHI pc))
419
;                         (decode VOID pc (and UHI insn1 (const UHI #x7fff))
420
;                                 (const SI 0)))
421
;               (sequence VOID
422
;                         (set-quiet USI (scratch USI insn) (ifetch USI pc))
423
;                         (if VOID (ne USI (and USI insn (const USI #x80000000))
424
;                                    (const USI 0))
425
;                             (decode VOID pc (srl USI insn (const WI 16)) (const SI 0))
426
;                             (sequence VOID
427
;                                       ; ??? parallel support
428
;                                       (decode VOID pc (srl USI insn (const WI 16))
429
;                                               (const SI 0))
430
;                                       (decode VOID (add AI pc (const AI 2))
431
;                                               (and USI insn (const WI #x7fff))
432
;                                               (const SI 1))))))
433
;           )
434
;)
435
 
436
; This is how to execute a decoded instruction.
437
 
438
;(define-execute
439
;  (sequence VOID () ; () is empty option list
440
;            ((AI new_pc))
441
;            (set AI new_pc (execute: AI (const 0)) #:quiet)
442
;            (set AI pc new_pc #:direct)
443
;            )
444
;)
445
 
446
; FIXME: It might simplify things to separate the execute process from the
447
; one that updates the PC.
448
 
449
; Instruction fields.
450
;
451
; Attributes:
452
; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)
453
; ABS-ADDR: absolute address (for reloc and disassembly purposes?)
454
; RESERVED: bits are not used to decode insn, must be all 0
455
; RELOC: there is a relocation associated with this field (experiment)
456
 
457
(define-attr
458
  (for ifield operand)
459
  (type boolean)
460
  (name RELOC)
461
  (comment "there is a reloc associated with this field (experiment)")
462
)
463
 
464
(dnf f-op1       "op1"                 () 0 4)
465
(dnf f-op2       "op2"                 () 8 4)
466
(dnf f-cond      "cond"                () 4 4)
467
(dnf f-r1        "r1"                  () 4 4)
468
(dnf f-r2        "r2"                  () 12 4)
469
(df f-simm8      "simm8"               () 8 8 INT #f #f)
470
(df f-simm16     "simm16"              () 16 16 INT #f #f)
471
(dnf f-shift-op2 "shift op2"           () 8 3)
472
(dnf f-uimm3     "uimm3"               () 5 3)
473
(dnf f-uimm4     "uimm4"               () 12 4)
474
(dnf f-uimm5     "uimm5"               () 11 5)
475
(dnf f-uimm8     "uimm8"               () 8 8)
476
(dnf f-uimm16    "uimm16"              () 16 16)
477
(dnf f-uimm24    "uimm24"              (ABS-ADDR RELOC) 8 24)
478
(dnf f-hi16      "high 16 bits"        (SIGN-OPT) 16 16)
479
(df f-disp8      "disp8, slot unknown" (PCREL-ADDR RELOC) 8 8 INT
480
    ((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 2)))
481
    ((value pc) (add WI (sll WI value (const 2)) (and WI pc (const -4)))))
482
(df f-disp16     "disp16"              (PCREL-ADDR RELOC) 16 16 INT
483
    ((value pc) (sra WI (sub WI value pc) (const 2)))
484
    ((value pc) (add WI (sll WI value (const 2)) pc)))
485
(df f-disp24     "disp24"              (PCREL-ADDR RELOC) 8 24 INT
486
    ((value pc) (sra WI (sub WI value pc) (const 2)))
487
    ((value pc) (add WI (sll WI value (const 2)) pc)))
488
 
489
(dnf f-op23      "op2.3"               ()  9 3)
490
(dnf f-op3       "op3"                 () 14 2)
491
(dnf f-acc       "acc"                 ()  8 1)
492
(dnf f-accs      "accs"                () 12 2)
493
(dnf f-accd      "accd"                ()  4 2)
494
(dnf f-bits67    "bits67"              ()  6 2)
495
(dnf f-bit4      "bit4"                ()  4 1)
496
(dnf f-bit14     "bit14"               () 14 1)
497
 
498
(define-ifield (name f-imm1) (comment "1 bit immediate, 0->1 1->2")
499
  (attrs)
500
  (start 15) (length 1)
501
  (encode (value pc) (sub WI value (const WI 1)))
502
  (decode (value pc) (add WI value (const WI 1)))
503
)
504
 
505
; Enums.
506
 
507
; insn-op1: bits 0-3
508
; FIXME: should use die macro or some such
509
(define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1
510
  ("0" "1" "2" "3" "4" "5" "6" "7"
511
   "8" "9" "10" "11" "12" "13" "14" "15")
512
)
513
 
514
; insn-op2: bits 8-11
515
; FIXME: should use die macro or some such
516
(define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2
517
  ("0" "1" "2" "3" "4" "5" "6" "7"
518
   "8" "9" "10" "11" "12" "13" "14" "15")
519
)
520
 
521
; Hardware pieces.
522
; These entries list the elements of the raw hardware.
523
; They're also used to provide tables and other elements of the assembly
524
; language.
525
 
526
(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
527
 
528
(dnh h-hi16 "high 16 bits" ()
529
     (immediate (UINT 16))
530
     () () ()
531
)
532
 
533
; These two aren't technically needed.
534
; They're here for illustration sake mostly.
535
; Plus they cause the value to be stored in the extraction buffers to only
536
; be 16 bits wide (vs 32 or 64).  Whoopie ding.  But it's fun.
537
(dnh h-slo16 "signed low 16 bits" ()
538
     (immediate (INT 16))
539
     () () ()
540
)
541
(dnh h-ulo16 "unsigned low 16 bits" ()
542
     (immediate (UINT 16))
543
     () () ()
544
)
545
 
546
(define-keyword
547
  (name gr-names)
548
  (print-name h-gr)
549
  (prefix "")
550
  (values (fp 13) (lr 14) (sp 15)
551
          (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
552
          (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15))
553
)
554
 
555
(define-hardware
556
  (name h-gr)
557
  (comment "general registers")
558
  (attrs PROFILE CACHE-ADDR)
559
  (type register WI (16))
560
  (indices extern-keyword gr-names)
561
)
562
 
563
(define-keyword
564
  (name cr-names)
565
  (print-name h-cr)
566
  (prefix "")
567
  (values (psw 0)   (cbr 1)   (spi 2)   (spu 3)
568
          (bpc 6)   (bbpsw 8) (bbpc 14) (evb 5)
569
          (cr0 0)   (cr1 1)   (cr2 2)   (cr3 3)
570
          (cr4 4)   (cr5 5)   (cr6 6)   (cr7 7)
571
          (cr8 8)   (cr9 9)   (cr10 10) (cr11 11)
572
          (cr12 12) (cr13 13) (cr14 14) (cr15 15))
573
)
574
 
575
(define-hardware
576
  (name h-cr)
577
  (comment "control registers")
578
  (type register UWI (16))
579
  (indices extern-keyword cr-names)
580
  (get (index) (c-call UWI "@cpu@_h_cr_get_handler" index))
581
  (set (index newval) (c-call VOID "@cpu@_h_cr_set_handler" index newval))
582
)
583
 
584
; The actual accumulator is only 56 bits.
585
; The top 8 bits are sign extended from bit 8 (when counting msb = bit 0).
586
; To simplify the accumulator instructions, no attempt is made to keep the
587
; top 8 bits properly sign extended (currently there's no point since they
588
; all ignore them).  When the value is read it is properly sign extended
589
; [in the `get' handler].
590
(define-hardware
591
  (name h-accum)
592
  (comment "accumulator")
593
  (type register DI)
594
  (get () (c-call DI "@cpu@_h_accum_get_handler"))
595
  (set (newval) (c-call VOID "@cpu@_h_accum_set_handler" newval))
596
)
597
 
598
; FIXME: Revisit after sanitization can be removed.  Remove h-accum.
599
(define-hardware
600
  (name h-accums)
601
  (comment "accumulators")
602
  (attrs (MACH m32rx,m32r2))
603
  (type register DI (2))
604
  (indices keyword "" ((a0 0) (a1 1)))
605
  ; get/set so a0 accesses are redirected to h-accum.
606
  ; They're also so reads can properly sign extend the value.
607
  ; FIXME: Needn't be a function call.
608
  (get (index) (c-call DI "@cpu@_h_accums_get_handler" index))
609
  (set (index newval) (c-call VOID "@cpu@_h_accums_set_handler" index newval))
610
)
611
 
612
; For condbit operand.  FIXME: Need to allow spec of get/set of operands.
613
; Having this separate from h-psw keeps the parts that use it simpler
614
; [since they greatly outnumber those that use h-psw].
615
(dsh h-cond "condition bit" () (register BI))
616
 
617
; The actual values of psw,bpsw,bbpsw are recorded here to allow access
618
; to them as a unit.
619
(define-hardware
620
  (name h-psw)
621
  (comment "psw part of psw")
622
  (type register UQI)
623
  ; get/set to handle cond bit.
624
  ; FIXME: missing: use's and clobber's
625
  ; FIXME: remove c-call?
626
  (get () (c-call UQI "@cpu@_h_psw_get_handler"))
627
  (set (newval) (c-call VOID "@cpu@_h_psw_set_handler" newval))
628
)
629
(dsh h-bpsw  "backup psw"      () (register UQI))
630
(dsh h-bbpsw "backup bpsw"     () (register UQI))
631
 
632
; FIXME: Later make add get/set specs and support SMP.
633
(dsh h-lock  "lock"  () (register BI))
634
 
635
; Instruction Operands.
636
; These entries provide a layer between the assembler and the raw hardware
637
; description, and are used to refer to hardware elements in the semantic
638
; code.  Usually there's a bit of over-specification, but in more complicated
639
; instruction sets there isn't.
640
 
641
; M32R specific operand attributes:
642
 
643
(define-attr
644
  (for operand)
645
  (type boolean)
646
  (name HASH-PREFIX)
647
  (comment "immediates have an optional '#' prefix")
648
)
649
 
650
; ??? Convention says this should be o-sr, but then the insn definitions
651
; should refer to o-sr which is clumsy.  The "o-" could be implicit, but
652
; then it should be implicit for all the symbols here, but then there would
653
; be confusion between (f-)simm8 and (h-)simm8.
654
; So for now the rule is exactly as it appears here.
655
 
656
(dnop sr     "source register"              () h-gr   f-r2)
657
(dnop dr     "destination register"         () h-gr   f-r1)
658
;; The assembler relies upon the fact that dr and src1 are the same field.
659
;; FIXME: Revisit.
660
(dnop src1   "source register 1"            () h-gr   f-r1)
661
(dnop src2   "source register 2"            () h-gr   f-r2)
662
(dnop scr    "source control register"      () h-cr   f-r2)
663
(dnop dcr    "destination control register" () h-cr   f-r1)
664
 
665
(dnop simm8  "8 bit signed immediate"       (HASH-PREFIX) h-sint f-simm8)
666
(dnop simm16 "16 bit signed immediate"      (HASH-PREFIX) h-sint f-simm16)
667
(dnop uimm3  "3 bit unsigned number"        (HASH-PREFIX) h-uint f-uimm3)
668
(dnop uimm4  "4 bit trap number"            (HASH-PREFIX) h-uint f-uimm4)
669
(dnop uimm5  "5 bit shift count"            (HASH-PREFIX) h-uint f-uimm5)
670
(dnop uimm8  "8 bit unsigned immediate"     (HASH-PREFIX) h-uint f-uimm8)
671
(dnop uimm16 "16 bit unsigned immediate"    (HASH-PREFIX) h-uint f-uimm16)
672
 
673
(dnop imm1   "1 bit immediate"              ((MACH m32rx,m32r2) HASH-PREFIX) h-uint f-imm1)
674
(dnop accd   "accumulator destination register" ((MACH m32rx,m32r2))        h-accums f-accd)
675
(dnop accs   "accumulator source register"  ((MACH m32rx,m32r2))            h-accums f-accs)
676
(dnop acc    "accumulator reg (d)"          ((MACH m32rx,m32r2))            h-accums f-acc)
677
 
678
; slo16,ulo16 are used in both with-hash-prefix/no-hash-prefix cases.
679
; e.g. add3 r3,r3,#1 and ld r3,@(4,r4).  We could use HASH-PREFIX.
680
; Instead we create a fake operand `hash'.  The m32r is an illustration port,
681
; so we often try out various ways of doing things.
682
 
683
(define-operand (name hash) (comment "# prefix") (attrs)
684
  (type h-sint) ; doesn't really matter
685
  (index f-nil)
686
  (handlers (parse "hash") (print "hash"))
687
)
688
 
689
; For high(foo),shigh(foo).
690
(define-operand
691
  (name hi16)
692
  (comment "high 16 bit immediate, sign optional")
693
  (attrs)
694
  (type h-hi16)
695
  (index f-hi16)
696
  (handlers (parse "hi16"))
697
)
698
 
699
; For low(foo),sda(foo).
700
(define-operand
701
  (name slo16)
702
  (comment "16 bit signed immediate, for low()")
703
  (attrs)
704
  (type h-slo16)
705
  (index f-simm16)
706
  (handlers (parse "slo16"))
707
)
708
 
709
; For low(foo).
710
(define-operand
711
  (name ulo16)
712
  (comment "16 bit unsigned immediate, for low()")
713
  (attrs)
714
  (type h-ulo16)
715
  (index f-uimm16)
716
  (handlers (parse "ulo16"))
717
)
718
 
719
(dnop uimm24 "24 bit address" (HASH-PREFIX) h-addr f-uimm24)
720
 
721
(define-operand
722
  (name disp8)
723
  (comment "8 bit displacement")
724
  (attrs RELAX)
725
  (type h-iaddr)
726
  (index f-disp8)
727
  ; ??? Early experiments had insert/extract fields here.
728
  ; Moving these to f-disp8 made things cleaner, but may wish to re-introduce
729
  ; fields here to handle more complicated cases.
730
)
731
 
732
(dnop disp16 "16 bit displacement" () h-iaddr f-disp16)
733
(dnop disp24 "24 bit displacement" (RELAX) h-iaddr f-disp24)
734
 
735
; These hardware elements are refered to frequently.
736
 
737
(dnop condbit "condition bit" (SEM-ONLY) h-cond f-nil)
738
(dnop accum "accumulator" (SEM-ONLY) h-accum f-nil)
739
 
740
; Instruction definitions.
741
;
742
; Notes while wip:
743
; - dni is a cover macro to the real "this is an instruction" keyword.
744
;   The syntax of the real one is yet to be determined.
745
;   At the lowest level (i.e. the "real" one) it will probably take a variable
746
;   list of arguments where each argument [perhaps after the standard three of
747
;   name, comment, attrs] is "(keyword arg-to-keyword)".  This syntax is simple
748
;   and yet completely upward extensible.  And given the macro facility, one
749
;   needn't code at that low a level so even though it'll be more verbose than
750
;   necessary it won't matter.  This same reasoning can be applied to most
751
;   types of entries in this file.
752
 
753
; M32R specific instruction attributes:
754
 
755
; FILL-SLOT: Need next insn to begin on 32 bit boundary.
756
; (A "slot" as used here is a 32 bit quantity that can either be filled with
757
; one 32 bit insn or two 16 bit insns which go in the "left bin" and "right
758
; bin" where the left bin is the one with a lower address).
759
 
760
(define-attr
761
  (for insn)
762
  (type boolean)
763
  (name FILL-SLOT)
764
  (comment "fill right bin with `nop' if insn is in left bin")
765
)
766
 
767
(define-attr
768
  (for insn)
769
  (type boolean)
770
  (name SPECIAL)
771
  (comment "non-public m32rx insn")
772
)
773
 
774
(define-attr
775
  (for insn)
776
  (type boolean)
777
  (name SPECIAL_M32R)
778
  (comment "non-public m32r insn")
779
)
780
 
781
(define-attr
782
  (for insn)
783
  (type boolean)
784
  (name SPECIAL_FLOAT)
785
  (comment "floating point insn")
786
)
787
 
788
; IDOC attribute for instruction documentation.
789
 
790
(define-attr
791
  (for insn)
792
  (type enum)
793
  (name IDOC)
794
  (comment "insn kind for documentation")
795
  (attrs META)
796
  (values
797
   (MEM - () "Memory")
798
   (ALU - () "ALU")
799
   (BR - () "Branch")
800
   (ACCUM - () "Accumulator")
801
   (MAC - () "Multiply/Accumulate")
802
   (MISC - () "Miscellaneous")
803
  )
804
)
805
 
806
(define-pmacro (bin-op mnemonic op2-op sem-op imm-prefix imm)
807
  (begin
808
     (dni mnemonic
809
          (.str mnemonic " reg/reg")
810
          ((PIPE OS) (IDOC ALU))
811
          (.str mnemonic " $dr,$sr")
812
          (+ OP1_0 op2-op dr sr)
813
          (set dr (sem-op dr sr))
814
          ()
815
     )
816
     (dni (.sym mnemonic "3")
817
          (.str mnemonic " reg/" imm)
818
          ((IDOC ALU))
819
          (.str mnemonic "3 $dr,$sr," imm-prefix "$" imm)
820
          (+ OP1_8 op2-op dr sr imm)
821
          (set dr (sem-op sr imm))
822
          ()
823
     )
824
   )
825
)
826
(bin-op add OP2_10 add "$hash" slo16)
827
; sub isn't present because sub3 doesn't exist.
828
(bin-op and OP2_12 and "" uimm16)
829
(bin-op or OP2_14 or "$hash" ulo16)
830
(bin-op xor OP2_13 xor "" uimm16)
831
 
832
(dni addi "addi"
833
     ((PIPE OS) (IDOC ALU))
834
     ;#.(string-append "addi " "$dr,$simm8") ; #. experiment
835
     "addi $dr,$simm8"
836
     (+ OP1_4 dr simm8)
837
     (set dr (add dr simm8))
838
     ((m32r/d (unit u-exec))
839
      (m32rx (unit u-exec))
840
      (m32r2 (unit u-exec)))
841
)
842
 
843
(dni addv "addv"
844
     ((PIPE OS) (IDOC ALU))
845
     "addv $dr,$sr"
846
     (+ OP1_0 OP2_8 dr sr)
847
     (parallel ()
848
               (set dr (add dr sr))
849
               (set condbit (add-oflag dr sr (const 0))))
850
     ()
851
)
852
 
853
(dni addv3 "addv3"
854
     ((IDOC ALU))
855
     "addv3 $dr,$sr,$simm16"
856
     (+ OP1_8 OP2_8 dr sr simm16)
857
     (parallel ()
858
               (set dr (add sr simm16))
859
               (set condbit (add-oflag sr simm16 (const 0))))
860
     ()
861
)
862
 
863
(dni addx "addx"
864
     ((PIPE OS) (IDOC ALU))
865
     "addx $dr,$sr"
866
     (+ OP1_0 OP2_9 dr sr)
867
     (parallel ()
868
               (set dr (addc dr sr condbit))
869
               (set condbit (add-cflag dr sr condbit)))
870
     ()
871
)
872
 
873
(dni bc8 "bc with 8 bit displacement"
874
     (COND-CTI (PIPE O) (IDOC BR))
875
     "bc.s $disp8"
876
     (+ OP1_7 (f-r1 12) disp8)
877
     (if condbit (set pc disp8))
878
     ((m32r/d (unit u-cti))
879
      (m32rx (unit u-cti))
880
      (m32r2 (unit u-cti)))
881
)
882
 
883
(dnmi bc8r "relaxable bc8"
884
     (COND-CTI RELAXABLE (PIPE O) (IDOC BR))
885
     "bc $disp8"
886
     (emit bc8 disp8)
887
)
888
 
889
(dni bc24 "bc with 24 bit displacement"
890
     (COND-CTI (IDOC BR))
891
     "bc.l $disp24"
892
     (+ OP1_15 (f-r1 12) disp24)
893
     (if condbit (set pc disp24))
894
     ((m32r/d (unit u-cti))
895
      (m32rx (unit u-cti))
896
      (m32r2 (unit u-cti)))
897
)
898
 
899
(dnmi bc24r "relaxable bc24"
900
     (COND-CTI RELAXED (IDOC BR))
901
     "bc $disp24"
902
     (emit bc24 disp24)
903
)
904
 
905
(dni beq "beq"
906
     (COND-CTI (IDOC BR))
907
     "beq $src1,$src2,$disp16"
908
     (+ OP1_11 OP2_0 src1 src2 disp16)
909
     (if (eq src1 src2) (set pc disp16))
910
     ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
911
      (m32rx (unit u-cti) (unit u-cmp (cycles 0)))
912
      (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
913
)
914
 
915
(define-pmacro (cbranch sym comment op2-op comp-op)
916
  (dni sym comment (COND-CTI (IDOC BR))
917
        (.str sym " $src2,$disp16")
918
        (+ OP1_11 op2-op (f-r1 0) src2 disp16)
919
        (if (comp-op src2 (const WI 0)) (set pc disp16))
920
        ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
921
         (m32rx (unit u-cti) (unit u-cmp (cycles 0)))
922
         (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
923
        )
924
)
925
(cbranch beqz "beqz" OP2_8 eq)
926
(cbranch bgez "bgez" OP2_11 ge)
927
(cbranch bgtz "bgtz" OP2_13 gt)
928
(cbranch blez "blez" OP2_12 le)
929
(cbranch bltz "bltz" OP2_10 lt)
930
(cbranch bnez "bnez" OP2_9 ne)
931
 
932
(dni bl8 "bl with 8 bit displacement"
933
     (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
934
     "bl.s $disp8"
935
     (+ OP1_7 (f-r1 14) disp8)
936
     (sequence ()
937
               (set (reg h-gr 14)
938
                    (add (and pc (const -4)) (const 4)))
939
               (set pc disp8))
940
     ((m32r/d (unit u-cti))
941
      (m32rx (unit u-cti))
942
      (m32r2 (unit u-cti)))
943
)
944
 
945
(dnmi bl8r "relaxable bl8"
946
     (UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR))
947
     "bl $disp8"
948
     (emit bl8 disp8)
949
)
950
 
951
(dni bl24 "bl with 24 bit displacement"
952
     (UNCOND-CTI (IDOC BR))
953
     "bl.l $disp24"
954
     (+ OP1_15 (f-r1 14) disp24)
955
     (sequence ()
956
               (set (reg h-gr 14) (add pc (const 4)))
957
               (set pc disp24))
958
     ((m32r/d (unit u-cti))
959
      (m32rx (unit u-cti))
960
      (m32r2 (unit u-cti)))
961
)
962
 
963
(dnmi bl24r "relaxable bl24"
964
     (UNCOND-CTI RELAXED (IDOC BR))
965
     "bl $disp24"
966
     (emit bl24 disp24)
967
)
968
 
969
(dni bcl8 "bcl with 8 bit displacement"
970
     (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR))
971
     "bcl.s $disp8"
972
     (+ OP1_7 (f-r1 8) disp8)
973
     (if condbit
974
         (sequence ()
975
                   (set (reg h-gr 14)
976
                        (add (and pc (const -4))
977
                             (const 4)))
978
                   (set pc disp8)))
979
     ((m32rx (unit u-cti))
980
      (m32r2 (unit u-cti)))
981
)
982
 
983
(dnmi bcl8r "relaxable bcl8"
984
     (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR))
985
     "bcl $disp8"
986
     (emit bcl8 disp8)
987
)
988
 
989
(dni bcl24 "bcl with 24 bit displacement"
990
     (COND-CTI (MACH m32rx,m32r2) (IDOC BR))
991
     "bcl.l $disp24"
992
     (+ OP1_15 (f-r1 8) disp24)
993
     (if condbit
994
         (sequence ()
995
                   (set (reg h-gr 14) (add pc (const 4)))
996
                   (set pc disp24)))
997
     ((m32rx (unit u-cti))
998
      (m32r2 (unit u-cti)))
999
)
1000
 
1001
(dnmi bcl24r "relaxable bcl24"
1002
     (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR))
1003
     "bcl $disp24"
1004
     (emit bcl24 disp24)
1005
)
1006
 
1007
(dni bnc8 "bnc with 8 bit displacement"
1008
     (COND-CTI (PIPE O) (IDOC BR))
1009
     "bnc.s $disp8"
1010
     (+ OP1_7 (f-r1 13) disp8)
1011
     (if (not condbit) (set pc disp8))
1012
     ((m32r/d (unit u-cti))
1013
      (m32rx (unit u-cti))
1014
      (m32r2 (unit u-cti)))
1015
)
1016
 
1017
(dnmi bnc8r "relaxable bnc8"
1018
     (COND-CTI RELAXABLE (PIPE O) (IDOC BR))
1019
     "bnc $disp8"
1020
     (emit bnc8 disp8)
1021
)
1022
 
1023
(dni bnc24 "bnc with 24 bit displacement"
1024
     (COND-CTI (IDOC BR))
1025
     "bnc.l $disp24"
1026
     (+ OP1_15 (f-r1 13) disp24)
1027
     (if (not condbit) (set pc disp24))
1028
     ((m32r/d (unit u-cti))
1029
      (m32rx (unit u-cti))
1030
      (m32r2 (unit u-cti)))
1031
)
1032
 
1033
(dnmi bnc24r "relaxable bnc24"
1034
     (COND-CTI RELAXED (IDOC BR))
1035
     "bnc $disp24"
1036
     (emit bnc24 disp24)
1037
)
1038
 
1039
(dni bne "bne"
1040
     (COND-CTI (IDOC BR))
1041
     "bne $src1,$src2,$disp16"
1042
     (+ OP1_11 OP2_1 src1 src2 disp16)
1043
     (if (ne src1 src2) (set pc disp16))
1044
     ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
1045
      (m32rx (unit u-cti) (unit u-cmp (cycles 0)))
1046
      (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
1047
)
1048
 
1049
(dni bra8 "bra with 8 bit displacement"
1050
     (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
1051
     "bra.s $disp8"
1052
     (+ OP1_7 (f-r1 15) disp8)
1053
     (set pc disp8)
1054
     ((m32r/d (unit u-cti))
1055
      (m32rx (unit u-cti))
1056
      (m32r2 (unit u-cti)))
1057
)
1058
 
1059
(dnmi bra8r "relaxable bra8"
1060
     (UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR))
1061
     "bra $disp8"
1062
     (emit bra8 disp8)
1063
)
1064
 
1065
(dni bra24 "bra with 24 displacement"
1066
     (UNCOND-CTI (IDOC BR))
1067
     "bra.l $disp24"
1068
     (+ OP1_15 (f-r1 15) disp24)
1069
     (set pc disp24)
1070
     ((m32r/d (unit u-cti))
1071
      (m32rx (unit u-cti))
1072
      (m32r2 (unit u-cti)))
1073
)
1074
 
1075
(dnmi bra24r "relaxable bra24"
1076
     (UNCOND-CTI RELAXED (IDOC BR))
1077
     "bra $disp24"
1078
     (emit bra24 disp24)
1079
)
1080
 
1081
(dni bncl8 "bncl with 8 bit displacement"
1082
     (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR))
1083
     "bncl.s $disp8"
1084
     (+ OP1_7 (f-r1 9) disp8)
1085
     (if (not condbit)
1086
         (sequence ()
1087
                   (set (reg h-gr 14)
1088
                        (add (and pc (const -4))
1089
                             (const 4)))
1090
                   (set pc disp8)))
1091
     ((m32rx (unit u-cti))
1092
      (m32r2 (unit u-cti)))
1093
)
1094
 
1095
(dnmi bncl8r "relaxable bncl8"
1096
     (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR))
1097
     "bncl $disp8"
1098
     (emit bncl8 disp8)
1099
)
1100
 
1101
(dni bncl24 "bncl with 24 bit displacement"
1102
     (COND-CTI (MACH m32rx,m32r2) (IDOC BR))
1103
     "bncl.l $disp24"
1104
     (+ OP1_15 (f-r1 9) disp24)
1105
     (if (not condbit)
1106
         (sequence ()
1107
                   (set (reg h-gr 14) (add pc (const 4)))
1108
                   (set pc disp24)))
1109
     ((m32rx (unit u-cti))
1110
      (m32r2 (unit u-cti)))
1111
)
1112
 
1113
(dnmi bncl24r "relaxable bncl24"
1114
     (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR))
1115
     "bncl $disp24"
1116
     (emit bncl24 disp24)
1117
)
1118
 
1119
(dni cmp "cmp"
1120
     ((PIPE OS) (IDOC ALU))
1121
     "cmp $src1,$src2"
1122
     (+ OP1_0 OP2_4 src1 src2)
1123
     (set condbit (lt src1 src2))
1124
     ((m32r/d (unit u-cmp))
1125
      (m32rx (unit u-cmp))
1126
      (m32r2 (unit u-cmp)))
1127
)
1128
 
1129
(dni cmpi "cmpi"
1130
     ((IDOC ALU))
1131
     "cmpi $src2,$simm16"
1132
     (+ OP1_8 (f-r1 0) OP2_4 src2 simm16)
1133
     (set condbit (lt src2 simm16))
1134
     ((m32r/d (unit u-cmp))
1135
      (m32rx (unit u-cmp))
1136
      (m32r2 (unit u-cmp)))
1137
)
1138
 
1139
(dni cmpu "cmpu"
1140
     ((PIPE OS) (IDOC ALU))
1141
     "cmpu $src1,$src2"
1142
     (+ OP1_0 OP2_5 src1 src2)
1143
     (set condbit (ltu src1 src2))
1144
     ((m32r/d (unit u-cmp))
1145
      (m32rx (unit u-cmp))
1146
      (m32r2 (unit u-cmp)))
1147
)
1148
 
1149
(dni cmpui "cmpui"
1150
     ((IDOC ALU))
1151
     "cmpui $src2,$simm16"
1152
     (+ OP1_8 (f-r1 0) OP2_5 src2 simm16)
1153
     (set condbit (ltu src2 simm16))
1154
     ((m32r/d (unit u-cmp))
1155
      (m32rx (unit u-cmp))
1156
      (m32r2 (unit u-cmp)))
1157
)
1158
 
1159
(dni cmpeq "cmpeq"
1160
     ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU))
1161
     "cmpeq $src1,$src2"
1162
     (+ OP1_0 OP2_6 src1 src2)
1163
     (set condbit (eq src1 src2))
1164
     ((m32rx (unit u-cmp))
1165
      (m32r2 (unit u-cmp)))
1166
)
1167
 
1168
(dni cmpz "cmpz"
1169
     ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU))
1170
     "cmpz $src2"
1171
     (+ OP1_0 OP2_7 (f-r1 0) src2)
1172
     (set condbit (eq src2 (const 0)))
1173
     ((m32rx (unit u-cmp))
1174
      (m32r2 (unit u-cmp)))
1175
)
1176
 
1177
(dni div "div"
1178
     ((IDOC ALU))
1179
     "div $dr,$sr"
1180
     (+ OP1_9 OP2_0 dr sr (f-simm16 0))
1181
     (if (ne sr (const 0)) (set dr (div dr sr)))
1182
     ((m32r/d (unit u-exec (cycles 37)))
1183
      (m32rx (unit u-exec (cycles 37)))
1184
      (m32r2 (unit u-exec (cycles 37))))
1185
)
1186
 
1187
(dni divu "divu"
1188
     ((IDOC ALU))
1189
     "divu $dr,$sr"
1190
     (+ OP1_9 OP2_1 dr sr (f-simm16 0))
1191
     (if (ne sr (const 0)) (set dr (udiv dr sr)))
1192
     ((m32r/d (unit u-exec (cycles 37)))
1193
      (m32rx (unit u-exec (cycles 37)))
1194
      (m32r2 (unit u-exec (cycles 37))))
1195
)
1196
 
1197
(dni rem "rem"
1198
     ((IDOC ALU))
1199
     "rem $dr,$sr"
1200
     (+ OP1_9 OP2_2 dr sr (f-simm16 0))
1201
     ; FIXME: Check rounding direction.
1202
     (if (ne sr (const 0)) (set dr (mod dr sr)))
1203
     ((m32r/d (unit u-exec (cycles 37)))
1204
      (m32rx (unit u-exec (cycles 37)))
1205
      (m32r2 (unit u-exec (cycles 37))))
1206
)
1207
 
1208
(dni remu "remu"
1209
     ((IDOC ALU))
1210
     "remu $dr,$sr"
1211
     (+ OP1_9 OP2_3 dr sr (f-simm16 0))
1212
     ; FIXME: Check rounding direction.
1213
     (if (ne sr (const 0)) (set dr (umod dr sr)))
1214
     ((m32r/d (unit u-exec (cycles 37)))
1215
      (m32rx (unit u-exec (cycles 37)))
1216
      (m32r2 (unit u-exec (cycles 37))))
1217
)
1218
 
1219
(dni remh "remh"
1220
     ((MACH m32r2))
1221
     "remh $dr,$sr"
1222
     (+ OP1_9 OP2_2 dr sr (f-simm16 #x10))
1223
     ; FIXME: Check rounding direction.
1224
     (if (ne sr (const 0)) (set dr (mod (ext WI (trunc HI dr)) sr)))
1225
     ((m32r2 (unit u-exec (cycles 21))))
1226
)
1227
 
1228
(dni remuh "remuh"
1229
     ((MACH m32r2))
1230
     "remuh $dr,$sr"
1231
     (+ OP1_9 OP2_3 dr sr (f-simm16 #x10))
1232
     ; FIXME: Check rounding direction.
1233
     (if (ne sr (const 0)) (set dr (umod dr sr)))
1234
     ((m32r2 (unit u-exec (cycles 21))))
1235
)
1236
 
1237
(dni remb "remb"
1238
     ((MACH m32r2))
1239
     "remb $dr,$sr"
1240
     (+ OP1_9 OP2_2 dr sr (f-simm16 #x18))
1241
     ; FIXME: Check rounding direction.
1242
     (if (ne sr (const 0)) (set dr (mod (ext WI (trunc BI dr)) sr)))
1243
     ((m32r2 (unit u-exec (cycles 21))))
1244
)
1245
 
1246
(dni remub "remub"
1247
     ((MACH m32r2))
1248
     "remub $dr,$sr"
1249
     (+ OP1_9 OP2_3 dr sr (f-simm16 #x18))
1250
     ; FIXME: Check rounding direction.
1251
     (if (ne sr (const 0)) (set dr (umod dr sr)))
1252
     ((m32r2 (unit u-exec (cycles 21))))
1253
)
1254
 
1255
(dni divuh "divuh"
1256
     ((MACH m32r2))
1257
     "divuh $dr,$sr"
1258
     (+ OP1_9 OP2_1 dr sr (f-simm16 #x10))
1259
     (if (ne sr (const 0)) (set dr (udiv dr sr)))
1260
     ((m32r2 (unit u-exec (cycles 21))))
1261
)
1262
 
1263
(dni divb "divb"
1264
     ((MACH m32r2))
1265
     "divb $dr,$sr"
1266
     (+ OP1_9 OP2_0 dr sr (f-simm16 #x18))
1267
     (if (ne sr (const 0)) (set dr (div (ext WI (trunc BI dr)) sr)))
1268
     ((m32r2 (unit u-exec (cycles 21))))
1269
)
1270
 
1271
(dni divub "divub"
1272
     ((MACH m32r2))
1273
     "divub $dr,$sr"
1274
     (+ OP1_9 OP2_1 dr sr (f-simm16 #x18))
1275
     (if (ne sr (const 0)) (set dr (udiv dr sr)))
1276
     ((m32r2 (unit u-exec (cycles 21))))
1277
)
1278
 
1279
(dni divh "divh"
1280
     ((MACH m32rx,m32r2) (IDOC ALU))
1281
     "divh $dr,$sr"
1282
     (+ OP1_9 OP2_0 dr sr (f-simm16 #x10))
1283
     (if (ne sr (const 0)) (set dr (div (ext WI (trunc HI dr)) sr)))
1284
     ((m32rx (unit u-exec (cycles 21)))
1285
      (m32r2 (unit u-exec (cycles 21))))
1286
)
1287
 
1288
(dni jc "jc"
1289
     (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
1290
     "jc $sr"
1291
     (+ OP1_1 (f-r1 12) OP2_12 sr)
1292
     (if condbit (set pc (and sr (const -4))))
1293
     ((m32rx (unit u-cti))
1294
      (m32r2 (unit u-cti)))
1295
)
1296
 
1297
(dni jnc "jnc"
1298
     (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
1299
     "jnc $sr"
1300
     (+ OP1_1 (f-r1 13) OP2_12 sr)
1301
     (if (not condbit) (set pc (and sr (const -4))))
1302
     ((m32rx (unit u-cti))
1303
      (m32r2 (unit u-cti)))
1304
)
1305
 
1306
(dni jl "jl"
1307
     (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
1308
     "jl $sr"
1309
     (+ OP1_1 (f-r1 14) OP2_12 sr)
1310
     (parallel ()
1311
               (set (reg h-gr 14)
1312
                    (add (and pc (const -4)) (const 4)))
1313
               (set pc (and sr (const -4))))
1314
     ((m32r/d (unit u-cti))
1315
      (m32rx (unit u-cti))
1316
      (m32r2 (unit u-cti)))
1317
)
1318
 
1319
(dni jmp "jmp"
1320
     (UNCOND-CTI (PIPE O) (IDOC BR))
1321
     "jmp $sr"
1322
     (+ OP1_1 (f-r1 15) OP2_12 sr)
1323
     (set pc (and sr (const -4)))
1324
     ; The above works now so this kludge has been commented out.
1325
     ; It's kept around because the f-r1 reference in the semantic part
1326
     ; should work.
1327
     ; FIXME: kludge, instruction decoding not finished.
1328
     ; But this should work, so that's another FIXME.
1329
     ;(sequence VOID (if VOID (eq SI f-r1 (const SI 14))
1330
     ; FIXME: abuf->insn should be a macro of some sort.
1331
     ;(sequence VOID
1332
     ;         (if VOID (eq SI (c-code SI "((abuf->insn >> 8) & 15)")
1333
     ;                    (const SI 14))
1334
     ;             (set WI (reg WI h-gr 14)
1335
     ;                  (add WI (and WI pc (const WI -4)) (const WI 4))))
1336
     ;         (set WI pc sr))
1337
     ((m32r/d (unit u-cti))
1338
      (m32rx (unit u-cti))
1339
      (m32r2 (unit u-cti)))
1340
)
1341
 
1342
(define-pmacro (no-ext-expr mode expr) expr)
1343
(define-pmacro (ext-expr mode expr) (ext mode expr))
1344
(define-pmacro (zext-expr mode expr) (zext mode expr))
1345
 
1346
(define-pmacro (load-op suffix op2-op mode ext-op)
1347
  (begin
1348
    (dni (.sym ld suffix) (.str "ld" suffix)
1349
         ((PIPE O) (IDOC MEM))
1350
         (.str "ld" suffix " $dr,@$sr")
1351
         (+ OP1_2 op2-op dr sr)
1352
         (set dr (ext-op WI (mem mode sr)))
1353
         ((m32r/d (unit u-load))
1354
          (m32rx (unit u-load))
1355
          (m32r2 (unit u-load)))
1356
         )
1357
    (dnmi (.sym ld suffix "-2") (.str "ld" suffix "-2")
1358
          (NO-DIS (PIPE O) (IDOC MEM))
1359
          (.str "ld" suffix " $dr,@($sr)")
1360
          (emit (.sym ld suffix) dr sr))
1361
    (dni (.sym ld suffix -d) (.str "ld" suffix "-d")
1362
         ((IDOC MEM))
1363
         (.str "ld" suffix " $dr,@($slo16,$sr)")
1364
         (+ OP1_10 op2-op dr sr slo16)
1365
         (set dr (ext-op WI (mem mode (add sr slo16))))
1366
         ((m32r/d (unit u-load (cycles 2)))
1367
          (m32rx (unit u-load (cycles 2)))
1368
          (m32r2 (unit u-load (cycles 2))))
1369
         )
1370
    (dnmi (.sym ld suffix -d2) (.str "ld" suffix "-d2")
1371
          (NO-DIS (IDOC MEM))
1372
          (.str "ld" suffix " $dr,@($sr,$slo16)")
1373
          (emit (.sym ld suffix -d) dr sr slo16))
1374
    )
1375
)
1376
(load-op "" OP2_12 WI no-ext-expr)
1377
(load-op b OP2_8 QI ext-expr)
1378
(load-op h OP2_10 HI ext-expr)
1379
(load-op ub OP2_9 QI zext-expr)
1380
(load-op uh OP2_11 HI zext-expr)
1381
 
1382
(dni ld-plus "ld+"
1383
     ((PIPE O) (IDOC MEM))
1384
     "ld $dr,@$sr+"
1385
     (+ OP1_2 dr OP2_14 sr)
1386
     (parallel ()
1387
               ; wip: memory addresses in profiling support
1388
               ;(set dr (name ld-mem (mem WI sr)))
1389
               (set dr (mem WI sr))
1390
               (set sr (add sr (const 4))))
1391
     ; Note: `pred' is the constraint.  Also useful here is (ref name)
1392
     ; and returns true if operand  was referenced
1393
     ; (where "referenced" means _read_ if input operand and _written_ if
1394
     ; output operand).
1395
     ; args to unit are "unit-name (name1 value1) ..."
1396
     ; - cycles(done),issue,pred are also specified this way
1397
     ; - if unspecified, default is used
1398
     ; - for ins/outs, extra arg is passed that says what was specified
1399
     ;   - this is AND'd with `written' for outs
1400
     ((m32r/d (unit u-load (pred (const 1)))
1401
              (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
1402
      (m32rx (unit u-load)
1403
             (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
1404
      (m32r2 (unit u-load)
1405
             (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
1406
      )
1407
)
1408
 
1409
(dnmi pop "pop"
1410
      ((PIPE O) (IDOC MEM))
1411
      "pop $dr"
1412
      (emit ld-plus dr (sr 15)) ; "ld %0,@sp+"
1413
)
1414
 
1415
(dni ld24 "ld24"
1416
     ((IDOC MEM))
1417
     "ld24 $dr,$uimm24"
1418
     (+ OP1_14 dr uimm24)
1419
     (set dr uimm24)
1420
     ()
1421
)
1422
 
1423
; ldi8 appears before ldi16 so we try the shorter version first
1424
 
1425
(dni ldi8 "ldi8"
1426
     ((PIPE OS) (IDOC ALU))
1427
     "ldi8 $dr,$simm8"
1428
     (+ OP1_6 dr simm8)
1429
     (set dr simm8)
1430
     ()
1431
)
1432
 
1433
(dnmi ldi8a "ldi8 alias"
1434
     ((PIPE OS) (IDOC ALU))
1435
     "ldi $dr,$simm8"
1436
     (emit ldi8 dr simm8)
1437
)
1438
 
1439
(dni ldi16 "ldi16"
1440
     ((IDOC ALU))
1441
     "ldi16 $dr,$hash$slo16"
1442
     (+ OP1_9 OP2_15 (f-r2 0) dr slo16)
1443
     (set dr slo16)
1444
     ()
1445
)
1446
 
1447
(dnmi ldi16a "ldi16 alias"
1448
     ((IDOC ALU))
1449
     "ldi $dr,$hash$slo16"
1450
     (emit ldi16 dr slo16)
1451
)
1452
 
1453
(dni lock "lock"
1454
     ((PIPE O) (IDOC MISC))
1455
     "lock $dr,@$sr"
1456
     (+ OP1_2 OP2_13 dr sr)
1457
     (sequence ()
1458
               (set (reg h-lock) (const BI 1))
1459
               (set dr (mem WI sr)))
1460
     ((m32r/d (unit u-load))
1461
      (m32rx (unit u-load))
1462
      (m32r2 (unit u-load)))
1463
)
1464
 
1465
(dni machi "machi"
1466
     (
1467
      ; (MACH m32r) is a temporary hack.  This insn collides with machi-a
1468
      ; in the simulator so disable it for m32rx.
1469
      (MACH m32r) (PIPE S) (IDOC MAC)
1470
     )
1471
     "machi $src1,$src2"
1472
     (+ OP1_3 OP2_4 src1 src2)
1473
     ; FIXME: TRACE_RESULT will print the wrong thing since we
1474
     ; alter one of the arguments.
1475
     (set accum
1476
          (sra DI
1477
               (sll DI
1478
                    (add DI
1479
                         accum
1480
                         (mul DI
1481
                              (ext DI (and WI src1 (const #xffff0000)))
1482
                              (ext DI (trunc HI (sra WI src2 (const 16))))))
1483
                    (const 8))
1484
               (const 8)))
1485
     ((m32r/d (unit u-mac)))
1486
)
1487
 
1488
(dni machi-a "machi-a"
1489
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
1490
     "machi $src1,$src2,$acc"
1491
     (+ OP1_3 src1 acc (f-op23 4) src2)
1492
     (set acc
1493
          (sra DI
1494
               (sll DI
1495
                    (add DI
1496
                         acc
1497
                         (mul DI
1498
                              (ext DI (and WI src1 (const #xffff0000)))
1499
                              (ext DI (trunc HI (sra WI src2 (const 16))))))
1500
                    (const 8))
1501
               (const 8)))
1502
     ((m32rx (unit u-mac))
1503
      (m32r2 (unit u-mac)))
1504
)
1505
 
1506
(dni maclo "maclo"
1507
     ((MACH m32r) (PIPE S) (IDOC MAC))
1508
     "maclo $src1,$src2"
1509
     (+ OP1_3 OP2_5 src1 src2)
1510
     (set accum
1511
          (sra DI
1512
               (sll DI
1513
                    (add DI
1514
                         accum
1515
                         (mul DI
1516
                              (ext DI (sll WI src1 (const 16)))
1517
                              (ext DI (trunc HI src2))))
1518
                    (const 8))
1519
               (const 8)))
1520
     ((m32r/d (unit u-mac)))
1521
)
1522
 
1523
(dni maclo-a "maclo-a"
1524
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
1525
     "maclo $src1,$src2,$acc"
1526
     (+ OP1_3 src1 acc (f-op23 5) src2)
1527
     (set acc
1528
          (sra DI
1529
               (sll DI
1530
                    (add DI
1531
                         acc
1532
                         (mul DI
1533
                              (ext DI (sll WI src1 (const 16)))
1534
                              (ext DI (trunc HI src2))))
1535
                    (const 8))
1536
               (const 8)))
1537
     ((m32rx (unit u-mac))
1538
      (m32r2 (unit u-mac)))
1539
)
1540
 
1541
(dni macwhi "macwhi"
1542
     ((MACH m32r) (PIPE S) (IDOC MAC))
1543
     "macwhi $src1,$src2"
1544
     (+ OP1_3 OP2_6 src1 src2)
1545
     (set accum
1546
          (sra DI
1547
               (sll DI
1548
                    (add DI
1549
                         accum
1550
                         (mul DI
1551
                              (ext DI src1)
1552
                              (ext DI (trunc HI (sra WI src2 (const 16))))))
1553
                    (const 8))
1554
               (const 8)))
1555
     ((m32r/d (unit u-mac)))
1556
)
1557
 
1558
(dni macwhi-a "macwhi-a"
1559
     ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC))
1560
     "macwhi $src1,$src2,$acc"
1561
     (+ OP1_3 src1 acc (f-op23 6) src2)
1562
     ; Note that this doesn't do the sign extension, which is correct.
1563
     (set acc
1564
          (add acc
1565
               (mul (ext DI src1)
1566
                    (ext DI (trunc HI (sra src2 (const 16)))))))
1567
     ((m32rx (unit u-mac))
1568
      (m32r2 (unit u-mac)))
1569
)
1570
 
1571
(dni macwlo "macwlo"
1572
     ((MACH m32r) (PIPE S) (IDOC MAC))
1573
     "macwlo $src1,$src2"
1574
     (+ OP1_3 OP2_7 src1 src2)
1575
     (set accum
1576
          (sra DI
1577
               (sll DI
1578
                    (add DI
1579
                         accum
1580
                         (mul DI
1581
                              (ext DI src1)
1582
                              (ext DI (trunc HI src2))))
1583
                    (const 8))
1584
               (const 8)))
1585
     ((m32r/d (unit u-mac)))
1586
)
1587
 
1588
(dni macwlo-a "macwlo-a"
1589
     ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC))
1590
     "macwlo $src1,$src2,$acc"
1591
     (+ OP1_3 src1 acc (f-op23 7) src2)
1592
     ; Note that this doesn't do the sign extension, which is correct.
1593
     (set acc
1594
          (add acc
1595
               (mul (ext DI src1)
1596
                    (ext DI (trunc HI src2)))))
1597
     ((m32rx (unit u-mac))
1598
      (m32r2 (unit u-mac)))
1599
)
1600
 
1601
(dni mul "mul"
1602
     ((PIPE S) (IDOC ALU))
1603
     "mul $dr,$sr"
1604
     (+ OP1_1 OP2_6 dr sr)
1605
     (set dr (mul dr sr))
1606
     ((m32r/d (unit u-exec (cycles 4)))
1607
      (m32rx (unit u-exec (cycles 4)))
1608
      (m32r2 (unit u-exec (cycles 4))))
1609
)
1610
 
1611
(dni mulhi "mulhi"
1612
     ((MACH m32r) (PIPE S) (IDOC ACCUM))
1613
     "mulhi $src1,$src2"
1614
     (+ OP1_3 OP2_0 src1 src2)
1615
     (set accum
1616
          (sra DI
1617
               (sll DI
1618
                    (mul DI
1619
                         (ext DI (and WI src1 (const #xffff0000)))
1620
                         (ext DI (trunc HI (sra WI src2 (const 16)))))
1621
                    (const 16))
1622
               (const 16)))
1623
     ((m32r/d (unit u-mac)))
1624
)
1625
 
1626
(dni mulhi-a "mulhi-a"
1627
     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
1628
     "mulhi $src1,$src2,$acc"
1629
     (+ OP1_3 (f-op23 0) src1 acc src2)
1630
     (set acc
1631
          (sra DI
1632
               (sll DI
1633
                    (mul DI
1634
                         (ext DI (and WI src1 (const #xffff0000)))
1635
                         (ext DI (trunc HI (sra WI src2 (const 16)))))
1636
                    (const 16))
1637
               (const 16)))
1638
     ((m32rx (unit u-mac))
1639
      (m32r2 (unit u-mac)))
1640
)
1641
 
1642
(dni mullo "mullo"
1643
     ((MACH m32r) (PIPE S) (IDOC ACCUM))
1644
     "mullo $src1,$src2"
1645
     (+ OP1_3 OP2_1 src1 src2)
1646
     (set accum
1647
          (sra DI
1648
               (sll DI
1649
                    (mul DI
1650
                         (ext DI (sll WI src1 (const 16)))
1651
                         (ext DI (trunc HI src2)))
1652
                    (const 16))
1653
               (const 16)))
1654
     ((m32r/d (unit u-mac)))
1655
)
1656
 
1657
(dni mullo-a "mullo-a"
1658
     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
1659
     "mullo $src1,$src2,$acc"
1660
     (+ OP1_3 src1 acc (f-op23 1) src2)
1661
     (set acc
1662
          (sra DI
1663
               (sll DI
1664
                    (mul DI
1665
                         (ext DI (sll WI src1 (const 16)))
1666
                         (ext DI (trunc HI src2)))
1667
                    (const 16))
1668
               (const 16)))
1669
     ((m32rx (unit u-mac))
1670
      (m32r2 (unit u-mac)))
1671
)
1672
 
1673
(dni mulwhi "mulwhi"
1674
     ((MACH m32r) (PIPE S) (IDOC ACCUM))
1675
     "mulwhi $src1,$src2"
1676
     (+ OP1_3 OP2_2 src1 src2)
1677
     (set accum
1678
          (sra DI
1679
               (sll DI
1680
                    (mul DI
1681
                         (ext DI src1)
1682
                         (ext DI (trunc HI (sra WI src2 (const 16)))))
1683
                    (const 8))
1684
               (const 8)))
1685
     ((m32r/d (unit u-mac)))
1686
)
1687
 
1688
(dni mulwhi-a "mulwhi-a"
1689
     ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM))
1690
     "mulwhi $src1,$src2,$acc"
1691
     (+ OP1_3 src1 acc (f-op23 2) src2)
1692
     ; Note that this doesn't do the sign extension, which is correct.
1693
     (set acc
1694
          (mul (ext DI src1)
1695
               (ext DI (trunc HI (sra src2 (const 16))))))
1696
     ((m32rx (unit u-mac))
1697
      (m32r2 (unit u-mac)))
1698
)
1699
 
1700
(dni mulwlo "mulwlo"
1701
     ((MACH m32r) (PIPE S) (IDOC ACCUM))
1702
     "mulwlo $src1,$src2"
1703
     (+ OP1_3 OP2_3 src1 src2)
1704
     (set accum
1705
          (sra DI
1706
               (sll DI
1707
                    (mul DI
1708
                         (ext DI src1)
1709
                         (ext DI (trunc HI src2)))
1710
                    (const 8))
1711
               (const 8)))
1712
     ((m32r/d (unit u-mac)))
1713
)
1714
 
1715
(dni mulwlo-a "mulwlo-a"
1716
     ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM))
1717
     "mulwlo $src1,$src2,$acc"
1718
     (+ OP1_3 src1 acc (f-op23 3) src2)
1719
     ; Note that this doesn't do the sign extension, which is correct.
1720
     (set acc
1721
          (mul (ext DI src1)
1722
               (ext DI (trunc HI src2))))
1723
     ((m32rx (unit u-mac))
1724
      (m32r2 (unit u-mac)))
1725
)
1726
 
1727
(dni mv "mv"
1728
     ((PIPE OS) (IDOC ALU))
1729
     "mv $dr,$sr"
1730
     (+ OP1_1 OP2_8 dr sr)
1731
     (set dr sr)
1732
     ()
1733
)
1734
 
1735
(dni mvfachi "mvfachi"
1736
     ((MACH m32r) (PIPE S) (IDOC ACCUM))
1737
     "mvfachi $dr"
1738
     (+ OP1_5 OP2_15 (f-r2 0) dr)
1739
     (set dr (trunc WI (sra DI accum (const 32))))
1740
     ((m32r/d (unit u-exec (cycles 2))))
1741
)
1742
 
1743
(dni mvfachi-a "mvfachi-a"
1744
     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
1745
     "mvfachi $dr,$accs"
1746
     (+ OP1_5 dr OP2_15 accs (f-op3 0))
1747
     (set dr (trunc WI (sra DI accs (const 32))))
1748
     ((m32rx (unit u-exec (cycles 2)))
1749
      (m32r2 (unit u-exec (cycles 2))))
1750
)
1751
 
1752
(dni mvfaclo "mvfaclo"
1753
     ((MACH m32r) (PIPE S) (IDOC ACCUM))
1754
     "mvfaclo $dr"
1755
     (+ OP1_5 OP2_15 (f-r2 1) dr)
1756
     (set dr (trunc WI accum))
1757
     ((m32r/d (unit u-exec (cycles 2))))
1758
)
1759
 
1760
(dni mvfaclo-a "mvfaclo-a"
1761
     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
1762
     "mvfaclo $dr,$accs"
1763
     (+ OP1_5 dr OP2_15 accs (f-op3 1))
1764
     (set dr (trunc WI accs))
1765
     ((m32rx (unit u-exec (cycles 2)))
1766
      (m32r2 (unit u-exec (cycles 2))))
1767
)
1768
 
1769
(dni mvfacmi "mvfacmi"
1770
     ((MACH m32r) (PIPE S) (IDOC ACCUM))
1771
     "mvfacmi $dr"
1772
     (+ OP1_5 OP2_15 (f-r2 2) dr)
1773
     (set dr (trunc WI (sra DI accum (const 16))))
1774
     ((m32r/d (unit u-exec (cycles 2))))
1775
)
1776
 
1777
(dni mvfacmi-a "mvfacmi-a"
1778
     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
1779
     "mvfacmi $dr,$accs"
1780
     (+ OP1_5 dr OP2_15 accs (f-op3 2))
1781
     (set dr (trunc WI (sra DI accs (const 16))))
1782
     ((m32rx (unit u-exec (cycles 2)))
1783
      (m32r2 (unit u-exec (cycles 2))))
1784
)
1785
 
1786
(dni mvfc "mvfc"
1787
     ((PIPE O) (IDOC MISC))
1788
     "mvfc $dr,$scr"
1789
     (+ OP1_1 OP2_9 dr scr)
1790
     (set dr scr)
1791
     ()
1792
)
1793
 
1794
(dni mvtachi "mvtachi"
1795
     ((MACH m32r) (PIPE S) (IDOC ACCUM))
1796
     "mvtachi $src1"
1797
     (+ OP1_5 OP2_7 (f-r2 0) src1)
1798
     (set accum
1799
          (or DI
1800
              (and DI accum (const DI #xffffffff))
1801
              (sll DI (ext DI src1) (const 32))))
1802
     ((m32r/d (unit u-exec (in sr src1))))
1803
)
1804
 
1805
(dni mvtachi-a "mvtachi-a"
1806
     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
1807
     "mvtachi $src1,$accs"
1808
     (+ OP1_5 src1 OP2_7 accs (f-op3 0))
1809
     (set accs
1810
          (or DI
1811
              (and DI accs (const DI #xffffffff))
1812
              (sll DI (ext DI src1) (const 32))))
1813
     ((m32rx (unit u-exec (in sr src1)))
1814
      (m32r2 (unit u-exec (in sr src1))))
1815
)
1816
 
1817
(dni mvtaclo "mvtaclo"
1818
     ((MACH m32r) (PIPE S) (IDOC ACCUM))
1819
     "mvtaclo $src1"
1820
     (+ OP1_5 OP2_7 (f-r2 1) src1)
1821
     (set accum
1822
          (or DI
1823
              (and DI accum (const DI #xffffffff00000000))
1824
              (zext DI src1)))
1825
     ((m32r/d (unit u-exec (in sr src1))))
1826
)
1827
 
1828
(dni mvtaclo-a "mvtaclo-a"
1829
     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
1830
     "mvtaclo $src1,$accs"
1831
     (+ OP1_5 src1 OP2_7 accs (f-op3 1))
1832
     (set accs
1833
          (or DI
1834
              (and DI accs (const DI #xffffffff00000000))
1835
              (zext DI src1)))
1836
     ((m32rx (unit u-exec (in sr src1)))
1837
      (m32r2 (unit u-exec (in sr src1))))
1838
)
1839
 
1840
(dni mvtc "mvtc"
1841
     ((PIPE O) (IDOC MISC))
1842
     "mvtc $sr,$dcr"
1843
     (+ OP1_1 OP2_10 dcr sr)
1844
     (set dcr sr)
1845
     ()
1846
)
1847
 
1848
(dni neg "neg"
1849
     ((PIPE OS) (IDOC ALU))
1850
     "neg $dr,$sr"
1851
     (+ OP1_0 OP2_3 dr sr)
1852
     (set dr (neg sr))
1853
     ()
1854
)
1855
 
1856
(dni nop "nop"
1857
     ((PIPE OS) (IDOC MISC))
1858
     "nop"
1859
     (+ OP1_7 OP2_0 (f-r1 0) (f-r2 0))
1860
     (c-code VOID "PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);\n")
1861
     ; FIXME: quick hack: parallel nops don't contribute to cycle count.
1862
     ; Other kinds of nops do however (which we currently ignore).
1863
     ((m32r/d (unit u-exec (cycles 0)))
1864
      (m32rx (unit u-exec (cycles 0)))
1865
      (m32r2 (unit u-exec (cycles 0))))
1866
)
1867
 
1868
(dni not "not"
1869
     ((PIPE OS) (IDOC ALU))
1870
     "not $dr,$sr"
1871
     (+ OP1_0 OP2_11 dr sr)
1872
     (set dr (inv sr))
1873
     ()
1874
)
1875
 
1876
(dni rac "rac"
1877
     ((MACH m32r) (PIPE S) (IDOC MAC))
1878
     "rac"
1879
     (+ OP1_5 OP2_9 (f-r1 0) (f-r2 0))
1880
     (sequence ((DI tmp1))
1881
               (set tmp1 (sll DI accum (const 1)))
1882
               (set tmp1 (add DI tmp1 (const DI #x8000)))
1883
               (set accum
1884
                    (cond DI
1885
                          ((gt tmp1 (const DI #x00007fffffff0000))
1886
                           (const DI #x00007fffffff0000))
1887
                          ((lt tmp1 (const DI #xffff800000000000))
1888
                           (const DI #xffff800000000000))
1889
                          (else (and tmp1 (const DI #xffffffffffff0000)))))
1890
               )
1891
     ((m32r/d (unit u-mac)))
1892
)
1893
 
1894
(dni rac-dsi "rac-dsi"
1895
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
1896
     "rac $accd,$accs,$imm1"
1897
     (+ OP1_5 accd (f-bits67 0) OP2_9 accs (f-bit14 0) imm1)
1898
     (sequence ((DI tmp1))
1899
               (set tmp1 (sll accs imm1))
1900
               (set tmp1 (add tmp1 (const DI #x8000)))
1901
               (set accd
1902
                    (cond DI
1903
                          ((gt tmp1 (const DI #x00007fffffff0000))
1904
                           (const DI #x00007fffffff0000))
1905
                          ((lt tmp1 (const DI #xffff800000000000))
1906
                           (const DI #xffff800000000000))
1907
                          (else (and tmp1 (const DI #xffffffffffff0000)))))
1908
               )
1909
     ((m32rx (unit u-mac))
1910
      (m32r2 (unit u-mac)))
1911
)
1912
 
1913
(dnmi rac-d "rac-d"
1914
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
1915
     "rac $accd"
1916
     (emit rac-dsi accd (f-accs 0) (f-imm1 0))
1917
)
1918
 
1919
(dnmi rac-ds "rac-ds"
1920
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
1921
     "rac $accd,$accs"
1922
     (emit rac-dsi accd accs (f-imm1 0))
1923
)
1924
 
1925
 
1926
(dni rach "rach"
1927
     ((MACH m32r) (PIPE S) (IDOC MAC))
1928
     "rach"
1929
     (+ OP1_5 OP2_8 (f-r1 0) (f-r2 0))
1930
     (sequence ((DI tmp1))
1931
               ; Lop off top 8 bits.
1932
               ; The sign bit we want to use is bit 55 so the 64 bit value
1933
               ; isn't properly signed which we deal with in the if's below.
1934
               (set tmp1 (and accum (const DI #xffffffffffffff)))
1935
               (if (andif (ge tmp1 (const DI #x003fff80000000))
1936
                          (le tmp1 (const DI #x7fffffffffffff)))
1937
                   (set tmp1 (const DI #x003fff80000000))
1938
                   ; else part
1939
                   (if (andif (ge tmp1 (const DI #x80000000000000))
1940
                              (le tmp1 (const DI #xffc00000000000)))
1941
                       (set tmp1 (const DI #xffc00000000000))
1942
                       (set tmp1 (and (add accum (const DI #x40000000))
1943
                                      (const DI #xffffffff80000000)))))
1944
               (set tmp1 (sll tmp1 (const 1)))
1945
               ; Sign extend top 8 bits.
1946
               (set accum
1947
                    ; FIXME: 7?
1948
                    (sra DI (sll DI tmp1 (const 7)) (const 7)))
1949
               )
1950
     ((m32r/d (unit u-mac)))
1951
)
1952
 
1953
(dni rach-dsi "rach-dsi"
1954
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
1955
     "rach $accd,$accs,$imm1"
1956
     (+ OP1_5 accd (f-bits67 0) OP2_8 accs (f-bit14 0) imm1)
1957
     (sequence ((DI tmp1))
1958
               (set tmp1 (sll accs imm1))
1959
               (set tmp1 (add tmp1 (const DI #x80000000)))
1960
               (set accd
1961
                    (cond DI
1962
                          ((gt tmp1 (const DI #x00007fff00000000))
1963
                           (const DI #x00007fff00000000))
1964
                          ((lt tmp1 (const DI #xffff800000000000))
1965
                           (const DI #xffff800000000000))
1966
                          (else (and tmp1 (const DI #xffffffff00000000)))))
1967
               )
1968
     ((m32rx (unit u-mac))
1969
      (m32r2 (unit u-mac)))
1970
)
1971
 
1972
(dnmi rach-d "rach-d"
1973
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
1974
     "rach $accd"
1975
     (emit rach-dsi accd (f-accs 0) (f-imm1 0))
1976
)
1977
 
1978
(dnmi rach-ds "rach-ds"
1979
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
1980
     "rach $accd,$accs"
1981
     (emit rach-dsi accd accs (f-imm1 0))
1982
)
1983
 
1984
(dni rte "rte"
1985
     (UNCOND-CTI (PIPE O) (IDOC BR))
1986
     "rte"
1987
     (+ OP1_1 OP2_13 (f-r1 0) (f-r2 6))
1988
     (sequence ()
1989
               ; pc = bpc & -4
1990
               (set pc (and (reg h-cr 6) (const -4)))
1991
               ; bpc = bbpc
1992
               (set (reg h-cr 6) (reg h-cr 14))
1993
               ; psw = bpsw
1994
               (set (reg h-psw) (reg h-bpsw))
1995
               ; bpsw = bbpsw
1996
               (set (reg h-bpsw) (reg h-bbpsw))
1997
     )
1998
     ()
1999
)
2000
 
2001
(dni seth "seth"
2002
     ((IDOC ALU))
2003
     "seth $dr,$hash$hi16"
2004
     (+ OP1_13 OP2_12 dr (f-r2 0) hi16)
2005
     (set dr (sll WI hi16 (const 16)))
2006
     ()
2007
)
2008
 
2009
(define-pmacro (shift-op sym op2-r-op op2-3-op op2-i-op sem-op)
2010
  (begin
2011
     (dni sym sym ((PIPE O_OS) (IDOC ALU))
2012
          (.str sym " $dr,$sr")
2013
          (+ OP1_1 op2-r-op dr sr)
2014
          (set dr (sem-op dr (and sr (const 31))))
2015
          ()
2016
     )
2017
     (dni (.sym sym "3") sym ((IDOC ALU))
2018
          (.str sym "3 $dr,$sr,$simm16")
2019
          (+ OP1_9 op2-3-op dr sr simm16)
2020
          (set dr (sem-op sr (and WI simm16 (const 31))))
2021
          ()
2022
     )
2023
     (dni (.sym sym "i") sym ((PIPE O_OS) (IDOC ALU))
2024
          (.str sym "i $dr,$uimm5")
2025
          (+ OP1_5 (f-shift-op2 op2-i-op) dr uimm5)
2026
          (set dr (sem-op dr uimm5))
2027
          ()
2028
     )
2029
   )
2030
)
2031
(shift-op sll OP2_4 OP2_12 2 sll)
2032
(shift-op sra OP2_2 OP2_10 1 sra)
2033
(shift-op srl OP2_0 OP2_8 0 srl)
2034
 
2035
(define-pmacro (store-op suffix op2-op mode)
2036
  (begin
2037
    (dni (.sym st suffix) (.str "st" suffix)
2038
         ((PIPE O) (IDOC MEM))
2039
         (.str "st" suffix " $src1,@$src2")
2040
         (+ OP1_2 op2-op src1 src2)
2041
         (set mode (mem mode src2) src1)
2042
         ((m32r/d (unit u-store (cycles 1)))
2043
          (m32rx (unit u-store (cycles 1)))
2044
          (m32r2 (unit u-store (cycles 1))))
2045
         )
2046
    (dnmi (.sym st suffix "-2") (.str "st" suffix "-2")
2047
          (NO-DIS (PIPE O) (IDOC MEM))
2048
          (.str "st" suffix " $src1,@($src2)")
2049
          (emit (.sym st suffix) src1 src2))
2050
    (dni (.sym st suffix -d) (.str "st" suffix "-d")
2051
         ((IDOC MEM))
2052
         (.str "st" suffix " $src1,@($slo16,$src2)")
2053
         (+ OP1_10 op2-op src1 src2 slo16)
2054
         (set mode (mem mode (add src2 slo16)) src1)
2055
         ((m32r/d (unit u-store (cycles 2)))
2056
          (m32rx (unit u-store (cycles 2)))
2057
          (m32r2 (unit u-store (cycles 2))))
2058
         )
2059
    (dnmi (.sym st suffix -d2) (.str "st" suffix "-d2")
2060
          (NO-DIS (IDOC MEM))
2061
          (.str "st" suffix " $src1,@($src2,$slo16)")
2062
          (emit (.sym st suffix -d) src1 src2 slo16))
2063
    )
2064
)
2065
(store-op "" OP2_4 WI)
2066
(store-op b OP2_0 QI)
2067
(store-op h OP2_2 HI)
2068
 
2069
(dni st-plus "st+"
2070
     ((PIPE O) (IDOC MEM))
2071
     "st $src1,@+$src2"
2072
     (+ OP1_2 OP2_6 src1 src2)
2073
     ; This has to be coded carefully to avoid an "earlyclobber" of src2.
2074
     (sequence ((WI new-src2))
2075
               (set new-src2 (add WI src2 (const WI 4)))
2076
               (set (mem WI new-src2) src1)
2077
               (set src2 new-src2))
2078
     ((m32r/d (unit u-store)
2079
              (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2080
      (m32rx (unit u-store)
2081
             (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2082
      (m32r2 (unit u-store)
2083
             (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2084
      )
2085
)
2086
 
2087
(dni sth-plus "sth+"
2088
     ((MACH m32rx,m32r2) (PIPE O) SPECIAL)
2089
     "sth $src1,@$src2+"
2090
     (+ OP1_2 OP2_3 src1 src2)
2091
     ; This has to be coded carefully to avoid an "earlyclobber" of src2.
2092
     (sequence ((HI new-src2))
2093
             (set (mem HI new-src2) src1)
2094
             (set new-src2 (add src2 (const 2)))
2095
             (set src2 new-src2))
2096
     ((m32rx (unit u-store)
2097
           (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2098
      (m32r2 (unit u-store)
2099
           (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2100
      )
2101
)
2102
 
2103
(dni stb-plus "stb+"
2104
     ((MACH m32rx,m32r2) (PIPE O) SPECIAL)
2105
     "stb $src1,@$src2+"
2106
     (+ OP1_2 OP2_1 src1 src2)
2107
     ; This has to be coded carefully to avoid an "earlyclobber" of src2.
2108
     (sequence ((QI new-src2))
2109
             (set (mem QI new-src2) src1)
2110
             (set new-src2 (add src2 (const 1)))
2111
             (set src2 new-src2))
2112
     ((m32rx (unit u-store)
2113
           (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2114
      (m32r2 (unit u-store)
2115
           (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2116
      )
2117
)
2118
 
2119
(dni st-minus "st-"
2120
     ((PIPE O) (IDOC MEM))
2121
     "st $src1,@-$src2"
2122
     (+ OP1_2 OP2_7 src1 src2)
2123
     ; This is the original way.  It doesn't work for parallel execution
2124
     ; because of the earlyclobber of src2.
2125
     ;(sequence ()
2126
     ;         (set src2 (sub src2 (const 4)))
2127
     ;         (set (mem WI src2) src1))
2128
     (sequence ((WI new-src2))
2129
               (set new-src2 (sub src2 (const 4)))
2130
               (set (mem WI new-src2) src1)
2131
               (set src2 new-src2))
2132
     ((m32r/d (unit u-store)
2133
              (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2134
      (m32rx (unit u-store)
2135
             (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2136
      (m32r2 (unit u-store)
2137
             (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2138
      )
2139
)
2140
 
2141
(dnmi push "push" ((PIPE O) (IDOC MEM))
2142
  "push $src1"
2143
  (emit st-minus src1 (src2 15)) ; "st %0,@-sp"
2144
)
2145
 
2146
(dni sub "sub"
2147
     ((PIPE OS) (IDOC ALU))
2148
     "sub $dr,$sr"
2149
     (+ OP1_0 OP2_2 dr sr)
2150
     (set dr (sub dr sr))
2151
     ()
2152
)
2153
 
2154
(dni subv "sub:rv"
2155
     ((PIPE OS) (IDOC ALU))
2156
     "subv $dr,$sr"
2157
     (+ OP1_0 OP2_0 dr sr)
2158
     (parallel ()
2159
               (set dr (sub dr sr))
2160
               (set condbit (sub-oflag dr sr (const 0))))
2161
     ()
2162
)
2163
 
2164
(dni subx "sub:rx"
2165
     ((PIPE OS) (IDOC ALU))
2166
     "subx $dr,$sr"
2167
     (+ OP1_0 OP2_1 dr sr)
2168
     (parallel ()
2169
               (set dr (subc dr sr condbit))
2170
               (set condbit (sub-cflag dr sr condbit)))
2171
     ()
2172
)
2173
 
2174
(dni trap "trap"
2175
     (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC MISC))
2176
     "trap $uimm4"
2177
     (+ OP1_1 OP2_15 (f-r1 0) uimm4)
2178
     (sequence ()
2179
               ; bbpc = bpc
2180
               (set (reg h-cr 14) (reg h-cr 6))
2181
               ; Set bpc to the return address.  Actually it's not quite the
2182
               ; return address as RTE rounds the address down to a word
2183
               ; boundary.
2184
               (set (reg h-cr 6) (add pc (const 4)))
2185
               ; bbpsw = bpsw
2186
               (set (reg h-bbpsw) (reg h-bpsw))
2187
               ; bpsw = psw
2188
               (set (reg h-bpsw) (reg h-psw))
2189
               ; sm is unchanged, ie,c are set to zero.
2190
               (set (reg h-psw) (and (reg h-psw) (const #x80)))
2191
               ; m32r_trap handles operating vs user mode
2192
               (set WI pc (c-call WI "m32r_trap" pc uimm4))
2193
     )
2194
     ()
2195
)
2196
 
2197
(dni unlock "unlock"
2198
     ((PIPE O) (IDOC MISC))
2199
     "unlock $src1,@$src2"
2200
     (+ OP1_2 OP2_5 src1 src2)
2201
     (sequence ()
2202
               (if (reg h-lock)
2203
                   (set (mem WI src2) src1))
2204
               (set (reg h-lock) (const BI 0)))
2205
     ((m32r/d (unit u-load))
2206
      (m32rx (unit u-load))
2207
      (m32r2 (unit u-load)))
2208
)
2209
 
2210
; Saturate into byte.
2211
(dni satb "satb"
2212
     ((MACH m32rx,m32r2) (IDOC ALU))
2213
     "satb $dr,$sr"
2214
     (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0300))
2215
     (set dr
2216
          ; FIXME: min/max would simplify this nicely of course.
2217
          (cond WI
2218
                ((ge sr (const 127)) (const 127))
2219
                ((le sr (const -128)) (const -128))
2220
                (else sr)))
2221
     ()
2222
)
2223
 
2224
; Saturate into half word.
2225
(dni sath "sath"
2226
     ((MACH m32rx,m32r2) (IDOC ALU))
2227
     "sath $dr,$sr"
2228
     (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0200))
2229
     (set dr
2230
          (cond WI
2231
                ((ge sr (const 32767)) (const 32767))
2232
                ((le sr (const -32768)) (const -32768))
2233
                (else sr)))
2234
     ()
2235
)
2236
 
2237
; Saturate word.
2238
(dni sat "sat"
2239
     ((MACH m32rx,m32r2) SPECIAL (IDOC ALU))
2240
     "sat $dr,$sr"
2241
     (+ OP1_8 dr OP2_6 sr (f-uimm16 0))
2242
     (set dr
2243
          (if WI condbit
2244
               (if WI (lt sr (const 0))
2245
                    (const #x7fffffff)
2246
                    (const #x80000000))
2247
               sr))
2248
     ()
2249
)
2250
 
2251
; Parallel compare byte zeros.
2252
; Set C bit in condition register if any byte in source register is zero.
2253
(dni pcmpbz "pcmpbz"
2254
     ((MACH m32rx,m32r2) (PIPE OS) SPECIAL (IDOC ALU))
2255
     "pcmpbz $src2"
2256
     (+ OP1_0 (f-r1 3) OP2_7 src2)
2257
     (set condbit
2258
          (cond BI
2259
                 ((eq (and src2 (const #xff)) (const 0)) (const BI 1))
2260
                 ((eq (and src2 (const #xff00)) (const 0)) (const BI 1))
2261
                 ((eq (and src2 (const #xff0000)) (const 0)) (const BI 1))
2262
                 ((eq (and src2 (const #xff000000)) (const 0)) (const BI 1))
2263
                 (else (const BI 0))))
2264
     ((m32rx (unit u-cmp))
2265
      (m32r2 (unit u-cmp)))
2266
)
2267
 
2268
; Add accumulators
2269
(dni sadd "sadd"
2270
     ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
2271
     "sadd"
2272
     (+ OP1_5 (f-r1 0) OP2_14 (f-r2 4))
2273
     (set (reg h-accums 0)
2274
          (add (sra (reg h-accums 1) (const 16))
2275
               (reg h-accums 0)))
2276
     ((m32rx (unit u-mac))
2277
      (m32r2 (unit u-mac)))
2278
)
2279
 
2280
; Multiply and add into accumulator 1
2281
(dni macwu1 "macwu1"
2282
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
2283
     "macwu1 $src1,$src2"
2284
     (+ OP1_5 src1 OP2_11 src2)
2285
     (set (reg h-accums 1)
2286
          (sra DI
2287
                (sll DI
2288
                      (add DI
2289
                            (reg h-accums 1)
2290
                            (mul DI
2291
                                  (ext DI src1)
2292
                                  (ext DI (and src2 (const #xffff)))))
2293
                      (const 8))
2294
                (const 8)))
2295
     ((m32rx (unit u-mac))
2296
      (m32r2 (unit u-mac)))
2297
)
2298
 
2299
; Multiply and subtract from accumulator 0
2300
(dni msblo "msblo"
2301
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
2302
     "msblo $src1,$src2"
2303
     (+ OP1_5 src1 OP2_13 src2)
2304
     (set accum
2305
          (sra DI
2306
                (sll DI
2307
                      (sub accum
2308
                           (sra DI
2309
                                 (sll DI
2310
                                       (mul DI
2311
                                             (ext DI (trunc HI src1))
2312
                                             (ext DI (trunc HI src2)))
2313
                                       (const 32))
2314
                                 (const 16)))
2315
                      (const 8))
2316
                (const 8)))
2317
     ((m32rx (unit u-mac))
2318
      (m32r2 (unit u-mac)))
2319
)
2320
 
2321
; Multiply into accumulator 1
2322
(dni mulwu1 "mulwu1"
2323
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
2324
     "mulwu1 $src1,$src2"
2325
     (+ OP1_5 src1 OP2_10 src2)
2326
     (set (reg h-accums 1)
2327
          (sra DI
2328
                (sll DI
2329
                      (mul DI
2330
                            (ext DI src1)
2331
                            (ext DI (and src2 (const #xffff))))
2332
                      (const 16))
2333
                (const 16)))
2334
     ((m32rx (unit u-mac))
2335
      (m32r2 (unit u-mac)))
2336
)
2337
 
2338
; Multiply and add into accumulator 1
2339
(dni maclh1 "maclh1"
2340
     ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
2341
     "maclh1 $src1,$src2"
2342
     (+ OP1_5 src1 OP2_12 src2)
2343
     (set (reg h-accums 1)
2344
          (sra DI
2345
                (sll DI
2346
                    (add DI
2347
                          (reg h-accums 1)
2348
                          (sll DI
2349
                                (ext DI
2350
                                      (mul SI
2351
                                            (ext SI (trunc HI src1))
2352
                                            (sra SI src2 (const SI 16))))
2353
                              (const 16)))
2354
                    (const 8))
2355
               (const 8)))
2356
     ((m32rx (unit u-mac))
2357
      (m32r2 (unit u-mac)))
2358
)
2359
 
2360
; skip instruction if C
2361
(dni sc "sc"
2362
     ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
2363
     "sc"
2364
     (+ OP1_7 (f-r1 4) OP2_0 (f-r2 1))
2365
     (skip (zext INT condbit))
2366
     ()
2367
)
2368
 
2369
; skip instruction if not C
2370
(dni snc "snc"
2371
     ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
2372
     "snc"
2373
     (+ OP1_7 (f-r1 5) OP2_0 (f-r2 1))
2374
     (skip (zext INT (not condbit)))
2375
     ()
2376
)
2377
 
2378
; PSW &= ~((unsigned char) uimm8 | 0x000ff00)
2379
(dni clrpsw "clrpsw"
2380
     ((PIPE O) SPECIAL_M32R)
2381
     "clrpsw $uimm8"
2382
     (+ OP1_7 (f-r1 2) uimm8)
2383
     (set USI (reg h-cr 0)
2384
              (and USI (reg h-cr 0)
2385
                     (or USI (inv BI uimm8) (const #xff00))))
2386
     ()
2387
)
2388
 
2389
; PSW |= (unsigned char) uimm8
2390
(dni setpsw "setpsw"
2391
     ((PIPE O) SPECIAL_M32R)
2392
     "setpsw $uimm8"
2393
     (+ OP1_7 (f-r1 1) uimm8)
2394
     (set USI (reg h-cr 0) uimm8)
2395
     ()
2396
)
2397
 
2398
; bset
2399
(dni bset "bset"
2400
     (SPECIAL_M32R)
2401
     "bset $uimm3,@($slo16,$sr)"
2402
     (+ OP1_10 (f-bit4 0) uimm3 OP2_6 sr slo16)
2403
     (set QI (mem QI (add sr slo16))
2404
             (or QI (mem QI (add sr slo16))
2405
                  (sll USI (const 1) (sub (const 7) uimm3))))
2406
     ()
2407
)
2408
 
2409
; bclr
2410
(dni bclr "bclr"
2411
     (SPECIAL_M32R)
2412
     "bclr $uimm3,@($slo16,$sr)"
2413
     (+ OP1_10 (f-bit4 0) uimm3  OP2_7 sr slo16)
2414
     (set QI (mem QI (add sr slo16))
2415
             (and QI (mem QI (add sr slo16))
2416
                   (inv QI (sll USI (const 1) (sub (const 7) uimm3)))))
2417
     ()
2418
)
2419
 
2420
; btst
2421
(dni btst "btst"
2422
     (SPECIAL_M32R (PIPE O))
2423
     "btst $uimm3,$sr"
2424
     (+ OP1_0 (f-bit4 0) uimm3 OP2_15 sr)
2425
     (set condbit (and QI (srl USI sr (sub (const 7) uimm3)) (const 1)))
2426
     ()
2427
)
2428
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.