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[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [gas/] [config/] [tc-bfin.c] - Blame information for rev 205

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1 205 julius
/* tc-bfin.c -- Assembler for the ADI Blackfin.
2
   Copyright 2005, 2006, 2007, 2008, 2009
3
   Free Software Foundation, Inc.
4
 
5
   This file is part of GAS, the GNU Assembler.
6
 
7
   GAS is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
 
12
   GAS is distributed in the hope that it will be useful,
13
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
   GNU General Public License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with GAS; see the file COPYING.  If not, write to the Free
19
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20
   02110-1301, USA.  */
21
 
22
#include "as.h"
23
#include "struc-symbol.h"
24
#include "bfin-defs.h"
25
#include "obstack.h"
26
#include "safe-ctype.h"
27
#ifdef OBJ_ELF
28
#include "dwarf2dbg.h"
29
#endif
30
#include "libbfd.h"
31
#include "elf/common.h"
32
#include "elf/bfin.h"
33
 
34
extern int yyparse (void);
35
struct yy_buffer_state;
36
typedef struct yy_buffer_state *YY_BUFFER_STATE;
37
extern YY_BUFFER_STATE yy_scan_string (const char *yy_str);
38
extern void yy_delete_buffer (YY_BUFFER_STATE b);
39
static parse_state parse (char *line);
40
 
41
/* Global variables. */
42
struct bfin_insn *insn;
43
int last_insn_size;
44
 
45
extern struct obstack mempool;
46
FILE *errorf;
47
 
48
/* Flags to set in the elf header */
49
#define DEFAULT_FLAGS 0
50
 
51
#ifdef OBJ_FDPIC_ELF
52
# define DEFAULT_FDPIC EF_BFIN_FDPIC
53
#else
54
# define DEFAULT_FDPIC 0
55
#endif
56
 
57
static flagword bfin_flags = DEFAULT_FLAGS | DEFAULT_FDPIC;
58
static const char *bfin_pic_flag = DEFAULT_FDPIC ? "-mfdpic" : (const char *)0;
59
 
60
/* Blackfin specific function to handle FD-PIC pointer initializations.  */
61
 
62
static void
63
bfin_pic_ptr (int nbytes)
64
{
65
  expressionS exp;
66
  char *p;
67
 
68
  if (nbytes != 4)
69
    abort ();
70
 
71
#ifdef md_flush_pending_output
72
  md_flush_pending_output ();
73
#endif
74
 
75
  if (is_it_end_of_statement ())
76
    {
77
      demand_empty_rest_of_line ();
78
      return;
79
    }
80
 
81
#ifdef md_cons_align
82
  md_cons_align (nbytes);
83
#endif
84
 
85
  do
86
    {
87
      bfd_reloc_code_real_type reloc_type = BFD_RELOC_BFIN_FUNCDESC;
88
 
89
      if (strncasecmp (input_line_pointer, "funcdesc(", 9) == 0)
90
        {
91
          input_line_pointer += 9;
92
          expression (&exp);
93
          if (*input_line_pointer == ')')
94
            input_line_pointer++;
95
          else
96
            as_bad (_("missing ')'"));
97
        }
98
      else
99
        error ("missing funcdesc in picptr");
100
 
101
      p = frag_more (4);
102
      memset (p, 0, 4);
103
      fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
104
                   reloc_type);
105
    }
106
  while (*input_line_pointer++ == ',');
107
 
108
  input_line_pointer--;                 /* Put terminator back into stream. */
109
  demand_empty_rest_of_line ();
110
}
111
 
112
static void
113
bfin_s_bss (int ignore ATTRIBUTE_UNUSED)
114
{
115
  register int temp;
116
 
117
  temp = get_absolute_expression ();
118
  subseg_set (bss_section, (subsegT) temp);
119
  demand_empty_rest_of_line ();
120
}
121
 
122
const pseudo_typeS md_pseudo_table[] = {
123
  {"align", s_align_bytes, 0},
124
  {"byte2", cons, 2},
125
  {"byte4", cons, 4},
126
  {"picptr", bfin_pic_ptr, 4},
127
  {"code", obj_elf_section, 0},
128
  {"db", cons, 1},
129
  {"dd", cons, 4},
130
  {"dw", cons, 2},
131
  {"p", s_ignore, 0},
132
  {"pdata", s_ignore, 0},
133
  {"var", s_ignore, 0},
134
  {"bss", bfin_s_bss, 0},
135
  {0, 0, 0}
136
};
137
 
138
/* Characters that are used to denote comments and line separators. */
139
const char comment_chars[] = "";
140
const char line_comment_chars[] = "#";
141
const char line_separator_chars[] = ";";
142
 
143
/* Characters that can be used to separate the mantissa from the
144
   exponent in floating point numbers. */
145
const char EXP_CHARS[] = "eE";
146
 
147
/* Characters that mean this number is a floating point constant.
148
   As in 0f12.456 or  0d1.2345e12.  */
149
const char FLT_CHARS[] = "fFdDxX";
150
 
151
typedef enum bfin_cpu_type
152
{
153
  BFIN_CPU_UNKNOWN,
154
  BFIN_CPU_BF512,
155
  BFIN_CPU_BF514,
156
  BFIN_CPU_BF516,
157
  BFIN_CPU_BF518,
158
  BFIN_CPU_BF522,
159
  BFIN_CPU_BF523,
160
  BFIN_CPU_BF524,
161
  BFIN_CPU_BF525,
162
  BFIN_CPU_BF526,
163
  BFIN_CPU_BF527,
164
  BFIN_CPU_BF531,
165
  BFIN_CPU_BF532,
166
  BFIN_CPU_BF533,
167
  BFIN_CPU_BF534,
168
  BFIN_CPU_BF536,
169
  BFIN_CPU_BF537,
170
  BFIN_CPU_BF538,
171
  BFIN_CPU_BF539,
172
  BFIN_CPU_BF542,
173
  BFIN_CPU_BF542M,
174
  BFIN_CPU_BF544,
175
  BFIN_CPU_BF544M,
176
  BFIN_CPU_BF547,
177
  BFIN_CPU_BF547M,
178
  BFIN_CPU_BF548,
179
  BFIN_CPU_BF548M,
180
  BFIN_CPU_BF549,
181
  BFIN_CPU_BF549M,
182
  BFIN_CPU_BF561
183
} bfin_cpu_t;
184
 
185
bfin_cpu_t bfin_cpu_type = BFIN_CPU_UNKNOWN;
186
/* -msi-revision support. There are three special values:
187
   -1      -msi-revision=none.
188
   0xffff  -msi-revision=any.  */
189
int bfin_si_revision;
190
 
191
unsigned int bfin_anomaly_checks = 0;
192
 
193
struct bfin_cpu
194
{
195
  const char *name;
196
  bfin_cpu_t type;
197
  int si_revision;
198
  unsigned int anomaly_checks;
199
};
200
 
201
struct bfin_cpu bfin_cpus[] =
202
{
203
  {"bf512", BFIN_CPU_BF512, 0x0001, AC_05000074},
204
  {"bf512", BFIN_CPU_BF512, 0x0000, AC_05000074},
205
 
206
  {"bf514", BFIN_CPU_BF514, 0x0001, AC_05000074},
207
  {"bf514", BFIN_CPU_BF514, 0x0000, AC_05000074},
208
 
209
  {"bf516", BFIN_CPU_BF516, 0x0001, AC_05000074},
210
  {"bf516", BFIN_CPU_BF516, 0x0000, AC_05000074},
211
 
212
  {"bf518", BFIN_CPU_BF518, 0x0001, AC_05000074},
213
  {"bf518", BFIN_CPU_BF518, 0x0000, AC_05000074},
214
 
215
  {"bf522", BFIN_CPU_BF522, 0x0002, AC_05000074},
216
  {"bf522", BFIN_CPU_BF522, 0x0001, AC_05000074},
217
  {"bf522", BFIN_CPU_BF522, 0x0000, AC_05000074},
218
 
219
  {"bf523", BFIN_CPU_BF523, 0x0002, AC_05000074},
220
  {"bf523", BFIN_CPU_BF523, 0x0001, AC_05000074},
221
  {"bf523", BFIN_CPU_BF523, 0x0000, AC_05000074},
222
 
223
  {"bf524", BFIN_CPU_BF524, 0x0002, AC_05000074},
224
  {"bf524", BFIN_CPU_BF524, 0x0001, AC_05000074},
225
  {"bf524", BFIN_CPU_BF524, 0x0000, AC_05000074},
226
 
227
  {"bf525", BFIN_CPU_BF525, 0x0002, AC_05000074},
228
  {"bf525", BFIN_CPU_BF525, 0x0001, AC_05000074},
229
  {"bf525", BFIN_CPU_BF525, 0x0000, AC_05000074},
230
 
231
  {"bf526", BFIN_CPU_BF526, 0x0002, AC_05000074},
232
  {"bf526", BFIN_CPU_BF526, 0x0001, AC_05000074},
233
  {"bf526", BFIN_CPU_BF526, 0x0000, AC_05000074},
234
 
235
  {"bf527", BFIN_CPU_BF527, 0x0002, AC_05000074},
236
  {"bf527", BFIN_CPU_BF527, 0x0001, AC_05000074},
237
  {"bf527", BFIN_CPU_BF527, 0x0000, AC_05000074},
238
 
239
  {"bf531", BFIN_CPU_BF531, 0x0006, AC_05000074},
240
  {"bf531", BFIN_CPU_BF531, 0x0005, AC_05000074},
241
  {"bf531", BFIN_CPU_BF531, 0x0004, AC_05000074},
242
  {"bf531", BFIN_CPU_BF531, 0x0003, AC_05000074},
243
 
244
  {"bf532", BFIN_CPU_BF532, 0x0006, AC_05000074},
245
  {"bf532", BFIN_CPU_BF532, 0x0005, AC_05000074},
246
  {"bf532", BFIN_CPU_BF532, 0x0004, AC_05000074},
247
  {"bf532", BFIN_CPU_BF532, 0x0003, AC_05000074},
248
 
249
  {"bf533", BFIN_CPU_BF533, 0x0006, AC_05000074},
250
  {"bf533", BFIN_CPU_BF533, 0x0005, AC_05000074},
251
  {"bf533", BFIN_CPU_BF533, 0x0004, AC_05000074},
252
  {"bf533", BFIN_CPU_BF533, 0x0003, AC_05000074},
253
 
254
  {"bf534", BFIN_CPU_BF534, 0x0003, AC_05000074},
255
  {"bf534", BFIN_CPU_BF534, 0x0002, AC_05000074},
256
  {"bf534", BFIN_CPU_BF534, 0x0001, AC_05000074},
257
 
258
  {"bf536", BFIN_CPU_BF536, 0x0003, AC_05000074},
259
  {"bf536", BFIN_CPU_BF536, 0x0002, AC_05000074},
260
  {"bf536", BFIN_CPU_BF536, 0x0001, AC_05000074},
261
 
262
  {"bf537", BFIN_CPU_BF537, 0x0003, AC_05000074},
263
  {"bf537", BFIN_CPU_BF537, 0x0002, AC_05000074},
264
  {"bf537", BFIN_CPU_BF537, 0x0001, AC_05000074},
265
 
266
  {"bf538", BFIN_CPU_BF538, 0x0005, AC_05000074},
267
  {"bf538", BFIN_CPU_BF538, 0x0004, AC_05000074},
268
  {"bf538", BFIN_CPU_BF538, 0x0003, AC_05000074},
269
  {"bf538", BFIN_CPU_BF538, 0x0002, AC_05000074},
270
 
271
  {"bf539", BFIN_CPU_BF539, 0x0005, AC_05000074},
272
  {"bf539", BFIN_CPU_BF539, 0x0004, AC_05000074},
273
  {"bf539", BFIN_CPU_BF539, 0x0003, AC_05000074},
274
  {"bf539", BFIN_CPU_BF539, 0x0002, AC_05000074},
275
 
276
  {"bf542m", BFIN_CPU_BF542M, 0x0003, AC_05000074},
277
 
278
  {"bf542", BFIN_CPU_BF542, 0x0002, AC_05000074},
279
  {"bf542", BFIN_CPU_BF542, 0x0001, AC_05000074},
280
  {"bf542", BFIN_CPU_BF542, 0x0000, AC_05000074},
281
 
282
  {"bf544m", BFIN_CPU_BF544M, 0x0003, AC_05000074},
283
 
284
  {"bf544", BFIN_CPU_BF544, 0x0002, AC_05000074},
285
  {"bf544", BFIN_CPU_BF544, 0x0001, AC_05000074},
286
  {"bf544", BFIN_CPU_BF544, 0x0000, AC_05000074},
287
 
288
  {"bf547m", BFIN_CPU_BF547M, 0x0003, AC_05000074},
289
 
290
  {"bf547", BFIN_CPU_BF547, 0x0002, AC_05000074},
291
  {"bf547", BFIN_CPU_BF547, 0x0001, AC_05000074},
292
  {"bf547", BFIN_CPU_BF547, 0x0000, AC_05000074},
293
 
294
  {"bf548m", BFIN_CPU_BF548M, 0x0003, AC_05000074},
295
 
296
  {"bf548", BFIN_CPU_BF548, 0x0002, AC_05000074},
297
  {"bf548", BFIN_CPU_BF548, 0x0001, AC_05000074},
298
  {"bf548", BFIN_CPU_BF548, 0x0000, AC_05000074},
299
 
300
  {"bf549m", BFIN_CPU_BF549M, 0x0003, AC_05000074},
301
 
302
  {"bf549", BFIN_CPU_BF549, 0x0002, AC_05000074},
303
  {"bf549", BFIN_CPU_BF549, 0x0001, AC_05000074},
304
  {"bf549", BFIN_CPU_BF549, 0x0000, AC_05000074},
305
 
306
  {"bf561", BFIN_CPU_BF561, 0x0005, AC_05000074},
307
  {"bf561", BFIN_CPU_BF561, 0x0003, AC_05000074},
308
  {"bf561", BFIN_CPU_BF561, 0x0002, AC_05000074},
309
 
310
  {NULL, 0, 0, 0}
311
};
312
 
313
/* Define bfin-specific command-line options (there are none). */
314
const char *md_shortopts = "";
315
 
316
#define OPTION_FDPIC            (OPTION_MD_BASE)
317
#define OPTION_NOPIC            (OPTION_MD_BASE + 1)
318
#define OPTION_MCPU             (OPTION_MD_BASE + 2)
319
 
320
struct option md_longopts[] =
321
{
322
  { "mcpu",             required_argument,      NULL, OPTION_MCPU       },
323
  { "mfdpic",           no_argument,            NULL, OPTION_FDPIC      },
324
  { "mnopic",           no_argument,            NULL, OPTION_NOPIC      },
325
  { "mno-fdpic",        no_argument,            NULL, OPTION_NOPIC      },
326
  { NULL,               no_argument,            NULL, 0                 },
327
};
328
 
329
size_t md_longopts_size = sizeof (md_longopts);
330
 
331
 
332
int
333
md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED)
334
{
335
  switch (c)
336
    {
337
    default:
338
      return 0;
339
 
340
    case OPTION_MCPU:
341
      {
342
        const char *p, *q;
343
        int i;
344
 
345
        i = 0;
346
        while ((p = bfin_cpus[i].name) != NULL)
347
          {
348
            if (strncmp (arg, p, strlen (p)) == 0)
349
              break;
350
            i++;
351
          }
352
 
353
        if (p == NULL)
354
          as_fatal ("-mcpu=%s is not valid", arg);
355
 
356
        bfin_cpu_type = bfin_cpus[i].type;
357
 
358
        q = arg + strlen (p);
359
 
360
        if (*q == '\0')
361
          {
362
            bfin_si_revision = bfin_cpus[i].si_revision;
363
            bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks;
364
          }
365
        else if (strcmp (q, "-none") == 0)
366
          bfin_si_revision = -1;
367
        else if (strcmp (q, "-any") == 0)
368
          {
369
            bfin_si_revision = 0xffff;
370
            while (bfin_cpus[i].type == bfin_cpu_type)
371
              {
372
                bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks;
373
                i++;
374
              }
375
          }
376
        else
377
          {
378
            unsigned int si_major, si_minor;
379
            int rev_len, n;
380
 
381
            rev_len = strlen (q);
382
 
383
            if (sscanf (q, "-%u.%u%n", &si_major, &si_minor, &n) != 2
384
                || n != rev_len
385
                || si_major > 0xff || si_minor > 0xff)
386
              {
387
              invalid_silicon_revision:
388
                as_fatal ("-mcpu=%s has invalid silicon revision", arg);
389
              }
390
 
391
            bfin_si_revision = (si_major << 8) | si_minor;
392
 
393
            while (bfin_cpus[i].type == bfin_cpu_type
394
                   && bfin_cpus[i].si_revision != bfin_si_revision)
395
              i++;
396
 
397
            if (bfin_cpus[i].type != bfin_cpu_type)
398
              goto invalid_silicon_revision;
399
 
400
            bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks;
401
          }
402
 
403
        break;
404
      }
405
 
406
    case OPTION_FDPIC:
407
      bfin_flags |= EF_BFIN_FDPIC;
408
      bfin_pic_flag = "-mfdpic";
409
      break;
410
 
411
    case OPTION_NOPIC:
412
      bfin_flags &= ~(EF_BFIN_FDPIC);
413
      bfin_pic_flag = 0;
414
      break;
415
    }
416
 
417
  return 1;
418
}
419
 
420
void
421
md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
422
{
423
  fprintf (stream, _(" BFIN specific command line options:\n"));
424
}
425
 
426
/* Perform machine-specific initializations.  */
427
void
428
md_begin ()
429
{
430
  /* Set the ELF flags if desired. */
431
  if (bfin_flags)
432
    bfd_set_private_flags (stdoutput, bfin_flags);
433
 
434
  /* Set the default machine type. */
435
  if (!bfd_set_arch_mach (stdoutput, bfd_arch_bfin, 0))
436
    as_warn (_("Could not set architecture and machine."));
437
 
438
  /* Ensure that lines can begin with '(', for multiple
439
     register stack pops. */
440
  lex_type ['('] = LEX_BEGIN_NAME;
441
 
442
#ifdef OBJ_ELF
443
  record_alignment (text_section, 2);
444
  record_alignment (data_section, 2);
445
  record_alignment (bss_section, 2);
446
#endif
447
 
448
  errorf = stderr;
449
  obstack_init (&mempool);
450
 
451
#ifdef DEBUG
452
  extern int debug_codeselection;
453
  debug_codeselection = 1;
454
#endif 
455
 
456
  last_insn_size = 0;
457
}
458
 
459
/* Perform the main parsing, and assembly of the input here.  Also,
460
   call the required routines for alignment and fixups here.
461
   This is called for every line that contains real assembly code.  */
462
 
463
void
464
md_assemble (char *line)
465
{
466
  char *toP = 0;
467
  extern char *current_inputline;
468
  int size, insn_size;
469
  struct bfin_insn *tmp_insn;
470
  size_t len;
471
  static size_t buffer_len = 0;
472
  parse_state state;
473
 
474
  len = strlen (line);
475
  if (len + 2 > buffer_len)
476
    {
477
      if (buffer_len > 0)
478
        free (current_inputline);
479
      buffer_len = len + 40;
480
      current_inputline = xmalloc (buffer_len);
481
    }
482
  memcpy (current_inputline, line, len);
483
  current_inputline[len] = ';';
484
  current_inputline[len + 1] = '\0';
485
 
486
  state = parse (current_inputline);
487
  if (state == NO_INSN_GENERATED)
488
    return;
489
 
490
  for (insn_size = 0, tmp_insn = insn; tmp_insn; tmp_insn = tmp_insn->next)
491
    if (!tmp_insn->reloc || !tmp_insn->exp->symbol)
492
      insn_size += 2;
493
 
494
  if (insn_size)
495
    toP = frag_more (insn_size);
496
 
497
  last_insn_size = insn_size;
498
 
499
#ifdef DEBUG
500
  printf ("INS:");
501
#endif
502
  while (insn)
503
    {
504
      if (insn->reloc && insn->exp->symbol)
505
        {
506
          char *prev_toP = toP - 2;
507
          switch (insn->reloc)
508
            {
509
            case BFD_RELOC_BFIN_24_PCREL_JUMP_L:
510
            case BFD_RELOC_24_PCREL:
511
            case BFD_RELOC_BFIN_16_LOW:
512
            case BFD_RELOC_BFIN_16_HIGH:
513
              size = 4;
514
              break;
515
            default:
516
              size = 2;
517
            }
518
 
519
          /* Following if condition checks for the arithmetic relocations.
520
             If the case then it doesn't required to generate the code.
521
             It has been assumed that, their ID will be contiguous.  */
522
          if ((BFD_ARELOC_BFIN_PUSH <= insn->reloc
523
               && BFD_ARELOC_BFIN_COMP >= insn->reloc)
524
              || insn->reloc == BFD_RELOC_BFIN_16_IMM)
525
            {
526
              size = 2;
527
            }
528
          if (insn->reloc == BFD_ARELOC_BFIN_CONST
529
              || insn->reloc == BFD_ARELOC_BFIN_PUSH)
530
            size = 4;
531
 
532
          fix_new (frag_now,
533
                   (prev_toP - frag_now->fr_literal),
534
                   size, insn->exp->symbol, insn->exp->value,
535
                   insn->pcrel, insn->reloc);
536
        }
537
      else
538
        {
539
          md_number_to_chars (toP, insn->value, 2);
540
          toP += 2;
541
        }
542
 
543
#ifdef DEBUG
544
      printf (" reloc :");
545
      printf (" %02x%02x", ((unsigned char *) &insn->value)[0],
546
              ((unsigned char *) &insn->value)[1]);
547
      printf ("\n");
548
#endif
549
      insn = insn->next;
550
    }
551
#ifdef OBJ_ELF
552
  dwarf2_emit_insn (insn_size);
553
#endif
554
 
555
  while (*line++ != '\0')
556
    if (*line == '\n')
557
      bump_line_counters ();
558
}
559
 
560
/* Parse one line of instructions, and generate opcode for it.
561
   To parse the line, YACC and LEX are used, because the instruction set
562
   syntax doesn't confirm to the AT&T assembly syntax.
563
   To call a YACC & LEX generated parser, we must provide the input via
564
   a FILE stream, otherwise stdin is used by default.  Below the input
565
   to the function will be put into a temporary file, then the generated
566
   parser uses the temporary file for parsing.  */
567
 
568
static parse_state
569
parse (char *line)
570
{
571
  parse_state state;
572
  YY_BUFFER_STATE buffstate;
573
 
574
  buffstate = yy_scan_string (line);
575
 
576
  /* our lex requires setting the start state to keyword
577
     every line as the first word may be a keyword.
578
     Fixes a bug where we could not have keywords as labels.  */
579
  set_start_state ();
580
 
581
  /* Call yyparse here.  */
582
  state = yyparse ();
583
  if (state == SEMANTIC_ERROR)
584
    {
585
      as_bad (_("Parse failed."));
586
      insn = 0;
587
    }
588
 
589
  yy_delete_buffer (buffstate);
590
  return state;
591
}
592
 
593
/* We need to handle various expressions properly.
594
   Such as, [SP--] = 34, concerned by md_assemble().  */
595
 
596
void
597
md_operand (expressionS * expressionP)
598
{
599
  if (*input_line_pointer == '[')
600
    {
601
      as_tsktsk ("We found a '['!");
602
      input_line_pointer++;
603
      expression (expressionP);
604
    }
605
}
606
 
607
/* Handle undefined symbols. */
608
symbolS *
609
md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
610
{
611
  return (symbolS *) 0;
612
}
613
 
614
int
615
md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
616
                               segT segment ATTRIBUTE_UNUSED)
617
{
618
  return 0;
619
}
620
 
621
/* Convert from target byte order to host byte order.  */
622
 
623
static int
624
md_chars_to_number (char *val, int n)
625
{
626
  int retval;
627
 
628
  for (retval = 0; n--;)
629
    {
630
      retval <<= 8;
631
      retval |= val[n];
632
    }
633
  return retval;
634
}
635
 
636
void
637
md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED)
638
{
639
  char *where = fixP->fx_frag->fr_literal + fixP->fx_where;
640
 
641
  long value = *valueP;
642
  long newval;
643
 
644
  switch (fixP->fx_r_type)
645
    {
646
    case BFD_RELOC_BFIN_GOT:
647
    case BFD_RELOC_BFIN_GOT17M4:
648
    case BFD_RELOC_BFIN_FUNCDESC_GOT17M4:
649
      fixP->fx_no_overflow = 1;
650
      newval = md_chars_to_number (where, 2);
651
      newval |= 0x0 & 0x7f;
652
      md_number_to_chars (where, newval, 2);
653
      break;
654
 
655
    case BFD_RELOC_BFIN_10_PCREL:
656
      if (!value)
657
        break;
658
      if (value < -1024 || value > 1022)
659
        as_bad_where (fixP->fx_file, fixP->fx_line,
660
                      _("pcrel too far BFD_RELOC_BFIN_10"));
661
 
662
      /* 11 bit offset even numbered, so we remove right bit.  */
663
      value = value >> 1;
664
      newval = md_chars_to_number (where, 2);
665
      newval |= value & 0x03ff;
666
      md_number_to_chars (where, newval, 2);
667
      break;
668
 
669
    case BFD_RELOC_BFIN_12_PCREL_JUMP:
670
    case BFD_RELOC_BFIN_12_PCREL_JUMP_S:
671
    case BFD_RELOC_12_PCREL:
672
      if (!value)
673
        break;
674
 
675
      if (value < -4096 || value > 4094)
676
        as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far BFD_RELOC_BFIN_12"));
677
      /* 13 bit offset even numbered, so we remove right bit.  */
678
      value = value >> 1;
679
      newval = md_chars_to_number (where, 2);
680
      newval |= value & 0xfff;
681
      md_number_to_chars (where, newval, 2);
682
      break;
683
 
684
    case BFD_RELOC_BFIN_16_LOW:
685
    case BFD_RELOC_BFIN_16_HIGH:
686
      fixP->fx_done = FALSE;
687
      break;
688
 
689
    case BFD_RELOC_BFIN_24_PCREL_JUMP_L:
690
    case BFD_RELOC_BFIN_24_PCREL_CALL_X:
691
    case BFD_RELOC_24_PCREL:
692
      if (!value)
693
        break;
694
 
695
      if (value < -16777216 || value > 16777214)
696
        as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far BFD_RELOC_BFIN_24"));
697
 
698
      /* 25 bit offset even numbered, so we remove right bit.  */
699
      value = value >> 1;
700
      value++;
701
 
702
      md_number_to_chars (where - 2, value >> 16, 1);
703
      md_number_to_chars (where, value, 1);
704
      md_number_to_chars (where + 1, value >> 8, 1);
705
      break;
706
 
707
    case BFD_RELOC_BFIN_5_PCREL:        /* LSETUP (a, b) : "a" */
708
      if (!value)
709
        break;
710
      if (value < 4 || value > 30)
711
        as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far BFD_RELOC_BFIN_5"));
712
      value = value >> 1;
713
      newval = md_chars_to_number (where, 1);
714
      newval = (newval & 0xf0) | (value & 0xf);
715
      md_number_to_chars (where, newval, 1);
716
      break;
717
 
718
    case BFD_RELOC_BFIN_11_PCREL:       /* LSETUP (a, b) : "b" */
719
      if (!value)
720
        break;
721
      value += 2;
722
      if (value < 4 || value > 2046)
723
        as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far BFD_RELOC_BFIN_11_PCREL"));
724
      /* 11 bit unsigned even, so we remove right bit.  */
725
      value = value >> 1;
726
      newval = md_chars_to_number (where, 2);
727
      newval |= value & 0x03ff;
728
      md_number_to_chars (where, newval, 2);
729
      break;
730
 
731
    case BFD_RELOC_8:
732
      if (value < -0x80 || value >= 0x7f)
733
        as_bad_where (fixP->fx_file, fixP->fx_line, _("rel too far BFD_RELOC_8"));
734
      md_number_to_chars (where, value, 1);
735
      break;
736
 
737
    case BFD_RELOC_BFIN_16_IMM:
738
    case BFD_RELOC_16:
739
      if (value < -0x8000 || value >= 0x7fff)
740
        as_bad_where (fixP->fx_file, fixP->fx_line, _("rel too far BFD_RELOC_16"));
741
      md_number_to_chars (where, value, 2);
742
      break;
743
 
744
    case BFD_RELOC_32:
745
      md_number_to_chars (where, value, 4);
746
      break;
747
 
748
    case BFD_RELOC_BFIN_PLTPC:
749
      md_number_to_chars (where, value, 2);
750
      break;
751
 
752
    case BFD_RELOC_BFIN_FUNCDESC:
753
    case BFD_RELOC_VTABLE_INHERIT:
754
    case BFD_RELOC_VTABLE_ENTRY:
755
      fixP->fx_done = FALSE;
756
      break;
757
 
758
    default:
759
      if ((BFD_ARELOC_BFIN_PUSH > fixP->fx_r_type) || (BFD_ARELOC_BFIN_COMP < fixP->fx_r_type))
760
        {
761
          fprintf (stderr, "Relocation %d not handled in gas." " Contact support.\n", fixP->fx_r_type);
762
          return;
763
        }
764
    }
765
 
766
  if (!fixP->fx_addsy)
767
    fixP->fx_done = TRUE;
768
 
769
}
770
 
771
/* Round up a section size to the appropriate boundary.  */
772
valueT
773
md_section_align (segment, size)
774
     segT segment;
775
     valueT size;
776
{
777
  int boundary = bfd_get_section_alignment (stdoutput, segment);
778
  return ((size + (1 << boundary) - 1) & (-1 << boundary));
779
}
780
 
781
 
782
char *
783
md_atof (int type, char * litP, int * sizeP)
784
{
785
  return ieee_md_atof (type, litP, sizeP, FALSE);
786
}
787
 
788
 
789
/* If while processing a fixup, a reloc really needs to be created
790
   then it is done here.  */
791
 
792
arelent *
793
tc_gen_reloc (seg, fixp)
794
     asection *seg ATTRIBUTE_UNUSED;
795
     fixS *fixp;
796
{
797
  arelent *reloc;
798
 
799
  reloc               = (arelent *) xmalloc (sizeof (arelent));
800
  reloc->sym_ptr_ptr  = (asymbol **) xmalloc (sizeof (asymbol *));
801
  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
802
  reloc->address      = fixp->fx_frag->fr_address + fixp->fx_where;
803
 
804
  reloc->addend = fixp->fx_offset;
805
  reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
806
 
807
  if (reloc->howto == (reloc_howto_type *) NULL)
808
    {
809
      as_bad_where (fixp->fx_file, fixp->fx_line,
810
                    /* xgettext:c-format.  */
811
                    _("reloc %d not supported by object file format"),
812
                    (int) fixp->fx_r_type);
813
 
814
      xfree (reloc);
815
 
816
      return NULL;
817
    }
818
 
819
  return reloc;
820
}
821
 
822
/*  The location from which a PC relative jump should be calculated,
823
    given a PC relative reloc.  */
824
 
825
long
826
md_pcrel_from_section (fixP, sec)
827
     fixS *fixP;
828
     segT sec;
829
{
830
  if (fixP->fx_addsy != (symbolS *) NULL
831
      && (!S_IS_DEFINED (fixP->fx_addsy)
832
      || S_GET_SEGMENT (fixP->fx_addsy) != sec))
833
    {
834
      /* The symbol is undefined (or is defined but not in this section).
835
         Let the linker figure it out.  */
836
      return 0;
837
    }
838
  return fixP->fx_frag->fr_address + fixP->fx_where;
839
}
840
 
841
/* Return true if the fix can be handled by GAS, false if it must
842
   be passed through to the linker.  */
843
 
844
bfd_boolean
845
bfin_fix_adjustable (fixS *fixP)
846
{
847
  switch (fixP->fx_r_type)
848
    {
849
  /* Adjust_reloc_syms doesn't know about the GOT.  */
850
    case BFD_RELOC_BFIN_GOT:
851
    case BFD_RELOC_BFIN_PLTPC:
852
  /* We need the symbol name for the VTABLE entries.  */
853
    case BFD_RELOC_VTABLE_INHERIT:
854
    case BFD_RELOC_VTABLE_ENTRY:
855
      return 0;
856
 
857
    default:
858
      return 1;
859
    }
860
}
861
 
862
/* Special extra functions that help bfin-parse.y perform its job.  */
863
 
864
struct obstack mempool;
865
 
866
INSTR_T
867
conscode (INSTR_T head, INSTR_T tail)
868
{
869
  if (!head)
870
    return tail;
871
  head->next = tail;
872
  return head;
873
}
874
 
875
INSTR_T
876
conctcode (INSTR_T head, INSTR_T tail)
877
{
878
  INSTR_T temp = (head);
879
  if (!head)
880
    return tail;
881
  while (temp->next)
882
    temp = temp->next;
883
  temp->next = tail;
884
 
885
  return head;
886
}
887
 
888
INSTR_T
889
note_reloc (INSTR_T code, Expr_Node * symbol, int reloc, int pcrel)
890
{
891
  /* Assert that the symbol is not an operator.  */
892
  gas_assert (symbol->type == Expr_Node_Reloc);
893
 
894
  return note_reloc1 (code, symbol->value.s_value, reloc, pcrel);
895
 
896
}
897
 
898
INSTR_T
899
note_reloc1 (INSTR_T code, const char *symbol, int reloc, int pcrel)
900
{
901
  code->reloc = reloc;
902
  code->exp = mkexpr (0, symbol_find_or_make (symbol));
903
  code->pcrel = pcrel;
904
  return code;
905
}
906
 
907
INSTR_T
908
note_reloc2 (INSTR_T code, const char *symbol, int reloc, int value, int pcrel)
909
{
910
  code->reloc = reloc;
911
  code->exp = mkexpr (value, symbol_find_or_make (symbol));
912
  code->pcrel = pcrel;
913
  return code;
914
}
915
 
916
INSTR_T
917
gencode (unsigned long x)
918
{
919
  INSTR_T cell = obstack_alloc (&mempool, sizeof (struct bfin_insn));
920
  memset (cell, 0, sizeof (struct bfin_insn));
921
  cell->value = (x);
922
  return cell;
923
}
924
 
925
int reloc;
926
int ninsns;
927
int count_insns;
928
 
929
static void *
930
allocate (int n)
931
{
932
  return obstack_alloc (&mempool, n);
933
}
934
 
935
Expr_Node *
936
Expr_Node_Create (Expr_Node_Type type,
937
                  Expr_Node_Value value,
938
                  Expr_Node *Left_Child,
939
                  Expr_Node *Right_Child)
940
{
941
 
942
 
943
  Expr_Node *node = (Expr_Node *) allocate (sizeof (Expr_Node));
944
  node->type = type;
945
  node->value = value;
946
  node->Left_Child = Left_Child;
947
  node->Right_Child = Right_Child;
948
  return node;
949
}
950
 
951
static const char *con = ".__constant";
952
static const char *op = ".__operator";
953
static INSTR_T Expr_Node_Gen_Reloc_R (Expr_Node * head);
954
INSTR_T Expr_Node_Gen_Reloc (Expr_Node *head, int parent_reloc);
955
 
956
INSTR_T
957
Expr_Node_Gen_Reloc (Expr_Node * head, int parent_reloc)
958
{
959
  /* Top level reloction expression generator VDSP style.
960
   If the relocation is just by itself, generate one item
961
   else generate this convoluted expression.  */
962
 
963
  INSTR_T note = NULL_CODE;
964
  INSTR_T note1 = NULL_CODE;
965
  int pcrel = 1;  /* Is the parent reloc pcrelative?
966
                  This calculation here and HOWTO should match.  */
967
 
968
  if (parent_reloc)
969
    {
970
      /*  If it's 32 bit quantity then 16bit code needs to be added.  */
971
      int value = 0;
972
 
973
      if (head->type == Expr_Node_Constant)
974
        {
975
          /* If note1 is not null code, we have to generate a right
976
             aligned value for the constant. Otherwise the reloc is
977
             a part of the basic command and the yacc file
978
             generates this.  */
979
          value = head->value.i_value;
980
        }
981
      switch (parent_reloc)
982
        {
983
          /*  Some relocations will need to allocate extra words.  */
984
        case BFD_RELOC_BFIN_16_IMM:
985
        case BFD_RELOC_BFIN_16_LOW:
986
        case BFD_RELOC_BFIN_16_HIGH:
987
          note1 = conscode (gencode (value), NULL_CODE);
988
          pcrel = 0;
989
          break;
990
        case BFD_RELOC_BFIN_PLTPC:
991
          note1 = conscode (gencode (value), NULL_CODE);
992
          pcrel = 0;
993
          break;
994
        case BFD_RELOC_16:
995
        case BFD_RELOC_BFIN_GOT:
996
        case BFD_RELOC_BFIN_GOT17M4:
997
        case BFD_RELOC_BFIN_FUNCDESC_GOT17M4:
998
          note1 = conscode (gencode (value), NULL_CODE);
999
          pcrel = 0;
1000
          break;
1001
        case BFD_RELOC_24_PCREL:
1002
        case BFD_RELOC_BFIN_24_PCREL_JUMP_L:
1003
        case BFD_RELOC_BFIN_24_PCREL_CALL_X:
1004
          /* These offsets are even numbered pcrel.  */
1005
          note1 = conscode (gencode (value >> 1), NULL_CODE);
1006
          break;
1007
        default:
1008
          note1 = NULL_CODE;
1009
        }
1010
    }
1011
  if (head->type == Expr_Node_Constant)
1012
    note = note1;
1013
  else if (head->type == Expr_Node_Reloc)
1014
    {
1015
      note = note_reloc1 (gencode (0), head->value.s_value, parent_reloc, pcrel);
1016
      if (note1 != NULL_CODE)
1017
        note = conscode (note1, note);
1018
    }
1019
  else if (head->type == Expr_Node_Binop
1020
           && (head->value.op_value == Expr_Op_Type_Add
1021
               || head->value.op_value == Expr_Op_Type_Sub)
1022
           && head->Left_Child->type == Expr_Node_Reloc
1023
           && head->Right_Child->type == Expr_Node_Constant)
1024
    {
1025
      int val = head->Right_Child->value.i_value;
1026
      if (head->value.op_value == Expr_Op_Type_Sub)
1027
        val = -val;
1028
      note = conscode (note_reloc2 (gencode (0), head->Left_Child->value.s_value,
1029
                                    parent_reloc, val, 0),
1030
                       NULL_CODE);
1031
      if (note1 != NULL_CODE)
1032
        note = conscode (note1, note);
1033
    }
1034
  else
1035
    {
1036
      /* Call the recursive function.  */
1037
      note = note_reloc1 (gencode (0), op, parent_reloc, pcrel);
1038
      if (note1 != NULL_CODE)
1039
        note = conscode (note1, note);
1040
      note = conctcode (Expr_Node_Gen_Reloc_R (head), note);
1041
    }
1042
  return note;
1043
}
1044
 
1045
static INSTR_T
1046
Expr_Node_Gen_Reloc_R (Expr_Node * head)
1047
{
1048
 
1049
  INSTR_T note = 0;
1050
  INSTR_T note1 = 0;
1051
 
1052
  switch (head->type)
1053
    {
1054
    case Expr_Node_Constant:
1055
      note = conscode (note_reloc2 (gencode (0), con, BFD_ARELOC_BFIN_CONST, head->value.i_value, 0), NULL_CODE);
1056
      break;
1057
    case Expr_Node_Reloc:
1058
      note = conscode (note_reloc (gencode (0), head, BFD_ARELOC_BFIN_PUSH, 0), NULL_CODE);
1059
      break;
1060
    case Expr_Node_Binop:
1061
      note1 = conctcode (Expr_Node_Gen_Reloc_R (head->Left_Child), Expr_Node_Gen_Reloc_R (head->Right_Child));
1062
      switch (head->value.op_value)
1063
        {
1064
        case Expr_Op_Type_Add:
1065
          note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_ADD, 0), NULL_CODE));
1066
          break;
1067
        case Expr_Op_Type_Sub:
1068
          note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_SUB, 0), NULL_CODE));
1069
          break;
1070
        case Expr_Op_Type_Mult:
1071
          note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_MULT, 0), NULL_CODE));
1072
          break;
1073
        case Expr_Op_Type_Div:
1074
          note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_DIV, 0), NULL_CODE));
1075
          break;
1076
        case Expr_Op_Type_Mod:
1077
          note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_MOD, 0), NULL_CODE));
1078
          break;
1079
        case Expr_Op_Type_Lshift:
1080
          note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_LSHIFT, 0), NULL_CODE));
1081
          break;
1082
        case Expr_Op_Type_Rshift:
1083
          note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_RSHIFT, 0), NULL_CODE));
1084
          break;
1085
        case Expr_Op_Type_BAND:
1086
          note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_AND, 0), NULL_CODE));
1087
          break;
1088
        case Expr_Op_Type_BOR:
1089
          note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_OR, 0), NULL_CODE));
1090
          break;
1091
        case Expr_Op_Type_BXOR:
1092
          note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_XOR, 0), NULL_CODE));
1093
          break;
1094
        case Expr_Op_Type_LAND:
1095
          note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_LAND, 0), NULL_CODE));
1096
          break;
1097
        case Expr_Op_Type_LOR:
1098
          note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_LOR, 0), NULL_CODE));
1099
          break;
1100
        default:
1101
          fprintf (stderr, "%s:%d:Unknown operator found for arithmetic" " relocation", __FILE__, __LINE__);
1102
 
1103
 
1104
        }
1105
      break;
1106
    case Expr_Node_Unop:
1107
      note1 = conscode (Expr_Node_Gen_Reloc_R (head->Left_Child), NULL_CODE);
1108
      switch (head->value.op_value)
1109
        {
1110
        case Expr_Op_Type_NEG:
1111
          note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_NEG, 0), NULL_CODE));
1112
          break;
1113
        case Expr_Op_Type_COMP:
1114
          note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_COMP, 0), NULL_CODE));
1115
          break;
1116
        default:
1117
          fprintf (stderr, "%s:%d:Unknown operator found for arithmetic" " relocation", __FILE__, __LINE__);
1118
        }
1119
      break;
1120
    default:
1121
      fprintf (stderr, "%s:%d:Unknown node expression found during " "arithmetic relocation generation", __FILE__, __LINE__);
1122
    }
1123
  return note;
1124
}
1125
 
1126
/* Blackfin opcode generation.  */
1127
 
1128
/* These functions are called by the generated parser
1129
   (from bfin-parse.y), the register type classification
1130
   happens in bfin-lex.l.  */
1131
 
1132
#include "bfin-aux.h"
1133
#include "opcode/bfin.h"
1134
 
1135
#define INIT(t)  t c_code = init_##t
1136
#define ASSIGN(x) c_code.opcode |= ((x & c_code.mask_##x)<<c_code.bits_##x)
1137
#define ASSIGN_R(x) c_code.opcode |= (((x ? (x->regno & CODE_MASK) : 0) & c_code.mask_##x)<<c_code.bits_##x)
1138
 
1139
#define HI(x) ((x >> 16) & 0xffff)
1140
#define LO(x) ((x      ) & 0xffff)
1141
 
1142
#define GROUP(x) ((x->regno & CLASS_MASK) >> 4)
1143
 
1144
#define GEN_OPCODE32()  \
1145
        conscode (gencode (HI (c_code.opcode)), \
1146
        conscode (gencode (LO (c_code.opcode)), NULL_CODE))
1147
 
1148
#define GEN_OPCODE16()  \
1149
        conscode (gencode (c_code.opcode), NULL_CODE)
1150
 
1151
 
1152
/*  32 BIT INSTRUCTIONS.  */
1153
 
1154
 
1155
/* DSP32 instruction generation.  */
1156
 
1157
INSTR_T
1158
bfin_gen_dsp32mac (int op1, int MM, int mmod, int w1, int P,
1159
                   int h01, int h11, int h00, int h10, int op0,
1160
                   REG_T dst, REG_T src0, REG_T src1, int w0)
1161
{
1162
  INIT (DSP32Mac);
1163
 
1164
  ASSIGN (op0);
1165
  ASSIGN (op1);
1166
  ASSIGN (MM);
1167
  ASSIGN (mmod);
1168
  ASSIGN (w0);
1169
  ASSIGN (w1);
1170
  ASSIGN (h01);
1171
  ASSIGN (h11);
1172
  ASSIGN (h00);
1173
  ASSIGN (h10);
1174
  ASSIGN (P);
1175
 
1176
  /* If we have full reg assignments, mask out LSB to encode
1177
  single or simultaneous even/odd register moves.  */
1178
  if (P)
1179
    {
1180
      dst->regno &= 0x06;
1181
    }
1182
 
1183
  ASSIGN_R (dst);
1184
  ASSIGN_R (src0);
1185
  ASSIGN_R (src1);
1186
 
1187
  return GEN_OPCODE32 ();
1188
}
1189
 
1190
INSTR_T
1191
bfin_gen_dsp32mult (int op1, int MM, int mmod, int w1, int P,
1192
                    int h01, int h11, int h00, int h10, int op0,
1193
                    REG_T dst, REG_T src0, REG_T src1, int w0)
1194
{
1195
  INIT (DSP32Mult);
1196
 
1197
  ASSIGN (op0);
1198
  ASSIGN (op1);
1199
  ASSIGN (MM);
1200
  ASSIGN (mmod);
1201
  ASSIGN (w0);
1202
  ASSIGN (w1);
1203
  ASSIGN (h01);
1204
  ASSIGN (h11);
1205
  ASSIGN (h00);
1206
  ASSIGN (h10);
1207
  ASSIGN (P);
1208
 
1209
  if (P)
1210
    {
1211
      dst->regno &= 0x06;
1212
    }
1213
 
1214
  ASSIGN_R (dst);
1215
  ASSIGN_R (src0);
1216
  ASSIGN_R (src1);
1217
 
1218
  return GEN_OPCODE32 ();
1219
}
1220
 
1221
INSTR_T
1222
bfin_gen_dsp32alu (int HL, int aopcde, int aop, int s, int x,
1223
              REG_T dst0, REG_T dst1, REG_T src0, REG_T src1)
1224
{
1225
  INIT (DSP32Alu);
1226
 
1227
  ASSIGN (HL);
1228
  ASSIGN (aopcde);
1229
  ASSIGN (aop);
1230
  ASSIGN (s);
1231
  ASSIGN (x);
1232
  ASSIGN_R (dst0);
1233
  ASSIGN_R (dst1);
1234
  ASSIGN_R (src0);
1235
  ASSIGN_R (src1);
1236
 
1237
  return GEN_OPCODE32 ();
1238
}
1239
 
1240
INSTR_T
1241
bfin_gen_dsp32shift (int sopcde, REG_T dst0, REG_T src0,
1242
                REG_T src1, int sop, int HLs)
1243
{
1244
  INIT (DSP32Shift);
1245
 
1246
  ASSIGN (sopcde);
1247
  ASSIGN (sop);
1248
  ASSIGN (HLs);
1249
 
1250
  ASSIGN_R (dst0);
1251
  ASSIGN_R (src0);
1252
  ASSIGN_R (src1);
1253
 
1254
  return GEN_OPCODE32 ();
1255
}
1256
 
1257
INSTR_T
1258
bfin_gen_dsp32shiftimm (int sopcde, REG_T dst0, int immag,
1259
                   REG_T src1, int sop, int HLs)
1260
{
1261
  INIT (DSP32ShiftImm);
1262
 
1263
  ASSIGN (sopcde);
1264
  ASSIGN (sop);
1265
  ASSIGN (HLs);
1266
 
1267
  ASSIGN_R (dst0);
1268
  ASSIGN (immag);
1269
  ASSIGN_R (src1);
1270
 
1271
  return GEN_OPCODE32 ();
1272
}
1273
 
1274
/* LOOP SETUP.  */
1275
 
1276
INSTR_T
1277
bfin_gen_loopsetup (Expr_Node * psoffset, REG_T c, int rop,
1278
               Expr_Node * peoffset, REG_T reg)
1279
{
1280
  int soffset, eoffset;
1281
  INIT (LoopSetup);
1282
 
1283
  soffset = (EXPR_VALUE (psoffset) >> 1);
1284
  ASSIGN (soffset);
1285
  eoffset = (EXPR_VALUE (peoffset) >> 1);
1286
  ASSIGN (eoffset);
1287
  ASSIGN (rop);
1288
  ASSIGN_R (c);
1289
  ASSIGN_R (reg);
1290
 
1291
  return
1292
      conscode (gencode (HI (c_code.opcode)),
1293
                conctcode (Expr_Node_Gen_Reloc (psoffset, BFD_RELOC_BFIN_5_PCREL),
1294
                           conctcode (gencode (LO (c_code.opcode)), Expr_Node_Gen_Reloc (peoffset, BFD_RELOC_BFIN_11_PCREL))));
1295
 
1296
}
1297
 
1298
/*  Call, Link.  */
1299
 
1300
INSTR_T
1301
bfin_gen_calla (Expr_Node * addr, int S)
1302
{
1303
  int val;
1304
  int high_val;
1305
  int reloc = 0;
1306
  INIT (CALLa);
1307
 
1308
  switch(S){
1309
   case 0 : reloc = BFD_RELOC_BFIN_24_PCREL_JUMP_L; break;
1310
   case 1 : reloc = BFD_RELOC_24_PCREL; break;
1311
   case 2 : reloc = BFD_RELOC_BFIN_PLTPC; break;
1312
   default : break;
1313
  }
1314
 
1315
  ASSIGN (S);
1316
 
1317
  val = EXPR_VALUE (addr) >> 1;
1318
  high_val = val >> 16;
1319
 
1320
  return conscode (gencode (HI (c_code.opcode) | (high_val & 0xff)),
1321
                     Expr_Node_Gen_Reloc (addr, reloc));
1322
  }
1323
 
1324
INSTR_T
1325
bfin_gen_linkage (int R, int framesize)
1326
{
1327
  INIT (Linkage);
1328
 
1329
  ASSIGN (R);
1330
  ASSIGN (framesize);
1331
 
1332
  return GEN_OPCODE32 ();
1333
}
1334
 
1335
 
1336
/* Load and Store.  */
1337
 
1338
INSTR_T
1339
bfin_gen_ldimmhalf (REG_T reg, int H, int S, int Z, Expr_Node * phword, int reloc)
1340
{
1341
  int grp, hword;
1342
  unsigned val = EXPR_VALUE (phword);
1343
  INIT (LDIMMhalf);
1344
 
1345
  ASSIGN (H);
1346
  ASSIGN (S);
1347
  ASSIGN (Z);
1348
 
1349
  ASSIGN_R (reg);
1350
  grp = (GROUP (reg));
1351
  ASSIGN (grp);
1352
  if (reloc == 2)
1353
    {
1354
      return conscode (gencode (HI (c_code.opcode)), Expr_Node_Gen_Reloc (phword, BFD_RELOC_BFIN_16_IMM));
1355
    }
1356
  else if (reloc == 1)
1357
    {
1358
      return conscode (gencode (HI (c_code.opcode)), Expr_Node_Gen_Reloc (phword, IS_H (*reg) ? BFD_RELOC_BFIN_16_HIGH : BFD_RELOC_BFIN_16_LOW));
1359
    }
1360
  else
1361
    {
1362
      hword = val;
1363
      ASSIGN (hword);
1364
    }
1365
  return GEN_OPCODE32 ();
1366
}
1367
 
1368
INSTR_T
1369
bfin_gen_ldstidxi (REG_T ptr, REG_T reg, int W, int sz, int Z, Expr_Node * poffset)
1370
{
1371
  INIT (LDSTidxI);
1372
 
1373
  if (!IS_PREG (*ptr) || (!IS_DREG (*reg) && !Z))
1374
    {
1375
      fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n");
1376
      return 0;
1377
    }
1378
 
1379
  ASSIGN_R (ptr);
1380
  ASSIGN_R (reg);
1381
  ASSIGN (W);
1382
  ASSIGN (sz);
1383
 
1384
  ASSIGN (Z);
1385
 
1386
  if (poffset->type != Expr_Node_Constant)
1387
    {
1388
      /* a GOT relocation such as R0 = [P5 + symbol@GOT] */
1389
      /* distinguish between R0 = [P5 + symbol@GOT] and
1390
         P5 = [P5 + _current_shared_library_p5_offset_]
1391
      */
1392
      if (poffset->type == Expr_Node_Reloc
1393
          && !strcmp (poffset->value.s_value,
1394
                      "_current_shared_library_p5_offset_"))
1395
        {
1396
          return  conscode (gencode (HI (c_code.opcode)),
1397
                            Expr_Node_Gen_Reloc(poffset, BFD_RELOC_16));
1398
        }
1399
      else if (poffset->type != Expr_Node_GOT_Reloc)
1400
        abort ();
1401
 
1402
      return conscode (gencode (HI (c_code.opcode)),
1403
                       Expr_Node_Gen_Reloc(poffset->Left_Child,
1404
                                           poffset->value.i_value));
1405
    }
1406
  else
1407
    {
1408
      int value, offset;
1409
      switch (sz)
1410
        {                               /* load/store access size */
1411
        case 0:                  /* 32 bit */
1412
          value = EXPR_VALUE (poffset) >> 2;
1413
          break;
1414
        case 1:                 /* 16 bit */
1415
          value = EXPR_VALUE (poffset) >> 1;
1416
          break;
1417
        case 2:                 /* 8 bit */
1418
          value = EXPR_VALUE (poffset);
1419
          break;
1420
        default:
1421
          abort ();
1422
        }
1423
 
1424
      offset = (value & 0xffff);
1425
      ASSIGN (offset);
1426
      return GEN_OPCODE32 ();
1427
    }
1428
}
1429
 
1430
 
1431
INSTR_T
1432
bfin_gen_ldst (REG_T ptr, REG_T reg, int aop, int sz, int Z, int W)
1433
{
1434
  INIT (LDST);
1435
 
1436
  if (!IS_PREG (*ptr) || (!IS_DREG (*reg) && !Z))
1437
    {
1438
      fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n");
1439
      return 0;
1440
    }
1441
 
1442
  ASSIGN_R (ptr);
1443
  ASSIGN_R (reg);
1444
  ASSIGN (aop);
1445
  ASSIGN (sz);
1446
  ASSIGN (Z);
1447
  ASSIGN (W);
1448
 
1449
  return GEN_OPCODE16 ();
1450
}
1451
 
1452
INSTR_T
1453
bfin_gen_ldstii (REG_T ptr, REG_T reg, Expr_Node * poffset, int W, int op)
1454
{
1455
  int offset;
1456
  int value = 0;
1457
  INIT (LDSTii);
1458
 
1459
 
1460
  if (!IS_PREG (*ptr))
1461
    {
1462
      fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n");
1463
      return 0;
1464
    }
1465
 
1466
  switch (op)
1467
    {
1468
    case 1:
1469
    case 2:
1470
      value = EXPR_VALUE (poffset) >> 1;
1471
      break;
1472
    case 0:
1473
    case 3:
1474
      value = EXPR_VALUE (poffset) >> 2;
1475
      break;
1476
    }
1477
 
1478
  ASSIGN_R (ptr);
1479
  ASSIGN_R (reg);
1480
 
1481
  offset = value;
1482
  ASSIGN (offset);
1483
  ASSIGN (W);
1484
  ASSIGN (op);
1485
 
1486
  return GEN_OPCODE16 ();
1487
}
1488
 
1489
INSTR_T
1490
bfin_gen_ldstiifp (REG_T sreg, Expr_Node * poffset, int W)
1491
{
1492
  /* Set bit 4 if it's a Preg.  */
1493
  int reg = (sreg->regno & CODE_MASK) | (IS_PREG (*sreg) ? 0x8 : 0x0);
1494
  int offset = ((~(EXPR_VALUE (poffset) >> 2)) & 0x1f) + 1;
1495
  INIT (LDSTiiFP);
1496
  ASSIGN (reg);
1497
  ASSIGN (offset);
1498
  ASSIGN (W);
1499
 
1500
  return GEN_OPCODE16 ();
1501
}
1502
 
1503
INSTR_T
1504
bfin_gen_ldstpmod (REG_T ptr, REG_T reg, int aop, int W, REG_T idx)
1505
{
1506
  INIT (LDSTpmod);
1507
 
1508
  ASSIGN_R (ptr);
1509
  ASSIGN_R (reg);
1510
  ASSIGN (aop);
1511
  ASSIGN (W);
1512
  ASSIGN_R (idx);
1513
 
1514
  return GEN_OPCODE16 ();
1515
}
1516
 
1517
INSTR_T
1518
bfin_gen_dspldst (REG_T i, REG_T reg, int aop, int W, int m)
1519
{
1520
  INIT (DspLDST);
1521
 
1522
  ASSIGN_R (i);
1523
  ASSIGN_R (reg);
1524
  ASSIGN (aop);
1525
  ASSIGN (W);
1526
  ASSIGN (m);
1527
 
1528
  return GEN_OPCODE16 ();
1529
}
1530
 
1531
INSTR_T
1532
bfin_gen_logi2op (int opc, int src, int dst)
1533
{
1534
  INIT (LOGI2op);
1535
 
1536
  ASSIGN (opc);
1537
  ASSIGN (src);
1538
  ASSIGN (dst);
1539
 
1540
  return GEN_OPCODE16 ();
1541
}
1542
 
1543
INSTR_T
1544
bfin_gen_brcc (int T, int B, Expr_Node * poffset)
1545
{
1546
  int offset;
1547
  INIT (BRCC);
1548
 
1549
  ASSIGN (T);
1550
  ASSIGN (B);
1551
  offset = ((EXPR_VALUE (poffset) >> 1));
1552
  ASSIGN (offset);
1553
  return conscode (gencode (c_code.opcode), Expr_Node_Gen_Reloc (poffset, BFD_RELOC_BFIN_10_PCREL));
1554
}
1555
 
1556
INSTR_T
1557
bfin_gen_ujump (Expr_Node * poffset)
1558
{
1559
  int offset;
1560
  INIT (UJump);
1561
 
1562
  offset = ((EXPR_VALUE (poffset) >> 1));
1563
  ASSIGN (offset);
1564
 
1565
  return conscode (gencode (c_code.opcode),
1566
                   Expr_Node_Gen_Reloc (
1567
                       poffset, BFD_RELOC_BFIN_12_PCREL_JUMP_S));
1568
}
1569
 
1570
INSTR_T
1571
bfin_gen_alu2op (REG_T dst, REG_T src, int opc)
1572
{
1573
  INIT (ALU2op);
1574
 
1575
  ASSIGN_R (dst);
1576
  ASSIGN_R (src);
1577
  ASSIGN (opc);
1578
 
1579
  return GEN_OPCODE16 ();
1580
}
1581
 
1582
INSTR_T
1583
bfin_gen_compi2opd (REG_T dst, int src, int op)
1584
{
1585
  INIT (COMPI2opD);
1586
 
1587
  ASSIGN_R (dst);
1588
  ASSIGN (src);
1589
  ASSIGN (op);
1590
 
1591
  return GEN_OPCODE16 ();
1592
}
1593
 
1594
INSTR_T
1595
bfin_gen_compi2opp (REG_T dst, int src, int op)
1596
{
1597
  INIT (COMPI2opP);
1598
 
1599
  ASSIGN_R (dst);
1600
  ASSIGN (src);
1601
  ASSIGN (op);
1602
 
1603
  return GEN_OPCODE16 ();
1604
}
1605
 
1606
INSTR_T
1607
bfin_gen_dagmodik (REG_T i, int op)
1608
{
1609
  INIT (DagMODik);
1610
 
1611
  ASSIGN_R (i);
1612
  ASSIGN (op);
1613
 
1614
  return GEN_OPCODE16 ();
1615
}
1616
 
1617
INSTR_T
1618
bfin_gen_dagmodim (REG_T i, REG_T m, int op, int br)
1619
{
1620
  INIT (DagMODim);
1621
 
1622
  ASSIGN_R (i);
1623
  ASSIGN_R (m);
1624
  ASSIGN (op);
1625
  ASSIGN (br);
1626
 
1627
  return GEN_OPCODE16 ();
1628
}
1629
 
1630
INSTR_T
1631
bfin_gen_ptr2op (REG_T dst, REG_T src, int opc)
1632
{
1633
  INIT (PTR2op);
1634
 
1635
  ASSIGN_R (dst);
1636
  ASSIGN_R (src);
1637
  ASSIGN (opc);
1638
 
1639
  return GEN_OPCODE16 ();
1640
}
1641
 
1642
INSTR_T
1643
bfin_gen_comp3op (REG_T src0, REG_T src1, REG_T dst, int opc)
1644
{
1645
  INIT (COMP3op);
1646
 
1647
  ASSIGN_R (src0);
1648
  ASSIGN_R (src1);
1649
  ASSIGN_R (dst);
1650
  ASSIGN (opc);
1651
 
1652
  return GEN_OPCODE16 ();
1653
}
1654
 
1655
INSTR_T
1656
bfin_gen_ccflag (REG_T x, int y, int opc, int I, int G)
1657
{
1658
  INIT (CCflag);
1659
 
1660
  ASSIGN_R (x);
1661
  ASSIGN (y);
1662
  ASSIGN (opc);
1663
  ASSIGN (I);
1664
  ASSIGN (G);
1665
 
1666
  return GEN_OPCODE16 ();
1667
}
1668
 
1669
INSTR_T
1670
bfin_gen_ccmv (REG_T src, REG_T dst, int T)
1671
{
1672
  int s, d;
1673
  INIT (CCmv);
1674
 
1675
  ASSIGN_R (src);
1676
  ASSIGN_R (dst);
1677
  s = (GROUP (src));
1678
  ASSIGN (s);
1679
  d = (GROUP (dst));
1680
  ASSIGN (d);
1681
  ASSIGN (T);
1682
 
1683
  return GEN_OPCODE16 ();
1684
}
1685
 
1686
INSTR_T
1687
bfin_gen_cc2stat (int cbit, int op, int D)
1688
{
1689
  INIT (CC2stat);
1690
 
1691
  ASSIGN (cbit);
1692
  ASSIGN (op);
1693
  ASSIGN (D);
1694
 
1695
  return GEN_OPCODE16 ();
1696
}
1697
 
1698
INSTR_T
1699
bfin_gen_regmv (REG_T src, REG_T dst)
1700
{
1701
  int gs, gd;
1702
  INIT (RegMv);
1703
 
1704
  ASSIGN_R (src);
1705
  ASSIGN_R (dst);
1706
 
1707
  gs = (GROUP (src));
1708
  ASSIGN (gs);
1709
  gd = (GROUP (dst));
1710
  ASSIGN (gd);
1711
 
1712
  return GEN_OPCODE16 ();
1713
}
1714
 
1715
INSTR_T
1716
bfin_gen_cc2dreg (int op, REG_T reg)
1717
{
1718
  INIT (CC2dreg);
1719
 
1720
  ASSIGN (op);
1721
  ASSIGN_R (reg);
1722
 
1723
  return GEN_OPCODE16 ();
1724
}
1725
 
1726
INSTR_T
1727
bfin_gen_progctrl (int prgfunc, int poprnd)
1728
{
1729
  INIT (ProgCtrl);
1730
 
1731
  ASSIGN (prgfunc);
1732
  ASSIGN (poprnd);
1733
 
1734
  return GEN_OPCODE16 ();
1735
}
1736
 
1737
INSTR_T
1738
bfin_gen_cactrl (REG_T reg, int a, int op)
1739
{
1740
  INIT (CaCTRL);
1741
 
1742
  ASSIGN_R (reg);
1743
  ASSIGN (a);
1744
  ASSIGN (op);
1745
 
1746
  return GEN_OPCODE16 ();
1747
}
1748
 
1749
INSTR_T
1750
bfin_gen_pushpopmultiple (int dr, int pr, int d, int p, int W)
1751
{
1752
  INIT (PushPopMultiple);
1753
 
1754
  ASSIGN (dr);
1755
  ASSIGN (pr);
1756
  ASSIGN (d);
1757
  ASSIGN (p);
1758
  ASSIGN (W);
1759
 
1760
  return GEN_OPCODE16 ();
1761
}
1762
 
1763
INSTR_T
1764
bfin_gen_pushpopreg (REG_T reg, int W)
1765
{
1766
  int grp;
1767
  INIT (PushPopReg);
1768
 
1769
  ASSIGN_R (reg);
1770
  grp = (GROUP (reg));
1771
  ASSIGN (grp);
1772
  ASSIGN (W);
1773
 
1774
  return GEN_OPCODE16 ();
1775
}
1776
 
1777
/* Pseudo Debugging Support.  */
1778
 
1779
INSTR_T
1780
bfin_gen_pseudodbg (int fn, int reg, int grp)
1781
{
1782
  INIT (PseudoDbg);
1783
 
1784
  ASSIGN (fn);
1785
  ASSIGN (reg);
1786
  ASSIGN (grp);
1787
 
1788
  return GEN_OPCODE16 ();
1789
}
1790
 
1791
INSTR_T
1792
bfin_gen_pseudodbg_assert (int dbgop, REG_T regtest, int expected)
1793
{
1794
  int grp;
1795
  INIT (PseudoDbg_Assert);
1796
 
1797
  ASSIGN (dbgop);
1798
  ASSIGN_R (regtest);
1799
  grp = GROUP (regtest);
1800
  ASSIGN (grp);
1801
  ASSIGN (expected);
1802
 
1803
  return GEN_OPCODE32 ();
1804
}
1805
 
1806
/* Multiple instruction generation.  */
1807
 
1808
INSTR_T
1809
bfin_gen_multi_instr (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2)
1810
{
1811
  INSTR_T walk;
1812
 
1813
  /* If it's a 0, convert into MNOP. */
1814
  if (dsp32)
1815
    {
1816
      walk = dsp32->next;
1817
      SET_MULTI_INSTRUCTION_BIT (dsp32);
1818
    }
1819
  else
1820
    {
1821
      dsp32 = gencode (0xc803);
1822
      walk = gencode (0x1800);
1823
      dsp32->next = walk;
1824
    }
1825
 
1826
  if (!dsp16_grp1)
1827
    {
1828
      dsp16_grp1 = gencode (0x0000);
1829
    }
1830
 
1831
  if (!dsp16_grp2)
1832
    {
1833
      dsp16_grp2 = gencode (0x0000);
1834
    }
1835
 
1836
  walk->next = dsp16_grp1;
1837
  dsp16_grp1->next = dsp16_grp2;
1838
  dsp16_grp2->next = NULL_CODE;
1839
 
1840
  return dsp32;
1841
}
1842
 
1843
INSTR_T
1844
bfin_gen_loop (Expr_Node *expr, REG_T reg, int rop, REG_T preg)
1845
{
1846
  const char *loopsym;
1847
  char *lbeginsym, *lendsym;
1848
  Expr_Node_Value lbeginval, lendval;
1849
  Expr_Node *lbegin, *lend;
1850
 
1851
  loopsym = expr->value.s_value;
1852
  lbeginsym = (char *) xmalloc (strlen (loopsym) + strlen ("__BEGIN") + 5);
1853
  lendsym = (char *) xmalloc (strlen (loopsym) + strlen ("__END") + 5);
1854
 
1855
  lbeginsym[0] = 0;
1856
  lendsym[0] = 0;
1857
 
1858
  strcat (lbeginsym, "L$L$");
1859
  strcat (lbeginsym, loopsym);
1860
  strcat (lbeginsym, "__BEGIN");
1861
 
1862
  strcat (lendsym, "L$L$");
1863
  strcat (lendsym, loopsym);
1864
  strcat (lendsym, "__END");
1865
 
1866
  lbeginval.s_value = lbeginsym;
1867
  lendval.s_value = lendsym;
1868
 
1869
  lbegin = Expr_Node_Create (Expr_Node_Reloc, lbeginval, NULL, NULL);
1870
  lend   = Expr_Node_Create (Expr_Node_Reloc, lendval, NULL, NULL);
1871
 
1872
  symbol_remove (symbol_find (loopsym), &symbol_rootP, &symbol_lastP);
1873
 
1874
  return bfin_gen_loopsetup(lbegin, reg, rop, lend, preg);
1875
}
1876
 
1877
void
1878
bfin_loop_beginend (Expr_Node *expr, int begin)
1879
{
1880
  const char *loopsym;
1881
  char *label_name;
1882
  symbolS *line_label;
1883
  const char *suffix = begin ? "__BEGIN" : "__END";
1884
 
1885
  loopsym = expr->value.s_value;
1886
  label_name = (char *) xmalloc (strlen (loopsym) + strlen (suffix) + 5);
1887
 
1888
  label_name[0] = 0;
1889
 
1890
  strcat (label_name, "L$L$");
1891
  strcat (label_name, loopsym);
1892
  strcat (label_name, suffix);
1893
 
1894
  line_label = colon (label_name);
1895
 
1896
  /* LOOP_END follows the last instruction in the loop.
1897
     Adjust label address.  */
1898
  if (!begin)
1899
    ((struct local_symbol *) line_label)->lsy_value -= last_insn_size;
1900
}
1901
 
1902
bfd_boolean
1903
bfin_eol_in_insn (char *line)
1904
{
1905
   /* Allow a new-line to appear in the middle of a multi-issue instruction.  */
1906
 
1907
   char *temp = line;
1908
 
1909
  if (*line != '\n')
1910
    return FALSE;
1911
 
1912
  /* A semi-colon followed by a newline is always the end of a line.  */
1913
  if (line[-1] == ';')
1914
    return FALSE;
1915
 
1916
  if (line[-1] == '|')
1917
    return TRUE;
1918
 
1919
  /* If the || is on the next line, there might be leading whitespace.  */
1920
  temp++;
1921
  while (*temp == ' ' || *temp == '\t') temp++;
1922
 
1923
  if (*temp == '|')
1924
    return TRUE;
1925
 
1926
  return FALSE;
1927
}
1928
 
1929
bfd_boolean
1930
bfin_start_label (char *s, char *ptr)
1931
{
1932
  while (s != ptr)
1933
    {
1934
      if (*s == '(' || *s == '[')
1935
        return FALSE;
1936
      s++;
1937
    }
1938
 
1939
  return TRUE;
1940
}
1941
 
1942
int
1943
bfin_force_relocation (struct fix *fixp)
1944
{
1945
  if (fixp->fx_r_type ==BFD_RELOC_BFIN_16_LOW
1946
      || fixp->fx_r_type == BFD_RELOC_BFIN_16_HIGH)
1947
    return TRUE;
1948
 
1949
  return generic_force_reloc (fixp);
1950
}
1951
 
1952
/* This is a stripped down version of the disassembler.  The only thing it
1953
   does is return a mask of registers modified by an instruction.  Only
1954
   instructions that can occur in a parallel-issue bundle are handled, and
1955
   only the registers that can cause a conflict are recorded.  */
1956
 
1957
#define DREG_MASK(n) (0x101 << (n))
1958
#define DREGH_MASK(n) (0x100 << (n))
1959
#define DREGL_MASK(n) (0x001 << (n))
1960
#define IREG_MASK(n) (1 << ((n) + 16))
1961
 
1962
static int
1963
decode_ProgCtrl_0 (int iw0)
1964
{
1965
  if (iw0 == 0)
1966
    return 0;
1967
  abort ();
1968
}
1969
 
1970
static int
1971
decode_LDSTpmod_0 (int iw0)
1972
{
1973
  /* LDSTpmod
1974
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1975
     | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1976
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
1977
  int W   = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1978
  int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1979
  int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1980
  int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1981
  int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1982
 
1983
  if (aop == 1 && W == 0 && idx == ptr)
1984
    return DREGL_MASK (reg);
1985
  else if (aop == 2 && W == 0 && idx == ptr)
1986
    return DREGH_MASK (reg);
1987
  else if (aop == 1 && W == 1 && idx == ptr)
1988
    return 0;
1989
  else if (aop == 2 && W == 1 && idx == ptr)
1990
    return 0;
1991
  else if (aop == 0 && W == 0)
1992
    return DREG_MASK (reg);
1993
  else if (aop == 1 && W == 0)
1994
    return DREGL_MASK (reg);
1995
  else if (aop == 2 && W == 0)
1996
    return DREGH_MASK (reg);
1997
  else if (aop == 3 && W == 0)
1998
    return DREG_MASK (reg);
1999
  else if (aop == 3 && W == 1)
2000
    return DREG_MASK (reg);
2001
  else if (aop == 0 && W == 1)
2002
    return 0;
2003
  else if (aop == 1 && W == 1)
2004
    return 0;
2005
  else if (aop == 2 && W == 1)
2006
    return 0;
2007
  else
2008
    return 0;
2009
 
2010
  return 2;
2011
}
2012
 
2013
static int
2014
decode_dagMODim_0 (int iw0)
2015
{
2016
  /* dagMODim
2017
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2018
     | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
2019
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2020
  int i  = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
2021
  int op  = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
2022
 
2023
  if (op == 0 || op == 1)
2024
    return IREG_MASK (i);
2025
  else
2026
    return 0;
2027
 
2028
  return 2;
2029
}
2030
 
2031
static int
2032
decode_dagMODik_0 (int iw0)
2033
{
2034
  /* dagMODik
2035
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2036
     | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2037
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2038
  int i  = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2039
  return IREG_MASK (i);
2040
}
2041
 
2042
/* GOOD */
2043
static int
2044
decode_dspLDST_0 (int iw0)
2045
{
2046
  /* dspLDST
2047
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2048
     | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2049
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2050
  int i   = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2051
  int m   = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2052
  int W   = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2053
  int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2054
  int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2055
 
2056
  if (aop == 0 && W == 0 && m == 0)
2057
    return DREG_MASK (reg) | IREG_MASK (i);
2058
  else if (aop == 0 && W == 0 && m == 1)
2059
    return DREGL_MASK (reg) | IREG_MASK (i);
2060
  else if (aop == 0 && W == 0 && m == 2)
2061
    return DREGH_MASK (reg) | IREG_MASK (i);
2062
  else if (aop == 1 && W == 0 && m == 0)
2063
    return DREG_MASK (reg) | IREG_MASK (i);
2064
  else if (aop == 1 && W == 0 && m == 1)
2065
    return DREGL_MASK (reg) | IREG_MASK (i);
2066
  else if (aop == 1 && W == 0 && m == 2)
2067
    return DREGH_MASK (reg) | IREG_MASK (i);
2068
  else if (aop == 2 && W == 0 && m == 0)
2069
    return DREG_MASK (reg);
2070
  else if (aop == 2 && W == 0 && m == 1)
2071
    return DREGL_MASK (reg);
2072
  else if (aop == 2 && W == 0 && m == 2)
2073
    return DREGH_MASK (reg);
2074
  else if (aop == 0 && W == 1 && m == 0)
2075
    return IREG_MASK (i);
2076
  else if (aop == 0 && W == 1 && m == 1)
2077
    return IREG_MASK (i);
2078
  else if (aop == 0 && W == 1 && m == 2)
2079
    return IREG_MASK (i);
2080
  else if (aop == 1 && W == 1 && m == 0)
2081
    return IREG_MASK (i);
2082
  else if (aop == 1 && W == 1 && m == 1)
2083
    return IREG_MASK (i);
2084
  else if (aop == 1 && W == 1 && m == 2)
2085
    return IREG_MASK (i);
2086
  else if (aop == 2 && W == 1 && m == 0)
2087
    return 0;
2088
  else if (aop == 2 && W == 1 && m == 1)
2089
    return 0;
2090
  else if (aop == 2 && W == 1 && m == 2)
2091
    return 0;
2092
  else if (aop == 3 && W == 0)
2093
    return DREG_MASK (reg) | IREG_MASK (i);
2094
  else if (aop == 3 && W == 1)
2095
    return IREG_MASK (i);
2096
 
2097
  abort ();
2098
}
2099
 
2100
/* GOOD */
2101
static int
2102
decode_LDST_0 (int iw0)
2103
{
2104
  /* LDST
2105
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2106
     | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2107
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2108
  int Z   = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2109
  int W   = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2110
  int sz  = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2111
  int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2112
  int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2113
 
2114
  if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2115
    return DREG_MASK (reg);
2116
  else if (aop == 0 && sz == 0 && Z == 1 && W == 0)
2117
    return 0;
2118
  else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2119
    return DREG_MASK (reg);
2120
  else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2121
    return DREG_MASK (reg);
2122
  else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2123
    return DREG_MASK (reg);
2124
  else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2125
    return DREG_MASK (reg);
2126
  else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2127
    return DREG_MASK (reg);
2128
  else if (aop == 1 && sz == 0 && Z == 1 && W == 0)
2129
    return 0;
2130
  else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2131
    return DREG_MASK (reg);
2132
  else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2133
    return DREG_MASK (reg);
2134
  else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2135
    return DREG_MASK (reg);
2136
  else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2137
    return DREG_MASK (reg);
2138
  else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2139
    return DREG_MASK (reg);
2140
  else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2141
    return 0;
2142
  else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2143
    return DREG_MASK (reg);
2144
  else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2145
    return DREG_MASK (reg);
2146
  else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2147
    return DREG_MASK (reg);
2148
  else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2149
    return DREG_MASK (reg);
2150
  else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2151
    return 0;
2152
  else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2153
    return 0;
2154
  else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2155
    return 0;
2156
  else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2157
    return 0;
2158
  else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2159
    return 0;
2160
  else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2161
    return 0;
2162
  else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2163
    return 0;
2164
  else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2165
    return 0;
2166
  else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2167
    return 0;
2168
  else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2169
    return 0;
2170
  else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2171
    return 0;
2172
  else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2173
    return 0;
2174
 
2175
  abort ();
2176
}
2177
 
2178
static int
2179
decode_LDSTiiFP_0 (int iw0)
2180
{
2181
  /* LDSTiiFP
2182
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2183
     | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2184
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2185
  int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2186
  int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2187
 
2188
  if (W == 0)
2189
    return reg < 8 ? DREG_MASK (reg) : 0;
2190
  else
2191
    return 0;
2192
}
2193
 
2194
static int
2195
decode_LDSTii_0 (int iw0)
2196
{
2197
  /* LDSTii
2198
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2199
     | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2200
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2201
  int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2202
  int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2203
  int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2204
 
2205
  if (W == 0 && op != 3)
2206
    return DREG_MASK (reg);
2207
  else if (W == 0 && op == 3)
2208
   return 0;
2209
  else if (W == 1 && op == 0)
2210
    return 0;
2211
  else if (W == 1 && op == 1)
2212
    return 0;
2213
  else if (W == 1 && op == 3)
2214
    return 0;
2215
 
2216
  abort ();
2217
}
2218
 
2219
static int
2220
decode_dsp32mac_0 (int iw0, int iw1)
2221
{
2222
  int result = 0;
2223
  /* dsp32mac
2224
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2225
     | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2226
     |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2227
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2228
  int op1  = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2229
  int w1   = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2230
  int P    = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2231
  int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2232
  int w0   = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2233
  int MM   = ((iw1 >> DSP32Mac_MM_bits) & DSP32Mac_MM_mask);
2234
  int dst  = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2235
  int op0  = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2236
 
2237
  if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2238
    return 0;
2239
 
2240
  if (op1 == 3 && MM)
2241
    return 0;
2242
 
2243
  if ((w1 || w0) && mmod == M_W32)
2244
    return 0;
2245
 
2246
  if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
2247
    return 0;
2248
 
2249
  if (w1 == 1 || op1 != 3)
2250
    {
2251
      if (w1)
2252
        {
2253
          if (P)
2254
            return DREG_MASK (dst + 1);
2255
          else
2256
            return DREGH_MASK (dst);
2257
        }
2258
    }
2259
 
2260
  if (w0 == 1 || op0 != 3)
2261
    {
2262
      if (w0)
2263
        {
2264
          if (P)
2265
            return DREG_MASK (dst);
2266
          else
2267
            return DREGL_MASK (dst);
2268
        }
2269
    }
2270
 
2271
  return result;
2272
}
2273
 
2274
static int
2275
decode_dsp32mult_0 (int iw0, int iw1)
2276
{
2277
  /* dsp32mult
2278
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2279
     | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
2280
     |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2281
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2282
  int w1   = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2283
  int P    = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2284
  int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2285
  int w0   = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2286
  int dst  = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2287
  int result = 0;
2288
 
2289
  if (w1 == 0 && w0 == 0)
2290
    return 0;
2291
 
2292
  if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
2293
    return 0;
2294
 
2295
  if (w1)
2296
    {
2297
      if (P)
2298
        return DREG_MASK (dst | 1);
2299
      else
2300
        return DREGH_MASK (dst);
2301
    }
2302
 
2303
  if (w0)
2304
    {
2305
      if (P)
2306
        return DREG_MASK (dst);
2307
      else
2308
        return DREGL_MASK (dst);
2309
    }
2310
 
2311
  return result;
2312
}
2313
 
2314
static int
2315
decode_dsp32alu_0 (int iw0, int iw1)
2316
{
2317
  /* dsp32alu
2318
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2319
     | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
2320
     |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
2321
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2322
  int s    = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
2323
  int x    = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
2324
  int aop  = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
2325
  int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
2326
  int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
2327
  int HL   = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
2328
  int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
2329
 
2330
  if (aop == 0 && aopcde == 9 && s == 0)
2331
    return 0;
2332
  else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
2333
    return 0;
2334
  else if (aop >= x * 2 && aopcde == 5)
2335
    return HL ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2336
  else if (HL == 0 && aopcde == 2)
2337
    return DREGL_MASK (dst0);
2338
  else if (HL == 1 && aopcde == 2)
2339
    return DREGH_MASK (dst0);
2340
  else if (HL == 0 && aopcde == 3)
2341
    return DREGL_MASK (dst0);
2342
  else if (HL == 1 && aopcde == 3)
2343
    return DREGH_MASK (dst0);
2344
 
2345
  else if (aop == 0 && aopcde == 9 && s == 1)
2346
    return 0;
2347
  else if (aop == 1 && aopcde == 9 && s == 0)
2348
    return 0;
2349
  else if (aop == 2 && aopcde == 9 && s == 1)
2350
    return 0;
2351
  else if (aop == 3 && aopcde == 9 && s == 0)
2352
    return 0;
2353
  else if (aopcde == 8)
2354
    return 0;
2355
  else if (aop == 0 && aopcde == 11)
2356
    return DREG_MASK (dst0);
2357
  else if (aop == 1 && aopcde == 11)
2358
    return HL ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2359
  else if (aopcde == 11)
2360
    return 0;
2361
  else if (aopcde == 22)
2362
    return DREG_MASK (dst0);
2363
 
2364
  else if ((aop == 0 || aop == 1) && aopcde == 14)
2365
    return 0;
2366
  else if (aop == 3 && HL == 0 && aopcde == 14)
2367
    return 0;
2368
 
2369
  else if (aop == 3 && HL == 0 && aopcde == 15)
2370
    return DREG_MASK (dst0);
2371
 
2372
  else if (aop == 1 && aopcde == 16)
2373
    return 0;
2374
 
2375
  else if (aop == 0 && aopcde == 16)
2376
    return 0;
2377
 
2378
  else if (aop == 3 && HL == 0 && aopcde == 16)
2379
    return 0;
2380
 
2381
  else if (aop == 3 && HL == 0 && aopcde == 7)
2382
    return DREG_MASK (dst0);
2383
  else if ((aop == 0 || aop == 1 || aop == 2) && aopcde == 7)
2384
    return DREG_MASK (dst0);
2385
 
2386
  else if (aop == 0 && aopcde == 12)
2387
    return DREG_MASK (dst0);
2388
  else if (aop == 1 && aopcde == 12)
2389
    return DREG_MASK (dst0) | DREG_MASK (dst1);
2390
  else if (aop == 3 && aopcde == 12)
2391
    return HL ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2392
 
2393
  else if (aopcde == 0)
2394
    return DREG_MASK (dst0);
2395
  else if (aopcde == 1)
2396
    return DREG_MASK (dst0) | DREG_MASK (dst1);
2397
 
2398
  else if (aop == 0 && aopcde == 10)
2399
    return DREGL_MASK (dst0);
2400
  else if (aop == 1 && aopcde == 10)
2401
    return DREGL_MASK (dst0);
2402
 
2403
  else if ((aop == 1 || aop == 0) && aopcde == 4)
2404
    return DREG_MASK (dst0);
2405
  else if (aop == 2 && aopcde == 4)
2406
    return DREG_MASK (dst0) | DREG_MASK (dst1);
2407
 
2408
  else if (aop == 0 && aopcde == 17)
2409
    return DREG_MASK (dst0) | DREG_MASK (dst1);
2410
  else if (aop == 1 && aopcde == 17)
2411
    return DREG_MASK (dst0) | DREG_MASK (dst1);
2412
  else if (aop == 0 && aopcde == 18)
2413
    return 0;
2414
  else if (aop == 3 && aopcde == 18)
2415
    return 0;
2416
 
2417
  else if ((aop == 0 || aop == 1 || aop == 2) && aopcde == 6)
2418
    return DREG_MASK (dst0);
2419
 
2420
  else if ((aop == 0 || aop == 1) && aopcde == 20)
2421
    return DREG_MASK (dst0);
2422
 
2423
  else if ((aop == 0 || aop == 1) && aopcde == 21)
2424
    return DREG_MASK (dst0) | DREG_MASK (dst1);
2425
 
2426
  else if (aop == 0 && aopcde == 23 && HL == 1)
2427
    return DREG_MASK (dst0);
2428
  else if (aop == 0 && aopcde == 23 && HL == 0)
2429
    return DREG_MASK (dst0);
2430
 
2431
  else if (aop == 0 && aopcde == 24)
2432
    return DREG_MASK (dst0);
2433
  else if (aop == 1 && aopcde == 24)
2434
    return DREG_MASK (dst0) | DREG_MASK (dst1);
2435
  else if (aopcde == 13)
2436
    return DREG_MASK (dst0) | DREG_MASK (dst1);
2437
  else
2438
    return 0;
2439
 
2440
  return 4;
2441
}
2442
 
2443
static int
2444
decode_dsp32shift_0 (int iw0, int iw1)
2445
{
2446
  /* dsp32shift
2447
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2448
     | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
2449
     |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
2450
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2451
  int HLs  = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
2452
  int sop  = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
2453
  int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
2454
  int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
2455
  int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
2456
  int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
2457
 
2458
  if (sop == 0 && sopcde == 0)
2459
    return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2460
  else if (sop == 1 && sopcde == 0)
2461
    return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2462
  else if (sop == 2 && sopcde == 0)
2463
    return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2464
  else if (sop == 0 && sopcde == 3)
2465
    return 0;
2466
  else if (sop == 1 && sopcde == 3)
2467
    return 0;
2468
  else if (sop == 2 && sopcde == 3)
2469
    return 0;
2470
  else if (sop == 3 && sopcde == 3)
2471
    return DREG_MASK (dst0);
2472
  else if (sop == 0 && sopcde == 1)
2473
    return DREG_MASK (dst0);
2474
  else if (sop == 1 && sopcde == 1)
2475
    return DREG_MASK (dst0);
2476
  else if (sop == 2 && sopcde == 1)
2477
    return DREG_MASK (dst0);
2478
  else if (sopcde == 2)
2479
    return DREG_MASK (dst0);
2480
  else if (sopcde == 4)
2481
    return DREG_MASK (dst0);
2482
  else if (sop == 0 && sopcde == 5)
2483
    return DREGL_MASK (dst0);
2484
  else if (sop == 1 && sopcde == 5)
2485
    return DREGL_MASK (dst0);
2486
  else if (sop == 2 && sopcde == 5)
2487
    return DREGL_MASK (dst0);
2488
  else if (sop == 0 && sopcde == 6)
2489
    return DREGL_MASK (dst0);
2490
  else if (sop == 1 && sopcde == 6)
2491
    return DREGL_MASK (dst0);
2492
  else if (sop == 3 && sopcde == 6)
2493
    return DREGL_MASK (dst0);
2494
  else if (sop == 0 && sopcde == 7)
2495
    return DREGL_MASK (dst0);
2496
  else if (sop == 1 && sopcde == 7)
2497
    return DREGL_MASK (dst0);
2498
  else if (sop == 2 && sopcde == 7)
2499
    return DREGL_MASK (dst0);
2500
  else if (sop == 3 && sopcde == 7)
2501
    return DREGL_MASK (dst0);
2502
  else if (sop == 0 && sopcde == 8)
2503
    return DREG_MASK (src0) | DREG_MASK (src1);
2504
#if 0
2505
    {
2506
      OUTS (outf, "BITMUX (");
2507
      OUTS (outf, dregs (src0));
2508
      OUTS (outf, ", ");
2509
      OUTS (outf, dregs (src1));
2510
      OUTS (outf, ", A0) (ASR)");
2511
    }
2512
#endif
2513
  else if (sop == 1 && sopcde == 8)
2514
    return DREG_MASK (src0) | DREG_MASK (src1);
2515
#if 0
2516
    {
2517
      OUTS (outf, "BITMUX (");
2518
      OUTS (outf, dregs (src0));
2519
      OUTS (outf, ", ");
2520
      OUTS (outf, dregs (src1));
2521
      OUTS (outf, ", A0) (ASL)");
2522
    }
2523
#endif
2524
  else if (sopcde == 9)
2525
    return sop < 2 ? DREGL_MASK (dst0) : DREG_MASK (dst0);
2526
  else if (sopcde == 10)
2527
    return DREG_MASK (dst0);
2528
  else if (sop == 0 && sopcde == 11)
2529
    return DREGL_MASK (dst0);
2530
  else if (sop == 1 && sopcde == 11)
2531
    return DREGL_MASK (dst0);
2532
  else if (sop == 0 && sopcde == 12)
2533
    return 0;
2534
  else if (sop == 1 && sopcde == 12)
2535
    return DREGL_MASK (dst0);
2536
  else if (sop == 0 && sopcde == 13)
2537
    return DREG_MASK (dst0);
2538
  else if (sop == 1 && sopcde == 13)
2539
    return DREG_MASK (dst0);
2540
  else if (sop == 2 && sopcde == 13)
2541
    return DREG_MASK (dst0);
2542
 
2543
  abort ();
2544
}
2545
 
2546
static int
2547
decode_dsp32shiftimm_0 (int iw0, int iw1)
2548
{
2549
  /* dsp32shiftimm
2550
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2551
     | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
2552
     |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
2553
     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
2554
  int sop      = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
2555
  int bit8     = ((iw1 >> 8) & 0x1);
2556
  int dst0     = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
2557
  int sopcde   = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
2558
  int HLs      = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
2559
 
2560
 
2561
  if (sop == 0 && sopcde == 0)
2562
    return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2563
  else if (sop == 1 && sopcde == 0 && bit8 == 0)
2564
    return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2565
  else if (sop == 1 && sopcde == 0 && bit8 == 1)
2566
    return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2567
  else if (sop == 2 && sopcde == 0 && bit8 == 0)
2568
    return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2569
  else if (sop == 2 && sopcde == 0 && bit8 == 1)
2570
    return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2571
  else if (sop == 2 && sopcde == 3 && HLs == 1)
2572
    return 0;
2573
  else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
2574
    return 0;
2575
  else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
2576
    return 0;
2577
  else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
2578
    return 0;
2579
  else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
2580
    return 0;
2581
  else if (sop == 1 && sopcde == 3 && HLs == 0)
2582
    return 0;
2583
  else if (sop == 1 && sopcde == 3 && HLs == 1)
2584
    return 0;
2585
  else if (sop == 2 && sopcde == 3 && HLs == 0)
2586
    return 0;
2587
  else if (sop == 1 && sopcde == 1 && bit8 == 0)
2588
    return DREG_MASK (dst0);
2589
  else if (sop == 1 && sopcde == 1 && bit8 == 1)
2590
    return DREG_MASK (dst0);
2591
  else if (sop == 2 && sopcde == 1 && bit8 == 1)
2592
    return DREG_MASK (dst0);
2593
  else if (sop == 2 && sopcde == 1 && bit8 == 0)
2594
    return DREG_MASK (dst0);
2595
  else if (sop == 0 && sopcde == 1)
2596
    return DREG_MASK (dst0);
2597
  else if (sop == 1 && sopcde == 2)
2598
    return DREG_MASK (dst0);
2599
  else if (sop == 2 && sopcde == 2 && bit8 == 1)
2600
    return DREG_MASK (dst0);
2601
  else if (sop == 2 && sopcde == 2 && bit8 == 0)
2602
    return DREG_MASK (dst0);
2603
  else if (sop == 3 && sopcde == 2)
2604
    return DREG_MASK (dst0);
2605
  else if (sop == 0 && sopcde == 2)
2606
    return DREG_MASK (dst0);
2607
 
2608
  abort ();
2609
}
2610
 
2611
int
2612
insn_regmask (int iw0, int iw1)
2613
{
2614
  if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
2615
    return 0; /* MNOP */
2616
  else if ((iw0 & 0xff00) == 0x0000)
2617
    return decode_ProgCtrl_0 (iw0);
2618
  else if ((iw0 & 0xffc0) == 0x0240)
2619
    abort ();
2620
  else if ((iw0 & 0xff80) == 0x0100)
2621
    abort ();
2622
  else if ((iw0 & 0xfe00) == 0x0400)
2623
    abort ();
2624
  else if ((iw0 & 0xfe00) == 0x0600)
2625
    abort ();
2626
  else if ((iw0 & 0xf800) == 0x0800)
2627
    abort ();
2628
  else if ((iw0 & 0xffe0) == 0x0200)
2629
    abort ();
2630
  else if ((iw0 & 0xff00) == 0x0300)
2631
    abort ();
2632
  else if ((iw0 & 0xf000) == 0x1000)
2633
    abort ();
2634
  else if ((iw0 & 0xf000) == 0x2000)
2635
    abort ();
2636
  else if ((iw0 & 0xf000) == 0x3000)
2637
    abort ();
2638
  else if ((iw0 & 0xfc00) == 0x4000)
2639
    abort ();
2640
  else if ((iw0 & 0xfe00) == 0x4400)
2641
    abort ();
2642
  else if ((iw0 & 0xf800) == 0x4800)
2643
    abort ();
2644
  else if ((iw0 & 0xf000) == 0x5000)
2645
    abort ();
2646
  else if ((iw0 & 0xf800) == 0x6000)
2647
    abort ();
2648
  else if ((iw0 & 0xf800) == 0x6800)
2649
    abort ();
2650
  else if ((iw0 & 0xf000) == 0x8000)
2651
    return decode_LDSTpmod_0 (iw0);
2652
  else if ((iw0 & 0xff60) == 0x9e60)
2653
    return decode_dagMODim_0 (iw0);
2654
  else if ((iw0 & 0xfff0) == 0x9f60)
2655
    return decode_dagMODik_0 (iw0);
2656
  else if ((iw0 & 0xfc00) == 0x9c00)
2657
    return decode_dspLDST_0 (iw0);
2658
  else if ((iw0 & 0xf000) == 0x9000)
2659
    return decode_LDST_0 (iw0);
2660
  else if ((iw0 & 0xfc00) == 0xb800)
2661
    return decode_LDSTiiFP_0 (iw0);
2662
  else if ((iw0 & 0xe000) == 0xA000)
2663
    return decode_LDSTii_0 (iw0);
2664
  else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
2665
    abort ();
2666
  else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
2667
    abort ();
2668
  else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
2669
    abort ();
2670
  else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
2671
    abort ();
2672
  else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
2673
    abort ();
2674
  else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
2675
    return decode_dsp32mac_0 (iw0, iw1);
2676
  else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
2677
    return decode_dsp32mult_0 (iw0, iw1);
2678
  else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
2679
    return decode_dsp32alu_0 (iw0, iw1);
2680
  else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
2681
    return decode_dsp32shift_0 (iw0, iw1);
2682
  else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
2683
    return decode_dsp32shiftimm_0 (iw0, iw1);
2684
  else if ((iw0 & 0xff00) == 0xf800)
2685
    abort ();
2686
  else if ((iw0 & 0xFFC0) == 0xf000 && (iw1 & 0x0000) == 0x0000)
2687
    abort ();
2688
 
2689
  abort ();
2690
}

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