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This is as.info, produced by makeinfo version 4.8 from as.texinfo.
2
 
3
START-INFO-DIR-ENTRY
4
* As: (as).                     The GNU assembler.
5
* Gas: (as).                    The GNU assembler.
6
END-INFO-DIR-ENTRY
7
 
8
   This file documents the GNU Assembler "as".
9
 
10
   Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002,
11
2006, 2007, 2008, 2009 Free Software Foundation, Inc.
12
 
13
   Permission is granted to copy, distribute and/or modify this document
14
under the terms of the GNU Free Documentation License, Version 1.3 or
15
any later version published by the Free Software Foundation; with no
16
Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
17
Texts.  A copy of the license is included in the section entitled "GNU
18
Free Documentation License".
19
 
20

21
File: as.info,  Node: Top,  Next: Overview,  Up: (dir)
22
 
23
Using as
24
********
25
 
26
This file is a user guide to the GNU assembler `as' (GNU Binutils)
27
version 2.20.1.
28
 
29
   This document is distributed under the terms of the GNU Free
30
Documentation License.  A copy of the license is included in the
31
section entitled "GNU Free Documentation License".
32
 
33
* Menu:
34
 
35
* Overview::                    Overview
36
* Invoking::                    Command-Line Options
37
* Syntax::                      Syntax
38
* Sections::                    Sections and Relocation
39
* Symbols::                     Symbols
40
* Expressions::                 Expressions
41
* Pseudo Ops::                  Assembler Directives
42
 
43
* Object Attributes::           Object Attributes
44
* Machine Dependencies::        Machine Dependent Features
45
* Reporting Bugs::              Reporting Bugs
46
* Acknowledgements::            Who Did What
47
* GNU Free Documentation License::  GNU Free Documentation License
48
* AS Index::                    AS Index
49
 
50

51
File: as.info,  Node: Overview,  Next: Invoking,  Prev: Top,  Up: Top
52
 
53
1 Overview
54
**********
55
 
56
Here is a brief summary of how to invoke `as'.  For details, see *Note
57
Command-Line Options: Invoking.
58
 
59
     as [-a[cdghlns][=FILE]] [-alternate] [-D]
60
      [-debug-prefix-map OLD=NEW]
61
      [-defsym SYM=VAL] [-f] [-g] [-gstabs]
62
      [-gstabs+] [-gdwarf-2] [-help] [-I DIR] [-J]
63
      [-K] [-L] [-listing-lhs-width=NUM]
64
      [-listing-lhs-width2=NUM] [-listing-rhs-width=NUM]
65
      [-listing-cont-lines=NUM] [-keep-locals] [-o
66
      OBJFILE] [-R] [-reduce-memory-overheads] [-statistics]
67
      [-v] [-version] [-version] [-W] [-warn]
68
      [-fatal-warnings] [-w] [-x] [-Z] [@FILE]
69
      [-target-help] [TARGET-OPTIONS]
70
      [-|FILES ...]
71
 
72
     _Target Alpha options:_
73
        [-mCPU]
74
        [-mdebug | -no-mdebug]
75
        [-replace | -noreplace]
76
        [-relax] [-g] [-GSIZE]
77
        [-F] [-32addr]
78
 
79
     _Target ARC options:_
80
        [-marc[5|6|7|8]]
81
        [-EB|-EL]
82
 
83
     _Target ARM options:_
84
        [-mcpu=PROCESSOR[+EXTENSION...]]
85
        [-march=ARCHITECTURE[+EXTENSION...]]
86
        [-mfpu=FLOATING-POINT-FORMAT]
87
        [-mfloat-abi=ABI]
88
        [-meabi=VER]
89
        [-mthumb]
90
        [-EB|-EL]
91
        [-mapcs-32|-mapcs-26|-mapcs-float|
92
         -mapcs-reentrant]
93
        [-mthumb-interwork] [-k]
94
 
95
     _Target CRIS options:_
96
        [-underscore | -no-underscore]
97
        [-pic] [-N]
98
        [-emulation=criself | -emulation=crisaout]
99
        [-march=v0_v10 | -march=v10 | -march=v32 | -march=common_v10_v32]
100
 
101
     _Target D10V options:_
102
        [-O]
103
 
104
     _Target D30V options:_
105
        [-O|-n|-N]
106
 
107
     _Target H8/300 options:_
108
        [-h-tick-hex]
109
 
110
     _Target i386 options:_
111
        [-32|-64] [-n]
112
        [-march=CPU[+EXTENSION...]] [-mtune=CPU]
113
 
114
     _Target i960 options:_
115
        [-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB|
116
         -AKC|-AMC]
117
        [-b] [-no-relax]
118
 
119
     _Target IA-64 options:_
120
        [-mconstant-gp|-mauto-pic]
121
        [-milp32|-milp64|-mlp64|-mp64]
122
        [-mle|mbe]
123
        [-mtune=itanium1|-mtune=itanium2]
124
        [-munwind-check=warning|-munwind-check=error]
125
        [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
126
        [-x|-xexplicit] [-xauto] [-xdebug]
127
 
128
     _Target IP2K options:_
129
        [-mip2022|-mip2022ext]
130
 
131
     _Target M32C options:_
132
        [-m32c|-m16c] [-relax] [-h-tick-hex]
133
 
134
     _Target M32R options:_
135
        [-m32rx|-[no-]warn-explicit-parallel-conflicts|
136
        -W[n]p]
137
 
138
     _Target M680X0 options:_
139
        [-l] [-m68000|-m68010|-m68020|...]
140
 
141
     _Target M68HC11 options:_
142
        [-m68hc11|-m68hc12|-m68hcs12]
143
        [-mshort|-mlong]
144
        [-mshort-double|-mlong-double]
145
        [-force-long-branches] [-short-branches]
146
        [-strict-direct-mode] [-print-insn-syntax]
147
        [-print-opcodes] [-generate-example]
148
 
149
     _Target MCORE options:_
150
        [-jsri2bsr] [-sifilter] [-relax]
151
        [-mcpu=[210|340]]
152
     _Target MICROBLAZE options:_
153
 
154
     _Target MIPS options:_
155
        [-nocpp] [-EL] [-EB] [-O[OPTIMIZATION LEVEL]]
156
        [-g[DEBUG LEVEL]] [-G NUM] [-KPIC] [-call_shared]
157
        [-non_shared] [-xgot [-mvxworks-pic]
158
        [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
159
        [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
160
        [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
161
        [-mips64] [-mips64r2]
162
        [-construct-floats] [-no-construct-floats]
163
        [-trap] [-no-break] [-break] [-no-trap]
164
        [-mfix7000] [-mno-fix7000]
165
        [-mips16] [-no-mips16]
166
        [-msmartmips] [-mno-smartmips]
167
        [-mips3d] [-no-mips3d]
168
        [-mdmx] [-no-mdmx]
169
        [-mdsp] [-mno-dsp]
170
        [-mdspr2] [-mno-dspr2]
171
        [-mmt] [-mno-mt]
172
        [-mdebug] [-no-mdebug]
173
        [-mpdr] [-mno-pdr]
174
 
175
     _Target MMIX options:_
176
        [-fixed-special-register-names] [-globalize-symbols]
177
        [-gnu-syntax] [-relax] [-no-predefined-symbols]
178
        [-no-expand] [-no-merge-gregs] [-x]
179
        [-linker-allocated-gregs]
180
 
181
     _Target PDP11 options:_
182
        [-mpic|-mno-pic] [-mall] [-mno-extensions]
183
        [-mEXTENSION|-mno-EXTENSION]
184
        [-mCPU] [-mMACHINE]
185
 
186
     _Target picoJava options:_
187
        [-mb|-me]
188
 
189
     _Target PowerPC options:_
190
        [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|
191
         -m403|-m405|-mppc64|-m620|-mppc64bridge|-mbooke]
192
        [-mcom|-many|-maltivec|-mvsx] [-memb]
193
        [-mregnames|-mno-regnames]
194
        [-mrelocatable|-mrelocatable-lib]
195
        [-mlittle|-mlittle-endian|-mbig|-mbig-endian]
196
        [-msolaris|-mno-solaris]
197
 
198
     _Target s390 options:_
199
        [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
200
        [-mregnames|-mno-regnames]
201
        [-mwarn-areg-zero]
202
 
203
     _Target SCORE options:_
204
        [-EB][-EL][-FIXDD][-NWARN]
205
        [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
206
        [-march=score7][-march=score3]
207
        [-USE_R1][-KPIC][-O0][-G NUM][-V]
208
 
209
     _Target SPARC options:_
210
        [-Av6|-Av7|-Av8|-Asparclet|-Asparclite
211
         -Av8plus|-Av8plusa|-Av9|-Av9a]
212
        [-xarch=v8plus|-xarch=v8plusa] [-bump]
213
        [-32|-64]
214
 
215
     _Target TIC54X options:_
216
      [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
217
      [-merrors-to-file |-me ]
218
 
219
 
220
     _Target Z80 options:_
221
       [-z80] [-r800]
222
       [ -ignore-undocumented-instructions] [-Wnud]
223
       [ -ignore-unportable-instructions] [-Wnup]
224
       [ -warn-undocumented-instructions] [-Wud]
225
       [ -warn-unportable-instructions] [-Wup]
226
       [ -forbid-undocumented-instructions] [-Fud]
227
       [ -forbid-unportable-instructions] [-Fup]
228
 
229
 
230
     _Target Xtensa options:_
231
      [-[no-]text-section-literals] [-[no-]absolute-literals]
232
      [-[no-]target-align] [-[no-]longcalls]
233
      [-[no-]transform]
234
      [-rename-section OLDNAME=NEWNAME]
235
 
236
`@FILE'
237
     Read command-line options from FILE.  The options read are
238
     inserted in place of the original @FILE option.  If FILE does not
239
     exist, or cannot be read, then the option will be treated
240
     literally, and not removed.
241
 
242
     Options in FILE are separated by whitespace.  A whitespace
243
     character may be included in an option by surrounding the entire
244
     option in either single or double quotes.  Any character
245
     (including a backslash) may be included by prefixing the character
246
     to be included with a backslash.  The FILE may itself contain
247
     additional @FILE options; any such options will be processed
248
     recursively.
249
 
250
`-a[cdghlmns]'
251
     Turn on listings, in any of a variety of ways:
252
 
253
    `-ac'
254
          omit false conditionals
255
 
256
    `-ad'
257
          omit debugging directives
258
 
259
    `-ag'
260
          include general information, like as version and options
261
          passed
262
 
263
    `-ah'
264
          include high-level source
265
 
266
    `-al'
267
          include assembly
268
 
269
    `-am'
270
          include macro expansions
271
 
272
    `-an'
273
          omit forms processing
274
 
275
    `-as'
276
          include symbols
277
 
278
    `=file'
279
          set the name of the listing file
280
 
281
     You may combine these options; for example, use `-aln' for assembly
282
     listing without forms processing.  The `=file' option, if used,
283
     must be the last one.  By itself, `-a' defaults to `-ahls'.
284
 
285
`--alternate'
286
     Begin in alternate macro mode.  *Note `.altmacro': Altmacro.
287
 
288
`-D'
289
     Ignored.  This option is accepted for script compatibility with
290
     calls to other assemblers.
291
 
292
`--debug-prefix-map OLD=NEW'
293
     When assembling files in directory `OLD', record debugging
294
     information describing them as in `NEW' instead.
295
 
296
`--defsym SYM=VALUE'
297
     Define the symbol SYM to be VALUE before assembling the input file.
298
     VALUE must be an integer constant.  As in C, a leading `0x'
299
     indicates a hexadecimal value, and a leading `0' indicates an octal
300
     value.  The value of the symbol can be overridden inside a source
301
     file via the use of a `.set' pseudo-op.
302
 
303
`-f'
304
     "fast"--skip whitespace and comment preprocessing (assume source is
305
     compiler output).
306
 
307
`-g'
308
`--gen-debug'
309
     Generate debugging information for each assembler source line
310
     using whichever debug format is preferred by the target.  This
311
     currently means either STABS, ECOFF or DWARF2.
312
 
313
`--gstabs'
314
     Generate stabs debugging information for each assembler line.  This
315
     may help debugging assembler code, if the debugger can handle it.
316
 
317
`--gstabs+'
318
     Generate stabs debugging information for each assembler line, with
319
     GNU extensions that probably only gdb can handle, and that could
320
     make other debuggers crash or refuse to read your program.  This
321
     may help debugging assembler code.  Currently the only GNU
322
     extension is the location of the current working directory at
323
     assembling time.
324
 
325
`--gdwarf-2'
326
     Generate DWARF2 debugging information for each assembler line.
327
     This may help debugging assembler code, if the debugger can handle
328
     it.  Note--this option is only supported by some targets, not all
329
     of them.
330
 
331
`--help'
332
     Print a summary of the command line options and exit.
333
 
334
`--target-help'
335
     Print a summary of all target specific options and exit.
336
 
337
`-I DIR'
338
     Add directory DIR to the search list for `.include' directives.
339
 
340
`-J'
341
     Don't warn about signed overflow.
342
 
343
`-K'
344
     Issue warnings when difference tables altered for long
345
     displacements.
346
 
347
`-L'
348
`--keep-locals'
349
     Keep (in the symbol table) local symbols.  These symbols start with
350
     system-specific local label prefixes, typically `.L' for ELF
351
     systems or `L' for traditional a.out systems.  *Note Symbol
352
     Names::.
353
 
354
`--listing-lhs-width=NUMBER'
355
     Set the maximum width, in words, of the output data column for an
356
     assembler listing to NUMBER.
357
 
358
`--listing-lhs-width2=NUMBER'
359
     Set the maximum width, in words, of the output data column for
360
     continuation lines in an assembler listing to NUMBER.
361
 
362
`--listing-rhs-width=NUMBER'
363
     Set the maximum width of an input source line, as displayed in a
364
     listing, to NUMBER bytes.
365
 
366
`--listing-cont-lines=NUMBER'
367
     Set the maximum number of lines printed in a listing for a single
368
     line of input to NUMBER + 1.
369
 
370
`-o OBJFILE'
371
     Name the object-file output from `as' OBJFILE.
372
 
373
`-R'
374
     Fold the data section into the text section.
375
 
376
     Set the default size of GAS's hash tables to a prime number close
377
     to NUMBER.  Increasing this value can reduce the length of time it
378
     takes the assembler to perform its tasks, at the expense of
379
     increasing the assembler's memory requirements.  Similarly
380
     reducing this value can reduce the memory requirements at the
381
     expense of speed.
382
 
383
`--reduce-memory-overheads'
384
     This option reduces GAS's memory requirements, at the expense of
385
     making the assembly processes slower.  Currently this switch is a
386
     synonym for `--hash-size=4051', but in the future it may have
387
     other effects as well.
388
 
389
`--statistics'
390
     Print the maximum space (in bytes) and total time (in seconds)
391
     used by assembly.
392
 
393
`--strip-local-absolute'
394
     Remove local absolute symbols from the outgoing symbol table.
395
 
396
`-v'
397
`-version'
398
     Print the `as' version.
399
 
400
`--version'
401
     Print the `as' version and exit.
402
 
403
`-W'
404
`--no-warn'
405
     Suppress warning messages.
406
 
407
`--fatal-warnings'
408
     Treat warnings as errors.
409
 
410
`--warn'
411
     Don't suppress warning messages or treat them as errors.
412
 
413
`-w'
414
     Ignored.
415
 
416
`-x'
417
     Ignored.
418
 
419
`-Z'
420
     Generate an object file even after errors.
421
 
422
`-- | FILES ...'
423
     Standard input, or source files to assemble.
424
 
425
 
426
   The following options are available when as is configured for an ARC
427
processor.
428
 
429
`-marc[5|6|7|8]'
430
     This option selects the core processor variant.
431
 
432
`-EB | -EL'
433
     Select either big-endian (-EB) or little-endian (-EL) output.
434
 
435
   The following options are available when as is configured for the ARM
436
processor family.
437
 
438
`-mcpu=PROCESSOR[+EXTENSION...]'
439
     Specify which ARM processor variant is the target.
440
 
441
`-march=ARCHITECTURE[+EXTENSION...]'
442
     Specify which ARM architecture variant is used by the target.
443
 
444
`-mfpu=FLOATING-POINT-FORMAT'
445
     Select which Floating Point architecture is the target.
446
 
447
`-mfloat-abi=ABI'
448
     Select which floating point ABI is in use.
449
 
450
`-mthumb'
451
     Enable Thumb only instruction decoding.
452
 
453
`-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant'
454
     Select which procedure calling convention is in use.
455
 
456
`-EB | -EL'
457
     Select either big-endian (-EB) or little-endian (-EL) output.
458
 
459
`-mthumb-interwork'
460
     Specify that the code has been generated with interworking between
461
     Thumb and ARM code in mind.
462
 
463
`-k'
464
     Specify that PIC code has been generated.
465
 
466
   See the info pages for documentation of the CRIS-specific options.
467
 
468
   The following options are available when as is configured for a D10V
469
processor.
470
`-O'
471
     Optimize output by parallelizing instructions.
472
 
473
   The following options are available when as is configured for a D30V
474
processor.
475
`-O'
476
     Optimize output by parallelizing instructions.
477
 
478
`-n'
479
     Warn when nops are generated.
480
 
481
`-N'
482
     Warn when a nop after a 32-bit multiply instruction is generated.
483
 
484
   The following options are available when as is configured for the
485
Intel 80960 processor.
486
 
487
`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC'
488
     Specify which variant of the 960 architecture is the target.
489
 
490
`-b'
491
     Add code to collect statistics about branches taken.
492
 
493
`-no-relax'
494
     Do not alter compare-and-branch instructions for long
495
     displacements; error if necessary.
496
 
497
 
498
   The following options are available when as is configured for the
499
Ubicom IP2K series.
500
 
501
`-mip2022ext'
502
     Specifies that the extended IP2022 instructions are allowed.
503
 
504
`-mip2022'
505
     Restores the default behaviour, which restricts the permitted
506
     instructions to just the basic IP2022 ones.
507
 
508
 
509
   The following options are available when as is configured for the
510
Renesas M32C and M16C processors.
511
 
512
`-m32c'
513
     Assemble M32C instructions.
514
 
515
`-m16c'
516
     Assemble M16C instructions (the default).
517
 
518
`-relax'
519
     Enable support for link-time relaxations.
520
 
521
`-h-tick-hex'
522
     Support H'00 style hex constants in addition to 0x00 style.
523
 
524
 
525
   The following options are available when as is configured for the
526
Renesas M32R (formerly Mitsubishi M32R) series.
527
 
528
`--m32rx'
529
     Specify which processor in the M32R family is the target.  The
530
     default is normally the M32R, but this option changes it to the
531
     M32RX.
532
 
533
`--warn-explicit-parallel-conflicts or --Wp'
534
     Produce warning messages when questionable parallel constructs are
535
     encountered.
536
 
537
`--no-warn-explicit-parallel-conflicts or --Wnp'
538
     Do not produce warning messages when questionable parallel
539
     constructs are encountered.
540
 
541
 
542
   The following options are available when as is configured for the
543
Motorola 68000 series.
544
 
545
`-l'
546
     Shorten references to undefined symbols, to one word instead of
547
     two.
548
 
549
`-m68000 | -m68008 | -m68010 | -m68020 | -m68030'
550
`| -m68040 | -m68060 | -m68302 | -m68331 | -m68332'
551
`| -m68333 | -m68340 | -mcpu32 | -m5200'
552
     Specify what processor in the 68000 family is the target.  The
553
     default is normally the 68020, but this can be changed at
554
     configuration time.
555
 
556
`-m68881 | -m68882 | -mno-68881 | -mno-68882'
557
     The target machine does (or does not) have a floating-point
558
     coprocessor.  The default is to assume a coprocessor for 68020,
559
     68030, and cpu32.  Although the basic 68000 is not compatible with
560
     the 68881, a combination of the two can be specified, since it's
561
     possible to do emulation of the coprocessor instructions with the
562
     main processor.
563
 
564
`-m68851 | -mno-68851'
565
     The target machine does (or does not) have a memory-management
566
     unit coprocessor.  The default is to assume an MMU for 68020 and
567
     up.
568
 
569
 
570
   For details about the PDP-11 machine dependent features options, see
571
*Note PDP-11-Options::.
572
 
573
`-mpic | -mno-pic'
574
     Generate position-independent (or position-dependent) code.  The
575
     default is `-mpic'.
576
 
577
`-mall'
578
`-mall-extensions'
579
     Enable all instruction set extensions.  This is the default.
580
 
581
`-mno-extensions'
582
     Disable all instruction set extensions.
583
 
584
`-mEXTENSION | -mno-EXTENSION'
585
     Enable (or disable) a particular instruction set extension.
586
 
587
`-mCPU'
588
     Enable the instruction set extensions supported by a particular
589
     CPU, and disable all other extensions.
590
 
591
`-mMACHINE'
592
     Enable the instruction set extensions supported by a particular
593
     machine model, and disable all other extensions.
594
 
595
   The following options are available when as is configured for a
596
picoJava processor.
597
 
598
`-mb'
599
     Generate "big endian" format output.
600
 
601
`-ml'
602
     Generate "little endian" format output.
603
 
604
 
605
   The following options are available when as is configured for the
606
Motorola 68HC11 or 68HC12 series.
607
 
608
`-m68hc11 | -m68hc12 | -m68hcs12'
609
     Specify what processor is the target.  The default is defined by
610
     the configuration option when building the assembler.
611
 
612
`-mshort'
613
     Specify to use the 16-bit integer ABI.
614
 
615
`-mlong'
616
     Specify to use the 32-bit integer ABI.
617
 
618
`-mshort-double'
619
     Specify to use the 32-bit double ABI.
620
 
621
`-mlong-double'
622
     Specify to use the 64-bit double ABI.
623
 
624
`--force-long-branches'
625
     Relative branches are turned into absolute ones. This concerns
626
     conditional branches, unconditional branches and branches to a sub
627
     routine.
628
 
629
`-S | --short-branches'
630
     Do not turn relative branches into absolute ones when the offset
631
     is out of range.
632
 
633
`--strict-direct-mode'
634
     Do not turn the direct addressing mode into extended addressing
635
     mode when the instruction does not support direct addressing mode.
636
 
637
`--print-insn-syntax'
638
     Print the syntax of instruction in case of error.
639
 
640
`--print-opcodes'
641
     print the list of instructions with syntax and then exit.
642
 
643
`--generate-example'
644
     print an example of instruction for each possible instruction and
645
     then exit.  This option is only useful for testing `as'.
646
 
647
 
648
   The following options are available when `as' is configured for the
649
SPARC architecture:
650
 
651
`-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite'
652
`-Av8plus | -Av8plusa | -Av9 | -Av9a'
653
     Explicitly select a variant of the SPARC architecture.
654
 
655
     `-Av8plus' and `-Av8plusa' select a 32 bit environment.  `-Av9'
656
     and `-Av9a' select a 64 bit environment.
657
 
658
     `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with
659
     UltraSPARC extensions.
660
 
661
`-xarch=v8plus | -xarch=v8plusa'
662
     For compatibility with the Solaris v9 assembler.  These options are
663
     equivalent to -Av8plus and -Av8plusa, respectively.
664
 
665
`-bump'
666
     Warn when the assembler switches to another architecture.
667
 
668
   The following options are available when as is configured for the
669
'c54x architecture.
670
 
671
`-mfar-mode'
672
     Enable extended addressing mode.  All addresses and relocations
673
     will assume extended addressing (usually 23 bits).
674
 
675
`-mcpu=CPU_VERSION'
676
     Sets the CPU version being compiled for.
677
 
678
`-merrors-to-file FILENAME'
679
     Redirect error output to a file, for broken systems which don't
680
     support such behaviour in the shell.
681
 
682
   The following options are available when as is configured for a MIPS
683
processor.
684
 
685
`-G NUM'
686
     This option sets the largest size of an object that can be
687
     referenced implicitly with the `gp' register.  It is only accepted
688
     for targets that use ECOFF format, such as a DECstation running
689
     Ultrix.  The default value is 8.
690
 
691
`-EB'
692
     Generate "big endian" format output.
693
 
694
`-EL'
695
     Generate "little endian" format output.
696
 
697
`-mips1'
698
`-mips2'
699
`-mips3'
700
`-mips4'
701
`-mips5'
702
`-mips32'
703
`-mips32r2'
704
`-mips64'
705
`-mips64r2'
706
     Generate code for a particular MIPS Instruction Set Architecture
707
     level.  `-mips1' is an alias for `-march=r3000', `-mips2' is an
708
     alias for `-march=r6000', `-mips3' is an alias for `-march=r4000'
709
     and `-mips4' is an alias for `-march=r8000'.  `-mips5', `-mips32',
710
     `-mips32r2', `-mips64', and `-mips64r2' correspond to generic
711
     `MIPS V', `MIPS32', `MIPS32 Release 2', `MIPS64', and `MIPS64
712
     Release 2' ISA processors, respectively.
713
 
714
`-march=CPU'
715
     Generate code for a particular MIPS cpu.
716
 
717
`-mtune=CPU'
718
     Schedule and tune for a particular MIPS cpu.
719
 
720
`-mfix7000'
721
`-mno-fix7000'
722
     Cause nops to be inserted if the read of the destination register
723
     of an mfhi or mflo instruction occurs in the following two
724
     instructions.
725
 
726
`-mdebug'
727
`-no-mdebug'
728
     Cause stabs-style debugging output to go into an ECOFF-style
729
     .mdebug section instead of the standard ELF .stabs sections.
730
 
731
`-mpdr'
732
`-mno-pdr'
733
     Control generation of `.pdr' sections.
734
 
735
`-mgp32'
736
`-mfp32'
737
     The register sizes are normally inferred from the ISA and ABI, but
738
     these flags force a certain group of registers to be treated as 32
739
     bits wide at all times.  `-mgp32' controls the size of
740
     general-purpose registers and `-mfp32' controls the size of
741
     floating-point registers.
742
 
743
`-mips16'
744
`-no-mips16'
745
     Generate code for the MIPS 16 processor.  This is equivalent to
746
     putting `.set mips16' at the start of the assembly file.
747
     `-no-mips16' turns off this option.
748
 
749
`-msmartmips'
750
`-mno-smartmips'
751
     Enables the SmartMIPS extension to the MIPS32 instruction set.
752
     This is equivalent to putting `.set smartmips' at the start of the
753
     assembly file.  `-mno-smartmips' turns off this option.
754
 
755
`-mips3d'
756
`-no-mips3d'
757
     Generate code for the MIPS-3D Application Specific Extension.
758
     This tells the assembler to accept MIPS-3D instructions.
759
     `-no-mips3d' turns off this option.
760
 
761
`-mdmx'
762
`-no-mdmx'
763
     Generate code for the MDMX Application Specific Extension.  This
764
     tells the assembler to accept MDMX instructions.  `-no-mdmx' turns
765
     off this option.
766
 
767
`-mdsp'
768
`-mno-dsp'
769
     Generate code for the DSP Release 1 Application Specific Extension.
770
     This tells the assembler to accept DSP Release 1 instructions.
771
     `-mno-dsp' turns off this option.
772
 
773
`-mdspr2'
774
`-mno-dspr2'
775
     Generate code for the DSP Release 2 Application Specific Extension.
776
     This option implies -mdsp.  This tells the assembler to accept DSP
777
     Release 2 instructions.  `-mno-dspr2' turns off this option.
778
 
779
`-mmt'
780
`-mno-mt'
781
     Generate code for the MT Application Specific Extension.  This
782
     tells the assembler to accept MT instructions.  `-mno-mt' turns
783
     off this option.
784
 
785
`--construct-floats'
786
`--no-construct-floats'
787
     The `--no-construct-floats' option disables the construction of
788
     double width floating point constants by loading the two halves of
789
     the value into the two single width floating point registers that
790
     make up the double width register.  By default
791
     `--construct-floats' is selected, allowing construction of these
792
     floating point constants.
793
 
794
`--emulation=NAME'
795
     This option causes `as' to emulate `as' configured for some other
796
     target, in all respects, including output format (choosing between
797
     ELF and ECOFF only), handling of pseudo-opcodes which may generate
798
     debugging information or store symbol table information, and
799
     default endianness.  The available configuration names are:
800
     `mipsecoff', `mipself', `mipslecoff', `mipsbecoff', `mipslelf',
801
     `mipsbelf'.  The first two do not alter the default endianness
802
     from that of the primary target for which the assembler was
803
     configured; the others change the default to little- or big-endian
804
     as indicated by the `b' or `l' in the name.  Using `-EB' or `-EL'
805
     will override the endianness selection in any case.
806
 
807
     This option is currently supported only when the primary target
808
     `as' is configured for is a MIPS ELF or ECOFF target.
809
     Furthermore, the primary target or others specified with
810
     `--enable-targets=...' at configuration time must include support
811
     for the other format, if both are to be available.  For example,
812
     the Irix 5 configuration includes support for both.
813
 
814
     Eventually, this option will support more configurations, with more
815
     fine-grained control over the assembler's behavior, and will be
816
     supported for more processors.
817
 
818
`-nocpp'
819
     `as' ignores this option.  It is accepted for compatibility with
820
     the native tools.
821
 
822
`--trap'
823
`--no-trap'
824
`--break'
825
`--no-break'
826
     Control how to deal with multiplication overflow and division by
827
     zero.  `--trap' or `--no-break' (which are synonyms) take a trap
828
     exception (and only work for Instruction Set Architecture level 2
829
     and higher); `--break' or `--no-trap' (also synonyms, and the
830
     default) take a break exception.
831
 
832
`-n'
833
     When this option is used, `as' will issue a warning every time it
834
     generates a nop instruction from a macro.
835
 
836
   The following options are available when as is configured for an
837
MCore processor.
838
 
839
`-jsri2bsr'
840
`-nojsri2bsr'
841
     Enable or disable the JSRI to BSR transformation.  By default this
842
     is enabled.  The command line option `-nojsri2bsr' can be used to
843
     disable it.
844
 
845
`-sifilter'
846
`-nosifilter'
847
     Enable or disable the silicon filter behaviour.  By default this
848
     is disabled.  The default can be overridden by the `-sifilter'
849
     command line option.
850
 
851
`-relax'
852
     Alter jump instructions for long displacements.
853
 
854
`-mcpu=[210|340]'
855
     Select the cpu type on the target hardware.  This controls which
856
     instructions can be assembled.
857
 
858
`-EB'
859
     Assemble for a big endian target.
860
 
861
`-EL'
862
     Assemble for a little endian target.
863
 
864
 
865
   See the info pages for documentation of the MMIX-specific options.
866
 
867
   The following options are available when as is configured for the
868
s390 processor family.
869
 
870
`-m31'
871
`-m64'
872
     Select the word size, either 31/32 bits or 64 bits.
873
 
874
`-mesa'
875
 
876
`-mzarch'
877
     Select the architecture mode, either the Enterprise System
878
     Architecture (esa) or the z/Architecture mode (zarch).
879
 
880
`-march=PROCESSOR'
881
     Specify which s390 processor variant is the target, `g6', `g6',
882
     `z900', `z990', `z9-109', `z9-ec', or `z10'.
883
 
884
`-mregnames'
885
`-mno-regnames'
886
     Allow or disallow symbolic names for registers.
887
 
888
`-mwarn-areg-zero'
889
     Warn whenever the operand for a base or index register has been
890
     specified but evaluates to zero.
891
 
892
   The following options are available when as is configured for an
893
Xtensa processor.
894
 
895
`--text-section-literals | --no-text-section-literals'
896
     With `--text-section-literals', literal pools are interspersed in
897
     the text section.  The default is `--no-text-section-literals',
898
     which places literals in a separate section in the output file.
899
     These options only affect literals referenced via PC-relative
900
     `L32R' instructions; literals for absolute mode `L32R'
901
     instructions are handled separately.
902
 
903
`--absolute-literals | --no-absolute-literals'
904
     Indicate to the assembler whether `L32R' instructions use absolute
905
     or PC-relative addressing.  The default is to assume absolute
906
     addressing if the Xtensa processor includes the absolute `L32R'
907
     addressing option.  Otherwise, only the PC-relative `L32R' mode
908
     can be used.
909
 
910
`--target-align | --no-target-align'
911
     Enable or disable automatic alignment to reduce branch penalties
912
     at the expense of some code density.  The default is
913
     `--target-align'.
914
 
915
`--longcalls | --no-longcalls'
916
     Enable or disable transformation of call instructions to allow
917
     calls across a greater range of addresses.  The default is
918
     `--no-longcalls'.
919
 
920
`--transform | --no-transform'
921
     Enable or disable all assembler transformations of Xtensa
922
     instructions.  The default is `--transform'; `--no-transform'
923
     should be used only in the rare cases when the instructions must
924
     be exactly as specified in the assembly source.
925
 
926
`--rename-section OLDNAME=NEWNAME'
927
     When generating output sections, rename the OLDNAME section to
928
     NEWNAME.
929
 
930
   The following options are available when as is configured for a Z80
931
family processor.
932
`-z80'
933
     Assemble for Z80 processor.
934
 
935
`-r800'
936
     Assemble for R800 processor.
937
 
938
`-ignore-undocumented-instructions'
939
`-Wnud'
940
     Assemble undocumented Z80 instructions that also work on R800
941
     without warning.
942
 
943
`-ignore-unportable-instructions'
944
`-Wnup'
945
     Assemble all undocumented Z80 instructions without warning.
946
 
947
`-warn-undocumented-instructions'
948
`-Wud'
949
     Issue a warning for undocumented Z80 instructions that also work
950
     on R800.
951
 
952
`-warn-unportable-instructions'
953
`-Wup'
954
     Issue a warning for undocumented Z80 instructions that do not work
955
     on R800.
956
 
957
`-forbid-undocumented-instructions'
958
`-Fud'
959
     Treat all undocumented instructions as errors.
960
 
961
`-forbid-unportable-instructions'
962
`-Fup'
963
     Treat undocumented Z80 instructions that do not work on R800 as
964
     errors.
965
 
966
* Menu:
967
 
968
* Manual::                      Structure of this Manual
969
* GNU Assembler::               The GNU Assembler
970
* Object Formats::              Object File Formats
971
* Command Line::                Command Line
972
* Input Files::                 Input Files
973
* Object::                      Output (Object) File
974
* Errors::                      Error and Warning Messages
975
 
976

977
File: as.info,  Node: Manual,  Next: GNU Assembler,  Up: Overview
978
 
979
1.1 Structure of this Manual
980
============================
981
 
982
This manual is intended to describe what you need to know to use GNU
983
`as'.  We cover the syntax expected in source files, including notation
984
for symbols, constants, and expressions; the directives that `as'
985
understands; and of course how to invoke `as'.
986
 
987
   This manual also describes some of the machine-dependent features of
988
various flavors of the assembler.
989
 
990
   On the other hand, this manual is _not_ intended as an introduction
991
to programming in assembly language--let alone programming in general!
992
In a similar vein, we make no attempt to introduce the machine
993
architecture; we do _not_ describe the instruction set, standard
994
mnemonics, registers or addressing modes that are standard to a
995
particular architecture.  You may want to consult the manufacturer's
996
machine architecture manual for this information.
997
 
998

999
File: as.info,  Node: GNU Assembler,  Next: Object Formats,  Prev: Manual,  Up: Overview
1000
 
1001
1.2 The GNU Assembler
1002
=====================
1003
 
1004
GNU `as' is really a family of assemblers.  If you use (or have used)
1005
the GNU assembler on one architecture, you should find a fairly similar
1006
environment when you use it on another architecture.  Each version has
1007
much in common with the others, including object file formats, most
1008
assembler directives (often called "pseudo-ops") and assembler syntax.
1009
 
1010
   `as' is primarily intended to assemble the output of the GNU C
1011
compiler `gcc' for use by the linker `ld'.  Nevertheless, we've tried
1012
to make `as' assemble correctly everything that other assemblers for
1013
the same machine would assemble.  Any exceptions are documented
1014
explicitly (*note Machine Dependencies::).  This doesn't mean `as'
1015
always uses the same syntax as another assembler for the same
1016
architecture; for example, we know of several incompatible versions of
1017
680x0 assembly language syntax.
1018
 
1019
   Unlike older assemblers, `as' is designed to assemble a source
1020
program in one pass of the source file.  This has a subtle impact on the
1021
`.org' directive (*note `.org': Org.).
1022
 
1023

1024
File: as.info,  Node: Object Formats,  Next: Command Line,  Prev: GNU Assembler,  Up: Overview
1025
 
1026
1.3 Object File Formats
1027
=======================
1028
 
1029
The GNU assembler can be configured to produce several alternative
1030
object file formats.  For the most part, this does not affect how you
1031
write assembly language programs; but directives for debugging symbols
1032
are typically different in different file formats.  *Note Symbol
1033
Attributes: Symbol Attributes.
1034
 
1035

1036
File: as.info,  Node: Command Line,  Next: Input Files,  Prev: Object Formats,  Up: Overview
1037
 
1038
1.4 Command Line
1039
================
1040
 
1041
After the program name `as', the command line may contain options and
1042
file names.  Options may appear in any order, and may be before, after,
1043
or between file names.  The order of file names is significant.
1044
 
1045
   `--' (two hyphens) by itself names the standard input file
1046
explicitly, as one of the files for `as' to assemble.
1047
 
1048
   Except for `--' any command line argument that begins with a hyphen
1049
(`-') is an option.  Each option changes the behavior of `as'.  No
1050
option changes the way another option works.  An option is a `-'
1051
followed by one or more letters; the case of the letter is important.
1052
All options are optional.
1053
 
1054
   Some options expect exactly one file name to follow them.  The file
1055
name may either immediately follow the option's letter (compatible with
1056
older assemblers) or it may be the next command argument (GNU
1057
standard).  These two command lines are equivalent:
1058
 
1059
     as -o my-object-file.o mumble.s
1060
     as -omy-object-file.o mumble.s
1061
 
1062

1063
File: as.info,  Node: Input Files,  Next: Object,  Prev: Command Line,  Up: Overview
1064
 
1065
1.5 Input Files
1066
===============
1067
 
1068
We use the phrase "source program", abbreviated "source", to describe
1069
the program input to one run of `as'.  The program may be in one or
1070
more files; how the source is partitioned into files doesn't change the
1071
meaning of the source.
1072
 
1073
   The source program is a concatenation of the text in all the files,
1074
in the order specified.
1075
 
1076
   Each time you run `as' it assembles exactly one source program.  The
1077
source program is made up of one or more files.  (The standard input is
1078
also a file.)
1079
 
1080
   You give `as' a command line that has zero or more input file names.
1081
The input files are read (from left file name to right).  A command
1082
line argument (in any position) that has no special meaning is taken to
1083
be an input file name.
1084
 
1085
   If you give `as' no file names it attempts to read one input file
1086
from the `as' standard input, which is normally your terminal.  You may
1087
have to type  to tell `as' there is no more program to assemble.
1088
 
1089
   Use `--' if you need to explicitly name the standard input file in
1090
your command line.
1091
 
1092
   If the source is empty, `as' produces a small, empty object file.
1093
 
1094
Filenames and Line-numbers
1095
--------------------------
1096
 
1097
There are two ways of locating a line in the input file (or files) and
1098
either may be used in reporting error messages.  One way refers to a
1099
line number in a physical file; the other refers to a line number in a
1100
"logical" file.  *Note Error and Warning Messages: Errors.
1101
 
1102
   "Physical files" are those files named in the command line given to
1103
`as'.
1104
 
1105
   "Logical files" are simply names declared explicitly by assembler
1106
directives; they bear no relation to physical files.  Logical file
1107
names help error messages reflect the original source file, when `as'
1108
source is itself synthesized from other files.  `as' understands the
1109
`#' directives emitted by the `gcc' preprocessor.  See also *Note
1110
`.file': File.
1111
 
1112

1113
File: as.info,  Node: Object,  Next: Errors,  Prev: Input Files,  Up: Overview
1114
 
1115
1.6 Output (Object) File
1116
========================
1117
 
1118
Every time you run `as' it produces an output file, which is your
1119
assembly language program translated into numbers.  This file is the
1120
object file.  Its default name is `a.out'.  You can give it another
1121
name by using the `-o' option.  Conventionally, object file names end
1122
with `.o'.  The default name is used for historical reasons: older
1123
assemblers were capable of assembling self-contained programs directly
1124
into a runnable program.  (For some formats, this isn't currently
1125
possible, but it can be done for the `a.out' format.)
1126
 
1127
   The object file is meant for input to the linker `ld'.  It contains
1128
assembled program code, information to help `ld' integrate the
1129
assembled program into a runnable file, and (optionally) symbolic
1130
information for the debugger.
1131
 
1132

1133
File: as.info,  Node: Errors,  Prev: Object,  Up: Overview
1134
 
1135
1.7 Error and Warning Messages
1136
==============================
1137
 
1138
`as' may write warnings and error messages to the standard error file
1139
(usually your terminal).  This should not happen when  a compiler runs
1140
`as' automatically.  Warnings report an assumption made so that `as'
1141
could keep assembling a flawed program; errors report a grave problem
1142
that stops the assembly.
1143
 
1144
   Warning messages have the format
1145
 
1146
     file_name:NNN:Warning Message Text
1147
 
1148
(where NNN is a line number).  If a logical file name has been given
1149
(*note `.file': File.) it is used for the filename, otherwise the name
1150
of the current input file is used.  If a logical line number was given
1151
(*note `.line': Line.)  then it is used to calculate the number printed,
1152
otherwise the actual line in the current source file is printed.  The
1153
message text is intended to be self explanatory (in the grand Unix
1154
tradition).
1155
 
1156
   Error messages have the format
1157
     file_name:NNN:FATAL:Error Message Text
1158
   The file name and line number are derived as for warning messages.
1159
The actual message text may be rather less explanatory because many of
1160
them aren't supposed to happen.
1161
 
1162

1163
File: as.info,  Node: Invoking,  Next: Syntax,  Prev: Overview,  Up: Top
1164
 
1165
2 Command-Line Options
1166
**********************
1167
 
1168
This chapter describes command-line options available in _all_ versions
1169
of the GNU assembler; see *Note Machine Dependencies::, for options
1170
specific to particular machine architectures.
1171
 
1172
   If you are invoking `as' via the GNU C compiler, you can use the
1173
`-Wa' option to pass arguments through to the assembler.  The assembler
1174
arguments must be separated from each other (and the `-Wa') by commas.
1175
For example:
1176
 
1177
     gcc -c -g -O -Wa,-alh,-L file.c
1178
 
1179
This passes two options to the assembler: `-alh' (emit a listing to
1180
standard output with high-level and assembly source) and `-L' (retain
1181
local symbols in the symbol table).
1182
 
1183
   Usually you do not need to use this `-Wa' mechanism, since many
1184
compiler command-line options are automatically passed to the assembler
1185
by the compiler.  (You can call the GNU compiler driver with the `-v'
1186
option to see precisely what options it passes to each compilation
1187
pass, including the assembler.)
1188
 
1189
* Menu:
1190
 
1191
* a::             -a[cdghlns] enable listings
1192
* alternate::     --alternate enable alternate macro syntax
1193
* D::             -D for compatibility
1194
* f::             -f to work faster
1195
* I::             -I for .include search path
1196
 
1197
* K::             -K for difference tables
1198
 
1199
* L::             -L to retain local symbols
1200
* listing::       --listing-XXX to configure listing output
1201
* M::             -M or --mri to assemble in MRI compatibility mode
1202
* MD::            --MD for dependency tracking
1203
* o::             -o to name the object file
1204
* R::             -R to join data and text sections
1205
* statistics::    --statistics to see statistics about assembly
1206
* traditional-format:: --traditional-format for compatible output
1207
* v::             -v to announce version
1208
* W::             -W, --no-warn, --warn, --fatal-warnings to control warnings
1209
* Z::             -Z to make object file even after errors
1210
 
1211

1212
File: as.info,  Node: a,  Next: alternate,  Up: Invoking
1213
 
1214
2.1 Enable Listings: `-a[cdghlns]'
1215
==================================
1216
 
1217
These options enable listing output from the assembler.  By itself,
1218
`-a' requests high-level, assembly, and symbols listing.  You can use
1219
other letters to select specific options for the list: `-ah' requests a
1220
high-level language listing, `-al' requests an output-program assembly
1221
listing, and `-as' requests a symbol table listing.  High-level
1222
listings require that a compiler debugging option like `-g' be used,
1223
and that assembly listings (`-al') be requested also.
1224
 
1225
   Use the `-ag' option to print a first section with general assembly
1226
information, like as version, switches passed, or time stamp.
1227
 
1228
   Use the `-ac' option to omit false conditionals from a listing.  Any
1229
lines which are not assembled because of a false `.if' (or `.ifdef', or
1230
any other conditional), or a true `.if' followed by an `.else', will be
1231
omitted from the listing.
1232
 
1233
   Use the `-ad' option to omit debugging directives from the listing.
1234
 
1235
   Once you have specified one of these options, you can further control
1236
listing output and its appearance using the directives `.list',
1237
`.nolist', `.psize', `.eject', `.title', and `.sbttl'.  The `-an'
1238
option turns off all forms processing.  If you do not request listing
1239
output with one of the `-a' options, the listing-control directives
1240
have no effect.
1241
 
1242
   The letters after `-a' may be combined into one option, _e.g._,
1243
`-aln'.
1244
 
1245
   Note if the assembler source is coming from the standard input (e.g.,
1246
because it is being created by `gcc' and the `-pipe' command line switch
1247
is being used) then the listing will not contain any comments or
1248
preprocessor directives.  This is because the listing code buffers
1249
input source lines from stdin only after they have been preprocessed by
1250
the assembler.  This reduces memory usage and makes the code more
1251
efficient.
1252
 
1253

1254
File: as.info,  Node: alternate,  Next: D,  Prev: a,  Up: Invoking
1255
 
1256
2.2 `--alternate'
1257
=================
1258
 
1259
Begin in alternate macro mode, see *Note `.altmacro': Altmacro.
1260
 
1261

1262
File: as.info,  Node: D,  Next: f,  Prev: alternate,  Up: Invoking
1263
 
1264
2.3 `-D'
1265
========
1266
 
1267
This option has no effect whatsoever, but it is accepted to make it more
1268
likely that scripts written for other assemblers also work with `as'.
1269
 
1270

1271
File: as.info,  Node: f,  Next: I,  Prev: D,  Up: Invoking
1272
 
1273
2.4 Work Faster: `-f'
1274
=====================
1275
 
1276
`-f' should only be used when assembling programs written by a
1277
(trusted) compiler.  `-f' stops the assembler from doing whitespace and
1278
comment preprocessing on the input file(s) before assembling them.
1279
*Note Preprocessing: Preprocessing.
1280
 
1281
     _Warning:_ if you use `-f' when the files actually need to be
1282
     preprocessed (if they contain comments, for example), `as' does
1283
     not work correctly.
1284
 
1285

1286
File: as.info,  Node: I,  Next: K,  Prev: f,  Up: Invoking
1287
 
1288
2.5 `.include' Search Path: `-I' PATH
1289
=====================================
1290
 
1291
Use this option to add a PATH to the list of directories `as' searches
1292
for files specified in `.include' directives (*note `.include':
1293
Include.).  You may use `-I' as many times as necessary to include a
1294
variety of paths.  The current working directory is always searched
1295
first; after that, `as' searches any `-I' directories in the same order
1296
as they were specified (left to right) on the command line.
1297
 
1298

1299
File: as.info,  Node: K,  Next: L,  Prev: I,  Up: Invoking
1300
 
1301
2.6 Difference Tables: `-K'
1302
===========================
1303
 
1304
`as' sometimes alters the code emitted for directives of the form
1305
`.word SYM1-SYM2'.  *Note `.word': Word.  You can use the `-K' option
1306
if you want a warning issued when this is done.
1307
 
1308

1309
File: as.info,  Node: L,  Next: listing,  Prev: K,  Up: Invoking
1310
 
1311
2.7 Include Local Symbols: `-L'
1312
===============================
1313
 
1314
Symbols beginning with system-specific local label prefixes, typically
1315
`.L' for ELF systems or `L' for traditional a.out systems, are called
1316
"local symbols".  *Note Symbol Names::.  Normally you do not see such
1317
symbols when debugging, because they are intended for the use of
1318
programs (like compilers) that compose assembler programs, not for your
1319
notice.  Normally both `as' and `ld' discard such symbols, so you do
1320
not normally debug with them.
1321
 
1322
   This option tells `as' to retain those local symbols in the object
1323
file.  Usually if you do this you also tell the linker `ld' to preserve
1324
those symbols.
1325
 
1326

1327
File: as.info,  Node: listing,  Next: M,  Prev: L,  Up: Invoking
1328
 
1329
2.8 Configuring listing output: `--listing'
1330
===========================================
1331
 
1332
The listing feature of the assembler can be enabled via the command
1333
line switch `-a' (*note a::).  This feature combines the input source
1334
file(s) with a hex dump of the corresponding locations in the output
1335
object file, and displays them as a listing file.  The format of this
1336
listing can be controlled by directives inside the assembler source
1337
(i.e., `.list' (*note List::), `.title' (*note Title::), `.sbttl'
1338
(*note Sbttl::), `.psize' (*note Psize::), and `.eject' (*note Eject::)
1339
and also by the following switches:
1340
 
1341
`--listing-lhs-width=`number''
1342
     Sets the maximum width, in words, of the first line of the hex
1343
     byte dump.  This dump appears on the left hand side of the listing
1344
     output.
1345
 
1346
`--listing-lhs-width2=`number''
1347
     Sets the maximum width, in words, of any further lines of the hex
1348
     byte dump for a given input source line.  If this value is not
1349
     specified, it defaults to being the same as the value specified
1350
     for `--listing-lhs-width'.  If neither switch is used the default
1351
     is to one.
1352
 
1353
`--listing-rhs-width=`number''
1354
     Sets the maximum width, in characters, of the source line that is
1355
     displayed alongside the hex dump.  The default value for this
1356
     parameter is 100.  The source line is displayed on the right hand
1357
     side of the listing output.
1358
 
1359
`--listing-cont-lines=`number''
1360
     Sets the maximum number of continuation lines of hex dump that
1361
     will be displayed for a given single line of source input.  The
1362
     default value is 4.
1363
 
1364

1365
File: as.info,  Node: M,  Next: MD,  Prev: listing,  Up: Invoking
1366
 
1367
2.9 Assemble in MRI Compatibility Mode: `-M'
1368
============================================
1369
 
1370
The `-M' or `--mri' option selects MRI compatibility mode.  This
1371
changes the syntax and pseudo-op handling of `as' to make it compatible
1372
with the `ASM68K' or the `ASM960' (depending upon the configured
1373
target) assembler from Microtec Research.  The exact nature of the MRI
1374
syntax will not be documented here; see the MRI manuals for more
1375
information.  Note in particular that the handling of macros and macro
1376
arguments is somewhat different.  The purpose of this option is to
1377
permit assembling existing MRI assembler code using `as'.
1378
 
1379
   The MRI compatibility is not complete.  Certain operations of the
1380
MRI assembler depend upon its object file format, and can not be
1381
supported using other object file formats.  Supporting these would
1382
require enhancing each object file format individually.  These are:
1383
 
1384
   * global symbols in common section
1385
 
1386
     The m68k MRI assembler supports common sections which are merged
1387
     by the linker.  Other object file formats do not support this.
1388
     `as' handles common sections by treating them as a single common
1389
     symbol.  It permits local symbols to be defined within a common
1390
     section, but it can not support global symbols, since it has no
1391
     way to describe them.
1392
 
1393
   * complex relocations
1394
 
1395
     The MRI assemblers support relocations against a negated section
1396
     address, and relocations which combine the start addresses of two
1397
     or more sections.  These are not support by other object file
1398
     formats.
1399
 
1400
   * `END' pseudo-op specifying start address
1401
 
1402
     The MRI `END' pseudo-op permits the specification of a start
1403
     address.  This is not supported by other object file formats.  The
1404
     start address may instead be specified using the `-e' option to
1405
     the linker, or in a linker script.
1406
 
1407
   * `IDNT', `.ident' and `NAME' pseudo-ops
1408
 
1409
     The MRI `IDNT', `.ident' and `NAME' pseudo-ops assign a module
1410
     name to the output file.  This is not supported by other object
1411
     file formats.
1412
 
1413
   * `ORG' pseudo-op
1414
 
1415
     The m68k MRI `ORG' pseudo-op begins an absolute section at a given
1416
     address.  This differs from the usual `as' `.org' pseudo-op, which
1417
     changes the location within the current section.  Absolute
1418
     sections are not supported by other object file formats.  The
1419
     address of a section may be assigned within a linker script.
1420
 
1421
   There are some other features of the MRI assembler which are not
1422
supported by `as', typically either because they are difficult or
1423
because they seem of little consequence.  Some of these may be
1424
supported in future releases.
1425
 
1426
   * EBCDIC strings
1427
 
1428
     EBCDIC strings are not supported.
1429
 
1430
   * packed binary coded decimal
1431
 
1432
     Packed binary coded decimal is not supported.  This means that the
1433
     `DC.P' and `DCB.P' pseudo-ops are not supported.
1434
 
1435
   * `FEQU' pseudo-op
1436
 
1437
     The m68k `FEQU' pseudo-op is not supported.
1438
 
1439
   * `NOOBJ' pseudo-op
1440
 
1441
     The m68k `NOOBJ' pseudo-op is not supported.
1442
 
1443
   * `OPT' branch control options
1444
 
1445
     The m68k `OPT' branch control options--`B', `BRS', `BRB', `BRL',
1446
     and `BRW'--are ignored.  `as' automatically relaxes all branches,
1447
     whether forward or backward, to an appropriate size, so these
1448
     options serve no purpose.
1449
 
1450
   * `OPT' list control options
1451
 
1452
     The following m68k `OPT' list control options are ignored: `C',
1453
     `CEX', `CL', `CRE', `E', `G', `I', `M', `MEX', `MC', `MD', `X'.
1454
 
1455
   * other `OPT' options
1456
 
1457
     The following m68k `OPT' options are ignored: `NEST', `O', `OLD',
1458
     `OP', `P', `PCO', `PCR', `PCS', `R'.
1459
 
1460
   * `OPT' `D' option is default
1461
 
1462
     The m68k `OPT' `D' option is the default, unlike the MRI assembler.
1463
     `OPT NOD' may be used to turn it off.
1464
 
1465
   * `XREF' pseudo-op.
1466
 
1467
     The m68k `XREF' pseudo-op is ignored.
1468
 
1469
   * `.debug' pseudo-op
1470
 
1471
     The i960 `.debug' pseudo-op is not supported.
1472
 
1473
   * `.extended' pseudo-op
1474
 
1475
     The i960 `.extended' pseudo-op is not supported.
1476
 
1477
   * `.list' pseudo-op.
1478
 
1479
     The various options of the i960 `.list' pseudo-op are not
1480
     supported.
1481
 
1482
   * `.optimize' pseudo-op
1483
 
1484
     The i960 `.optimize' pseudo-op is not supported.
1485
 
1486
   * `.output' pseudo-op
1487
 
1488
     The i960 `.output' pseudo-op is not supported.
1489
 
1490
   * `.setreal' pseudo-op
1491
 
1492
     The i960 `.setreal' pseudo-op is not supported.
1493
 
1494
 
1495

1496
File: as.info,  Node: MD,  Next: o,  Prev: M,  Up: Invoking
1497
 
1498
2.10 Dependency Tracking: `--MD'
1499
================================
1500
 
1501
`as' can generate a dependency file for the file it creates.  This file
1502
consists of a single rule suitable for `make' describing the
1503
dependencies of the main source file.
1504
 
1505
   The rule is written to the file named in its argument.
1506
 
1507
   This feature is used in the automatic updating of makefiles.
1508
 
1509

1510
File: as.info,  Node: o,  Next: R,  Prev: MD,  Up: Invoking
1511
 
1512
2.11 Name the Object File: `-o'
1513
===============================
1514
 
1515
There is always one object file output when you run `as'.  By default
1516
it has the name `a.out' (or `b.out', for Intel 960 targets only).  You
1517
use this option (which takes exactly one filename) to give the object
1518
file a different name.
1519
 
1520
   Whatever the object file is called, `as' overwrites any existing
1521
file of the same name.
1522
 
1523

1524
File: as.info,  Node: R,  Next: statistics,  Prev: o,  Up: Invoking
1525
 
1526
2.12 Join Data and Text Sections: `-R'
1527
======================================
1528
 
1529
`-R' tells `as' to write the object file as if all data-section data
1530
lives in the text section.  This is only done at the very last moment:
1531
your binary data are the same, but data section parts are relocated
1532
differently.  The data section part of your object file is zero bytes
1533
long because all its bytes are appended to the text section.  (*Note
1534
Sections and Relocation: Sections.)
1535
 
1536
   When you specify `-R' it would be possible to generate shorter
1537
address displacements (because we do not have to cross between text and
1538
data section).  We refrain from doing this simply for compatibility with
1539
older versions of `as'.  In future, `-R' may work this way.
1540
 
1541
   When `as' is configured for COFF or ELF output, this option is only
1542
useful if you use sections named `.text' and `.data'.
1543
 
1544
   `-R' is not supported for any of the HPPA targets.  Using `-R'
1545
generates a warning from `as'.
1546
 
1547

1548
File: as.info,  Node: statistics,  Next: traditional-format,  Prev: R,  Up: Invoking
1549
 
1550
2.13 Display Assembly Statistics: `--statistics'
1551
================================================
1552
 
1553
Use `--statistics' to display two statistics about the resources used by
1554
`as': the maximum amount of space allocated during the assembly (in
1555
bytes), and the total execution time taken for the assembly (in CPU
1556
seconds).
1557
 
1558

1559
File: as.info,  Node: traditional-format,  Next: v,  Prev: statistics,  Up: Invoking
1560
 
1561
2.14 Compatible Output: `--traditional-format'
1562
==============================================
1563
 
1564
For some targets, the output of `as' is different in some ways from the
1565
output of some existing assembler.  This switch requests `as' to use
1566
the traditional format instead.
1567
 
1568
   For example, it disables the exception frame optimizations which
1569
`as' normally does by default on `gcc' output.
1570
 
1571

1572
File: as.info,  Node: v,  Next: W,  Prev: traditional-format,  Up: Invoking
1573
 
1574
2.15 Announce Version: `-v'
1575
===========================
1576
 
1577
You can find out what version of as is running by including the option
1578
`-v' (which you can also spell as `-version') on the command line.
1579
 
1580

1581
File: as.info,  Node: W,  Next: Z,  Prev: v,  Up: Invoking
1582
 
1583
2.16 Control Warnings: `-W', `--warn', `--no-warn', `--fatal-warnings'
1584
======================================================================
1585
 
1586
`as' should never give a warning or error message when assembling
1587
compiler output.  But programs written by people often cause `as' to
1588
give a warning that a particular assumption was made.  All such
1589
warnings are directed to the standard error file.
1590
 
1591
   If you use the `-W' and `--no-warn' options, no warnings are issued.
1592
This only affects the warning messages: it does not change any
1593
particular of how `as' assembles your file.  Errors, which stop the
1594
assembly, are still reported.
1595
 
1596
   If you use the `--fatal-warnings' option, `as' considers files that
1597
generate warnings to be in error.
1598
 
1599
   You can switch these options off again by specifying `--warn', which
1600
causes warnings to be output as usual.
1601
 
1602

1603
File: as.info,  Node: Z,  Prev: W,  Up: Invoking
1604
 
1605
2.17 Generate Object File in Spite of Errors: `-Z'
1606
==================================================
1607
 
1608
After an error message, `as' normally produces no output.  If for some
1609
reason you are interested in object file output even after `as' gives
1610
an error message on your program, use the `-Z' option.  If there are
1611
any errors, `as' continues anyways, and writes an object file after a
1612
final warning message of the form `N errors, M warnings, generating bad
1613
object file.'
1614
 
1615

1616
File: as.info,  Node: Syntax,  Next: Sections,  Prev: Invoking,  Up: Top
1617
 
1618
3 Syntax
1619
********
1620
 
1621
This chapter describes the machine-independent syntax allowed in a
1622
source file.  `as' syntax is similar to what many other assemblers use;
1623
it is inspired by the BSD 4.2 assembler, except that `as' does not
1624
assemble Vax bit-fields.
1625
 
1626
* Menu:
1627
 
1628
* Preprocessing::              Preprocessing
1629
* Whitespace::                  Whitespace
1630
* Comments::                    Comments
1631
* Symbol Intro::                Symbols
1632
* Statements::                  Statements
1633
* Constants::                   Constants
1634
 
1635

1636
File: as.info,  Node: Preprocessing,  Next: Whitespace,  Up: Syntax
1637
 
1638
3.1 Preprocessing
1639
=================
1640
 
1641
The `as' internal preprocessor:
1642
   * adjusts and removes extra whitespace.  It leaves one space or tab
1643
     before the keywords on a line, and turns any other whitespace on
1644
     the line into a single space.
1645
 
1646
   * removes all comments, replacing them with a single space, or an
1647
     appropriate number of newlines.
1648
 
1649
   * converts character constants into the appropriate numeric values.
1650
 
1651
   It does not do macro processing, include file handling, or anything
1652
else you may get from your C compiler's preprocessor.  You can do
1653
include file processing with the `.include' directive (*note
1654
`.include': Include.).  You can use the GNU C compiler driver to get
1655
other "CPP" style preprocessing by giving the input file a `.S' suffix.
1656
*Note Options Controlling the Kind of Output: (gcc.info)Overall
1657
Options.
1658
 
1659
   Excess whitespace, comments, and character constants cannot be used
1660
in the portions of the input text that are not preprocessed.
1661
 
1662
   If the first line of an input file is `#NO_APP' or if you use the
1663
`-f' option, whitespace and comments are not removed from the input
1664
file.  Within an input file, you can ask for whitespace and comment
1665
removal in specific portions of the by putting a line that says `#APP'
1666
before the text that may contain whitespace or comments, and putting a
1667
line that says `#NO_APP' after this text.  This feature is mainly
1668
intend to support `asm' statements in compilers whose output is
1669
otherwise free of comments and whitespace.
1670
 
1671

1672
File: as.info,  Node: Whitespace,  Next: Comments,  Prev: Preprocessing,  Up: Syntax
1673
 
1674
3.2 Whitespace
1675
==============
1676
 
1677
"Whitespace" is one or more blanks or tabs, in any order.  Whitespace
1678
is used to separate symbols, and to make programs neater for people to
1679
read.  Unless within character constants (*note Character Constants:
1680
Characters.), any whitespace means the same as exactly one space.
1681
 
1682

1683
File: as.info,  Node: Comments,  Next: Symbol Intro,  Prev: Whitespace,  Up: Syntax
1684
 
1685
3.3 Comments
1686
============
1687
 
1688
There are two ways of rendering comments to `as'.  In both cases the
1689
comment is equivalent to one space.
1690
 
1691
   Anything from `/*' through the next `*/' is a comment.  This means
1692
you may not nest these comments.
1693
 
1694
     /*
1695
       The only way to include a newline ('\n') in a comment
1696
       is to use this sort of comment.
1697
     */
1698
 
1699
     /* This sort of comment does not nest. */
1700
 
1701
   Anything from the "line comment" character to the next newline is
1702
considered a comment and is ignored.  The line comment character is `;'
1703
on the ARC; `@' on the ARM; `;' for the H8/300 family; `;' for the HPPA;
1704
`#' on the i386 and x86-64; `#' on the i960; `;' for the PDP-11; `;'
1705
for picoJava; `#' for Motorola PowerPC; `#' for IBM S/390; `#' for the
1706
Sunplus SCORE; `!' for the Renesas / SuperH SH; `!' on the SPARC; `#'
1707
on the ip2k; `#' on the m32c; `#' on the m32r; `|' on the 680x0; `#' on
1708
the 68HC11 and 68HC12; `#' on the Vax; `;' for the Z80; `!' for the
1709
Z8000; `#' on the V850; `#' for Xtensa systems; see *Note Machine
1710
Dependencies::.
1711
 
1712
   On some machines there are two different line comment characters.
1713
One character only begins a comment if it is the first non-whitespace
1714
character on a line, while the other always begins a comment.
1715
 
1716
   The V850 assembler also supports a double dash as starting a comment
1717
that extends to the end of the line.
1718
 
1719
   `--';
1720
 
1721
   To be compatible with past assemblers, lines that begin with `#'
1722
have a special interpretation.  Following the `#' should be an absolute
1723
expression (*note Expressions::): the logical line number of the _next_
1724
line.  Then a string (*note Strings: Strings.) is allowed: if present
1725
it is a new logical file name.  The rest of the line, if any, should be
1726
whitespace.
1727
 
1728
   If the first non-whitespace characters on the line are not numeric,
1729
the line is ignored.  (Just like a comment.)
1730
 
1731
                               # This is an ordinary comment.
1732
     # 42-6 "new_file_name"    # New logical file name
1733
                               # This is logical line # 36.
1734
   This feature is deprecated, and may disappear from future versions
1735
of `as'.
1736
 
1737

1738
File: as.info,  Node: Symbol Intro,  Next: Statements,  Prev: Comments,  Up: Syntax
1739
 
1740
3.4 Symbols
1741
===========
1742
 
1743
A "symbol" is one or more characters chosen from the set of all letters
1744
(both upper and lower case), digits and the three characters `_.$'.  On
1745
most machines, you can also use `$' in symbol names; exceptions are
1746
noted in *Note Machine Dependencies::.  No symbol may begin with a
1747
digit.  Case is significant.  There is no length limit: all characters
1748
are significant.  Symbols are delimited by characters not in that set,
1749
or by the beginning of a file (since the source program must end with a
1750
newline, the end of a file is not a possible symbol delimiter).  *Note
1751
Symbols::.
1752
 
1753

1754
File: as.info,  Node: Statements,  Next: Constants,  Prev: Symbol Intro,  Up: Syntax
1755
 
1756
3.5 Statements
1757
==============
1758
 
1759
A "statement" ends at a newline character (`\n') or line separator
1760
character.  (The line separator is usually `;', unless this conflicts
1761
with the comment character; see *Note Machine Dependencies::.)  The
1762
newline or separator character is considered part of the preceding
1763
statement.  Newlines and separators within character constants are an
1764
exception: they do not end statements.
1765
 
1766
It is an error to end any statement with end-of-file:  the last
1767
character of any input file should be a newline.
1768
 
1769
   An empty statement is allowed, and may include whitespace.  It is
1770
ignored.
1771
 
1772
   A statement begins with zero or more labels, optionally followed by a
1773
key symbol which determines what kind of statement it is.  The key
1774
symbol determines the syntax of the rest of the statement.  If the
1775
symbol begins with a dot `.' then the statement is an assembler
1776
directive: typically valid for any computer.  If the symbol begins with
1777
a letter the statement is an assembly language "instruction": it
1778
assembles into a machine language instruction.  Different versions of
1779
`as' for different computers recognize different instructions.  In
1780
fact, the same symbol may represent a different instruction in a
1781
different computer's assembly language.
1782
 
1783
   A label is a symbol immediately followed by a colon (`:').
1784
Whitespace before a label or after a colon is permitted, but you may not
1785
have whitespace between a label's symbol and its colon. *Note Labels::.
1786
 
1787
   For HPPA targets, labels need not be immediately followed by a
1788
colon, but the definition of a label must begin in column zero.  This
1789
also implies that only one label may be defined on each line.
1790
 
1791
     label:     .directive    followed by something
1792
     another_label:           # This is an empty statement.
1793
                instruction   operand_1, operand_2, ...
1794
 
1795

1796
File: as.info,  Node: Constants,  Prev: Statements,  Up: Syntax
1797
 
1798
3.6 Constants
1799
=============
1800
 
1801
A constant is a number, written so that its value is known by
1802
inspection, without knowing any context.  Like this:
1803
     .byte  74, 0112, 092, 0x4A, 0X4a, 'J, '\J # All the same value.
1804
     .ascii "Ring the bell\7"                  # A string constant.
1805
     .octa  0x123456789abcdef0123456789ABCDEF0 # A bignum.
1806
     .float 0f-314159265358979323846264338327\
1807
     95028841971.693993751E-40                 # - pi, a flonum.
1808
 
1809
* Menu:
1810
 
1811
* Characters::                  Character Constants
1812
* Numbers::                     Number Constants
1813
 
1814

1815
File: as.info,  Node: Characters,  Next: Numbers,  Up: Constants
1816
 
1817
3.6.1 Character Constants
1818
-------------------------
1819
 
1820
There are two kinds of character constants.  A "character" stands for
1821
one character in one byte and its value may be used in numeric
1822
expressions.  String constants (properly called string _literals_) are
1823
potentially many bytes and their values may not be used in arithmetic
1824
expressions.
1825
 
1826
* Menu:
1827
 
1828
* Strings::                     Strings
1829
* Chars::                       Characters
1830
 
1831

1832
File: as.info,  Node: Strings,  Next: Chars,  Up: Characters
1833
 
1834
3.6.1.1 Strings
1835
...............
1836
 
1837
A "string" is written between double-quotes.  It may contain
1838
double-quotes or null characters.  The way to get special characters
1839
into a string is to "escape" these characters: precede them with a
1840
backslash `\' character.  For example `\\' represents one backslash:
1841
the first `\' is an escape which tells `as' to interpret the second
1842
character literally as a backslash (which prevents `as' from
1843
recognizing the second `\' as an escape character).  The complete list
1844
of escapes follows.
1845
 
1846
`\b'
1847
     Mnemonic for backspace; for ASCII this is octal code 010.
1848
 
1849
`\f'
1850
     Mnemonic for FormFeed; for ASCII this is octal code 014.
1851
 
1852
`\n'
1853
     Mnemonic for newline; for ASCII this is octal code 012.
1854
 
1855
`\r'
1856
     Mnemonic for carriage-Return; for ASCII this is octal code 015.
1857
 
1858
`\t'
1859
     Mnemonic for horizontal Tab; for ASCII this is octal code 011.
1860
 
1861
`\ DIGIT DIGIT DIGIT'
1862
     An octal character code.  The numeric code is 3 octal digits.  For
1863
     compatibility with other Unix systems, 8 and 9 are accepted as
1864
     digits: for example, `\008' has the value 010, and `\009' the
1865
     value 011.
1866
 
1867
`\`x' HEX-DIGITS...'
1868
     A hex character code.  All trailing hex digits are combined.
1869
     Either upper or lower case `x' works.
1870
 
1871
`\\'
1872
     Represents one `\' character.
1873
 
1874
`\"'
1875
     Represents one `"' character.  Needed in strings to represent this
1876
     character, because an unescaped `"' would end the string.
1877
 
1878
`\ ANYTHING-ELSE'
1879
     Any other character when escaped by `\' gives a warning, but
1880
     assembles as if the `\' was not present.  The idea is that if you
1881
     used an escape sequence you clearly didn't want the literal
1882
     interpretation of the following character.  However `as' has no
1883
     other interpretation, so `as' knows it is giving you the wrong
1884
     code and warns you of the fact.
1885
 
1886
   Which characters are escapable, and what those escapes represent,
1887
varies widely among assemblers.  The current set is what we think the
1888
BSD 4.2 assembler recognizes, and is a subset of what most C compilers
1889
recognize.  If you are in doubt, do not use an escape sequence.
1890
 
1891

1892
File: as.info,  Node: Chars,  Prev: Strings,  Up: Characters
1893
 
1894
3.6.1.2 Characters
1895
..................
1896
 
1897
A single character may be written as a single quote immediately
1898
followed by that character.  The same escapes apply to characters as to
1899
strings.  So if you want to write the character backslash, you must
1900
write `'\\' where the first `\' escapes the second `\'.  As you can
1901
see, the quote is an acute accent, not a grave accent.  A newline
1902
immediately following an acute accent is taken as a literal character
1903
and does not count as the end of a statement.  The value of a character
1904
constant in a numeric expression is the machine's byte-wide code for
1905
that character.  `as' assumes your character code is ASCII: `'A' means
1906
65, `'B' means 66, and so on.
1907
 
1908

1909
File: as.info,  Node: Numbers,  Prev: Characters,  Up: Constants
1910
 
1911
3.6.2 Number Constants
1912
----------------------
1913
 
1914
`as' distinguishes three kinds of numbers according to how they are
1915
stored in the target machine.  _Integers_ are numbers that would fit
1916
into an `int' in the C language.  _Bignums_ are integers, but they are
1917
stored in more than 32 bits.  _Flonums_ are floating point numbers,
1918
described below.
1919
 
1920
* Menu:
1921
 
1922
* Integers::                    Integers
1923
* Bignums::                     Bignums
1924
* Flonums::                     Flonums
1925
 
1926

1927
File: as.info,  Node: Integers,  Next: Bignums,  Up: Numbers
1928
 
1929
3.6.2.1 Integers
1930
................
1931
 
1932
A binary integer is `0b' or `0B' followed by zero or more of the binary
1933
digits `01'.
1934
 
1935
   An octal integer is `0' followed by zero or more of the octal digits
1936
(`01234567').
1937
 
1938
   A decimal integer starts with a non-zero digit followed by zero or
1939
more digits (`0123456789').
1940
 
1941
   A hexadecimal integer is `0x' or `0X' followed by one or more
1942
hexadecimal digits chosen from `0123456789abcdefABCDEF'.
1943
 
1944
   Integers have the usual values.  To denote a negative integer, use
1945
the prefix operator `-' discussed under expressions (*note Prefix
1946
Operators: Prefix Ops.).
1947
 
1948

1949
File: as.info,  Node: Bignums,  Next: Flonums,  Prev: Integers,  Up: Numbers
1950
 
1951
3.6.2.2 Bignums
1952
...............
1953
 
1954
A "bignum" has the same syntax and semantics as an integer except that
1955
the number (or its negative) takes more than 32 bits to represent in
1956
binary.  The distinction is made because in some places integers are
1957
permitted while bignums are not.
1958
 
1959

1960
File: as.info,  Node: Flonums,  Prev: Bignums,  Up: Numbers
1961
 
1962
3.6.2.3 Flonums
1963
...............
1964
 
1965
A "flonum" represents a floating point number.  The translation is
1966
indirect: a decimal floating point number from the text is converted by
1967
`as' to a generic binary floating point number of more than sufficient
1968
precision.  This generic floating point number is converted to a
1969
particular computer's floating point format (or formats) by a portion
1970
of `as' specialized to that computer.
1971
 
1972
   A flonum is written by writing (in order)
1973
   * The digit `0'.  (`0' is optional on the HPPA.)
1974
 
1975
   * A letter, to tell `as' the rest of the number is a flonum.  `e' is
1976
     recommended.  Case is not important.
1977
 
1978
     On the H8/300, Renesas / SuperH SH, and AMD 29K architectures, the
1979
     letter must be one of the letters `DFPRSX' (in upper or lower
1980
     case).
1981
 
1982
     On the ARC, the letter must be one of the letters `DFRS' (in upper
1983
     or lower case).
1984
 
1985
     On the Intel 960 architecture, the letter must be one of the
1986
     letters `DFT' (in upper or lower case).
1987
 
1988
     On the HPPA architecture, the letter must be `E' (upper case only).
1989
 
1990
   * An optional sign: either `+' or `-'.
1991
 
1992
   * An optional "integer part": zero or more decimal digits.
1993
 
1994
   * An optional "fractional part": `.' followed by zero or more
1995
     decimal digits.
1996
 
1997
   * An optional exponent, consisting of:
1998
 
1999
        * An `E' or `e'.
2000
 
2001
        * Optional sign: either `+' or `-'.
2002
 
2003
        * One or more decimal digits.
2004
 
2005
 
2006
   At least one of the integer part or the fractional part must be
2007
present.  The floating point number has the usual base-10 value.
2008
 
2009
   `as' does all processing using integers.  Flonums are computed
2010
independently of any floating point hardware in the computer running
2011
`as'.
2012
 
2013

2014
File: as.info,  Node: Sections,  Next: Symbols,  Prev: Syntax,  Up: Top
2015
 
2016
4 Sections and Relocation
2017
*************************
2018
 
2019
* Menu:
2020
 
2021
* Secs Background::             Background
2022
* Ld Sections::                 Linker Sections
2023
* As Sections::                 Assembler Internal Sections
2024
* Sub-Sections::                Sub-Sections
2025
* bss::                         bss Section
2026
 
2027

2028
File: as.info,  Node: Secs Background,  Next: Ld Sections,  Up: Sections
2029
 
2030
4.1 Background
2031
==============
2032
 
2033
Roughly, a section is a range of addresses, with no gaps; all data "in"
2034
those addresses is treated the same for some particular purpose.  For
2035
example there may be a "read only" section.
2036
 
2037
   The linker `ld' reads many object files (partial programs) and
2038
combines their contents to form a runnable program.  When `as' emits an
2039
object file, the partial program is assumed to start at address 0.
2040
`ld' assigns the final addresses for the partial program, so that
2041
different partial programs do not overlap.  This is actually an
2042
oversimplification, but it suffices to explain how `as' uses sections.
2043
 
2044
   `ld' moves blocks of bytes of your program to their run-time
2045
addresses.  These blocks slide to their run-time addresses as rigid
2046
units; their length does not change and neither does the order of bytes
2047
within them.  Such a rigid unit is called a _section_.  Assigning
2048
run-time addresses to sections is called "relocation".  It includes the
2049
task of adjusting mentions of object-file addresses so they refer to
2050
the proper run-time addresses.  For the H8/300, and for the Renesas /
2051
SuperH SH, `as' pads sections if needed to ensure they end on a word
2052
(sixteen bit) boundary.
2053
 
2054
   An object file written by `as' has at least three sections, any of
2055
which may be empty.  These are named "text", "data" and "bss" sections.
2056
 
2057
   When it generates COFF or ELF output, `as' can also generate
2058
whatever other named sections you specify using the `.section'
2059
directive (*note `.section': Section.).  If you do not use any
2060
directives that place output in the `.text' or `.data' sections, these
2061
sections still exist, but are empty.
2062
 
2063
   When `as' generates SOM or ELF output for the HPPA, `as' can also
2064
generate whatever other named sections you specify using the `.space'
2065
and `.subspace' directives.  See `HP9000 Series 800 Assembly Language
2066
Reference Manual' (HP 92432-90001) for details on the `.space' and
2067
`.subspace' assembler directives.
2068
 
2069
   Additionally, `as' uses different names for the standard text, data,
2070
and bss sections when generating SOM output.  Program text is placed
2071
into the `$CODE$' section, data into `$DATA$', and BSS into `$BSS$'.
2072
 
2073
   Within the object file, the text section starts at address `0', the
2074
data section follows, and the bss section follows the data section.
2075
 
2076
   When generating either SOM or ELF output files on the HPPA, the text
2077
section starts at address `0', the data section at address `0x4000000',
2078
and the bss section follows the data section.
2079
 
2080
   To let `ld' know which data changes when the sections are relocated,
2081
and how to change that data, `as' also writes to the object file
2082
details of the relocation needed.  To perform relocation `ld' must
2083
know, each time an address in the object file is mentioned:
2084
   * Where in the object file is the beginning of this reference to an
2085
     address?
2086
 
2087
   * How long (in bytes) is this reference?
2088
 
2089
   * Which section does the address refer to?  What is the numeric
2090
     value of
2091
          (ADDRESS) - (START-ADDRESS OF SECTION)?
2092
 
2093
   * Is the reference to an address "Program-Counter relative"?
2094
 
2095
   In fact, every address `as' ever uses is expressed as
2096
     (SECTION) + (OFFSET INTO SECTION)
2097
   Further, most expressions `as' computes have this section-relative
2098
nature.  (For some object formats, such as SOM for the HPPA, some
2099
expressions are symbol-relative instead.)
2100
 
2101
   In this manual we use the notation {SECNAME N} to mean "offset N
2102
into section SECNAME."
2103
 
2104
   Apart from text, data and bss sections you need to know about the
2105
"absolute" section.  When `ld' mixes partial programs, addresses in the
2106
absolute section remain unchanged.  For example, address `{absolute 0}'
2107
is "relocated" to run-time address 0 by `ld'.  Although the linker
2108
never arranges two partial programs' data sections with overlapping
2109
addresses after linking, _by definition_ their absolute sections must
2110
overlap.  Address `{absolute 239}' in one part of a program is always
2111
the same address when the program is running as address `{absolute
2112
239}' in any other part of the program.
2113
 
2114
   The idea of sections is extended to the "undefined" section.  Any
2115
address whose section is unknown at assembly time is by definition
2116
rendered {undefined U}--where U is filled in later.  Since numbers are
2117
always defined, the only way to generate an undefined address is to
2118
mention an undefined symbol.  A reference to a named common block would
2119
be such a symbol: its value is unknown at assembly time so it has
2120
section _undefined_.
2121
 
2122
   By analogy the word _section_ is used to describe groups of sections
2123
in the linked program.  `ld' puts all partial programs' text sections
2124
in contiguous addresses in the linked program.  It is customary to
2125
refer to the _text section_ of a program, meaning all the addresses of
2126
all partial programs' text sections.  Likewise for data and bss
2127
sections.
2128
 
2129
   Some sections are manipulated by `ld'; others are invented for use
2130
of `as' and have no meaning except during assembly.
2131
 
2132

2133
File: as.info,  Node: Ld Sections,  Next: As Sections,  Prev: Secs Background,  Up: Sections
2134
 
2135
4.2 Linker Sections
2136
===================
2137
 
2138
`ld' deals with just four kinds of sections, summarized below.
2139
 
2140
*named sections*
2141
*text section*
2142
*data section*
2143
     These sections hold your program.  `as' and `ld' treat them as
2144
     separate but equal sections.  Anything you can say of one section
2145
     is true of another.  When the program is running, however, it is
2146
     customary for the text section to be unalterable.  The text
2147
     section is often shared among processes: it contains instructions,
2148
     constants and the like.  The data section of a running program is
2149
     usually alterable: for example, C variables would be stored in the
2150
     data section.
2151
 
2152
*bss section*
2153
     This section contains zeroed bytes when your program begins
2154
     running.  It is used to hold uninitialized variables or common
2155
     storage.  The length of each partial program's bss section is
2156
     important, but because it starts out containing zeroed bytes there
2157
     is no need to store explicit zero bytes in the object file.  The
2158
     bss section was invented to eliminate those explicit zeros from
2159
     object files.
2160
 
2161
*absolute section*
2162
     Address 0 of this section is always "relocated" to runtime address
2163
     0.  This is useful if you want to refer to an address that `ld'
2164
     must not change when relocating.  In this sense we speak of
2165
     absolute addresses being "unrelocatable": they do not change
2166
     during relocation.
2167
 
2168
*undefined section*
2169
     This "section" is a catch-all for address references to objects
2170
     not in the preceding sections.
2171
 
2172
   An idealized example of three relocatable sections follows.  The
2173
example uses the traditional section names `.text' and `.data'.  Memory
2174
addresses are on the horizontal axis.
2175
 
2176
                           +-----+----+--+
2177
     partial program # 1:  |ttttt|dddd|00|
2178
                           +-----+----+--+
2179
 
2180
                           text   data bss
2181
                           seg.   seg. seg.
2182
 
2183
                           +---+---+---+
2184
     partial program # 2:  |TTT|DDD|000|
2185
                           +---+---+---+
2186
 
2187
                           +--+---+-----+--+----+---+-----+~~
2188
     linked program:       |  |TTT|ttttt|  |dddd|DDD|00000|
2189
                           +--+---+-----+--+----+---+-----+~~
2190
 
2191
         addresses:        0 ...
2192
 
2193

2194
File: as.info,  Node: As Sections,  Next: Sub-Sections,  Prev: Ld Sections,  Up: Sections
2195
 
2196
4.3 Assembler Internal Sections
2197
===============================
2198
 
2199
These sections are meant only for the internal use of `as'.  They have
2200
no meaning at run-time.  You do not really need to know about these
2201
sections for most purposes; but they can be mentioned in `as' warning
2202
messages, so it might be helpful to have an idea of their meanings to
2203
`as'.  These sections are used to permit the value of every expression
2204
in your assembly language program to be a section-relative address.
2205
 
2206
ASSEMBLER-INTERNAL-LOGIC-ERROR!
2207
     An internal assembler logic error has been found.  This means
2208
     there is a bug in the assembler.
2209
 
2210
expr section
2211
     The assembler stores complex expression internally as combinations
2212
     of symbols.  When it needs to represent an expression as a symbol,
2213
     it puts it in the expr section.
2214
 
2215

2216
File: as.info,  Node: Sub-Sections,  Next: bss,  Prev: As Sections,  Up: Sections
2217
 
2218
4.4 Sub-Sections
2219
================
2220
 
2221
Assembled bytes conventionally fall into two sections: text and data.
2222
You may have separate groups of data in named sections that you want to
2223
end up near to each other in the object file, even though they are not
2224
contiguous in the assembler source.  `as' allows you to use
2225
"subsections" for this purpose.  Within each section, there can be
2226
numbered subsections with values from 0 to 8192.  Objects assembled
2227
into the same subsection go into the object file together with other
2228
objects in the same subsection.  For example, a compiler might want to
2229
store constants in the text section, but might not want to have them
2230
interspersed with the program being assembled.  In this case, the
2231
compiler could issue a `.text 0' before each section of code being
2232
output, and a `.text 1' before each group of constants being output.
2233
 
2234
Subsections are optional.  If you do not use subsections, everything
2235
goes in subsection number zero.
2236
 
2237
   Each subsection is zero-padded up to a multiple of four bytes.
2238
(Subsections may be padded a different amount on different flavors of
2239
`as'.)
2240
 
2241
   Subsections appear in your object file in numeric order, lowest
2242
numbered to highest.  (All this to be compatible with other people's
2243
assemblers.)  The object file contains no representation of
2244
subsections; `ld' and other programs that manipulate object files see
2245
no trace of them.  They just see all your text subsections as a text
2246
section, and all your data subsections as a data section.
2247
 
2248
   To specify which subsection you want subsequent statements assembled
2249
into, use a numeric argument to specify it, in a `.text EXPRESSION' or
2250
a `.data EXPRESSION' statement.  When generating COFF output, you can
2251
also use an extra subsection argument with arbitrary named sections:
2252
`.section NAME, EXPRESSION'.  When generating ELF output, you can also
2253
use the `.subsection' directive (*note SubSection::) to specify a
2254
subsection: `.subsection EXPRESSION'.  EXPRESSION should be an absolute
2255
expression (*note Expressions::).  If you just say `.text' then `.text
2256
0' is assumed.  Likewise `.data' means `.data 0'.  Assembly begins in
2257
`text 0'.  For instance:
2258
     .text 0     # The default subsection is text 0 anyway.
2259
     .ascii "This lives in the first text subsection. *"
2260
     .text 1
2261
     .ascii "But this lives in the second text subsection."
2262
     .data 0
2263
     .ascii "This lives in the data section,"
2264
     .ascii "in the first data subsection."
2265
     .text 0
2266
     .ascii "This lives in the first text section,"
2267
     .ascii "immediately following the asterisk (*)."
2268
 
2269
   Each section has a "location counter" incremented by one for every
2270
byte assembled into that section.  Because subsections are merely a
2271
convenience restricted to `as' there is no concept of a subsection
2272
location counter.  There is no way to directly manipulate a location
2273
counter--but the `.align' directive changes it, and any label
2274
definition captures its current value.  The location counter of the
2275
section where statements are being assembled is said to be the "active"
2276
location counter.
2277
 
2278

2279
File: as.info,  Node: bss,  Prev: Sub-Sections,  Up: Sections
2280
 
2281
4.5 bss Section
2282
===============
2283
 
2284
The bss section is used for local common variable storage.  You may
2285
allocate address space in the bss section, but you may not dictate data
2286
to load into it before your program executes.  When your program starts
2287
running, all the contents of the bss section are zeroed bytes.
2288
 
2289
   The `.lcomm' pseudo-op defines a symbol in the bss section; see
2290
*Note `.lcomm': Lcomm.
2291
 
2292
   The `.comm' pseudo-op may be used to declare a common symbol, which
2293
is another form of uninitialized symbol; see *Note `.comm': Comm.
2294
 
2295
   When assembling for a target which supports multiple sections, such
2296
as ELF or COFF, you may switch into the `.bss' section and define
2297
symbols as usual; see *Note `.section': Section.  You may only assemble
2298
zero values into the section.  Typically the section will only contain
2299
symbol definitions and `.skip' directives (*note `.skip': Skip.).
2300
 
2301

2302
File: as.info,  Node: Symbols,  Next: Expressions,  Prev: Sections,  Up: Top
2303
 
2304
5 Symbols
2305
*********
2306
 
2307
Symbols are a central concept: the programmer uses symbols to name
2308
things, the linker uses symbols to link, and the debugger uses symbols
2309
to debug.
2310
 
2311
     _Warning:_ `as' does not place symbols in the object file in the
2312
     same order they were declared.  This may break some debuggers.
2313
 
2314
* Menu:
2315
 
2316
* Labels::                      Labels
2317
* Setting Symbols::             Giving Symbols Other Values
2318
* Symbol Names::                Symbol Names
2319
* Dot::                         The Special Dot Symbol
2320
* Symbol Attributes::           Symbol Attributes
2321
 
2322

2323
File: as.info,  Node: Labels,  Next: Setting Symbols,  Up: Symbols
2324
 
2325
5.1 Labels
2326
==========
2327
 
2328
A "label" is written as a symbol immediately followed by a colon `:'.
2329
The symbol then represents the current value of the active location
2330
counter, and is, for example, a suitable instruction operand.  You are
2331
warned if you use the same symbol to represent two different locations:
2332
the first definition overrides any other definitions.
2333
 
2334
   On the HPPA, the usual form for a label need not be immediately
2335
followed by a colon, but instead must start in column zero.  Only one
2336
label may be defined on a single line.  To work around this, the HPPA
2337
version of `as' also provides a special directive `.label' for defining
2338
labels more flexibly.
2339
 
2340

2341
File: as.info,  Node: Setting Symbols,  Next: Symbol Names,  Prev: Labels,  Up: Symbols
2342
 
2343
5.2 Giving Symbols Other Values
2344
===============================
2345
 
2346
A symbol can be given an arbitrary value by writing a symbol, followed
2347
by an equals sign `=', followed by an expression (*note Expressions::).
2348
This is equivalent to using the `.set' directive.  *Note `.set': Set.
2349
In the same way, using a double equals sign `='`=' here represents an
2350
equivalent of the `.eqv' directive.  *Note `.eqv': Eqv.
2351
 
2352
   Blackfin does not support symbol assignment with `='.
2353
 
2354

2355
File: as.info,  Node: Symbol Names,  Next: Dot,  Prev: Setting Symbols,  Up: Symbols
2356
 
2357
5.3 Symbol Names
2358
================
2359
 
2360
Symbol names begin with a letter or with one of `._'.  On most
2361
machines, you can also use `$' in symbol names; exceptions are noted in
2362
*Note Machine Dependencies::.  That character may be followed by any
2363
string of digits, letters, dollar signs (unless otherwise noted for a
2364
particular target machine), and underscores.
2365
 
2366
Case of letters is significant: `foo' is a different symbol name than
2367
`Foo'.
2368
 
2369
   Each symbol has exactly one name.  Each name in an assembly language
2370
program refers to exactly one symbol.  You may use that symbol name any
2371
number of times in a program.
2372
 
2373
Local Symbol Names
2374
------------------
2375
 
2376
A local symbol is any symbol beginning with certain local label
2377
prefixes.  By default, the local label prefix is `.L' for ELF systems or
2378
`L' for traditional a.out systems, but each target may have its own set
2379
of local label prefixes.  On the HPPA local symbols begin with `L$'.
2380
 
2381
   Local symbols are defined and used within the assembler, but they are
2382
normally not saved in object files.  Thus, they are not visible when
2383
debugging.  You may use the `-L' option (*note Include Local Symbols:
2384
`-L': L.) to retain the local symbols in the object files.
2385
 
2386
Local Labels
2387
------------
2388
 
2389
Local labels help compilers and programmers use names temporarily.
2390
They create symbols which are guaranteed to be unique over the entire
2391
scope of the input source code and which can be referred to by a simple
2392
notation.  To define a local label, write a label of the form `N:'
2393
(where N represents any positive integer).  To refer to the most recent
2394
previous definition of that label write `Nb', using the same number as
2395
when you defined the label.  To refer to the next definition of a local
2396
label, write `Nf'--the `b' stands for "backwards" and the `f' stands
2397
for "forwards".
2398
 
2399
   There is no restriction on how you can use these labels, and you can
2400
reuse them too.  So that it is possible to repeatedly define the same
2401
local label (using the same number `N'), although you can only refer to
2402
the most recently defined local label of that number (for a backwards
2403
reference) or the next definition of a specific local label for a
2404
forward reference.  It is also worth noting that the first 10 local
2405
labels (`0:'...`9:') are implemented in a slightly more efficient
2406
manner than the others.
2407
 
2408
   Here is an example:
2409
 
2410
     1:        branch 1f
2411
     2:        branch 1b
2412
     1:        branch 2f
2413
     2:        branch 1b
2414
 
2415
   Which is the equivalent of:
2416
 
2417
     label_1:  branch label_3
2418
     label_2:  branch label_1
2419
     label_3:  branch label_4
2420
     label_4:  branch label_3
2421
 
2422
   Local label names are only a notational device.  They are immediately
2423
transformed into more conventional symbol names before the assembler
2424
uses them.  The symbol names are stored in the symbol table, appear in
2425
error messages, and are optionally emitted to the object file.  The
2426
names are constructed using these parts:
2427
 
2428
`_local label prefix_'
2429
     All local symbols begin with the system-specific local label
2430
     prefix.  Normally both `as' and `ld' forget symbols that start
2431
     with the local label prefix.  These labels are used for symbols
2432
     you are never intended to see.  If you use the `-L' option then
2433
     `as' retains these symbols in the object file. If you also
2434
     instruct `ld' to retain these symbols, you may use them in
2435
     debugging.
2436
 
2437
`NUMBER'
2438
     This is the number that was used in the local label definition.
2439
     So if the label is written `55:' then the number is `55'.
2440
 
2441
`C-B'
2442
     This unusual character is included so you do not accidentally
2443
     invent a symbol of the same name.  The character has ASCII value
2444
     of `\002' (control-B).
2445
 
2446
`_ordinal number_'
2447
     This is a serial number to keep the labels distinct.  The first
2448
     definition of `0:' gets the number `1'.  The 15th definition of
2449
     `0:' gets the number `15', and so on.  Likewise the first
2450
     definition of `1:' gets the number `1' and its 15th definition
2451
     gets `15' as well.
2452
 
2453
   So for example, the first `1:' may be named `.L1C-B1', and the 44th
2454
`3:' may be named `.L3C-B44'.
2455
 
2456
Dollar Local Labels
2457
-------------------
2458
 
2459
`as' also supports an even more local form of local labels called
2460
dollar labels.  These labels go out of scope (i.e., they become
2461
undefined) as soon as a non-local label is defined.  Thus they remain
2462
valid for only a small region of the input source code.  Normal local
2463
labels, by contrast, remain in scope for the entire file, or until they
2464
are redefined by another occurrence of the same local label.
2465
 
2466
   Dollar labels are defined in exactly the same way as ordinary local
2467
labels, except that they have a dollar sign suffix to their numeric
2468
value, e.g., `55$:'.
2469
 
2470
   They can also be distinguished from ordinary local labels by their
2471
transformed names which use ASCII character `\001' (control-A) as the
2472
magic character to distinguish them from ordinary labels.  For example,
2473
the fifth definition of `6$' may be named `.L6C-A5'.
2474
 
2475

2476
File: as.info,  Node: Dot,  Next: Symbol Attributes,  Prev: Symbol Names,  Up: Symbols
2477
 
2478
5.4 The Special Dot Symbol
2479
==========================
2480
 
2481
The special symbol `.' refers to the current address that `as' is
2482
assembling into.  Thus, the expression `melvin: .long .' defines
2483
`melvin' to contain its own address.  Assigning a value to `.' is
2484
treated the same as a `.org' directive.  Thus, the expression `.=.+4'
2485
is the same as saying `.space 4'.
2486
 
2487

2488
File: as.info,  Node: Symbol Attributes,  Prev: Dot,  Up: Symbols
2489
 
2490
5.5 Symbol Attributes
2491
=====================
2492
 
2493
Every symbol has, as well as its name, the attributes "Value" and
2494
"Type".  Depending on output format, symbols can also have auxiliary
2495
attributes.
2496
 
2497
   If you use a symbol without defining it, `as' assumes zero for all
2498
these attributes, and probably won't warn you.  This makes the symbol
2499
an externally defined symbol, which is generally what you would want.
2500
 
2501
* Menu:
2502
 
2503
* Symbol Value::                Value
2504
* Symbol Type::                 Type
2505
 
2506
 
2507
* a.out Symbols::               Symbol Attributes: `a.out'
2508
 
2509
* COFF Symbols::                Symbol Attributes for COFF
2510
 
2511
* SOM Symbols::                Symbol Attributes for SOM
2512
 
2513

2514
File: as.info,  Node: Symbol Value,  Next: Symbol Type,  Up: Symbol Attributes
2515
 
2516
5.5.1 Value
2517
-----------
2518
 
2519
The value of a symbol is (usually) 32 bits.  For a symbol which labels a
2520
location in the text, data, bss or absolute sections the value is the
2521
number of addresses from the start of that section to the label.
2522
Naturally for text, data and bss sections the value of a symbol changes
2523
as `ld' changes section base addresses during linking.  Absolute
2524
symbols' values do not change during linking: that is why they are
2525
called absolute.
2526
 
2527
   The value of an undefined symbol is treated in a special way.  If it
2528
is 0 then the symbol is not defined in this assembler source file, and
2529
`ld' tries to determine its value from other files linked into the same
2530
program.  You make this kind of symbol simply by mentioning a symbol
2531
name without defining it.  A non-zero value represents a `.comm' common
2532
declaration.  The value is how much common storage to reserve, in bytes
2533
(addresses).  The symbol refers to the first address of the allocated
2534
storage.
2535
 
2536

2537
File: as.info,  Node: Symbol Type,  Next: a.out Symbols,  Prev: Symbol Value,  Up: Symbol Attributes
2538
 
2539
5.5.2 Type
2540
----------
2541
 
2542
The type attribute of a symbol contains relocation (section)
2543
information, any flag settings indicating that a symbol is external, and
2544
(optionally), other information for linkers and debuggers.  The exact
2545
format depends on the object-code output format in use.
2546
 
2547

2548
File: as.info,  Node: a.out Symbols,  Next: COFF Symbols,  Prev: Symbol Type,  Up: Symbol Attributes
2549
 
2550
5.5.3 Symbol Attributes: `a.out'
2551
--------------------------------
2552
 
2553
* Menu:
2554
 
2555
* Symbol Desc::                 Descriptor
2556
* Symbol Other::                Other
2557
 
2558

2559
File: as.info,  Node: Symbol Desc,  Next: Symbol Other,  Up: a.out Symbols
2560
 
2561
5.5.3.1 Descriptor
2562
..................
2563
 
2564
This is an arbitrary 16-bit value.  You may establish a symbol's
2565
descriptor value by using a `.desc' statement (*note `.desc': Desc.).
2566
A descriptor value means nothing to `as'.
2567
 
2568

2569
File: as.info,  Node: Symbol Other,  Prev: Symbol Desc,  Up: a.out Symbols
2570
 
2571
5.5.3.2 Other
2572
.............
2573
 
2574
This is an arbitrary 8-bit value.  It means nothing to `as'.
2575
 
2576

2577
File: as.info,  Node: COFF Symbols,  Next: SOM Symbols,  Prev: a.out Symbols,  Up: Symbol Attributes
2578
 
2579
5.5.4 Symbol Attributes for COFF
2580
--------------------------------
2581
 
2582
The COFF format supports a multitude of auxiliary symbol attributes;
2583
like the primary symbol attributes, they are set between `.def' and
2584
`.endef' directives.
2585
 
2586
5.5.4.1 Primary Attributes
2587
..........................
2588
 
2589
The symbol name is set with `.def'; the value and type, respectively,
2590
with `.val' and `.type'.
2591
 
2592
5.5.4.2 Auxiliary Attributes
2593
............................
2594
 
2595
The `as' directives `.dim', `.line', `.scl', `.size', `.tag', and
2596
`.weak' can generate auxiliary symbol table information for COFF.
2597
 
2598

2599
File: as.info,  Node: SOM Symbols,  Prev: COFF Symbols,  Up: Symbol Attributes
2600
 
2601
5.5.5 Symbol Attributes for SOM
2602
-------------------------------
2603
 
2604
The SOM format for the HPPA supports a multitude of symbol attributes
2605
set with the `.EXPORT' and `.IMPORT' directives.
2606
 
2607
   The attributes are described in `HP9000 Series 800 Assembly Language
2608
Reference Manual' (HP 92432-90001) under the `IMPORT' and `EXPORT'
2609
assembler directive documentation.
2610
 
2611

2612
File: as.info,  Node: Expressions,  Next: Pseudo Ops,  Prev: Symbols,  Up: Top
2613
 
2614
6 Expressions
2615
*************
2616
 
2617
An "expression" specifies an address or numeric value.  Whitespace may
2618
precede and/or follow an expression.
2619
 
2620
   The result of an expression must be an absolute number, or else an
2621
offset into a particular section.  If an expression is not absolute,
2622
and there is not enough information when `as' sees the expression to
2623
know its section, a second pass over the source program might be
2624
necessary to interpret the expression--but the second pass is currently
2625
not implemented.  `as' aborts with an error message in this situation.
2626
 
2627
* Menu:
2628
 
2629
* Empty Exprs::                 Empty Expressions
2630
* Integer Exprs::               Integer Expressions
2631
 
2632

2633
File: as.info,  Node: Empty Exprs,  Next: Integer Exprs,  Up: Expressions
2634
 
2635
6.1 Empty Expressions
2636
=====================
2637
 
2638
An empty expression has no value: it is just whitespace or null.
2639
Wherever an absolute expression is required, you may omit the
2640
expression, and `as' assumes a value of (absolute) 0.  This is
2641
compatible with other assemblers.
2642
 
2643

2644
File: as.info,  Node: Integer Exprs,  Prev: Empty Exprs,  Up: Expressions
2645
 
2646
6.2 Integer Expressions
2647
=======================
2648
 
2649
An "integer expression" is one or more _arguments_ delimited by
2650
_operators_.
2651
 
2652
* Menu:
2653
 
2654
* Arguments::                   Arguments
2655
* Operators::                   Operators
2656
* Prefix Ops::                  Prefix Operators
2657
* Infix Ops::                   Infix Operators
2658
 
2659

2660
File: as.info,  Node: Arguments,  Next: Operators,  Up: Integer Exprs
2661
 
2662
6.2.1 Arguments
2663
---------------
2664
 
2665
"Arguments" are symbols, numbers or subexpressions.  In other contexts
2666
arguments are sometimes called "arithmetic operands".  In this manual,
2667
to avoid confusing them with the "instruction operands" of the machine
2668
language, we use the term "argument" to refer to parts of expressions
2669
only, reserving the word "operand" to refer only to machine instruction
2670
operands.
2671
 
2672
   Symbols are evaluated to yield {SECTION NNN} where SECTION is one of
2673
text, data, bss, absolute, or undefined.  NNN is a signed, 2's
2674
complement 32 bit integer.
2675
 
2676
   Numbers are usually integers.
2677
 
2678
   A number can be a flonum or bignum.  In this case, you are warned
2679
that only the low order 32 bits are used, and `as' pretends these 32
2680
bits are an integer.  You may write integer-manipulating instructions
2681
that act on exotic constants, compatible with other assemblers.
2682
 
2683
   Subexpressions are a left parenthesis `(' followed by an integer
2684
expression, followed by a right parenthesis `)'; or a prefix operator
2685
followed by an argument.
2686
 
2687

2688
File: as.info,  Node: Operators,  Next: Prefix Ops,  Prev: Arguments,  Up: Integer Exprs
2689
 
2690
6.2.2 Operators
2691
---------------
2692
 
2693
"Operators" are arithmetic functions, like `+' or `%'.  Prefix
2694
operators are followed by an argument.  Infix operators appear between
2695
their arguments.  Operators may be preceded and/or followed by
2696
whitespace.
2697
 
2698

2699
File: as.info,  Node: Prefix Ops,  Next: Infix Ops,  Prev: Operators,  Up: Integer Exprs
2700
 
2701
6.2.3 Prefix Operator
2702
---------------------
2703
 
2704
`as' has the following "prefix operators".  They each take one
2705
argument, which must be absolute.
2706
 
2707
`-'
2708
     "Negation".  Two's complement negation.
2709
 
2710
`~'
2711
     "Complementation".  Bitwise not.
2712
 
2713

2714
File: as.info,  Node: Infix Ops,  Prev: Prefix Ops,  Up: Integer Exprs
2715
 
2716
6.2.4 Infix Operators
2717
---------------------
2718
 
2719
"Infix operators" take two arguments, one on either side.  Operators
2720
have precedence, but operations with equal precedence are performed left
2721
to right.  Apart from `+' or `-', both arguments must be absolute, and
2722
the result is absolute.
2723
 
2724
  1. Highest Precedence
2725
 
2726
    `*'
2727
          "Multiplication".
2728
 
2729
    `/'
2730
          "Division".  Truncation is the same as the C operator `/'
2731
 
2732
    `%'
2733
          "Remainder".
2734
 
2735
    `<<'
2736
          "Shift Left".  Same as the C operator `<<'.
2737
 
2738
    `>>'
2739
          "Shift Right".  Same as the C operator `>>'.
2740
 
2741
  2. Intermediate precedence
2742
 
2743
    `|'
2744
          "Bitwise Inclusive Or".
2745
 
2746
    `&'
2747
          "Bitwise And".
2748
 
2749
    `^'
2750
          "Bitwise Exclusive Or".
2751
 
2752
    `!'
2753
          "Bitwise Or Not".
2754
 
2755
  3. Low Precedence
2756
 
2757
    `+'
2758
          "Addition".  If either argument is absolute, the result has
2759
          the section of the other argument.  You may not add together
2760
          arguments from different sections.
2761
 
2762
    `-'
2763
          "Subtraction".  If the right argument is absolute, the result
2764
          has the section of the left argument.  If both arguments are
2765
          in the same section, the result is absolute.  You may not
2766
          subtract arguments from different sections.
2767
 
2768
    `=='
2769
          "Is Equal To"
2770
 
2771
    `<>'
2772
    `!='
2773
          "Is Not Equal To"
2774
 
2775
    `<'
2776
          "Is Less Than"
2777
 
2778
    `>'
2779
          "Is Greater Than"
2780
 
2781
    `>='
2782
          "Is Greater Than Or Equal To"
2783
 
2784
    `<='
2785
          "Is Less Than Or Equal To"
2786
 
2787
          The comparison operators can be used as infix operators.  A
2788
          true results has a value of -1 whereas a false result has a
2789
          value of 0.   Note, these operators perform signed
2790
          comparisons.
2791
 
2792
  4. Lowest Precedence
2793
 
2794
    `&&'
2795
          "Logical And".
2796
 
2797
    `||'
2798
          "Logical Or".
2799
 
2800
          These two logical operations can be used to combine the
2801
          results of sub expressions.  Note, unlike the comparison
2802
          operators a true result returns a value of 1 but a false
2803
          results does still return 0.  Also note that the logical or
2804
          operator has a slightly lower precedence than logical and.
2805
 
2806
 
2807
   In short, it's only meaningful to add or subtract the _offsets_ in an
2808
address; you can only have a defined section in one of the two
2809
arguments.
2810
 
2811

2812
File: as.info,  Node: Pseudo Ops,  Next: Object Attributes,  Prev: Expressions,  Up: Top
2813
 
2814
7 Assembler Directives
2815
**********************
2816
 
2817
All assembler directives have names that begin with a period (`.').
2818
The rest of the name is letters, usually in lower case.
2819
 
2820
   This chapter discusses directives that are available regardless of
2821
the target machine configuration for the GNU assembler.  Some machine
2822
configurations provide additional directives.  *Note Machine
2823
Dependencies::.
2824
 
2825
* Menu:
2826
 
2827
* Abort::                       `.abort'
2828
 
2829
* ABORT (COFF)::                `.ABORT'
2830
 
2831
* Align::                       `.align ABS-EXPR , ABS-EXPR'
2832
* Altmacro::                    `.altmacro'
2833
* Ascii::                       `.ascii "STRING"'...
2834
* Asciz::                       `.asciz "STRING"'...
2835
* Balign::                      `.balign ABS-EXPR , ABS-EXPR'
2836
* Byte::                        `.byte EXPRESSIONS'
2837
* CFI directives::              `.cfi_startproc [simple]', `.cfi_endproc', etc.
2838
* Comm::                        `.comm SYMBOL , LENGTH '
2839
* Data::                        `.data SUBSECTION'
2840
 
2841
* Def::                         `.def NAME'
2842
 
2843
* Desc::                        `.desc SYMBOL, ABS-EXPRESSION'
2844
 
2845
* Dim::                         `.dim'
2846
 
2847
* Double::                      `.double FLONUMS'
2848
* Eject::                       `.eject'
2849
* Else::                        `.else'
2850
* Elseif::                      `.elseif'
2851
* End::                         `.end'
2852
 
2853
* Endef::                       `.endef'
2854
 
2855
* Endfunc::                     `.endfunc'
2856
* Endif::                       `.endif'
2857
* Equ::                         `.equ SYMBOL, EXPRESSION'
2858
* Equiv::                       `.equiv SYMBOL, EXPRESSION'
2859
* Eqv::                         `.eqv SYMBOL, EXPRESSION'
2860
* Err::                         `.err'
2861
* Error::                       `.error STRING'
2862
* Exitm::                       `.exitm'
2863
* Extern::                      `.extern'
2864
* Fail::                        `.fail'
2865
* File::                        `.file'
2866
* Fill::                        `.fill REPEAT , SIZE , VALUE'
2867
* Float::                       `.float FLONUMS'
2868
* Func::                        `.func'
2869
* Global::                      `.global SYMBOL', `.globl SYMBOL'
2870
 
2871
* Gnu_attribute::               `.gnu_attribute TAG,VALUE'
2872
* Hidden::                      `.hidden NAMES'
2873
 
2874
* hword::                       `.hword EXPRESSIONS'
2875
* Ident::                       `.ident'
2876
* If::                          `.if ABSOLUTE EXPRESSION'
2877
* Incbin::                      `.incbin "FILE"[,SKIP[,COUNT]]'
2878
* Include::                     `.include "FILE"'
2879
* Int::                         `.int EXPRESSIONS'
2880
 
2881
* Internal::                    `.internal NAMES'
2882
 
2883
* Irp::                         `.irp SYMBOL,VALUES'...
2884
* Irpc::                        `.irpc SYMBOL,VALUES'...
2885
* Lcomm::                       `.lcomm SYMBOL , LENGTH'
2886
* Lflags::                      `.lflags'
2887
 
2888
* Line::                        `.line LINE-NUMBER'
2889
 
2890
* Linkonce::                    `.linkonce [TYPE]'
2891
* List::                        `.list'
2892
* Ln::                          `.ln LINE-NUMBER'
2893
* Loc::                         `.loc FILENO LINENO'
2894
* Loc_mark_labels::             `.loc_mark_labels ENABLE'
2895
 
2896
* Local::                       `.local NAMES'
2897
 
2898
* Long::                        `.long EXPRESSIONS'
2899
 
2900
* Macro::                       `.macro NAME ARGS'...
2901
* MRI::                         `.mri VAL'
2902
* Noaltmacro::                  `.noaltmacro'
2903
* Nolist::                      `.nolist'
2904
* Octa::                        `.octa BIGNUMS'
2905
* Org::                         `.org NEW-LC, FILL'
2906
* P2align::                     `.p2align ABS-EXPR, ABS-EXPR, ABS-EXPR'
2907
 
2908
* PopSection::                  `.popsection'
2909
* Previous::                    `.previous'
2910
 
2911
* Print::                       `.print STRING'
2912
 
2913
* Protected::                   `.protected NAMES'
2914
 
2915
* Psize::                       `.psize LINES, COLUMNS'
2916
* Purgem::                      `.purgem NAME'
2917
 
2918
* PushSection::                 `.pushsection NAME'
2919
 
2920
* Quad::                        `.quad BIGNUMS'
2921
* Reloc::                       `.reloc OFFSET, RELOC_NAME[, EXPRESSION]'
2922
* Rept::                        `.rept COUNT'
2923
* Sbttl::                       `.sbttl "SUBHEADING"'
2924
 
2925
* Scl::                         `.scl CLASS'
2926
 
2927
* Section::                     `.section NAME[, FLAGS]'
2928
 
2929
* Set::                         `.set SYMBOL, EXPRESSION'
2930
* Short::                       `.short EXPRESSIONS'
2931
* Single::                      `.single FLONUMS'
2932
 
2933
* Size::                        `.size [NAME , EXPRESSION]'
2934
 
2935
* Skip::                        `.skip SIZE , FILL'
2936
 
2937
* Sleb128::                     `.sleb128 EXPRESSIONS'
2938
 
2939
* Space::                       `.space SIZE , FILL'
2940
 
2941
* Stab::                        `.stabd, .stabn, .stabs'
2942
 
2943
* String::                      `.string "STR"', `.string8 "STR"', `.string16 "STR"', `.string32 "STR"', `.string64 "STR"'
2944
* Struct::                      `.struct EXPRESSION'
2945
 
2946
* SubSection::                  `.subsection'
2947
* Symver::                      `.symver NAME,NAME2@NODENAME'
2948
 
2949
 
2950
* Tag::                         `.tag STRUCTNAME'
2951
 
2952
* Text::                        `.text SUBSECTION'
2953
* Title::                       `.title "HEADING"'
2954
 
2955
* Type::                        `.type '
2956
 
2957
* Uleb128::                     `.uleb128 EXPRESSIONS'
2958
 
2959
* Val::                         `.val ADDR'
2960
 
2961
 
2962
* Version::                     `.version "STRING"'
2963
* VTableEntry::                 `.vtable_entry TABLE, OFFSET'
2964
* VTableInherit::               `.vtable_inherit CHILD, PARENT'
2965
 
2966
* Warning::                     `.warning STRING'
2967
* Weak::                        `.weak NAMES'
2968
* Weakref::                     `.weakref ALIAS, SYMBOL'
2969
* Word::                        `.word EXPRESSIONS'
2970
* Deprecated::                  Deprecated Directives
2971
 
2972

2973
File: as.info,  Node: Abort,  Next: ABORT (COFF),  Up: Pseudo Ops
2974
 
2975
7.1 `.abort'
2976
============
2977
 
2978
This directive stops the assembly immediately.  It is for compatibility
2979
with other assemblers.  The original idea was that the assembly
2980
language source would be piped into the assembler.  If the sender of
2981
the source quit, it could use this directive tells `as' to quit also.
2982
One day `.abort' will not be supported.
2983
 
2984

2985
File: as.info,  Node: ABORT (COFF),  Next: Align,  Prev: Abort,  Up: Pseudo Ops
2986
 
2987
7.2 `.ABORT' (COFF)
2988
===================
2989
 
2990
When producing COFF output, `as' accepts this directive as a synonym
2991
for `.abort'.
2992
 
2993

2994
File: as.info,  Node: Align,  Next: Altmacro,  Prev: ABORT (COFF),  Up: Pseudo Ops
2995
 
2996
7.3 `.align ABS-EXPR, ABS-EXPR, ABS-EXPR'
2997
=========================================
2998
 
2999
Pad the location counter (in the current subsection) to a particular
3000
storage boundary.  The first expression (which must be absolute) is the
3001
alignment required, as described below.
3002
 
3003
   The second expression (also absolute) gives the fill value to be
3004
stored in the padding bytes.  It (and the comma) may be omitted.  If it
3005
is omitted, the padding bytes are normally zero.  However, on some
3006
systems, if the section is marked as containing code and the fill value
3007
is omitted, the space is filled with no-op instructions.
3008
 
3009
   The third expression is also absolute, and is also optional.  If it
3010
is present, it is the maximum number of bytes that should be skipped by
3011
this alignment directive.  If doing the alignment would require
3012
skipping more bytes than the specified maximum, then the alignment is
3013
not done at all.  You can omit the fill value (the second argument)
3014
entirely by simply using two commas after the required alignment; this
3015
can be useful if you want the alignment to be filled with no-op
3016
instructions when appropriate.
3017
 
3018
   The way the required alignment is specified varies from system to
3019
system.  For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or32,
3020
s390, sparc, tic4x, tic80 and xtensa, the first expression is the
3021
alignment request in bytes.  For example `.align 8' advances the
3022
location counter until it is a multiple of 8.  If the location counter
3023
is already a multiple of 8, no change is needed.  For the tic54x, the
3024
first expression is the alignment request in words.
3025
 
3026
   For other systems, including ppc, i386 using a.out format, arm and
3027
strongarm, it is the number of low-order zero bits the location counter
3028
must have after advancement.  For example `.align 3' advances the
3029
location counter until it a multiple of 8.  If the location counter is
3030
already a multiple of 8, no change is needed.
3031
 
3032
   This inconsistency is due to the different behaviors of the various
3033
native assemblers for these systems which GAS must emulate.  GAS also
3034
provides `.balign' and `.p2align' directives, described later, which
3035
have a consistent behavior across all architectures (but are specific
3036
to GAS).
3037
 
3038

3039
File: as.info,  Node: Altmacro,  Next: Ascii,  Prev: Align,  Up: Pseudo Ops
3040
 
3041
7.4 `.altmacro'
3042
===============
3043
 
3044
Enable alternate macro mode, enabling:
3045
 
3046
`LOCAL NAME [ , ... ]'
3047
     One additional directive, `LOCAL', is available.  It is used to
3048
     generate a string replacement for each of the NAME arguments, and
3049
     replace any instances of NAME in each macro expansion.  The
3050
     replacement string is unique in the assembly, and different for
3051
     each separate macro expansion.  `LOCAL' allows you to write macros
3052
     that define symbols, without fear of conflict between separate
3053
     macro expansions.
3054
 
3055
`String delimiters'
3056
     You can write strings delimited in these other ways besides
3057
     `"STRING"':
3058
 
3059
    `'STRING''
3060
          You can delimit strings with single-quote characters.
3061
 
3062
    `'
3063
          You can delimit strings with matching angle brackets.
3064
 
3065
`single-character string escape'
3066
     To include any single character literally in a string (even if the
3067
     character would otherwise have some special meaning), you can
3068
     prefix the character with `!' (an exclamation mark).  For example,
3069
     you can write `<4.3 !> 5.4!!>' to get the literal text `4.3 >
3070
     5.4!'.
3071
 
3072
`Expression results as strings'
3073
     You can write `%EXPR' to evaluate the expression EXPR and use the
3074
     result as a string.
3075
 
3076

3077
File: as.info,  Node: Ascii,  Next: Asciz,  Prev: Altmacro,  Up: Pseudo Ops
3078
 
3079
7.5 `.ascii "STRING"'...
3080
========================
3081
 
3082
`.ascii' expects zero or more string literals (*note Strings::)
3083
separated by commas.  It assembles each string (with no automatic
3084
trailing zero byte) into consecutive addresses.
3085
 
3086

3087
File: as.info,  Node: Asciz,  Next: Balign,  Prev: Ascii,  Up: Pseudo Ops
3088
 
3089
7.6 `.asciz "STRING"'...
3090
========================
3091
 
3092
`.asciz' is just like `.ascii', but each string is followed by a zero
3093
byte.  The "z" in `.asciz' stands for "zero".
3094
 
3095

3096
File: as.info,  Node: Balign,  Next: Byte,  Prev: Asciz,  Up: Pseudo Ops
3097
 
3098
7.7 `.balign[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR'
3099
==============================================
3100
 
3101
Pad the location counter (in the current subsection) to a particular
3102
storage boundary.  The first expression (which must be absolute) is the
3103
alignment request in bytes.  For example `.balign 8' advances the
3104
location counter until it is a multiple of 8.  If the location counter
3105
is already a multiple of 8, no change is needed.
3106
 
3107
   The second expression (also absolute) gives the fill value to be
3108
stored in the padding bytes.  It (and the comma) may be omitted.  If it
3109
is omitted, the padding bytes are normally zero.  However, on some
3110
systems, if the section is marked as containing code and the fill value
3111
is omitted, the space is filled with no-op instructions.
3112
 
3113
   The third expression is also absolute, and is also optional.  If it
3114
is present, it is the maximum number of bytes that should be skipped by
3115
this alignment directive.  If doing the alignment would require
3116
skipping more bytes than the specified maximum, then the alignment is
3117
not done at all.  You can omit the fill value (the second argument)
3118
entirely by simply using two commas after the required alignment; this
3119
can be useful if you want the alignment to be filled with no-op
3120
instructions when appropriate.
3121
 
3122
   The `.balignw' and `.balignl' directives are variants of the
3123
`.balign' directive.  The `.balignw' directive treats the fill pattern
3124
as a two byte word value.  The `.balignl' directives treats the fill
3125
pattern as a four byte longword value.  For example, `.balignw
3126
4,0x368d' will align to a multiple of 4.  If it skips two bytes, they
3127
will be filled in with the value 0x368d (the exact placement of the
3128
bytes depends upon the endianness of the processor).  If it skips 1 or
3129
3 bytes, the fill value is undefined.
3130
 
3131

3132
File: as.info,  Node: Byte,  Next: CFI directives,  Prev: Balign,  Up: Pseudo Ops
3133
 
3134
7.8 `.byte EXPRESSIONS'
3135
=======================
3136
 
3137
`.byte' expects zero or more expressions, separated by commas.  Each
3138
expression is assembled into the next byte.
3139
 
3140

3141
File: as.info,  Node: CFI directives,  Next: Comm,  Prev: Byte,  Up: Pseudo Ops
3142
 
3143
7.9 `.cfi_startproc [simple]'
3144
=============================
3145
 
3146
`.cfi_startproc' is used at the beginning of each function that should
3147
have an entry in `.eh_frame'. It initializes some internal data
3148
structures. Don't forget to close the function by `.cfi_endproc'.
3149
 
3150
7.10 `.cfi_sections SECTION_LIST'
3151
=================================
3152
 
3153
`.cfi_sections' may be used to specify whether CFI directives should
3154
emit `.eh_frame' section and/or `.debug_frame' section.  If
3155
SECTION_LIST is `.eh_frame', `.eh_frame' is emitted, if SECTION_LIST is
3156
`.debug_frame', `.debug_frame' is emitted.  To emit both use
3157
`.eh_frame, .debug_frame'.  The default if this directive is not used
3158
is `.cfi_sections .eh_frame'.
3159
 
3160
   Unless `.cfi_startproc' is used along with parameter `simple' it
3161
also emits some architecture dependent initial CFI instructions.
3162
 
3163
7.11 `.cfi_endproc'
3164
===================
3165
 
3166
`.cfi_endproc' is used at the end of a function where it closes its
3167
unwind entry previously opened by `.cfi_startproc', and emits it to
3168
`.eh_frame'.
3169
 
3170
7.12 `.cfi_personality ENCODING [, EXP]'
3171
========================================
3172
 
3173
`.cfi_personality' defines personality routine and its encoding.
3174
ENCODING must be a constant determining how the personality should be
3175
encoded.  If it is 255 (`DW_EH_PE_omit'), second argument is not
3176
present, otherwise second argument should be a constant or a symbol
3177
name.  When using indirect encodings, the symbol provided should be the
3178
location where personality can be loaded from, not the personality
3179
routine itself.  The default after `.cfi_startproc' is
3180
`.cfi_personality 0xff', no personality routine.
3181
 
3182
7.13 `.cfi_lsda ENCODING [, EXP]'
3183
=================================
3184
 
3185
`.cfi_lsda' defines LSDA and its encoding.  ENCODING must be a constant
3186
determining how the LSDA should be encoded.  If it is 255
3187
(`DW_EH_PE_omit'), second argument is not present, otherwise second
3188
argument should be a constant or a symbol name.  The default after
3189
`.cfi_startproc' is `.cfi_lsda 0xff', no LSDA.
3190
 
3191
7.14 `.cfi_def_cfa REGISTER, OFFSET'
3192
====================================
3193
 
3194
`.cfi_def_cfa' defines a rule for computing CFA as: take address from
3195
REGISTER and add OFFSET to it.
3196
 
3197
7.15 `.cfi_def_cfa_register REGISTER'
3198
=====================================
3199
 
3200
`.cfi_def_cfa_register' modifies a rule for computing CFA. From now on
3201
REGISTER will be used instead of the old one. Offset remains the same.
3202
 
3203
7.16 `.cfi_def_cfa_offset OFFSET'
3204
=================================
3205
 
3206
`.cfi_def_cfa_offset' modifies a rule for computing CFA. Register
3207
remains the same, but OFFSET is new. Note that it is the absolute
3208
offset that will be added to a defined register to compute CFA address.
3209
 
3210
7.17 `.cfi_adjust_cfa_offset OFFSET'
3211
====================================
3212
 
3213
Same as `.cfi_def_cfa_offset' but OFFSET is a relative value that is
3214
added/substracted from the previous offset.
3215
 
3216
7.18 `.cfi_offset REGISTER, OFFSET'
3217
===================================
3218
 
3219
Previous value of REGISTER is saved at offset OFFSET from CFA.
3220
 
3221
7.19 `.cfi_rel_offset REGISTER, OFFSET'
3222
=======================================
3223
 
3224
Previous value of REGISTER is saved at offset OFFSET from the current
3225
CFA register.  This is transformed to `.cfi_offset' using the known
3226
displacement of the CFA register from the CFA.  This is often easier to
3227
use, because the number will match the code it's annotating.
3228
 
3229
7.20 `.cfi_register REGISTER1, REGISTER2'
3230
=========================================
3231
 
3232
Previous value of REGISTER1 is saved in register REGISTER2.
3233
 
3234
7.21 `.cfi_restore REGISTER'
3235
============================
3236
 
3237
`.cfi_restore' says that the rule for REGISTER is now the same as it
3238
was at the beginning of the function, after all initial instruction
3239
added by `.cfi_startproc' were executed.
3240
 
3241
7.22 `.cfi_undefined REGISTER'
3242
==============================
3243
 
3244
From now on the previous value of REGISTER can't be restored anymore.
3245
 
3246
7.23 `.cfi_same_value REGISTER'
3247
===============================
3248
 
3249
Current value of REGISTER is the same like in the previous frame, i.e.
3250
no restoration needed.
3251
 
3252
7.24 `.cfi_remember_state',
3253
===========================
3254
 
3255
First save all current rules for all registers by `.cfi_remember_state',
3256
then totally screw them up by subsequent `.cfi_*' directives and when
3257
everything is hopelessly bad, use `.cfi_restore_state' to restore the
3258
previous saved state.
3259
 
3260
7.25 `.cfi_return_column REGISTER'
3261
==================================
3262
 
3263
Change return column REGISTER, i.e. the return address is either
3264
directly in REGISTER or can be accessed by rules for REGISTER.
3265
 
3266
7.26 `.cfi_signal_frame'
3267
========================
3268
 
3269
Mark current function as signal trampoline.
3270
 
3271
7.27 `.cfi_window_save'
3272
=======================
3273
 
3274
SPARC register window has been saved.
3275
 
3276
7.28 `.cfi_escape' EXPRESSION[, ...]
3277
====================================
3278
 
3279
Allows the user to add arbitrary bytes to the unwind info.  One might
3280
use this to add OS-specific CFI opcodes, or generic CFI opcodes that
3281
GAS does not yet support.
3282
 
3283
7.29 `.cfi_val_encoded_addr REGISTER, ENCODING, LABEL'
3284
======================================================
3285
 
3286
The current value of REGISTER is LABEL.  The value of LABEL will be
3287
encoded in the output file according to ENCODING; see the description
3288
of `.cfi_personality' for details on this encoding.
3289
 
3290
   The usefulness of equating a register to a fixed label is probably
3291
limited to the return address register.  Here, it can be useful to mark
3292
a code segment that has only one return address which is reached by a
3293
direct branch and no copy of the return address exists in memory or
3294
another register.
3295
 
3296

3297
File: as.info,  Node: Comm,  Next: Data,  Prev: CFI directives,  Up: Pseudo Ops
3298
 
3299
7.30 `.comm SYMBOL , LENGTH '
3300
=============================
3301
 
3302
`.comm' declares a common symbol named SYMBOL.  When linking, a common
3303
symbol in one object file may be merged with a defined or common symbol
3304
of the same name in another object file.  If `ld' does not see a
3305
definition for the symbol-just one or more common symbols-then it will
3306
allocate LENGTH bytes of uninitialized memory.  LENGTH must be an
3307
absolute expression.  If `ld' sees multiple common symbols with the
3308
same name, and they do not all have the same size, it will allocate
3309
space using the largest size.
3310
 
3311
   When using ELF or (as a GNU extension) PE, the `.comm' directive
3312
takes an optional third argument.  This is the desired alignment of the
3313
symbol, specified for ELF as a byte boundary (for example, an alignment
3314
of 16 means that the least significant 4 bits of the address should be
3315
zero), and for PE as a power of two (for example, an alignment of 5
3316
means aligned to a 32-byte boundary).  The alignment must be an
3317
absolute expression, and it must be a power of two.  If `ld' allocates
3318
uninitialized memory for the common symbol, it will use the alignment
3319
when placing the symbol.  If no alignment is specified, `as' will set
3320
the alignment to the largest power of two less than or equal to the
3321
size of the symbol, up to a maximum of 16 on ELF, or the default
3322
section alignment of 4 on PE(1).
3323
 
3324
   The syntax for `.comm' differs slightly on the HPPA.  The syntax is
3325
`SYMBOL .comm, LENGTH'; SYMBOL is optional.
3326
 
3327
   ---------- Footnotes ----------
3328
 
3329
   (1) This is not the same as the executable image file alignment
3330
controlled by `ld''s `--section-alignment' option; image file sections
3331
in PE are aligned to multiples of 4096, which is far too large an
3332
alignment for ordinary variables.  It is rather the default alignment
3333
for (non-debug) sections within object (`*.o') files, which are less
3334
strictly aligned.
3335
 
3336

3337
File: as.info,  Node: Data,  Next: Def,  Prev: Comm,  Up: Pseudo Ops
3338
 
3339
7.31 `.data SUBSECTION'
3340
=======================
3341
 
3342
`.data' tells `as' to assemble the following statements onto the end of
3343
the data subsection numbered SUBSECTION (which is an absolute
3344
expression).  If SUBSECTION is omitted, it defaults to zero.
3345
 
3346

3347
File: as.info,  Node: Def,  Next: Desc,  Prev: Data,  Up: Pseudo Ops
3348
 
3349
7.32 `.def NAME'
3350
================
3351
 
3352
Begin defining debugging information for a symbol NAME; the definition
3353
extends until the `.endef' directive is encountered.
3354
 
3355

3356
File: as.info,  Node: Desc,  Next: Dim,  Prev: Def,  Up: Pseudo Ops
3357
 
3358
7.33 `.desc SYMBOL, ABS-EXPRESSION'
3359
===================================
3360
 
3361
This directive sets the descriptor of the symbol (*note Symbol
3362
Attributes::) to the low 16 bits of an absolute expression.
3363
 
3364
   The `.desc' directive is not available when `as' is configured for
3365
COFF output; it is only for `a.out' or `b.out' object format.  For the
3366
sake of compatibility, `as' accepts it, but produces no output, when
3367
configured for COFF.
3368
 
3369

3370
File: as.info,  Node: Dim,  Next: Double,  Prev: Desc,  Up: Pseudo Ops
3371
 
3372
7.34 `.dim'
3373
===========
3374
 
3375
This directive is generated by compilers to include auxiliary debugging
3376
information in the symbol table.  It is only permitted inside
3377
`.def'/`.endef' pairs.
3378
 
3379

3380
File: as.info,  Node: Double,  Next: Eject,  Prev: Dim,  Up: Pseudo Ops
3381
 
3382
7.35 `.double FLONUMS'
3383
======================
3384
 
3385
`.double' expects zero or more flonums, separated by commas.  It
3386
assembles floating point numbers.  The exact kind of floating point
3387
numbers emitted depends on how `as' is configured.  *Note Machine
3388
Dependencies::.
3389
 
3390

3391
File: as.info,  Node: Eject,  Next: Else,  Prev: Double,  Up: Pseudo Ops
3392
 
3393
7.36 `.eject'
3394
=============
3395
 
3396
Force a page break at this point, when generating assembly listings.
3397
 
3398

3399
File: as.info,  Node: Else,  Next: Elseif,  Prev: Eject,  Up: Pseudo Ops
3400
 
3401
7.37 `.else'
3402
============
3403
 
3404
`.else' is part of the `as' support for conditional assembly; see *Note
3405
`.if': If.  It marks the beginning of a section of code to be assembled
3406
if the condition for the preceding `.if' was false.
3407
 
3408

3409
File: as.info,  Node: Elseif,  Next: End,  Prev: Else,  Up: Pseudo Ops
3410
 
3411
7.38 `.elseif'
3412
==============
3413
 
3414
`.elseif' is part of the `as' support for conditional assembly; see
3415
*Note `.if': If.  It is shorthand for beginning a new `.if' block that
3416
would otherwise fill the entire `.else' section.
3417
 
3418

3419
File: as.info,  Node: End,  Next: Endef,  Prev: Elseif,  Up: Pseudo Ops
3420
 
3421
7.39 `.end'
3422
===========
3423
 
3424
`.end' marks the end of the assembly file.  `as' does not process
3425
anything in the file past the `.end' directive.
3426
 
3427

3428
File: as.info,  Node: Endef,  Next: Endfunc,  Prev: End,  Up: Pseudo Ops
3429
 
3430
7.40 `.endef'
3431
=============
3432
 
3433
This directive flags the end of a symbol definition begun with `.def'.
3434
 
3435

3436
File: as.info,  Node: Endfunc,  Next: Endif,  Prev: Endef,  Up: Pseudo Ops
3437
 
3438
7.41 `.endfunc'
3439
===============
3440
 
3441
`.endfunc' marks the end of a function specified with `.func'.
3442
 
3443

3444
File: as.info,  Node: Endif,  Next: Equ,  Prev: Endfunc,  Up: Pseudo Ops
3445
 
3446
7.42 `.endif'
3447
=============
3448
 
3449
`.endif' is part of the `as' support for conditional assembly; it marks
3450
the end of a block of code that is only assembled conditionally.  *Note
3451
`.if': If.
3452
 
3453

3454
File: as.info,  Node: Equ,  Next: Equiv,  Prev: Endif,  Up: Pseudo Ops
3455
 
3456
7.43 `.equ SYMBOL, EXPRESSION'
3457
==============================
3458
 
3459
This directive sets the value of SYMBOL to EXPRESSION.  It is
3460
synonymous with `.set'; see *Note `.set': Set.
3461
 
3462
   The syntax for `equ' on the HPPA is `SYMBOL .equ EXPRESSION'.
3463
 
3464
   The syntax for `equ' on the Z80 is `SYMBOL equ EXPRESSION'.  On the
3465
Z80 it is an eror if SYMBOL is already defined, but the symbol is not
3466
protected from later redefinition.  Compare *Note Equiv::.
3467
 
3468

3469
File: as.info,  Node: Equiv,  Next: Eqv,  Prev: Equ,  Up: Pseudo Ops
3470
 
3471
7.44 `.equiv SYMBOL, EXPRESSION'
3472
================================
3473
 
3474
The `.equiv' directive is like `.equ' and `.set', except that the
3475
assembler will signal an error if SYMBOL is already defined.  Note a
3476
symbol which has been referenced but not actually defined is considered
3477
to be undefined.
3478
 
3479
   Except for the contents of the error message, this is roughly
3480
equivalent to
3481
     .ifdef SYM
3482
     .err
3483
     .endif
3484
     .equ SYM,VAL
3485
   plus it protects the symbol from later redefinition.
3486
 
3487

3488
File: as.info,  Node: Eqv,  Next: Err,  Prev: Equiv,  Up: Pseudo Ops
3489
 
3490
7.45 `.eqv SYMBOL, EXPRESSION'
3491
==============================
3492
 
3493
The `.eqv' directive is like `.equiv', but no attempt is made to
3494
evaluate the expression or any part of it immediately.  Instead each
3495
time the resulting symbol is used in an expression, a snapshot of its
3496
current value is taken.
3497
 
3498

3499
File: as.info,  Node: Err,  Next: Error,  Prev: Eqv,  Up: Pseudo Ops
3500
 
3501
7.46 `.err'
3502
===========
3503
 
3504
If `as' assembles a `.err' directive, it will print an error message
3505
and, unless the `-Z' option was used, it will not generate an object
3506
file.  This can be used to signal an error in conditionally compiled
3507
code.
3508
 
3509

3510
File: as.info,  Node: Error,  Next: Exitm,  Prev: Err,  Up: Pseudo Ops
3511
 
3512
7.47 `.error "STRING"'
3513
======================
3514
 
3515
Similarly to `.err', this directive emits an error, but you can specify
3516
a string that will be emitted as the error message.  If you don't
3517
specify the message, it defaults to `".error directive invoked in
3518
source file"'.  *Note Error and Warning Messages: Errors.
3519
 
3520
      .error "This code has not been assembled and tested."
3521
 
3522

3523
File: as.info,  Node: Exitm,  Next: Extern,  Prev: Error,  Up: Pseudo Ops
3524
 
3525
7.48 `.exitm'
3526
=============
3527
 
3528
Exit early from the current macro definition.  *Note Macro::.
3529
 
3530

3531
File: as.info,  Node: Extern,  Next: Fail,  Prev: Exitm,  Up: Pseudo Ops
3532
 
3533
7.49 `.extern'
3534
==============
3535
 
3536
`.extern' is accepted in the source program--for compatibility with
3537
other assemblers--but it is ignored.  `as' treats all undefined symbols
3538
as external.
3539
 
3540

3541
File: as.info,  Node: Fail,  Next: File,  Prev: Extern,  Up: Pseudo Ops
3542
 
3543
7.50 `.fail EXPRESSION'
3544
=======================
3545
 
3546
Generates an error or a warning.  If the value of the EXPRESSION is 500
3547
or more, `as' will print a warning message.  If the value is less than
3548
500, `as' will print an error message.  The message will include the
3549
value of EXPRESSION.  This can occasionally be useful inside complex
3550
nested macros or conditional assembly.
3551
 
3552

3553
File: as.info,  Node: File,  Next: Fill,  Prev: Fail,  Up: Pseudo Ops
3554
 
3555
7.51 `.file'
3556
============
3557
 
3558
There are two different versions of the `.file' directive.  Targets
3559
that support DWARF2 line number information use the DWARF2 version of
3560
`.file'.  Other targets use the default version.
3561
 
3562
Default Version
3563
---------------
3564
 
3565
This version of the `.file' directive tells `as' that we are about to
3566
start a new logical file.  The syntax is:
3567
 
3568
     .file STRING
3569
 
3570
   STRING is the new file name.  In general, the filename is recognized
3571
whether or not it is surrounded by quotes `"'; but if you wish to
3572
specify an empty file name, you must give the quotes-`""'.  This
3573
statement may go away in future: it is only recognized to be compatible
3574
with old `as' programs.
3575
 
3576
DWARF2 Version
3577
--------------
3578
 
3579
When emitting DWARF2 line number information, `.file' assigns filenames
3580
to the `.debug_line' file name table.  The syntax is:
3581
 
3582
     .file FILENO FILENAME
3583
 
3584
   The FILENO operand should be a unique positive integer to use as the
3585
index of the entry in the table.  The FILENAME operand is a C string
3586
literal.
3587
 
3588
   The detail of filename indices is exposed to the user because the
3589
filename table is shared with the `.debug_info' section of the DWARF2
3590
debugging information, and thus the user must know the exact indices
3591
that table entries will have.
3592
 
3593

3594
File: as.info,  Node: Fill,  Next: Float,  Prev: File,  Up: Pseudo Ops
3595
 
3596
7.52 `.fill REPEAT , SIZE , VALUE'
3597
==================================
3598
 
3599
REPEAT, SIZE and VALUE are absolute expressions.  This emits REPEAT
3600
copies of SIZE bytes.  REPEAT may be zero or more.  SIZE may be zero or
3601
more, but if it is more than 8, then it is deemed to have the value 8,
3602
compatible with other people's assemblers.  The contents of each REPEAT
3603
bytes is taken from an 8-byte number.  The highest order 4 bytes are
3604
zero.  The lowest order 4 bytes are VALUE rendered in the byte-order of
3605
an integer on the computer `as' is assembling for.  Each SIZE bytes in
3606
a repetition is taken from the lowest order SIZE bytes of this number.
3607
Again, this bizarre behavior is compatible with other people's
3608
assemblers.
3609
 
3610
   SIZE and VALUE are optional.  If the second comma and VALUE are
3611
absent, VALUE is assumed zero.  If the first comma and following tokens
3612
are absent, SIZE is assumed to be 1.
3613
 
3614

3615
File: as.info,  Node: Float,  Next: Func,  Prev: Fill,  Up: Pseudo Ops
3616
 
3617
7.53 `.float FLONUMS'
3618
=====================
3619
 
3620
This directive assembles zero or more flonums, separated by commas.  It
3621
has the same effect as `.single'.  The exact kind of floating point
3622
numbers emitted depends on how `as' is configured.  *Note Machine
3623
Dependencies::.
3624
 
3625

3626
File: as.info,  Node: Func,  Next: Global,  Prev: Float,  Up: Pseudo Ops
3627
 
3628
7.54 `.func NAME[,LABEL]'
3629
=========================
3630
 
3631
`.func' emits debugging information to denote function NAME, and is
3632
ignored unless the file is assembled with debugging enabled.  Only
3633
`--gstabs[+]' is currently supported.  LABEL is the entry point of the
3634
function and if omitted NAME prepended with the `leading char' is used.
3635
`leading char' is usually `_' or nothing, depending on the target.  All
3636
functions are currently defined to have `void' return type.  The
3637
function must be terminated with `.endfunc'.
3638
 
3639

3640
File: as.info,  Node: Global,  Next: Gnu_attribute,  Prev: Func,  Up: Pseudo Ops
3641
 
3642
7.55 `.global SYMBOL', `.globl SYMBOL'
3643
======================================
3644
 
3645
`.global' makes the symbol visible to `ld'.  If you define SYMBOL in
3646
your partial program, its value is made available to other partial
3647
programs that are linked with it.  Otherwise, SYMBOL takes its
3648
attributes from a symbol of the same name from another file linked into
3649
the same program.
3650
 
3651
   Both spellings (`.globl' and `.global') are accepted, for
3652
compatibility with other assemblers.
3653
 
3654
   On the HPPA, `.global' is not always enough to make it accessible to
3655
other partial programs.  You may need the HPPA-only `.EXPORT' directive
3656
as well.  *Note HPPA Assembler Directives: HPPA Directives.
3657
 
3658

3659
File: as.info,  Node: Gnu_attribute,  Next: Hidden,  Prev: Global,  Up: Pseudo Ops
3660
 
3661
7.56 `.gnu_attribute TAG,VALUE'
3662
===============================
3663
 
3664
Record a GNU object attribute for this file.  *Note Object Attributes::.
3665
 
3666

3667
File: as.info,  Node: Hidden,  Next: hword,  Prev: Gnu_attribute,  Up: Pseudo Ops
3668
 
3669
7.57 `.hidden NAMES'
3670
====================
3671
 
3672
This is one of the ELF visibility directives.  The other two are
3673
`.internal' (*note `.internal': Internal.) and `.protected' (*note
3674
`.protected': Protected.).
3675
 
3676
   This directive overrides the named symbols default visibility (which
3677
is set by their binding: local, global or weak).  The directive sets
3678
the visibility to `hidden' which means that the symbols are not visible
3679
to other components.  Such symbols are always considered to be
3680
`protected' as well.
3681
 
3682

3683
File: as.info,  Node: hword,  Next: Ident,  Prev: Hidden,  Up: Pseudo Ops
3684
 
3685
7.58 `.hword EXPRESSIONS'
3686
=========================
3687
 
3688
This expects zero or more EXPRESSIONS, and emits a 16 bit number for
3689
each.
3690
 
3691
   This directive is a synonym for `.short'; depending on the target
3692
architecture, it may also be a synonym for `.word'.
3693
 
3694

3695
File: as.info,  Node: Ident,  Next: If,  Prev: hword,  Up: Pseudo Ops
3696
 
3697
7.59 `.ident'
3698
=============
3699
 
3700
This directive is used by some assemblers to place tags in object
3701
files.  The behavior of this directive varies depending on the target.
3702
When using the a.out object file format, `as' simply accepts the
3703
directive for source-file compatibility with existing assemblers, but
3704
does not emit anything for it.  When using COFF, comments are emitted
3705
to the `.comment' or `.rdata' section, depending on the target.  When
3706
using ELF, comments are emitted to the `.comment' section.
3707
 
3708

3709
File: as.info,  Node: If,  Next: Incbin,  Prev: Ident,  Up: Pseudo Ops
3710
 
3711
7.60 `.if ABSOLUTE EXPRESSION'
3712
==============================
3713
 
3714
`.if' marks the beginning of a section of code which is only considered
3715
part of the source program being assembled if the argument (which must
3716
be an ABSOLUTE EXPRESSION) is non-zero.  The end of the conditional
3717
section of code must be marked by `.endif' (*note `.endif': Endif.);
3718
optionally, you may include code for the alternative condition, flagged
3719
by `.else' (*note `.else': Else.).  If you have several conditions to
3720
check, `.elseif' may be used to avoid nesting blocks if/else within
3721
each subsequent `.else' block.
3722
 
3723
   The following variants of `.if' are also supported:
3724
`.ifdef SYMBOL'
3725
     Assembles the following section of code if the specified SYMBOL
3726
     has been defined.  Note a symbol which has been referenced but not
3727
     yet defined is considered to be undefined.
3728
 
3729
`.ifb TEXT'
3730
     Assembles the following section of code if the operand is blank
3731
     (empty).
3732
 
3733
`.ifc STRING1,STRING2'
3734
     Assembles the following section of code if the two strings are the
3735
     same.  The strings may be optionally quoted with single quotes.
3736
     If they are not quoted, the first string stops at the first comma,
3737
     and the second string stops at the end of the line.  Strings which
3738
     contain whitespace should be quoted.  The string comparison is
3739
     case sensitive.
3740
 
3741
`.ifeq ABSOLUTE EXPRESSION'
3742
     Assembles the following section of code if the argument is zero.
3743
 
3744
`.ifeqs STRING1,STRING2'
3745
     Another form of `.ifc'.  The strings must be quoted using double
3746
     quotes.
3747
 
3748
`.ifge ABSOLUTE EXPRESSION'
3749
     Assembles the following section of code if the argument is greater
3750
     than or equal to zero.
3751
 
3752
`.ifgt ABSOLUTE EXPRESSION'
3753
     Assembles the following section of code if the argument is greater
3754
     than zero.
3755
 
3756
`.ifle ABSOLUTE EXPRESSION'
3757
     Assembles the following section of code if the argument is less
3758
     than or equal to zero.
3759
 
3760
`.iflt ABSOLUTE EXPRESSION'
3761
     Assembles the following section of code if the argument is less
3762
     than zero.
3763
 
3764
`.ifnb TEXT'
3765
     Like `.ifb', but the sense of the test is reversed: this assembles
3766
     the following section of code if the operand is non-blank
3767
     (non-empty).
3768
 
3769
`.ifnc STRING1,STRING2.'
3770
     Like `.ifc', but the sense of the test is reversed: this assembles
3771
     the following section of code if the two strings are not the same.
3772
 
3773
`.ifndef SYMBOL'
3774
`.ifnotdef SYMBOL'
3775
     Assembles the following section of code if the specified SYMBOL
3776
     has not been defined.  Both spelling variants are equivalent.
3777
     Note a symbol which has been referenced but not yet defined is
3778
     considered to be undefined.
3779
 
3780
`.ifne ABSOLUTE EXPRESSION'
3781
     Assembles the following section of code if the argument is not
3782
     equal to zero (in other words, this is equivalent to `.if').
3783
 
3784
`.ifnes STRING1,STRING2'
3785
     Like `.ifeqs', but the sense of the test is reversed: this
3786
     assembles the following section of code if the two strings are not
3787
     the same.
3788
 
3789

3790
File: as.info,  Node: Incbin,  Next: Include,  Prev: If,  Up: Pseudo Ops
3791
 
3792
7.61 `.incbin "FILE"[,SKIP[,COUNT]]'
3793
====================================
3794
 
3795
The `incbin' directive includes FILE verbatim at the current location.
3796
You can control the search paths used with the `-I' command-line option
3797
(*note Command-Line Options: Invoking.).  Quotation marks are required
3798
around FILE.
3799
 
3800
   The SKIP argument skips a number of bytes from the start of the
3801
FILE.  The COUNT argument indicates the maximum number of bytes to
3802
read.  Note that the data is not aligned in any way, so it is the user's
3803
responsibility to make sure that proper alignment is provided both
3804
before and after the `incbin' directive.
3805
 
3806

3807
File: as.info,  Node: Include,  Next: Int,  Prev: Incbin,  Up: Pseudo Ops
3808
 
3809
7.62 `.include "FILE"'
3810
======================
3811
 
3812
This directive provides a way to include supporting files at specified
3813
points in your source program.  The code from FILE is assembled as if
3814
it followed the point of the `.include'; when the end of the included
3815
file is reached, assembly of the original file continues.  You can
3816
control the search paths used with the `-I' command-line option (*note
3817
Command-Line Options: Invoking.).  Quotation marks are required around
3818
FILE.
3819
 
3820

3821
File: as.info,  Node: Int,  Next: Internal,  Prev: Include,  Up: Pseudo Ops
3822
 
3823
7.63 `.int EXPRESSIONS'
3824
=======================
3825
 
3826
Expect zero or more EXPRESSIONS, of any section, separated by commas.
3827
For each expression, emit a number that, at run time, is the value of
3828
that expression.  The byte order and bit size of the number depends on
3829
what kind of target the assembly is for.
3830
 
3831

3832
File: as.info,  Node: Internal,  Next: Irp,  Prev: Int,  Up: Pseudo Ops
3833
 
3834
7.64 `.internal NAMES'
3835
======================
3836
 
3837
This is one of the ELF visibility directives.  The other two are
3838
`.hidden' (*note `.hidden': Hidden.) and `.protected' (*note
3839
`.protected': Protected.).
3840
 
3841
   This directive overrides the named symbols default visibility (which
3842
is set by their binding: local, global or weak).  The directive sets
3843
the visibility to `internal' which means that the symbols are
3844
considered to be `hidden' (i.e., not visible to other components), and
3845
that some extra, processor specific processing must also be performed
3846
upon the  symbols as well.
3847
 
3848

3849
File: as.info,  Node: Irp,  Next: Irpc,  Prev: Internal,  Up: Pseudo Ops
3850
 
3851
7.65 `.irp SYMBOL,VALUES'...
3852
============================
3853
 
3854
Evaluate a sequence of statements assigning different values to SYMBOL.
3855
The sequence of statements starts at the `.irp' directive, and is
3856
terminated by an `.endr' directive.  For each VALUE, SYMBOL is set to
3857
VALUE, and the sequence of statements is assembled.  If no VALUE is
3858
listed, the sequence of statements is assembled once, with SYMBOL set
3859
to the null string.  To refer to SYMBOL within the sequence of
3860
statements, use \SYMBOL.
3861
 
3862
   For example, assembling
3863
 
3864
             .irp    param,1,2,3
3865
             move    d\param,sp@-
3866
             .endr
3867
 
3868
   is equivalent to assembling
3869
 
3870
             move    d1,sp@-
3871
             move    d2,sp@-
3872
             move    d3,sp@-
3873
 
3874
   For some caveats with the spelling of SYMBOL, see also *Note Macro::.
3875
 
3876

3877
File: as.info,  Node: Irpc,  Next: Lcomm,  Prev: Irp,  Up: Pseudo Ops
3878
 
3879
7.66 `.irpc SYMBOL,VALUES'...
3880
=============================
3881
 
3882
Evaluate a sequence of statements assigning different values to SYMBOL.
3883
The sequence of statements starts at the `.irpc' directive, and is
3884
terminated by an `.endr' directive.  For each character in VALUE,
3885
SYMBOL is set to the character, and the sequence of statements is
3886
assembled.  If no VALUE is listed, the sequence of statements is
3887
assembled once, with SYMBOL set to the null string.  To refer to SYMBOL
3888
within the sequence of statements, use \SYMBOL.
3889
 
3890
   For example, assembling
3891
 
3892
             .irpc    param,123
3893
             move    d\param,sp@-
3894
             .endr
3895
 
3896
   is equivalent to assembling
3897
 
3898
             move    d1,sp@-
3899
             move    d2,sp@-
3900
             move    d3,sp@-
3901
 
3902
   For some caveats with the spelling of SYMBOL, see also the discussion
3903
at *Note Macro::.
3904
 
3905

3906
File: as.info,  Node: Lcomm,  Next: Lflags,  Prev: Irpc,  Up: Pseudo Ops
3907
 
3908
7.67 `.lcomm SYMBOL , LENGTH'
3909
=============================
3910
 
3911
Reserve LENGTH (an absolute expression) bytes for a local common
3912
denoted by SYMBOL.  The section and value of SYMBOL are those of the
3913
new local common.  The addresses are allocated in the bss section, so
3914
that at run-time the bytes start off zeroed.  SYMBOL is not declared
3915
global (*note `.global': Global.), so is normally not visible to `ld'.
3916
 
3917
   Some targets permit a third argument to be used with `.lcomm'.  This
3918
argument specifies the desired alignment of the symbol in the bss
3919
section.
3920
 
3921
   The syntax for `.lcomm' differs slightly on the HPPA.  The syntax is
3922
`SYMBOL .lcomm, LENGTH'; SYMBOL is optional.
3923
 
3924

3925
File: as.info,  Node: Lflags,  Next: Line,  Prev: Lcomm,  Up: Pseudo Ops
3926
 
3927
7.68 `.lflags'
3928
==============
3929
 
3930
`as' accepts this directive, for compatibility with other assemblers,
3931
but ignores it.
3932
 
3933

3934
File: as.info,  Node: Line,  Next: Linkonce,  Prev: Lflags,  Up: Pseudo Ops
3935
 
3936
7.69 `.line LINE-NUMBER'
3937
========================
3938
 
3939
Change the logical line number.  LINE-NUMBER must be an absolute
3940
expression.  The next line has that logical line number.  Therefore any
3941
other statements on the current line (after a statement separator
3942
character) are reported as on logical line number LINE-NUMBER - 1.  One
3943
day `as' will no longer support this directive: it is recognized only
3944
for compatibility with existing assembler programs.
3945
 
3946
Even though this is a directive associated with the `a.out' or `b.out'
3947
object-code formats, `as' still recognizes it when producing COFF
3948
output, and treats `.line' as though it were the COFF `.ln' _if_ it is
3949
found outside a `.def'/`.endef' pair.
3950
 
3951
   Inside a `.def', `.line' is, instead, one of the directives used by
3952
compilers to generate auxiliary symbol information for debugging.
3953
 
3954

3955
File: as.info,  Node: Linkonce,  Next: List,  Prev: Line,  Up: Pseudo Ops
3956
 
3957
7.70 `.linkonce [TYPE]'
3958
=======================
3959
 
3960
Mark the current section so that the linker only includes a single copy
3961
of it.  This may be used to include the same section in several
3962
different object files, but ensure that the linker will only include it
3963
once in the final output file.  The `.linkonce' pseudo-op must be used
3964
for each instance of the section.  Duplicate sections are detected
3965
based on the section name, so it should be unique.
3966
 
3967
   This directive is only supported by a few object file formats; as of
3968
this writing, the only object file format which supports it is the
3969
Portable Executable format used on Windows NT.
3970
 
3971
   The TYPE argument is optional.  If specified, it must be one of the
3972
following strings.  For example:
3973
     .linkonce same_size
3974
   Not all types may be supported on all object file formats.
3975
 
3976
`discard'
3977
     Silently discard duplicate sections.  This is the default.
3978
 
3979
`one_only'
3980
     Warn if there are duplicate sections, but still keep only one copy.
3981
 
3982
`same_size'
3983
     Warn if any of the duplicates have different sizes.
3984
 
3985
`same_contents'
3986
     Warn if any of the duplicates do not have exactly the same
3987
     contents.
3988
 
3989

3990
File: as.info,  Node: List,  Next: Ln,  Prev: Linkonce,  Up: Pseudo Ops
3991
 
3992
7.71 `.list'
3993
============
3994
 
3995
Control (in conjunction with the `.nolist' directive) whether or not
3996
assembly listings are generated.  These two directives maintain an
3997
internal counter (which is zero initially).   `.list' increments the
3998
counter, and `.nolist' decrements it.  Assembly listings are generated
3999
whenever the counter is greater than zero.
4000
 
4001
   By default, listings are disabled.  When you enable them (with the
4002
`-a' command line option; *note Command-Line Options: Invoking.), the
4003
initial value of the listing counter is one.
4004
 
4005

4006
File: as.info,  Node: Ln,  Next: Loc,  Prev: List,  Up: Pseudo Ops
4007
 
4008
7.72 `.ln LINE-NUMBER'
4009
======================
4010
 
4011
`.ln' is a synonym for `.line'.
4012
 
4013

4014
File: as.info,  Node: Loc,  Next: Loc_mark_labels,  Prev: Ln,  Up: Pseudo Ops
4015
 
4016
7.73 `.loc FILENO LINENO [COLUMN] [OPTIONS]'
4017
============================================
4018
 
4019
When emitting DWARF2 line number information, the `.loc' directive will
4020
add a row to the `.debug_line' line number matrix corresponding to the
4021
immediately following assembly instruction.  The FILENO, LINENO, and
4022
optional COLUMN arguments will be applied to the `.debug_line' state
4023
machine before the row is added.
4024
 
4025
   The OPTIONS are a sequence of the following tokens in any order:
4026
 
4027
`basic_block'
4028
     This option will set the `basic_block' register in the
4029
     `.debug_line' state machine to `true'.
4030
 
4031
`prologue_end'
4032
     This option will set the `prologue_end' register in the
4033
     `.debug_line' state machine to `true'.
4034
 
4035
`epilogue_begin'
4036
     This option will set the `epilogue_begin' register in the
4037
     `.debug_line' state machine to `true'.
4038
 
4039
`is_stmt VALUE'
4040
     This option will set the `is_stmt' register in the `.debug_line'
4041
     state machine to `value', which must be either 0 or 1.
4042
 
4043
`isa VALUE'
4044
     This directive will set the `isa' register in the `.debug_line'
4045
     state machine to VALUE, which must be an unsigned integer.
4046
 
4047
`discriminator VALUE'
4048
     This directive will set the `discriminator' register in the
4049
     `.debug_line' state machine to VALUE, which must be an unsigned
4050
     integer.
4051
 
4052
 
4053

4054
File: as.info,  Node: Loc_mark_labels,  Next: Local,  Prev: Loc,  Up: Pseudo Ops
4055
 
4056
7.74 `.loc_mark_labels ENABLE'
4057
==============================
4058
 
4059
When emitting DWARF2 line number information, the `.loc_mark_labels'
4060
directive makes the assembler emit an entry to the `.debug_line' line
4061
number matrix with the `basic_block' register in the state machine set
4062
whenever a code label is seen.  The ENABLE argument should be either 1
4063
or 0, to enable or disable this function respectively.
4064
 
4065

4066
File: as.info,  Node: Local,  Next: Long,  Prev: Loc_mark_labels,  Up: Pseudo Ops
4067
 
4068
7.75 `.local NAMES'
4069
===================
4070
 
4071
This directive, which is available for ELF targets, marks each symbol in
4072
the comma-separated list of `names' as a local symbol so that it will
4073
not be externally visible.  If the symbols do not already exist, they
4074
will be created.
4075
 
4076
   For targets where the `.lcomm' directive (*note Lcomm::) does not
4077
accept an alignment argument, which is the case for most ELF targets,
4078
the `.local' directive can be used in combination with `.comm' (*note
4079
Comm::) to define aligned local common data.
4080
 
4081

4082
File: as.info,  Node: Long,  Next: Macro,  Prev: Local,  Up: Pseudo Ops
4083
 
4084
7.76 `.long EXPRESSIONS'
4085
========================
4086
 
4087
`.long' is the same as `.int'.  *Note `.int': Int.
4088
 
4089

4090
File: as.info,  Node: Macro,  Next: MRI,  Prev: Long,  Up: Pseudo Ops
4091
 
4092
7.77 `.macro'
4093
=============
4094
 
4095
The commands `.macro' and `.endm' allow you to define macros that
4096
generate assembly output.  For example, this definition specifies a
4097
macro `sum' that puts a sequence of numbers into memory:
4098
 
4099
             .macro  sum from=0, to=5
4100
             .long   \from
4101
             .if     \to-\from
4102
             sum     "(\from+1)",\to
4103
             .endif
4104
             .endm
4105
 
4106
With that definition, `SUM 0,5' is equivalent to this assembly input:
4107
 
4108
             .long   0
4109
             .long   1
4110
             .long   2
4111
             .long   3
4112
             .long   4
4113
             .long   5
4114
 
4115
`.macro MACNAME'
4116
`.macro MACNAME MACARGS ...'
4117
     Begin the definition of a macro called MACNAME.  If your macro
4118
     definition requires arguments, specify their names after the macro
4119
     name, separated by commas or spaces.  You can qualify the macro
4120
     argument to indicate whether all invocations must specify a
4121
     non-blank value (through `:`req''), or whether it takes all of the
4122
     remaining arguments (through `:`vararg'').  You can supply a
4123
     default value for any macro argument by following the name with
4124
     `=DEFLT'.  You cannot define two macros with the same MACNAME
4125
     unless it has been subject to the `.purgem' directive (*note
4126
     Purgem::) between the two definitions.  For example, these are all
4127
     valid `.macro' statements:
4128
 
4129
    `.macro comm'
4130
          Begin the definition of a macro called `comm', which takes no
4131
          arguments.
4132
 
4133
    `.macro plus1 p, p1'
4134
    `.macro plus1 p p1'
4135
          Either statement begins the definition of a macro called
4136
          `plus1', which takes two arguments; within the macro
4137
          definition, write `\p' or `\p1' to evaluate the arguments.
4138
 
4139
    `.macro reserve_str p1=0 p2'
4140
          Begin the definition of a macro called `reserve_str', with two
4141
          arguments.  The first argument has a default value, but not
4142
          the second.  After the definition is complete, you can call
4143
          the macro either as `reserve_str A,B' (with `\p1' evaluating
4144
          to A and `\p2' evaluating to B), or as `reserve_str ,B' (with
4145
          `\p1' evaluating as the default, in this case `0', and `\p2'
4146
          evaluating to B).
4147
 
4148
    `.macro m p1:req, p2=0, p3:vararg'
4149
          Begin the definition of a macro called `m', with at least
4150
          three arguments.  The first argument must always have a value
4151
          specified, but not the second, which instead has a default
4152
          value. The third formal will get assigned all remaining
4153
          arguments specified at invocation time.
4154
 
4155
          When you call a macro, you can specify the argument values
4156
          either by position, or by keyword.  For example, `sum 9,17'
4157
          is equivalent to `sum to=17, from=9'.
4158
 
4159
 
4160
     Note that since each of the MACARGS can be an identifier exactly
4161
     as any other one permitted by the target architecture, there may be
4162
     occasional problems if the target hand-crafts special meanings to
4163
     certain characters when they occur in a special position.  For
4164
     example, if the colon (`:') is generally permitted to be part of a
4165
     symbol name, but the architecture specific code special-cases it
4166
     when occurring as the final character of a symbol (to denote a
4167
     label), then the macro parameter replacement code will have no way
4168
     of knowing that and consider the whole construct (including the
4169
     colon) an identifier, and check only this identifier for being the
4170
     subject to parameter substitution.  So for example this macro
4171
     definition:
4172
 
4173
                .macro label l
4174
          \l:
4175
                .endm
4176
 
4177
     might not work as expected.  Invoking `label foo' might not create
4178
     a label called `foo' but instead just insert the text `\l:' into
4179
     the assembler source, probably generating an error about an
4180
     unrecognised identifier.
4181
 
4182
     Similarly problems might occur with the period character (`.')
4183
     which is often allowed inside opcode names (and hence identifier
4184
     names).  So for example constructing a macro to build an opcode
4185
     from a base name and a length specifier like this:
4186
 
4187
                .macro opcode base length
4188
                  \base.\length
4189
                .endm
4190
 
4191
     and invoking it as `opcode store l' will not create a `store.l'
4192
     instruction but instead generate some kind of error as the
4193
     assembler tries to interpret the text `\base.\length'.
4194
 
4195
     There are several possible ways around this problem:
4196
 
4197
    `Insert white space'
4198
          If it is possible to use white space characters then this is
4199
          the simplest solution.  eg:
4200
 
4201
                .macro label l
4202
               \l :
4203
                .endm
4204
 
4205
    `Use `\()''
4206
          The string `\()' can be used to separate the end of a macro
4207
          argument from the following text.  eg:
4208
 
4209
                .macro opcode base length
4210
                       \base\().\length
4211
                .endm
4212
 
4213
    `Use the alternate macro syntax mode'
4214
          In the alternative macro syntax mode the ampersand character
4215
          (`&') can be used as a separator.  eg:
4216
 
4217
                .altmacro
4218
                .macro label l
4219
               l&:
4220
                .endm
4221
 
4222
     Note: this problem of correctly identifying string parameters to
4223
     pseudo ops also applies to the identifiers used in `.irp' (*note
4224
     Irp::) and `.irpc' (*note Irpc::) as well.
4225
 
4226
`.endm'
4227
     Mark the end of a macro definition.
4228
 
4229
`.exitm'
4230
     Exit early from the current macro definition.
4231
 
4232
`\@'
4233
     `as' maintains a counter of how many macros it has executed in
4234
     this pseudo-variable; you can copy that number to your output with
4235
     `\@', but _only within a macro definition_.
4236
 
4237
`LOCAL NAME [ , ... ]'
4238
     _Warning: `LOCAL' is only available if you select "alternate macro
4239
     syntax" with `--alternate' or `.altmacro'._ *Note `.altmacro':
4240
     Altmacro.
4241
 
4242

4243
File: as.info,  Node: MRI,  Next: Noaltmacro,  Prev: Macro,  Up: Pseudo Ops
4244
 
4245
7.78 `.mri VAL'
4246
===============
4247
 
4248
If VAL is non-zero, this tells `as' to enter MRI mode.  If VAL is zero,
4249
this tells `as' to exit MRI mode.  This change affects code assembled
4250
until the next `.mri' directive, or until the end of the file.  *Note
4251
MRI mode: M.
4252
 
4253

4254
File: as.info,  Node: Noaltmacro,  Next: Nolist,  Prev: MRI,  Up: Pseudo Ops
4255
 
4256
7.79 `.noaltmacro'
4257
==================
4258
 
4259
Disable alternate macro mode.  *Note Altmacro::.
4260
 
4261

4262
File: as.info,  Node: Nolist,  Next: Octa,  Prev: Noaltmacro,  Up: Pseudo Ops
4263
 
4264
7.80 `.nolist'
4265
==============
4266
 
4267
Control (in conjunction with the `.list' directive) whether or not
4268
assembly listings are generated.  These two directives maintain an
4269
internal counter (which is zero initially).   `.list' increments the
4270
counter, and `.nolist' decrements it.  Assembly listings are generated
4271
whenever the counter is greater than zero.
4272
 
4273

4274
File: as.info,  Node: Octa,  Next: Org,  Prev: Nolist,  Up: Pseudo Ops
4275
 
4276
7.81 `.octa BIGNUMS'
4277
====================
4278
 
4279
This directive expects zero or more bignums, separated by commas.  For
4280
each bignum, it emits a 16-byte integer.
4281
 
4282
   The term "octa" comes from contexts in which a "word" is two bytes;
4283
hence _octa_-word for 16 bytes.
4284
 
4285

4286
File: as.info,  Node: Org,  Next: P2align,  Prev: Octa,  Up: Pseudo Ops
4287
 
4288
7.82 `.org NEW-LC , FILL'
4289
=========================
4290
 
4291
Advance the location counter of the current section to NEW-LC.  NEW-LC
4292
is either an absolute expression or an expression with the same section
4293
as the current subsection.  That is, you can't use `.org' to cross
4294
sections: if NEW-LC has the wrong section, the `.org' directive is
4295
ignored.  To be compatible with former assemblers, if the section of
4296
NEW-LC is absolute, `as' issues a warning, then pretends the section of
4297
NEW-LC is the same as the current subsection.
4298
 
4299
   `.org' may only increase the location counter, or leave it
4300
unchanged; you cannot use `.org' to move the location counter backwards.
4301
 
4302
   Because `as' tries to assemble programs in one pass, NEW-LC may not
4303
be undefined.  If you really detest this restriction we eagerly await a
4304
chance to share your improved assembler.
4305
 
4306
   Beware that the origin is relative to the start of the section, not
4307
to the start of the subsection.  This is compatible with other people's
4308
assemblers.
4309
 
4310
   When the location counter (of the current subsection) is advanced,
4311
the intervening bytes are filled with FILL which should be an absolute
4312
expression.  If the comma and FILL are omitted, FILL defaults to zero.
4313
 
4314

4315
File: as.info,  Node: P2align,  Next: PopSection,  Prev: Org,  Up: Pseudo Ops
4316
 
4317
7.83 `.p2align[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR'
4318
================================================
4319
 
4320
Pad the location counter (in the current subsection) to a particular
4321
storage boundary.  The first expression (which must be absolute) is the
4322
number of low-order zero bits the location counter must have after
4323
advancement.  For example `.p2align 3' advances the location counter
4324
until it a multiple of 8.  If the location counter is already a
4325
multiple of 8, no change is needed.
4326
 
4327
   The second expression (also absolute) gives the fill value to be
4328
stored in the padding bytes.  It (and the comma) may be omitted.  If it
4329
is omitted, the padding bytes are normally zero.  However, on some
4330
systems, if the section is marked as containing code and the fill value
4331
is omitted, the space is filled with no-op instructions.
4332
 
4333
   The third expression is also absolute, and is also optional.  If it
4334
is present, it is the maximum number of bytes that should be skipped by
4335
this alignment directive.  If doing the alignment would require
4336
skipping more bytes than the specified maximum, then the alignment is
4337
not done at all.  You can omit the fill value (the second argument)
4338
entirely by simply using two commas after the required alignment; this
4339
can be useful if you want the alignment to be filled with no-op
4340
instructions when appropriate.
4341
 
4342
   The `.p2alignw' and `.p2alignl' directives are variants of the
4343
`.p2align' directive.  The `.p2alignw' directive treats the fill
4344
pattern as a two byte word value.  The `.p2alignl' directives treats the
4345
fill pattern as a four byte longword value.  For example, `.p2alignw
4346
2,0x368d' will align to a multiple of 4.  If it skips two bytes, they
4347
will be filled in with the value 0x368d (the exact placement of the
4348
bytes depends upon the endianness of the processor).  If it skips 1 or
4349
3 bytes, the fill value is undefined.
4350
 
4351

4352
File: as.info,  Node: PopSection,  Next: Previous,  Prev: P2align,  Up: Pseudo Ops
4353
 
4354
7.84 `.popsection'
4355
==================
4356
 
4357
This is one of the ELF section stack manipulation directives.  The
4358
others are `.section' (*note Section::), `.subsection' (*note
4359
SubSection::), `.pushsection' (*note PushSection::), and `.previous'
4360
(*note Previous::).
4361
 
4362
   This directive replaces the current section (and subsection) with
4363
the top section (and subsection) on the section stack.  This section is
4364
popped off the stack.
4365
 
4366

4367
File: as.info,  Node: Previous,  Next: Print,  Prev: PopSection,  Up: Pseudo Ops
4368
 
4369
7.85 `.previous'
4370
================
4371
 
4372
This is one of the ELF section stack manipulation directives.  The
4373
others are `.section' (*note Section::), `.subsection' (*note
4374
SubSection::), `.pushsection' (*note PushSection::), and `.popsection'
4375
(*note PopSection::).
4376
 
4377
   This directive swaps the current section (and subsection) with most
4378
recently referenced section/subsection pair prior to this one.  Multiple
4379
`.previous' directives in a row will flip between two sections (and
4380
their subsections).  For example:
4381
 
4382
     .section A
4383
      .subsection 1
4384
       .word 0x1234
4385
      .subsection 2
4386
       .word 0x5678
4387
     .previous
4388
      .word 0x9abc
4389
 
4390
   Will place 0x1234 and 0x9abc into subsection 1 and 0x5678 into
4391
subsection 2 of section A.  Whilst:
4392
 
4393
     .section A
4394
     .subsection 1
4395
       # Now in section A subsection 1
4396
       .word 0x1234
4397
     .section B
4398
     .subsection 0
4399
       # Now in section B subsection 0
4400
       .word 0x5678
4401
     .subsection 1
4402
       # Now in section B subsection 1
4403
       .word 0x9abc
4404
     .previous
4405
       # Now in section B subsection 0
4406
       .word 0xdef0
4407
 
4408
   Will place 0x1234 into section A, 0x5678 and 0xdef0 into subsection
4409
 
4410
 
4411
   In terms of the section stack, this directive swaps the current
4412
section with the top section on the section stack.
4413
 
4414

4415
File: as.info,  Node: Print,  Next: Protected,  Prev: Previous,  Up: Pseudo Ops
4416
 
4417
7.86 `.print STRING'
4418
====================
4419
 
4420
`as' will print STRING on the standard output during assembly.  You
4421
must put STRING in double quotes.
4422
 
4423

4424
File: as.info,  Node: Protected,  Next: Psize,  Prev: Print,  Up: Pseudo Ops
4425
 
4426
7.87 `.protected NAMES'
4427
=======================
4428
 
4429
This is one of the ELF visibility directives.  The other two are
4430
`.hidden' (*note Hidden::) and `.internal' (*note Internal::).
4431
 
4432
   This directive overrides the named symbols default visibility (which
4433
is set by their binding: local, global or weak).  The directive sets
4434
the visibility to `protected' which means that any references to the
4435
symbols from within the components that defines them must be resolved
4436
to the definition in that component, even if a definition in another
4437
component would normally preempt this.
4438
 
4439

4440
File: as.info,  Node: Psize,  Next: Purgem,  Prev: Protected,  Up: Pseudo Ops
4441
 
4442
7.88 `.psize LINES , COLUMNS'
4443
=============================
4444
 
4445
Use this directive to declare the number of lines--and, optionally, the
4446
number of columns--to use for each page, when generating listings.
4447
 
4448
   If you do not use `.psize', listings use a default line-count of 60.
4449
You may omit the comma and COLUMNS specification; the default width is
4450
200 columns.
4451
 
4452
   `as' generates formfeeds whenever the specified number of lines is
4453
exceeded (or whenever you explicitly request one, using `.eject').
4454
 
4455
   If you specify LINES as `0', no formfeeds are generated save those
4456
explicitly specified with `.eject'.
4457
 
4458

4459
File: as.info,  Node: Purgem,  Next: PushSection,  Prev: Psize,  Up: Pseudo Ops
4460
 
4461
7.89 `.purgem NAME'
4462
===================
4463
 
4464
Undefine the macro NAME, so that later uses of the string will not be
4465
expanded.  *Note Macro::.
4466
 
4467

4468
File: as.info,  Node: PushSection,  Next: Quad,  Prev: Purgem,  Up: Pseudo Ops
4469
 
4470
7.90 `.pushsection NAME [, SUBSECTION] [, "FLAGS"[, @TYPE[,ARGUMENTS]]]'
4471
========================================================================
4472
 
4473
This is one of the ELF section stack manipulation directives.  The
4474
others are `.section' (*note Section::), `.subsection' (*note
4475
SubSection::), `.popsection' (*note PopSection::), and `.previous'
4476
(*note Previous::).
4477
 
4478
   This directive pushes the current section (and subsection) onto the
4479
top of the section stack, and then replaces the current section and
4480
subsection with `name' and `subsection'. The optional `flags', `type'
4481
and `arguments' are treated the same as in the `.section' (*note
4482
Section::) directive.
4483
 
4484

4485
File: as.info,  Node: Quad,  Next: Reloc,  Prev: PushSection,  Up: Pseudo Ops
4486
 
4487
7.91 `.quad BIGNUMS'
4488
====================
4489
 
4490
`.quad' expects zero or more bignums, separated by commas.  For each
4491
bignum, it emits an 8-byte integer.  If the bignum won't fit in 8
4492
bytes, it prints a warning message; and just takes the lowest order 8
4493
bytes of the bignum.
4494
 
4495
   The term "quad" comes from contexts in which a "word" is two bytes;
4496
hence _quad_-word for 8 bytes.
4497
 
4498

4499
File: as.info,  Node: Reloc,  Next: Rept,  Prev: Quad,  Up: Pseudo Ops
4500
 
4501
7.92 `.reloc OFFSET, RELOC_NAME[, EXPRESSION]'
4502
==============================================
4503
 
4504
Generate a relocation at OFFSET of type RELOC_NAME with value
4505
EXPRESSION.  If OFFSET is a number, the relocation is generated in the
4506
current section.  If OFFSET is an expression that resolves to a symbol
4507
plus offset, the relocation is generated in the given symbol's section.
4508
EXPRESSION, if present, must resolve to a symbol plus addend or to an
4509
absolute value, but note that not all targets support an addend.  e.g.
4510
ELF REL targets such as i386 store an addend in the section contents
4511
rather than in the relocation.  This low level interface does not
4512
support addends stored in the section.
4513
 
4514

4515
File: as.info,  Node: Rept,  Next: Sbttl,  Prev: Reloc,  Up: Pseudo Ops
4516
 
4517
7.93 `.rept COUNT'
4518
==================
4519
 
4520
Repeat the sequence of lines between the `.rept' directive and the next
4521
`.endr' directive COUNT times.
4522
 
4523
   For example, assembling
4524
 
4525
             .rept   3
4526
             .long   0
4527
             .endr
4528
 
4529
   is equivalent to assembling
4530
 
4531
             .long   0
4532
             .long   0
4533
             .long   0
4534
 
4535

4536
File: as.info,  Node: Sbttl,  Next: Scl,  Prev: Rept,  Up: Pseudo Ops
4537
 
4538
7.94 `.sbttl "SUBHEADING"'
4539
==========================
4540
 
4541
Use SUBHEADING as the title (third line, immediately after the title
4542
line) when generating assembly listings.
4543
 
4544
   This directive affects subsequent pages, as well as the current page
4545
if it appears within ten lines of the top of a page.
4546
 
4547

4548
File: as.info,  Node: Scl,  Next: Section,  Prev: Sbttl,  Up: Pseudo Ops
4549
 
4550
7.95 `.scl CLASS'
4551
=================
4552
 
4553
Set the storage-class value for a symbol.  This directive may only be
4554
used inside a `.def'/`.endef' pair.  Storage class may flag whether a
4555
symbol is static or external, or it may record further symbolic
4556
debugging information.
4557
 
4558

4559
File: as.info,  Node: Section,  Next: Set,  Prev: Scl,  Up: Pseudo Ops
4560
 
4561
7.96 `.section NAME'
4562
====================
4563
 
4564
Use the `.section' directive to assemble the following code into a
4565
section named NAME.
4566
 
4567
   This directive is only supported for targets that actually support
4568
arbitrarily named sections; on `a.out' targets, for example, it is not
4569
accepted, even with a standard `a.out' section name.
4570
 
4571
COFF Version
4572
------------
4573
 
4574
   For COFF targets, the `.section' directive is used in one of the
4575
following ways:
4576
 
4577
     .section NAME[, "FLAGS"]
4578
     .section NAME[, SUBSECTION]
4579
 
4580
   If the optional argument is quoted, it is taken as flags to use for
4581
the section.  Each flag is a single character.  The following flags are
4582
recognized:
4583
`b'
4584
     bss section (uninitialized data)
4585
 
4586
`n'
4587
     section is not loaded
4588
 
4589
`w'
4590
     writable section
4591
 
4592
`d'
4593
     data section
4594
 
4595
`r'
4596
     read-only section
4597
 
4598
`x'
4599
     executable section
4600
 
4601
`s'
4602
     shared section (meaningful for PE targets)
4603
 
4604
`a'
4605
     ignored.  (For compatibility with the ELF version)
4606
 
4607
`y'
4608
     section is not readable (meaningful for PE targets)
4609
 
4610
`0-9'
4611
     single-digit power-of-two section alignment (GNU extension)
4612
 
4613
   If no flags are specified, the default flags depend upon the section
4614
name.  If the section name is not recognized, the default will be for
4615
the section to be loaded and writable.  Note the `n' and `w' flags
4616
remove attributes from the section, rather than adding them, so if they
4617
are used on their own it will be as if no flags had been specified at
4618
all.
4619
 
4620
   If the optional argument to the `.section' directive is not quoted,
4621
it is taken as a subsection number (*note Sub-Sections::).
4622
 
4623
ELF Version
4624
-----------
4625
 
4626
   This is one of the ELF section stack manipulation directives.  The
4627
others are `.subsection' (*note SubSection::), `.pushsection' (*note
4628
PushSection::), `.popsection' (*note PopSection::), and `.previous'
4629
(*note Previous::).
4630
 
4631
   For ELF targets, the `.section' directive is used like this:
4632
 
4633
     .section NAME [, "FLAGS"[, @TYPE[,FLAG_SPECIFIC_ARGUMENTS]]]
4634
 
4635
   The optional FLAGS argument is a quoted string which may contain any
4636
combination of the following characters:
4637
`a'
4638
     section is allocatable
4639
 
4640
`w'
4641
     section is writable
4642
 
4643
`x'
4644
     section is executable
4645
 
4646
`M'
4647
     section is mergeable
4648
 
4649
`S'
4650
     section contains zero terminated strings
4651
 
4652
`G'
4653
     section is a member of a section group
4654
 
4655
`T'
4656
     section is used for thread-local-storage
4657
 
4658
   The optional TYPE argument may contain one of the following
4659
constants:
4660
`@progbits'
4661
     section contains data
4662
 
4663
`@nobits'
4664
     section does not contain data (i.e., section only occupies space)
4665
 
4666
`@note'
4667
     section contains data which is used by things other than the
4668
     program
4669
 
4670
`@init_array'
4671
     section contains an array of pointers to init functions
4672
 
4673
`@fini_array'
4674
     section contains an array of pointers to finish functions
4675
 
4676
`@preinit_array'
4677
     section contains an array of pointers to pre-init functions
4678
 
4679
   Many targets only support the first three section types.
4680
 
4681
   Note on targets where the `@' character is the start of a comment (eg
4682
ARM) then another character is used instead.  For example the ARM port
4683
uses the `%' character.
4684
 
4685
   If FLAGS contains the `M' symbol then the TYPE argument must be
4686
specified as well as an extra argument--ENTSIZE--like this:
4687
 
4688
     .section NAME , "FLAGS"M, @TYPE, ENTSIZE
4689
 
4690
   Sections with the `M' flag but not `S' flag must contain fixed size
4691
constants, each ENTSIZE octets long. Sections with both `M' and `S'
4692
must contain zero terminated strings where each character is ENTSIZE
4693
bytes long. The linker may remove duplicates within sections with the
4694
same name, same entity size and same flags.  ENTSIZE must be an
4695
absolute expression.  For sections with both `M' and `S', a string
4696
which is a suffix of a larger string is considered a duplicate.  Thus
4697
`"def"' will be merged with `"abcdef"';  A reference to the first
4698
`"def"' will be changed to a reference to `"abcdef"+3'.
4699
 
4700
   If FLAGS contains the `G' symbol then the TYPE argument must be
4701
present along with an additional field like this:
4702
 
4703
     .section NAME , "FLAGS"G, @TYPE, GROUPNAME[, LINKAGE]
4704
 
4705
   The GROUPNAME field specifies the name of the section group to which
4706
this particular section belongs.  The optional linkage field can
4707
contain:
4708
`comdat'
4709
     indicates that only one copy of this section should be retained
4710
 
4711
`.gnu.linkonce'
4712
     an alias for comdat
4713
 
4714
   Note: if both the M and G flags are present then the fields for the
4715
Merge flag should come first, like this:
4716
 
4717
     .section NAME , "FLAGS"MG, @TYPE, ENTSIZE, GROUPNAME[, LINKAGE]
4718
 
4719
   If no flags are specified, the default flags depend upon the section
4720
name.  If the section name is not recognized, the default will be for
4721
the section to have none of the above flags: it will not be allocated
4722
in memory, nor writable, nor executable.  The section will contain data.
4723
 
4724
   For ELF targets, the assembler supports another type of `.section'
4725
directive for compatibility with the Solaris assembler:
4726
 
4727
     .section "NAME"[, FLAGS...]
4728
 
4729
   Note that the section name is quoted.  There may be a sequence of
4730
comma separated flags:
4731
`#alloc'
4732
     section is allocatable
4733
 
4734
`#write'
4735
     section is writable
4736
 
4737
`#execinstr'
4738
     section is executable
4739
 
4740
`#tls'
4741
     section is used for thread local storage
4742
 
4743
   This directive replaces the current section and subsection.  See the
4744
contents of the gas testsuite directory `gas/testsuite/gas/elf' for
4745
some examples of how this directive and the other section stack
4746
directives work.
4747
 
4748

4749
File: as.info,  Node: Set,  Next: Short,  Prev: Section,  Up: Pseudo Ops
4750
 
4751
7.97 `.set SYMBOL, EXPRESSION'
4752
==============================
4753
 
4754
Set the value of SYMBOL to EXPRESSION.  This changes SYMBOL's value and
4755
type to conform to EXPRESSION.  If SYMBOL was flagged as external, it
4756
remains flagged (*note Symbol Attributes::).
4757
 
4758
   You may `.set' a symbol many times in the same assembly.
4759
 
4760
   If you `.set' a global symbol, the value stored in the object file
4761
is the last value stored into it.
4762
 
4763
   The syntax for `set' on the HPPA is `SYMBOL .set EXPRESSION'.
4764
 
4765
   On Z80 `set' is a real instruction, use `SYMBOL defl EXPRESSION'
4766
instead.
4767
 
4768

4769
File: as.info,  Node: Short,  Next: Single,  Prev: Set,  Up: Pseudo Ops
4770
 
4771
7.98 `.short EXPRESSIONS'
4772
=========================
4773
 
4774
`.short' is normally the same as `.word'.  *Note `.word': Word.
4775
 
4776
   In some configurations, however, `.short' and `.word' generate
4777
numbers of different lengths.  *Note Machine Dependencies::.
4778
 
4779

4780
File: as.info,  Node: Single,  Next: Size,  Prev: Short,  Up: Pseudo Ops
4781
 
4782
7.99 `.single FLONUMS'
4783
======================
4784
 
4785
This directive assembles zero or more flonums, separated by commas.  It
4786
has the same effect as `.float'.  The exact kind of floating point
4787
numbers emitted depends on how `as' is configured.  *Note Machine
4788
Dependencies::.
4789
 
4790

4791
File: as.info,  Node: Size,  Next: Skip,  Prev: Single,  Up: Pseudo Ops
4792
 
4793
7.100 `.size'
4794
=============
4795
 
4796
This directive is used to set the size associated with a symbol.
4797
 
4798
COFF Version
4799
------------
4800
 
4801
   For COFF targets, the `.size' directive is only permitted inside
4802
`.def'/`.endef' pairs.  It is used like this:
4803
 
4804
     .size EXPRESSION
4805
 
4806
ELF Version
4807
-----------
4808
 
4809
   For ELF targets, the `.size' directive is used like this:
4810
 
4811
     .size NAME , EXPRESSION
4812
 
4813
   This directive sets the size associated with a symbol NAME.  The
4814
size in bytes is computed from EXPRESSION which can make use of label
4815
arithmetic.  This directive is typically used to set the size of
4816
function symbols.
4817
 
4818

4819
File: as.info,  Node: Skip,  Next: Sleb128,  Prev: Size,  Up: Pseudo Ops
4820
 
4821
7.101 `.skip SIZE , FILL'
4822
=========================
4823
 
4824
This directive emits SIZE bytes, each of value FILL.  Both SIZE and
4825
FILL are absolute expressions.  If the comma and FILL are omitted, FILL
4826
is assumed to be zero.  This is the same as `.space'.
4827
 
4828

4829
File: as.info,  Node: Sleb128,  Next: Space,  Prev: Skip,  Up: Pseudo Ops
4830
 
4831
7.102 `.sleb128 EXPRESSIONS'
4832
============================
4833
 
4834
SLEB128 stands for "signed little endian base 128."  This is a compact,
4835
variable length representation of numbers used by the DWARF symbolic
4836
debugging format.  *Note `.uleb128': Uleb128.
4837
 
4838

4839
File: as.info,  Node: Space,  Next: Stab,  Prev: Sleb128,  Up: Pseudo Ops
4840
 
4841
7.103 `.space SIZE , FILL'
4842
==========================
4843
 
4844
This directive emits SIZE bytes, each of value FILL.  Both SIZE and
4845
FILL are absolute expressions.  If the comma and FILL are omitted, FILL
4846
is assumed to be zero.  This is the same as `.skip'.
4847
 
4848
     _Warning:_ `.space' has a completely different meaning for HPPA
4849
     targets; use `.block' as a substitute.  See `HP9000 Series 800
4850
     Assembly Language Reference Manual' (HP 92432-90001) for the
4851
     meaning of the `.space' directive.  *Note HPPA Assembler
4852
     Directives: HPPA Directives, for a summary.
4853
 
4854

4855
File: as.info,  Node: Stab,  Next: String,  Prev: Space,  Up: Pseudo Ops
4856
 
4857
7.104 `.stabd, .stabn, .stabs'
4858
==============================
4859
 
4860
There are three directives that begin `.stab'.  All emit symbols (*note
4861
Symbols::), for use by symbolic debuggers.  The symbols are not entered
4862
in the `as' hash table: they cannot be referenced elsewhere in the
4863
source file.  Up to five fields are required:
4864
 
4865
STRING
4866
     This is the symbol's name.  It may contain any character except
4867
     `\000', so is more general than ordinary symbol names.  Some
4868
     debuggers used to code arbitrarily complex structures into symbol
4869
     names using this field.
4870
 
4871
TYPE
4872
     An absolute expression.  The symbol's type is set to the low 8
4873
     bits of this expression.  Any bit pattern is permitted, but `ld'
4874
     and debuggers choke on silly bit patterns.
4875
 
4876
OTHER
4877
     An absolute expression.  The symbol's "other" attribute is set to
4878
     the low 8 bits of this expression.
4879
 
4880
DESC
4881
     An absolute expression.  The symbol's descriptor is set to the low
4882
     16 bits of this expression.
4883
 
4884
VALUE
4885
     An absolute expression which becomes the symbol's value.
4886
 
4887
   If a warning is detected while reading a `.stabd', `.stabn', or
4888
`.stabs' statement, the symbol has probably already been created; you
4889
get a half-formed symbol in your object file.  This is compatible with
4890
earlier assemblers!
4891
 
4892
`.stabd TYPE , OTHER , DESC'
4893
     The "name" of the symbol generated is not even an empty string.
4894
     It is a null pointer, for compatibility.  Older assemblers used a
4895
     null pointer so they didn't waste space in object files with empty
4896
     strings.
4897
 
4898
     The symbol's value is set to the location counter, relocatably.
4899
     When your program is linked, the value of this symbol is the
4900
     address of the location counter when the `.stabd' was assembled.
4901
 
4902
`.stabn TYPE , OTHER , DESC , VALUE'
4903
     The name of the symbol is set to the empty string `""'.
4904
 
4905
`.stabs STRING ,  TYPE , OTHER , DESC , VALUE'
4906
     All five fields are specified.
4907
 
4908

4909
File: as.info,  Node: String,  Next: Struct,  Prev: Stab,  Up: Pseudo Ops
4910
 
4911
7.105 `.string' "STR", `.string8' "STR", `.string16'
4912
====================================================
4913
 
4914
"STR", `.string32' "STR", `.string64' "STR"
4915
 
4916
   Copy the characters in STR to the object file.  You may specify more
4917
than one string to copy, separated by commas.  Unless otherwise
4918
specified for a particular machine, the assembler marks the end of each
4919
string with a 0 byte.  You can use any of the escape sequences
4920
described in *Note Strings: Strings.
4921
 
4922
   The variants `string16', `string32' and `string64' differ from the
4923
`string' pseudo opcode in that each 8-bit character from STR is copied
4924
and expanded to 16, 32 or 64 bits respectively.  The expanded characters
4925
are stored in target endianness byte order.
4926
 
4927
   Example:
4928
        .string32 "BYE"
4929
     expands to:
4930
        .string   "B\0\0\0Y\0\0\0E\0\0\0"  /* On little endian targets.  */
4931
        .string   "\0\0\0B\0\0\0Y\0\0\0E"  /* On big endian targets.  */
4932
 
4933

4934
File: as.info,  Node: Struct,  Next: SubSection,  Prev: String,  Up: Pseudo Ops
4935
 
4936
7.106 `.struct EXPRESSION'
4937
==========================
4938
 
4939
Switch to the absolute section, and set the section offset to
4940
EXPRESSION, which must be an absolute expression.  You might use this
4941
as follows:
4942
             .struct 0
4943
     field1:
4944
             .struct field1 + 4
4945
     field2:
4946
             .struct field2 + 4
4947
     field3:
4948
   This would define the symbol `field1' to have the value 0, the symbol
4949
`field2' to have the value 4, and the symbol `field3' to have the value
4950
8.  Assembly would be left in the absolute section, and you would need
4951
to use a `.section' directive of some sort to change to some other
4952
section before further assembly.
4953
 
4954

4955
File: as.info,  Node: SubSection,  Next: Symver,  Prev: Struct,  Up: Pseudo Ops
4956
 
4957
7.107 `.subsection NAME'
4958
========================
4959
 
4960
This is one of the ELF section stack manipulation directives.  The
4961
others are `.section' (*note Section::), `.pushsection' (*note
4962
PushSection::), `.popsection' (*note PopSection::), and `.previous'
4963
(*note Previous::).
4964
 
4965
   This directive replaces the current subsection with `name'.  The
4966
current section is not changed.  The replaced subsection is put onto
4967
the section stack in place of the then current top of stack subsection.
4968
 
4969

4970
File: as.info,  Node: Symver,  Next: Tag,  Prev: SubSection,  Up: Pseudo Ops
4971
 
4972
7.108 `.symver'
4973
===============
4974
 
4975
Use the `.symver' directive to bind symbols to specific version nodes
4976
within a source file.  This is only supported on ELF platforms, and is
4977
typically used when assembling files to be linked into a shared library.
4978
There are cases where it may make sense to use this in objects to be
4979
bound into an application itself so as to override a versioned symbol
4980
from a shared library.
4981
 
4982
   For ELF targets, the `.symver' directive can be used like this:
4983
     .symver NAME, NAME2@NODENAME
4984
   If the symbol NAME is defined within the file being assembled, the
4985
`.symver' directive effectively creates a symbol alias with the name
4986
NAME2@NODENAME, and in fact the main reason that we just don't try and
4987
create a regular alias is that the @ character isn't permitted in
4988
symbol names.  The NAME2 part of the name is the actual name of the
4989
symbol by which it will be externally referenced.  The name NAME itself
4990
is merely a name of convenience that is used so that it is possible to
4991
have definitions for multiple versions of a function within a single
4992
source file, and so that the compiler can unambiguously know which
4993
version of a function is being mentioned.  The NODENAME portion of the
4994
alias should be the name of a node specified in the version script
4995
supplied to the linker when building a shared library.  If you are
4996
attempting to override a versioned symbol from a shared library, then
4997
NODENAME should correspond to the nodename of the symbol you are trying
4998
to override.
4999
 
5000
   If the symbol NAME is not defined within the file being assembled,
5001
all references to NAME will be changed to NAME2@NODENAME.  If no
5002
reference to NAME is made, NAME2@NODENAME will be removed from the
5003
symbol table.
5004
 
5005
   Another usage of the `.symver' directive is:
5006
     .symver NAME, NAME2@@NODENAME
5007
   In this case, the symbol NAME must exist and be defined within the
5008
file being assembled. It is similar to NAME2@NODENAME. The difference
5009
is NAME2@@NODENAME will also be used to resolve references to NAME2 by
5010
the linker.
5011
 
5012
   The third usage of the `.symver' directive is:
5013
     .symver NAME, NAME2@@@NODENAME
5014
   When NAME is not defined within the file being assembled, it is
5015
treated as NAME2@NODENAME. When NAME is defined within the file being
5016
assembled, the symbol name, NAME, will be changed to NAME2@@NODENAME.
5017
 
5018

5019
File: as.info,  Node: Tag,  Next: Text,  Prev: Symver,  Up: Pseudo Ops
5020
 
5021
7.109 `.tag STRUCTNAME'
5022
=======================
5023
 
5024
This directive is generated by compilers to include auxiliary debugging
5025
information in the symbol table.  It is only permitted inside
5026
`.def'/`.endef' pairs.  Tags are used to link structure definitions in
5027
the symbol table with instances of those structures.
5028
 
5029

5030
File: as.info,  Node: Text,  Next: Title,  Prev: Tag,  Up: Pseudo Ops
5031
 
5032
7.110 `.text SUBSECTION'
5033
========================
5034
 
5035
Tells `as' to assemble the following statements onto the end of the
5036
text subsection numbered SUBSECTION, which is an absolute expression.
5037
If SUBSECTION is omitted, subsection number zero is used.
5038
 
5039

5040
File: as.info,  Node: Title,  Next: Type,  Prev: Text,  Up: Pseudo Ops
5041
 
5042
7.111 `.title "HEADING"'
5043
========================
5044
 
5045
Use HEADING as the title (second line, immediately after the source
5046
file name and pagenumber) when generating assembly listings.
5047
 
5048
   This directive affects subsequent pages, as well as the current page
5049
if it appears within ten lines of the top of a page.
5050
 
5051

5052
File: as.info,  Node: Type,  Next: Uleb128,  Prev: Title,  Up: Pseudo Ops
5053
 
5054
7.112 `.type'
5055
=============
5056
 
5057
This directive is used to set the type of a symbol.
5058
 
5059
COFF Version
5060
------------
5061
 
5062
   For COFF targets, this directive is permitted only within
5063
`.def'/`.endef' pairs.  It is used like this:
5064
 
5065
     .type INT
5066
 
5067
   This records the integer INT as the type attribute of a symbol table
5068
entry.
5069
 
5070
ELF Version
5071
-----------
5072
 
5073
   For ELF targets, the `.type' directive is used like this:
5074
 
5075
     .type NAME , TYPE DESCRIPTION
5076
 
5077
   This sets the type of symbol NAME to be either a function symbol or
5078
an object symbol.  There are five different syntaxes supported for the
5079
TYPE DESCRIPTION field, in order to provide compatibility with various
5080
other assemblers.
5081
 
5082
   Because some of the characters used in these syntaxes (such as `@'
5083
and `#') are comment characters for some architectures, some of the
5084
syntaxes below do not work on all architectures.  The first variant
5085
will be accepted by the GNU assembler on all architectures so that
5086
variant should be used for maximum portability, if you do not need to
5087
assemble your code with other assemblers.
5088
 
5089
   The syntaxes supported are:
5090
 
5091
       .type  STT_
5092
       .type ,#
5093
       .type ,@
5094
       .type ,%
5095
       .type ,""
5096
 
5097
   The types supported are:
5098
 
5099
`STT_FUNC'
5100
`function'
5101
     Mark the symbol as being a function name.
5102
 
5103
`STT_GNU_IFUNC'
5104
`gnu_indirect_function'
5105
     Mark the symbol as an indirect function when evaluated during reloc
5106
     processing.  (This is only supported on Linux targeted assemblers).
5107
 
5108
`STT_OBJECT'
5109
`object'
5110
     Mark the symbol as being a data object.
5111
 
5112
`STT_TLS'
5113
`tls_object'
5114
     Mark the symbol as being a thead-local data object.
5115
 
5116
`STT_COMMON'
5117
`common'
5118
     Mark the symbol as being a common data object.
5119
 
5120
`STT_NOTYPE'
5121
`notype'
5122
     Does not mark the symbol in any way.  It is supported just for
5123
     completeness.
5124
 
5125
`gnu_unique_object'
5126
     Marks the symbol as being a globally unique data object.  The
5127
     dynamic linker will make sure that in the entire process there is
5128
     just one symbol with this name and type in use.  (This is only
5129
     supported on Linux targeted assemblers).
5130
 
5131
 
5132
   Note: Some targets support extra types in addition to those listed
5133
above.
5134
 
5135

5136
File: as.info,  Node: Uleb128,  Next: Val,  Prev: Type,  Up: Pseudo Ops
5137
 
5138
7.113 `.uleb128 EXPRESSIONS'
5139
============================
5140
 
5141
ULEB128 stands for "unsigned little endian base 128."  This is a
5142
compact, variable length representation of numbers used by the DWARF
5143
symbolic debugging format.  *Note `.sleb128': Sleb128.
5144
 
5145

5146
File: as.info,  Node: Val,  Next: Version,  Prev: Uleb128,  Up: Pseudo Ops
5147
 
5148
7.114 `.val ADDR'
5149
=================
5150
 
5151
This directive, permitted only within `.def'/`.endef' pairs, records
5152
the address ADDR as the value attribute of a symbol table entry.
5153
 
5154

5155
File: as.info,  Node: Version,  Next: VTableEntry,  Prev: Val,  Up: Pseudo Ops
5156
 
5157
7.115 `.version "STRING"'
5158
=========================
5159
 
5160
This directive creates a `.note' section and places into it an ELF
5161
formatted note of type NT_VERSION.  The note's name is set to `string'.
5162
 
5163

5164
File: as.info,  Node: VTableEntry,  Next: VTableInherit,  Prev: Version,  Up: Pseudo Ops
5165
 
5166
7.116 `.vtable_entry TABLE, OFFSET'
5167
===================================
5168
 
5169
This directive finds or creates a symbol `table' and creates a
5170
`VTABLE_ENTRY' relocation for it with an addend of `offset'.
5171
 
5172

5173
File: as.info,  Node: VTableInherit,  Next: Warning,  Prev: VTableEntry,  Up: Pseudo Ops
5174
 
5175
7.117 `.vtable_inherit CHILD, PARENT'
5176
=====================================
5177
 
5178
This directive finds the symbol `child' and finds or creates the symbol
5179
`parent' and then creates a `VTABLE_INHERIT' relocation for the parent
5180
whose addend is the value of the child symbol.  As a special case the
5181
parent name of `0' is treated as referring to the `*ABS*' section.
5182
 
5183

5184
File: as.info,  Node: Warning,  Next: Weak,  Prev: VTableInherit,  Up: Pseudo Ops
5185
 
5186
7.118 `.warning "STRING"'
5187
=========================
5188
 
5189
Similar to the directive `.error' (*note `.error "STRING"': Error.),
5190
but just emits a warning.
5191
 
5192

5193
File: as.info,  Node: Weak,  Next: Weakref,  Prev: Warning,  Up: Pseudo Ops
5194
 
5195
7.119 `.weak NAMES'
5196
===================
5197
 
5198
This directive sets the weak attribute on the comma separated list of
5199
symbol `names'.  If the symbols do not already exist, they will be
5200
created.
5201
 
5202
   On COFF targets other than PE, weak symbols are a GNU extension.
5203
This directive sets the weak attribute on the comma separated list of
5204
symbol `names'.  If the symbols do not already exist, they will be
5205
created.
5206
 
5207
   On the PE target, weak symbols are supported natively as weak
5208
aliases.  When a weak symbol is created that is not an alias, GAS
5209
creates an alternate symbol to hold the default value.
5210
 
5211

5212
File: as.info,  Node: Weakref,  Next: Word,  Prev: Weak,  Up: Pseudo Ops
5213
 
5214
7.120 `.weakref ALIAS, TARGET'
5215
==============================
5216
 
5217
This directive creates an alias to the target symbol that enables the
5218
symbol to be referenced with weak-symbol semantics, but without
5219
actually making it weak.  If direct references or definitions of the
5220
symbol are present, then the symbol will not be weak, but if all
5221
references to it are through weak references, the symbol will be marked
5222
as weak in the symbol table.
5223
 
5224
   The effect is equivalent to moving all references to the alias to a
5225
separate assembly source file, renaming the alias to the symbol in it,
5226
declaring the symbol as weak there, and running a reloadable link to
5227
merge the object files resulting from the assembly of the new source
5228
file and the old source file that had the references to the alias
5229
removed.
5230
 
5231
   The alias itself never makes to the symbol table, and is entirely
5232
handled within the assembler.
5233
 
5234

5235
File: as.info,  Node: Word,  Next: Deprecated,  Prev: Weakref,  Up: Pseudo Ops
5236
 
5237
7.121 `.word EXPRESSIONS'
5238
=========================
5239
 
5240
This directive expects zero or more EXPRESSIONS, of any section,
5241
separated by commas.
5242
 
5243
   The size of the number emitted, and its byte order, depend on what
5244
target computer the assembly is for.
5245
 
5246
     _Warning: Special Treatment to support Compilers_
5247
 
5248
   Machines with a 32-bit address space, but that do less than 32-bit
5249
addressing, require the following special treatment.  If the machine of
5250
interest to you does 32-bit addressing (or doesn't require it; *note
5251
Machine Dependencies::), you can ignore this issue.
5252
 
5253
   In order to assemble compiler output into something that works, `as'
5254
occasionally does strange things to `.word' directives.  Directives of
5255
the form `.word sym1-sym2' are often emitted by compilers as part of
5256
jump tables.  Therefore, when `as' assembles a directive of the form
5257
`.word sym1-sym2', and the difference between `sym1' and `sym2' does
5258
not fit in 16 bits, `as' creates a "secondary jump table", immediately
5259
before the next label.  This secondary jump table is preceded by a
5260
short-jump to the first byte after the secondary table.  This
5261
short-jump prevents the flow of control from accidentally falling into
5262
the new table.  Inside the table is a long-jump to `sym2'.  The
5263
original `.word' contains `sym1' minus the address of the long-jump to
5264
`sym2'.
5265
 
5266
   If there were several occurrences of `.word sym1-sym2' before the
5267
secondary jump table, all of them are adjusted.  If there was a `.word
5268
sym3-sym4', that also did not fit in sixteen bits, a long-jump to
5269
`sym4' is included in the secondary jump table, and the `.word'
5270
directives are adjusted to contain `sym3' minus the address of the
5271
long-jump to `sym4'; and so on, for as many entries in the original
5272
jump table as necessary.
5273
 
5274

5275
File: as.info,  Node: Deprecated,  Prev: Word,  Up: Pseudo Ops
5276
 
5277
7.122 Deprecated Directives
5278
===========================
5279
 
5280
One day these directives won't work.  They are included for
5281
compatibility with older assemblers.
5282
.abort
5283
 
5284
.line
5285
 
5286

5287
File: as.info,  Node: Object Attributes,  Next: Machine Dependencies,  Prev: Pseudo Ops,  Up: Top
5288
 
5289
8 Object Attributes
5290
*******************
5291
 
5292
`as' assembles source files written for a specific architecture into
5293
object files for that architecture.  But not all object files are alike.
5294
Many architectures support incompatible variations.  For instance,
5295
floating point arguments might be passed in floating point registers if
5296
the object file requires hardware floating point support--or floating
5297
point arguments might be passed in integer registers if the object file
5298
supports processors with no hardware floating point unit.  Or, if two
5299
objects are built for different generations of the same architecture,
5300
the combination may require the newer generation at run-time.
5301
 
5302
   This information is useful during and after linking.  At link time,
5303
`ld' can warn about incompatible object files.  After link time, tools
5304
like `gdb' can use it to process the linked file correctly.
5305
 
5306
   Compatibility information is recorded as a series of object
5307
attributes.  Each attribute has a "vendor", "tag", and "value".  The
5308
vendor is a string, and indicates who sets the meaning of the tag.  The
5309
tag is an integer, and indicates what property the attribute describes.
5310
The value may be a string or an integer, and indicates how the
5311
property affects this object.  Missing attributes are the same as
5312
attributes with a zero value or empty string value.
5313
 
5314
   Object attributes were developed as part of the ABI for the ARM
5315
Architecture.  The file format is documented in `ELF for the ARM
5316
Architecture'.
5317
 
5318
* Menu:
5319
 
5320
* GNU Object Attributes::               GNU Object Attributes
5321
* Defining New Object Attributes::      Defining New Object Attributes
5322
 
5323

5324
File: as.info,  Node: GNU Object Attributes,  Next: Defining New Object Attributes,  Up: Object Attributes
5325
 
5326
8.1 GNU Object Attributes
5327
=========================
5328
 
5329
The `.gnu_attribute' directive records an object attribute with vendor
5330
`gnu'.
5331
 
5332
   Except for `Tag_compatibility', which has both an integer and a
5333
string for its value, GNU attributes have a string value if the tag
5334
number is odd and an integer value if the tag number is even.  The
5335
second bit (`TAG & 2' is set for architecture-independent attributes
5336
and clear for architecture-dependent ones.
5337
 
5338
8.1.1 Common GNU attributes
5339
---------------------------
5340
 
5341
These attributes are valid on all architectures.
5342
 
5343
Tag_compatibility (32)
5344
     The compatibility attribute takes an integer flag value and a
5345
     vendor name.  If the flag value is 0, the file is compatible with
5346
     other toolchains.  If it is 1, then the file is only compatible
5347
     with the named toolchain.  If it is greater than 1, the file can
5348
     only be processed by other toolchains under some private
5349
     arrangement indicated by the flag value and the vendor name.
5350
 
5351
8.1.2 MIPS Attributes
5352
---------------------
5353
 
5354
Tag_GNU_MIPS_ABI_FP (4)
5355
     The floating-point ABI used by this object file.  The value will
5356
     be:
5357
 
5358
        * 0 for files not affected by the floating-point ABI.
5359
 
5360
        * 1 for files using the hardware floating-point with a standard
5361
          double-precision FPU.
5362
 
5363
        * 2 for files using the hardware floating-point ABI with a
5364
          single-precision FPU.
5365
 
5366
        * 3 for files using the software floating-point ABI.
5367
 
5368
        * 4 for files using the hardware floating-point ABI with 64-bit
5369
          wide double-precision floating-point registers and 32-bit
5370
          wide general purpose registers.
5371
 
5372
8.1.3 PowerPC Attributes
5373
------------------------
5374
 
5375
Tag_GNU_Power_ABI_FP (4)
5376
     The floating-point ABI used by this object file.  The value will
5377
     be:
5378
 
5379
        * 0 for files not affected by the floating-point ABI.
5380
 
5381
        * 1 for files using double-precision hardware floating-point
5382
          ABI.
5383
 
5384
        * 2 for files using the software floating-point ABI.
5385
 
5386
        * 3 for files using single-precision hardware floating-point
5387
          ABI.
5388
 
5389
Tag_GNU_Power_ABI_Vector (8)
5390
     The vector ABI used by this object file.  The value will be:
5391
 
5392
        * 0 for files not affected by the vector ABI.
5393
 
5394
        * 1 for files using general purpose registers to pass vectors.
5395
 
5396
        * 2 for files using AltiVec registers to pass vectors.
5397
 
5398
        * 3 for files using SPE registers to pass vectors.
5399
 
5400

5401
File: as.info,  Node: Defining New Object Attributes,  Prev: GNU Object Attributes,  Up: Object Attributes
5402
 
5403
8.2 Defining New Object Attributes
5404
==================================
5405
 
5406
If you want to define a new GNU object attribute, here are the places
5407
you will need to modify.  New attributes should be discussed on the
5408
`binutils' mailing list.
5409
 
5410
   * This manual, which is the official register of attributes.
5411
 
5412
   * The header for your architecture `include/elf', to define the tag.
5413
 
5414
   * The `bfd' support file for your architecture, to merge the
5415
     attribute and issue any appropriate link warnings.
5416
 
5417
   * Test cases in `ld/testsuite' for merging and link warnings.
5418
 
5419
   * `binutils/readelf.c' to display your attribute.
5420
 
5421
   * GCC, if you want the compiler to mark the attribute automatically.
5422
 
5423

5424
File: as.info,  Node: Machine Dependencies,  Next: Reporting Bugs,  Prev: Object Attributes,  Up: Top
5425
 
5426
9 Machine Dependent Features
5427
****************************
5428
 
5429
The machine instruction sets are (almost by definition) different on
5430
each machine where `as' runs.  Floating point representations vary as
5431
well, and `as' often supports a few additional directives or
5432
command-line options for compatibility with other assemblers on a
5433
particular platform.  Finally, some versions of `as' support special
5434
pseudo-instructions for branch optimization.
5435
 
5436
   This chapter discusses most of these differences, though it does not
5437
include details on any machine's instruction set.  For details on that
5438
subject, see the hardware manufacturer's manual.
5439
 
5440
* Menu:
5441
 
5442
 
5443
* Alpha-Dependent::             Alpha Dependent Features
5444
 
5445
* ARC-Dependent::               ARC Dependent Features
5446
 
5447
* ARM-Dependent::               ARM Dependent Features
5448
 
5449
* AVR-Dependent::               AVR Dependent Features
5450
 
5451
* Blackfin-Dependent::          Blackfin Dependent Features
5452
 
5453
* CR16-Dependent::              CR16 Dependent Features
5454
 
5455
* CRIS-Dependent::              CRIS Dependent Features
5456
 
5457
* D10V-Dependent::              D10V Dependent Features
5458
 
5459
* D30V-Dependent::              D30V Dependent Features
5460
 
5461
* H8/300-Dependent::            Renesas H8/300 Dependent Features
5462
 
5463
* HPPA-Dependent::              HPPA Dependent Features
5464
 
5465
* ESA/390-Dependent::           IBM ESA/390 Dependent Features
5466
 
5467
* i386-Dependent::              Intel 80386 and AMD x86-64 Dependent Features
5468
 
5469
* i860-Dependent::              Intel 80860 Dependent Features
5470
 
5471
* i960-Dependent::              Intel 80960 Dependent Features
5472
 
5473
* IA-64-Dependent::             Intel IA-64 Dependent Features
5474
 
5475
* IP2K-Dependent::              IP2K Dependent Features
5476
 
5477
* LM32-Dependent::              LM32 Dependent Features
5478
 
5479
* M32C-Dependent::              M32C Dependent Features
5480
 
5481
* M32R-Dependent::              M32R Dependent Features
5482
 
5483
* M68K-Dependent::              M680x0 Dependent Features
5484
 
5485
* M68HC11-Dependent::           M68HC11 and 68HC12 Dependent Features
5486
 
5487
* MicroBlaze-Dependent::        MICROBLAZE Dependent Features
5488
 
5489
* MIPS-Dependent::              MIPS Dependent Features
5490
 
5491
* MMIX-Dependent::              MMIX Dependent Features
5492
 
5493
* MSP430-Dependent::            MSP430 Dependent Features
5494
 
5495
* SH-Dependent::                Renesas / SuperH SH Dependent Features
5496
* SH64-Dependent::              SuperH SH64 Dependent Features
5497
 
5498
* PDP-11-Dependent::            PDP-11 Dependent Features
5499
 
5500
* PJ-Dependent::                picoJava Dependent Features
5501
 
5502
* PPC-Dependent::               PowerPC Dependent Features
5503
 
5504
* S/390-Dependent::             IBM S/390 Dependent Features
5505
 
5506
* SCORE-Dependent::             SCORE Dependent Features
5507
 
5508
* Sparc-Dependent::             SPARC Dependent Features
5509
 
5510
* TIC54X-Dependent::            TI TMS320C54x Dependent Features
5511
 
5512
* V850-Dependent::              V850 Dependent Features
5513
 
5514
* Xtensa-Dependent::            Xtensa Dependent Features
5515
 
5516
* Z80-Dependent::               Z80 Dependent Features
5517
 
5518
* Z8000-Dependent::             Z8000 Dependent Features
5519
 
5520
* Vax-Dependent::               VAX Dependent Features
5521
 
5522

5523
File: as.info,  Node: Alpha-Dependent,  Next: ARC-Dependent,  Up: Machine Dependencies
5524
 
5525
9.1 Alpha Dependent Features
5526
============================
5527
 
5528
* Menu:
5529
 
5530
* Alpha Notes::                Notes
5531
* Alpha Options::              Options
5532
* Alpha Syntax::               Syntax
5533
* Alpha Floating Point::       Floating Point
5534
* Alpha Directives::           Alpha Machine Directives
5535
* Alpha Opcodes::              Opcodes
5536
 
5537

5538
File: as.info,  Node: Alpha Notes,  Next: Alpha Options,  Up: Alpha-Dependent
5539
 
5540
9.1.1 Notes
5541
-----------
5542
 
5543
The documentation here is primarily for the ELF object format.  `as'
5544
also supports the ECOFF and EVAX formats, but features specific to
5545
these formats are not yet documented.
5546
 
5547

5548
File: as.info,  Node: Alpha Options,  Next: Alpha Syntax,  Prev: Alpha Notes,  Up: Alpha-Dependent
5549
 
5550
9.1.2 Options
5551
-------------
5552
 
5553
`-mCPU'
5554
     This option specifies the target processor.  If an attempt is made
5555
     to assemble an instruction which will not execute on the target
5556
     processor, the assembler may either expand the instruction as a
5557
     macro or issue an error message.  This option is equivalent to the
5558
     `.arch' directive.
5559
 
5560
     The following processor names are recognized: `21064', `21064a',
5561
     `21066', `21068', `21164', `21164a', `21164pc', `21264', `21264a',
5562
     `21264b', `ev4', `ev5', `lca45', `ev5', `ev56', `pca56', `ev6',
5563
     `ev67', `ev68'.  The special name `all' may be used to allow the
5564
     assembler to accept instructions valid for any Alpha processor.
5565
 
5566
     In order to support existing practice in OSF/1 with respect to
5567
     `.arch', and existing practice within `MILO' (the Linux ARC
5568
     bootloader), the numbered processor names (e.g. 21064) enable the
5569
     processor-specific PALcode instructions, while the
5570
     "electro-vlasic" names (e.g. `ev4') do not.
5571
 
5572
`-mdebug'
5573
`-no-mdebug'
5574
     Enables or disables the generation of `.mdebug' encapsulation for
5575
     stabs directives and procedure descriptors.  The default is to
5576
     automatically enable `.mdebug' when the first stabs directive is
5577
     seen.
5578
 
5579
`-relax'
5580
     This option forces all relocations to be put into the object file,
5581
     instead of saving space and resolving some relocations at assembly
5582
     time.  Note that this option does not propagate all symbol
5583
     arithmetic into the object file, because not all symbol arithmetic
5584
     can be represented.  However, the option can still be useful in
5585
     specific applications.
5586
 
5587
`-replace'
5588
 
5589
`-noreplace'
5590
     Enables or disables the optimization of procedure calls, both at
5591
     assemblage and at link time.  These options are only available for
5592
     VMS targets and `-replace' is the default.  See section 1.4.1 of
5593
     the OpenVMS Linker Utility Manual.
5594
 
5595
`-g'
5596
     This option is used when the compiler generates debug information.
5597
     When `gcc' is using `mips-tfile' to generate debug information
5598
     for ECOFF, local labels must be passed through to the object file.
5599
     Otherwise this option has no effect.
5600
 
5601
`-GSIZE'
5602
     A local common symbol larger than SIZE is placed in `.bss', while
5603
     smaller symbols are placed in `.sbss'.
5604
 
5605
`-F'
5606
`-32addr'
5607
     These options are ignored for backward compatibility.
5608
 
5609

5610
File: as.info,  Node: Alpha Syntax,  Next: Alpha Floating Point,  Prev: Alpha Options,  Up: Alpha-Dependent
5611
 
5612
9.1.3 Syntax
5613
------------
5614
 
5615
The assembler syntax closely follow the Alpha Reference Manual;
5616
assembler directives and general syntax closely follow the OSF/1 and
5617
OpenVMS syntax, with a few differences for ELF.
5618
 
5619
* Menu:
5620
 
5621
* Alpha-Chars::                Special Characters
5622
* Alpha-Regs::                 Register Names
5623
* Alpha-Relocs::               Relocations
5624
 
5625

5626
File: as.info,  Node: Alpha-Chars,  Next: Alpha-Regs,  Up: Alpha Syntax
5627
 
5628
9.1.3.1 Special Characters
5629
..........................
5630
 
5631
`#' is the line comment character.
5632
 
5633
   `;' can be used instead of a newline to separate statements.
5634
 
5635

5636
File: as.info,  Node: Alpha-Regs,  Next: Alpha-Relocs,  Prev: Alpha-Chars,  Up: Alpha Syntax
5637
 
5638
9.1.3.2 Register Names
5639
......................
5640
 
5641
The 32 integer registers are referred to as `$N' or `$rN'.  In
5642
addition, registers 15, 28, 29, and 30 may be referred to by the
5643
symbols `$fp', `$at', `$gp', and `$sp' respectively.
5644
 
5645
   The 32 floating-point registers are referred to as `$fN'.
5646
 
5647

5648
File: as.info,  Node: Alpha-Relocs,  Prev: Alpha-Regs,  Up: Alpha Syntax
5649
 
5650
9.1.3.3 Relocations
5651
...................
5652
 
5653
Some of these relocations are available for ECOFF, but mostly only for
5654
ELF.  They are modeled after the relocation format introduced in
5655
Digital Unix 4.0, but there are additions.
5656
 
5657
   The format is `!TAG' or `!TAG!NUMBER' where TAG is the name of the
5658
relocation.  In some cases NUMBER is used to relate specific
5659
instructions.
5660
 
5661
   The relocation is placed at the end of the instruction like so:
5662
 
5663
     ldah  $0,a($29)    !gprelhigh
5664
     lda   $0,a($0)     !gprellow
5665
     ldq   $1,b($29)    !literal!100
5666
     ldl   $2,0($1)     !lituse_base!100
5667
 
5668
`!literal'
5669
`!literal!N'
5670
     Used with an `ldq' instruction to load the address of a symbol
5671
     from the GOT.
5672
 
5673
     A sequence number N is optional, and if present is used to pair
5674
     `lituse' relocations with this `literal' relocation.  The `lituse'
5675
     relocations are used by the linker to optimize the code based on
5676
     the final location of the symbol.
5677
 
5678
     Note that these optimizations are dependent on the data flow of the
5679
     program.  Therefore, if _any_ `lituse' is paired with a `literal'
5680
     relocation, then _all_ uses of the register set by the `literal'
5681
     instruction must also be marked with `lituse' relocations.  This
5682
     is because the original `literal' instruction may be deleted or
5683
     transformed into another instruction.
5684
 
5685
     Also note that there may be a one-to-many relationship between
5686
     `literal' and `lituse', but not a many-to-one.  That is, if there
5687
     are two code paths that load up the same address and feed the
5688
     value to a single use, then the use may not use a `lituse'
5689
     relocation.
5690
 
5691
`!lituse_base!N'
5692
     Used with any memory format instruction (e.g. `ldl') to indicate
5693
     that the literal is used for an address load.  The offset field of
5694
     the instruction must be zero.  During relaxation, the code may be
5695
     altered to use a gp-relative load.
5696
 
5697
`!lituse_jsr!N'
5698
     Used with a register branch format instruction (e.g. `jsr') to
5699
     indicate that the literal is used for a call.  During relaxation,
5700
     the code may be altered to use a direct branch (e.g. `bsr').
5701
 
5702
`!lituse_jsrdirect!N'
5703
     Similar to `lituse_jsr', but also that this call cannot be vectored
5704
     through a PLT entry.  This is useful for functions with special
5705
     calling conventions which do not allow the normal call-clobbered
5706
     registers to be clobbered.
5707
 
5708
`!lituse_bytoff!N'
5709
     Used with a byte mask instruction (e.g. `extbl') to indicate that
5710
     only the low 3 bits of the address are relevant.  During
5711
     relaxation, the code may be altered to use an immediate instead of
5712
     a register shift.
5713
 
5714
`!lituse_addr!N'
5715
     Used with any other instruction to indicate that the original
5716
     address is in fact used, and the original `ldq' instruction may
5717
     not be altered or deleted.  This is useful in conjunction with
5718
     `lituse_jsr' to test whether a weak symbol is defined.
5719
 
5720
          ldq  $27,foo($29)   !literal!1
5721
          beq  $27,is_undef   !lituse_addr!1
5722
          jsr  $26,($27),foo  !lituse_jsr!1
5723
 
5724
`!lituse_tlsgd!N'
5725
     Used with a register branch format instruction to indicate that the
5726
     literal is the call to `__tls_get_addr' used to compute the
5727
     address of the thread-local storage variable whose descriptor was
5728
     loaded with `!tlsgd!N'.
5729
 
5730
`!lituse_tlsldm!N'
5731
     Used with a register branch format instruction to indicate that the
5732
     literal is the call to `__tls_get_addr' used to compute the
5733
     address of the base of the thread-local storage block for the
5734
     current module.  The descriptor for the module must have been
5735
     loaded with `!tlsldm!N'.
5736
 
5737
`!gpdisp!N'
5738
     Used with `ldah' and `lda' to load the GP from the current
5739
     address, a-la the `ldgp' macro.  The source register for the
5740
     `ldah' instruction must contain the address of the `ldah'
5741
     instruction.  There must be exactly one `lda' instruction paired
5742
     with the `ldah' instruction, though it may appear anywhere in the
5743
     instruction stream.  The immediate operands must be zero.
5744
 
5745
          bsr  $26,foo
5746
          ldah $29,0($26)     !gpdisp!1
5747
          lda  $29,0($29)     !gpdisp!1
5748
 
5749
`!gprelhigh'
5750
     Used with an `ldah' instruction to add the high 16 bits of a
5751
     32-bit displacement from the GP.
5752
 
5753
`!gprellow'
5754
     Used with any memory format instruction to add the low 16 bits of a
5755
     32-bit displacement from the GP.
5756
 
5757
`!gprel'
5758
     Used with any memory format instruction to add a 16-bit
5759
     displacement from the GP.
5760
 
5761
`!samegp'
5762
     Used with any branch format instruction to skip the GP load at the
5763
     target address.  The referenced symbol must have the same GP as the
5764
     source object file, and it must be declared to either not use `$27'
5765
     or perform a standard GP load in the first two instructions via the
5766
     `.prologue' directive.
5767
 
5768
`!tlsgd'
5769
`!tlsgd!N'
5770
     Used with an `lda' instruction to load the address of a TLS
5771
     descriptor for a symbol in the GOT.
5772
 
5773
     The sequence number N is optional, and if present it used to pair
5774
     the descriptor load with both the `literal' loading the address of
5775
     the `__tls_get_addr' function and the `lituse_tlsgd' marking the
5776
     call to that function.
5777
 
5778
     For proper relaxation, both the `tlsgd', `literal' and `lituse'
5779
     relocations must be in the same extended basic block.  That is,
5780
     the relocation with the lowest address must be executed first at
5781
     runtime.
5782
 
5783
`!tlsldm'
5784
`!tlsldm!N'
5785
     Used with an `lda' instruction to load the address of a TLS
5786
     descriptor for the current module in the GOT.
5787
 
5788
     Similar in other respects to `tlsgd'.
5789
 
5790
`!gotdtprel'
5791
     Used with an `ldq' instruction to load the offset of the TLS
5792
     symbol within its module's thread-local storage block.  Also known
5793
     as the dynamic thread pointer offset or dtp-relative offset.
5794
 
5795
`!dtprelhi'
5796
`!dtprello'
5797
`!dtprel'
5798
     Like `gprel' relocations except they compute dtp-relative offsets.
5799
 
5800
`!gottprel'
5801
     Used with an `ldq' instruction to load the offset of the TLS
5802
     symbol from the thread pointer.  Also known as the tp-relative
5803
     offset.
5804
 
5805
`!tprelhi'
5806
`!tprello'
5807
`!tprel'
5808
     Like `gprel' relocations except they compute tp-relative offsets.
5809
 
5810

5811
File: as.info,  Node: Alpha Floating Point,  Next: Alpha Directives,  Prev: Alpha Syntax,  Up: Alpha-Dependent
5812
 
5813
9.1.4 Floating Point
5814
--------------------
5815
 
5816
The Alpha family uses both IEEE and VAX floating-point numbers.
5817
 
5818

5819
File: as.info,  Node: Alpha Directives,  Next: Alpha Opcodes,  Prev: Alpha Floating Point,  Up: Alpha-Dependent
5820
 
5821
9.1.5 Alpha Assembler Directives
5822
--------------------------------
5823
 
5824
`as' for the Alpha supports many additional directives for
5825
compatibility with the native assembler.  This section describes them
5826
only briefly.
5827
 
5828
   These are the additional directives in `as' for the Alpha:
5829
 
5830
`.arch CPU'
5831
     Specifies the target processor.  This is equivalent to the `-mCPU'
5832
     command-line option.  *Note Options: Alpha Options, for a list of
5833
     values for CPU.
5834
 
5835
`.ent FUNCTION[, N]'
5836
     Mark the beginning of FUNCTION.  An optional number may follow for
5837
     compatibility with the OSF/1 assembler, but is ignored.  When
5838
     generating `.mdebug' information, this will create a procedure
5839
     descriptor for the function.  In ELF, it will mark the symbol as a
5840
     function a-la the generic `.type' directive.
5841
 
5842
`.end FUNCTION'
5843
     Mark the end of FUNCTION.  In ELF, it will set the size of the
5844
     symbol a-la the generic `.size' directive.
5845
 
5846
`.mask MASK, OFFSET'
5847
     Indicate which of the integer registers are saved in the current
5848
     function's stack frame.  MASK is interpreted a bit mask in which
5849
     bit N set indicates that register N is saved.  The registers are
5850
     saved in a block located OFFSET bytes from the "canonical frame
5851
     address" (CFA) which is the value of the stack pointer on entry to
5852
     the function.  The registers are saved sequentially, except that
5853
     the return address register (normally `$26') is saved first.
5854
 
5855
     This and the other directives that describe the stack frame are
5856
     currently only used when generating `.mdebug' information.  They
5857
     may in the future be used to generate DWARF2 `.debug_frame' unwind
5858
     information for hand written assembly.
5859
 
5860
`.fmask MASK, OFFSET'
5861
     Indicate which of the floating-point registers are saved in the
5862
     current stack frame.  The MASK and OFFSET parameters are
5863
     interpreted as with `.mask'.
5864
 
5865
`.frame FRAMEREG, FRAMEOFFSET, RETREG[, ARGOFFSET]'
5866
     Describes the shape of the stack frame.  The frame pointer in use
5867
     is FRAMEREG; normally this is either `$fp' or `$sp'.  The frame
5868
     pointer is FRAMEOFFSET bytes below the CFA.  The return address is
5869
     initially located in RETREG until it is saved as indicated in
5870
     `.mask'.  For compatibility with OSF/1 an optional ARGOFFSET
5871
     parameter is accepted and ignored.  It is believed to indicate the
5872
     offset from the CFA to the saved argument registers.
5873
 
5874
`.prologue N'
5875
     Indicate that the stack frame is set up and all registers have been
5876
     spilled.  The argument N indicates whether and how the function
5877
     uses the incoming "procedure vector" (the address of the called
5878
     function) in `$27'.  0 indicates that `$27' is not used; 1
5879
     indicates that the first two instructions of the function use `$27'
5880
     to perform a load of the GP register; 2 indicates that `$27' is
5881
     used in some non-standard way and so the linker cannot elide the
5882
     load of the procedure vector during relaxation.
5883
 
5884
`.usepv FUNCTION, WHICH'
5885
     Used to indicate the use of the `$27' register, similar to
5886
     `.prologue', but without the other semantics of needing to be
5887
     inside an open `.ent'/`.end' block.
5888
 
5889
     The WHICH argument should be either `no', indicating that `$27' is
5890
     not used, or `std', indicating that the first two instructions of
5891
     the function perform a GP load.
5892
 
5893
     One might use this directive instead of `.prologue' if you are
5894
     also using dwarf2 CFI directives.
5895
 
5896
`.gprel32 EXPRESSION'
5897
     Computes the difference between the address in EXPRESSION and the
5898
     GP for the current object file, and stores it in 4 bytes.  In
5899
     addition to being smaller than a full 8 byte address, this also
5900
     does not require a dynamic relocation when used in a shared
5901
     library.
5902
 
5903
`.t_floating EXPRESSION'
5904
     Stores EXPRESSION as an IEEE double precision value.
5905
 
5906
`.s_floating EXPRESSION'
5907
     Stores EXPRESSION as an IEEE single precision value.
5908
 
5909
`.f_floating EXPRESSION'
5910
     Stores EXPRESSION as a VAX F format value.
5911
 
5912
`.g_floating EXPRESSION'
5913
     Stores EXPRESSION as a VAX G format value.
5914
 
5915
`.d_floating EXPRESSION'
5916
     Stores EXPRESSION as a VAX D format value.
5917
 
5918
`.set FEATURE'
5919
     Enables or disables various assembler features.  Using the positive
5920
     name of the feature enables while using `noFEATURE' disables.
5921
 
5922
    `at'
5923
          Indicates that macro expansions may clobber the "assembler
5924
          temporary" (`$at' or `$28') register.  Some macros may not be
5925
          expanded without this and will generate an error message if
5926
          `noat' is in effect.  When `at' is in effect, a warning will
5927
          be generated if `$at' is used by the programmer.
5928
 
5929
    `macro'
5930
          Enables the expansion of macro instructions.  Note that
5931
          variants of real instructions, such as `br label' vs `br
5932
          $31,label' are considered alternate forms and not macros.
5933
 
5934
    `move'
5935
    `reorder'
5936
    `volatile'
5937
          These control whether and how the assembler may re-order
5938
          instructions.  Accepted for compatibility with the OSF/1
5939
          assembler, but `as' does not do instruction scheduling, so
5940
          these features are ignored.
5941
 
5942
   The following directives are recognized for compatibility with the
5943
OSF/1 assembler but are ignored.
5944
 
5945
     .proc           .aproc
5946
     .reguse         .livereg
5947
     .option         .aent
5948
     .ugen           .eflag
5949
     .alias          .noalias
5950
 
5951

5952
File: as.info,  Node: Alpha Opcodes,  Prev: Alpha Directives,  Up: Alpha-Dependent
5953
 
5954
9.1.6 Opcodes
5955
-------------
5956
 
5957
For detailed information on the Alpha machine instruction set, see the
5958
Alpha Architecture Handbook
5959
(ftp://ftp.digital.com/pub/Digital/info/semiconductor/literature/alphaahb.pdf).
5960
 
5961

5962
File: as.info,  Node: ARC-Dependent,  Next: ARM-Dependent,  Prev: Alpha-Dependent,  Up: Machine Dependencies
5963
 
5964
9.2 ARC Dependent Features
5965
==========================
5966
 
5967
* Menu:
5968
 
5969
* ARC Options::              Options
5970
* ARC Syntax::               Syntax
5971
* ARC Floating Point::       Floating Point
5972
* ARC Directives::           ARC Machine Directives
5973
* ARC Opcodes::              Opcodes
5974
 
5975

5976
File: as.info,  Node: ARC Options,  Next: ARC Syntax,  Up: ARC-Dependent
5977
 
5978
9.2.1 Options
5979
-------------
5980
 
5981
`-marc[5|6|7|8]'
5982
     This option selects the core processor variant.  Using `-marc' is
5983
     the same as `-marc6', which is also the default.
5984
 
5985
    `arc5'
5986
          Base instruction set.
5987
 
5988
    `arc6'
5989
          Jump-and-link (jl) instruction.  No requirement of an
5990
          instruction between setting flags and conditional jump.  For
5991
          example:
5992
 
5993
                 mov.f r0,r1
5994
                 beq   foo
5995
 
5996
    `arc7'
5997
          Break (brk) and sleep (sleep) instructions.
5998
 
5999
    `arc8'
6000
          Software interrupt (swi) instruction.
6001
 
6002
 
6003
     Note: the `.option' directive can to be used to select a core
6004
     variant from within assembly code.
6005
 
6006
`-EB'
6007
     This option specifies that the output generated by the assembler
6008
     should be marked as being encoded for a big-endian processor.
6009
 
6010
`-EL'
6011
     This option specifies that the output generated by the assembler
6012
     should be marked as being encoded for a little-endian processor -
6013
     this is the default.
6014
 
6015
 
6016

6017
File: as.info,  Node: ARC Syntax,  Next: ARC Floating Point,  Prev: ARC Options,  Up: ARC-Dependent
6018
 
6019
9.2.2 Syntax
6020
------------
6021
 
6022
* Menu:
6023
 
6024
* ARC-Chars::                Special Characters
6025
* ARC-Regs::                 Register Names
6026
 
6027

6028
File: as.info,  Node: ARC-Chars,  Next: ARC-Regs,  Up: ARC Syntax
6029
 
6030
9.2.2.1 Special Characters
6031
..........................
6032
 
6033
*TODO*
6034
 
6035

6036
File: as.info,  Node: ARC-Regs,  Prev: ARC-Chars,  Up: ARC Syntax
6037
 
6038
9.2.2.2 Register Names
6039
......................
6040
 
6041
*TODO*
6042
 
6043

6044
File: as.info,  Node: ARC Floating Point,  Next: ARC Directives,  Prev: ARC Syntax,  Up: ARC-Dependent
6045
 
6046
9.2.3 Floating Point
6047
--------------------
6048
 
6049
The ARC core does not currently have hardware floating point support.
6050
Software floating point support is provided by `GCC' and uses IEEE
6051
floating-point numbers.
6052
 
6053

6054
File: as.info,  Node: ARC Directives,  Next: ARC Opcodes,  Prev: ARC Floating Point,  Up: ARC-Dependent
6055
 
6056
9.2.4 ARC Machine Directives
6057
----------------------------
6058
 
6059
The ARC version of `as' supports the following additional machine
6060
directives:
6061
 
6062
`.2byte EXPRESSIONS'
6063
     *TODO*
6064
 
6065
`.3byte EXPRESSIONS'
6066
     *TODO*
6067
 
6068
`.4byte EXPRESSIONS'
6069
     *TODO*
6070
 
6071
`.extAuxRegister NAME,ADDRESS,MODE'
6072
     The ARCtangent A4 has extensible auxiliary register space.  The
6073
     auxiliary registers can be defined in the assembler source code by
6074
     using this directive.  The first parameter is the NAME of the new
6075
     auxiallry register.  The second parameter is the ADDRESS of the
6076
     register in the auxiliary register memory map for the variant of
6077
     the ARC.  The third parameter specifies the MODE in which the
6078
     register can be operated is and it can be one of:
6079
 
6080
    `r          (readonly)'
6081
 
6082
    `w          (write only)'
6083
 
6084
    `r|w        (read or write)'
6085
 
6086
     For example:
6087
 
6088
            .extAuxRegister mulhi,0x12,w
6089
 
6090
     This specifies an extension auxiliary register called _mulhi_
6091
     which is at address 0x12 in the memory space and which is only
6092
     writable.
6093
 
6094
`.extCondCode SUFFIX,VALUE'
6095
     The condition codes on the ARCtangent A4 are extensible and can be
6096
     specified by means of this assembler directive.  They are specified
6097
     by the suffix and the value for the condition code.  They can be
6098
     used to specify extra condition codes with any values.  For
6099
     example:
6100
 
6101
            .extCondCode is_busy,0x14
6102
 
6103
             add.is_busy  r1,r2,r3
6104
             bis_busy     _main
6105
 
6106
`.extCoreRegister NAME,REGNUM,MODE,SHORTCUT'
6107
     Specifies an extension core register NAME for the application.
6108
     This allows a register NAME with a valid REGNUM between 0 and 60,
6109
     with the following as valid values for MODE
6110
 
6111
    `_r_   (readonly)'
6112
 
6113
    `_w_   (write only)'
6114
 
6115
    `_r|w_ (read or write)'
6116
 
6117
     The other parameter gives a description of the register having a
6118
     SHORTCUT in the pipeline.  The valid values are:
6119
 
6120
    `can_shortcut'
6121
 
6122
    `cannot_shortcut'
6123
 
6124
     For example:
6125
 
6126
            .extCoreRegister mlo,57,r,can_shortcut
6127
 
6128
     This defines an extension core register mlo with the value 57 which
6129
     can shortcut the pipeline.
6130
 
6131
`.extInstruction NAME,OPCODE,SUBOPCODE,SUFFIXCLASS,SYNTAXCLASS'
6132
     The ARCtangent A4 allows the user to specify extension
6133
     instructions.  The extension instructions are not macros.  The
6134
     assembler creates encodings for use of these instructions
6135
     according to the specification by the user.  The parameters are:
6136
 
6137
    *NAME
6138
          Name of the extension instruction
6139
 
6140
    *OPCODE
6141
          Opcode to be used. (Bits 27:31 in the encoding).  Valid values
6142
          0x10-0x1f or 0x03
6143
 
6144
    *SUBOPCODE
6145
          Subopcode to be used.  Valid values are from 0x09-0x3f.
6146
          However the correct value also depends on SYNTAXCLASS
6147
 
6148
    *SUFFIXCLASS
6149
          Determines the kinds of suffixes to be allowed.  Valid values
6150
          are `SUFFIX_NONE', `SUFFIX_COND', `SUFFIX_FLAG' which
6151
          indicates the absence or presence of conditional suffixes and
6152
          flag setting by the extension instruction.  It is also
6153
          possible to specify that an instruction sets the flags and is
6154
          conditional by using `SUFFIX_CODE' | `SUFFIX_FLAG'.
6155
 
6156
    *SYNTAXCLASS
6157
          Determines the syntax class for the instruction.  It can have
6158
          the following values:
6159
 
6160
         ``SYNTAX_2OP':'
6161
               2 Operand Instruction
6162
 
6163
         ``SYNTAX_3OP':'
6164
               3 Operand Instruction
6165
 
6166
          In addition there could be modifiers for the syntax class as
6167
          described below:
6168
 
6169
               Syntax Class Modifiers are:
6170
 
6171
             - `OP1_MUST_BE_IMM': Modifies syntax class SYNTAX_3OP,
6172
               specifying that the first operand of a three-operand
6173
               instruction must be an immediate (i.e., the result is
6174
               discarded).  OP1_MUST_BE_IMM is used by bitwise ORing it
6175
               with SYNTAX_3OP as given in the example below.  This
6176
               could usually be used to set the flags using specific
6177
               instructions and not retain results.
6178
 
6179
             - `OP1_IMM_IMPLIED': Modifies syntax class SYNTAX_20P, it
6180
               specifies that there is an implied immediate destination
6181
               operand which does not appear in the syntax.  For
6182
               example, if the source code contains an instruction like:
6183
 
6184
                    inst r1,r2
6185
 
6186
               it really means that the first argument is an implied
6187
               immediate (that is, the result is discarded).  This is
6188
               the same as though the source code were: inst 0,r1,r2.
6189
               You use OP1_IMM_IMPLIED by bitwise ORing it with
6190
               SYNTAX_20P.
6191
 
6192
 
6193
     For example, defining 64-bit multiplier with immediate operands:
6194
 
6195
          .extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG ,
6196
                          SYNTAX_3OP|OP1_MUST_BE_IMM
6197
 
6198
     The above specifies an extension instruction called mp64 which has
6199
     3 operands, sets the flags, can be used with a condition code, for
6200
     which the first operand is an immediate.  (Equivalent to
6201
     discarding the result of the operation).
6202
 
6203
           .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED
6204
 
6205
     This describes a 2 operand instruction with an implicit first
6206
     immediate operand.  The result of this operation would be
6207
     discarded.
6208
 
6209
`.half EXPRESSIONS'
6210
     *TODO*
6211
 
6212
`.long EXPRESSIONS'
6213
     *TODO*
6214
 
6215
`.option ARC|ARC5|ARC6|ARC7|ARC8'
6216
     The `.option' directive must be followed by the desired core
6217
     version. Again `arc' is an alias for `arc6'.
6218
 
6219
     Note: the `.option' directive overrides the command line option
6220
     `-marc'; a warning is emitted when the version is not consistent
6221
     between the two - even for the implicit default core version
6222
     (arc6).
6223
 
6224
`.short EXPRESSIONS'
6225
     *TODO*
6226
 
6227
`.word EXPRESSIONS'
6228
     *TODO*
6229
 
6230
 
6231

6232
File: as.info,  Node: ARC Opcodes,  Prev: ARC Directives,  Up: ARC-Dependent
6233
 
6234
9.2.5 Opcodes
6235
-------------
6236
 
6237
For information on the ARC instruction set, see `ARC Programmers
6238
Reference Manual', ARC International (www.arc.com)
6239
 
6240

6241
File: as.info,  Node: ARM-Dependent,  Next: AVR-Dependent,  Prev: ARC-Dependent,  Up: Machine Dependencies
6242
 
6243
9.3 ARM Dependent Features
6244
==========================
6245
 
6246
* Menu:
6247
 
6248
* ARM Options::              Options
6249
* ARM Syntax::               Syntax
6250
* ARM Floating Point::       Floating Point
6251
* ARM Directives::           ARM Machine Directives
6252
* ARM Opcodes::              Opcodes
6253
* ARM Mapping Symbols::      Mapping Symbols
6254
* ARM Unwinding Tutorial::   Unwinding
6255
 
6256

6257
File: as.info,  Node: ARM Options,  Next: ARM Syntax,  Up: ARM-Dependent
6258
 
6259
9.3.1 Options
6260
-------------
6261
 
6262
`-mcpu=PROCESSOR[+EXTENSION...]'
6263
     This option specifies the target processor.  The assembler will
6264
     issue an error message if an attempt is made to assemble an
6265
     instruction which will not execute on the target processor.  The
6266
     following processor names are recognized: `arm1', `arm2', `arm250',
6267
     `arm3', `arm6', `arm60', `arm600', `arm610', `arm620', `arm7',
6268
     `arm7m', `arm7d', `arm7dm', `arm7di', `arm7dmi', `arm70', `arm700',
6269
     `arm700i', `arm710', `arm710t', `arm720', `arm720t', `arm740t',
6270
     `arm710c', `arm7100', `arm7500', `arm7500fe', `arm7t', `arm7tdmi',
6271
     `arm7tdmi-s', `arm8', `arm810', `strongarm', `strongarm1',
6272
     `strongarm110', `strongarm1100', `strongarm1110', `arm9', `arm920',
6273
     `arm920t', `arm922t', `arm940t', `arm9tdmi', `fa526' (Faraday
6274
     FA526 processor), `fa626' (Faraday FA626 processor), `arm9e',
6275
     `arm926e', `arm926ej-s', `arm946e-r0', `arm946e', `arm946e-s',
6276
     `arm966e-r0', `arm966e', `arm966e-s', `arm968e-s', `arm10t',
6277
     `arm10tdmi', `arm10e', `arm1020', `arm1020t', `arm1020e',
6278
     `arm1022e', `arm1026ej-s', `fa626te' (Faraday FA626TE processor),
6279
     `fa726te' (Faraday FA726TE processor), `arm1136j-s', `arm1136jf-s',
6280
     `arm1156t2-s', `arm1156t2f-s', `arm1176jz-s', `arm1176jzf-s',
6281
     `mpcore', `mpcorenovfp', `cortex-a8', `cortex-a9', `cortex-r4',
6282
     `cortex-m3', `cortex-m1', `cortex-m0', `ep9312' (ARM920 with
6283
     Cirrus Maverick coprocessor), `i80200' (Intel XScale processor)
6284
     `iwmmxt' (Intel(r) XScale processor with Wireless MMX(tm)
6285
     technology coprocessor) and `xscale'.  The special name `all' may
6286
     be used to allow the assembler to accept instructions valid for
6287
     any ARM processor.
6288
 
6289
     In addition to the basic instruction set, the assembler can be
6290
     told to accept various extension mnemonics that extend the
6291
     processor using the co-processor instruction space.  For example,
6292
     `-mcpu=arm920+maverick' is equivalent to specifying
6293
     `-mcpu=ep9312'.  The following extensions are currently supported:
6294
     `+maverick' `+iwmmxt' and `+xscale'.
6295
 
6296
`-march=ARCHITECTURE[+EXTENSION...]'
6297
     This option specifies the target architecture.  The assembler will
6298
     issue an error message if an attempt is made to assemble an
6299
     instruction which will not execute on the target architecture.
6300
     The following architecture names are recognized: `armv1', `armv2',
6301
     `armv2a', `armv2s', `armv3', `armv3m', `armv4', `armv4xm',
6302
     `armv4t', `armv4txm', `armv5', `armv5t', `armv5txm', `armv5te',
6303
     `armv5texp', `armv6', `armv6j', `armv6k', `armv6z', `armv6zk',
6304
     `armv7', `armv7-a', `armv7-r', `armv7-m', `iwmmxt' and `xscale'.
6305
     If both `-mcpu' and `-march' are specified, the assembler will use
6306
     the setting for `-mcpu'.
6307
 
6308
     The architecture option can be extended with the same instruction
6309
     set extension options as the `-mcpu' option.
6310
 
6311
`-mfpu=FLOATING-POINT-FORMAT'
6312
     This option specifies the floating point format to assemble for.
6313
     The assembler will issue an error message if an attempt is made to
6314
     assemble an instruction which will not execute on the target
6315
     floating point unit.  The following format options are recognized:
6316
     `softfpa', `fpe', `fpe2', `fpe3', `fpa', `fpa10', `fpa11',
6317
     `arm7500fe', `softvfp', `softvfp+vfp', `vfp', `vfp10', `vfp10-r0',
6318
     `vfp9', `vfpxd', `vfpv2' `vfpv3' `vfpv3-d16' `arm1020t',
6319
     `arm1020e', `arm1136jf-s', `maverick' and `neon'.
6320
 
6321
     In addition to determining which instructions are assembled, this
6322
     option also affects the way in which the `.double' assembler
6323
     directive behaves when assembling little-endian code.
6324
 
6325
     The default is dependent on the processor selected.  For
6326
     Architecture 5 or later, the default is to assembler for VFP
6327
     instructions; for earlier architectures the default is to assemble
6328
     for FPA instructions.
6329
 
6330
`-mthumb'
6331
     This option specifies that the assembler should start assembling
6332
     Thumb instructions; that is, it should behave as though the file
6333
     starts with a `.code 16' directive.
6334
 
6335
`-mthumb-interwork'
6336
     This option specifies that the output generated by the assembler
6337
     should be marked as supporting interworking.
6338
 
6339
`-mimplicit-it=never'
6340
`-mimplicit-it=always'
6341
`-mimplicit-it=arm'
6342
`-mimplicit-it=thumb'
6343
     The `-mimplicit-it' option controls the behavior of the assembler
6344
     when conditional instructions are not enclosed in IT blocks.
6345
     There are four possible behaviors.  If `never' is specified, such
6346
     constructs cause a warning in ARM code and an error in Thumb-2
6347
     code.  If `always' is specified, such constructs are accepted in
6348
     both ARM and Thumb-2 code, where the IT instruction is added
6349
     implicitly.  If `arm' is specified, such constructs are accepted
6350
     in ARM code and cause an error in Thumb-2 code.  If `thumb' is
6351
     specified, such constructs cause a warning in ARM code and are
6352
     accepted in Thumb-2 code.  If you omit this option, the behavior
6353
     is equivalent to `-mimplicit-it=arm'.
6354
 
6355
`-mapcs `[26|32]''
6356
     This option specifies that the output generated by the assembler
6357
     should be marked as supporting the indicated version of the Arm
6358
     Procedure.  Calling Standard.
6359
 
6360
`-matpcs'
6361
     This option specifies that the output generated by the assembler
6362
     should be marked as supporting the Arm/Thumb Procedure Calling
6363
     Standard.  If enabled this option will cause the assembler to
6364
     create an empty debugging section in the object file called
6365
     .arm.atpcs.  Debuggers can use this to determine the ABI being
6366
     used by.
6367
 
6368
`-mapcs-float'
6369
     This indicates the floating point variant of the APCS should be
6370
     used.  In this variant floating point arguments are passed in FP
6371
     registers rather than integer registers.
6372
 
6373
`-mapcs-reentrant'
6374
     This indicates that the reentrant variant of the APCS should be
6375
     used.  This variant supports position independent code.
6376
 
6377
`-mfloat-abi=ABI'
6378
     This option specifies that the output generated by the assembler
6379
     should be marked as using specified floating point ABI.  The
6380
     following values are recognized: `soft', `softfp' and `hard'.
6381
 
6382
`-meabi=VER'
6383
     This option specifies which EABI version the produced object files
6384
     should conform to.  The following values are recognized: `gnu', `4'
6385
     and `5'.
6386
 
6387
`-EB'
6388
     This option specifies that the output generated by the assembler
6389
     should be marked as being encoded for a big-endian processor.
6390
 
6391
`-EL'
6392
     This option specifies that the output generated by the assembler
6393
     should be marked as being encoded for a little-endian processor.
6394
 
6395
`-k'
6396
     This option specifies that the output of the assembler should be
6397
     marked as position-independent code (PIC).
6398
 
6399
`--fix-v4bx'
6400
     Allow `BX' instructions in ARMv4 code.  This is intended for use
6401
     with the linker option of the same name.
6402
 
6403
`-mwarn-deprecated'
6404
`-mno-warn-deprecated'
6405
     Enable or disable warnings about using deprecated options or
6406
     features.  The default is to warn.
6407
 
6408
 
6409

6410
File: as.info,  Node: ARM Syntax,  Next: ARM Floating Point,  Prev: ARM Options,  Up: ARM-Dependent
6411
 
6412
9.3.2 Syntax
6413
------------
6414
 
6415
* Menu:
6416
 
6417
* ARM-Instruction-Set::      Instruction Set
6418
* ARM-Chars::                Special Characters
6419
* ARM-Regs::                 Register Names
6420
* ARM-Relocations::          Relocations
6421
 
6422

6423
File: as.info,  Node: ARM-Instruction-Set,  Next: ARM-Chars,  Up: ARM Syntax
6424
 
6425
9.3.2.1 Instruction Set Syntax
6426
..............................
6427
 
6428
Two slightly different syntaxes are support for ARM and THUMB
6429
instructions.  The default, `divided', uses the old style where ARM and
6430
THUMB instructions had their own, separate syntaxes.  The new,
6431
`unified' syntax, which can be selected via the `.syntax' directive,
6432
and has the following main features:
6433
 
6434
*
6435
     Immediate operands do not require a `#' prefix.
6436
 
6437
*
6438
     The `IT' instruction may appear, and if it does it is validated
6439
     against subsequent conditional affixes.  In ARM mode it does not
6440
     generate machine code, in THUMB mode it does.
6441
 
6442
*
6443
     For ARM instructions the conditional affixes always appear at the
6444
     end of the instruction.  For THUMB instructions conditional
6445
     affixes can be used, but only inside the scope of an `IT'
6446
     instruction.
6447
 
6448
*
6449
     All of the instructions new to the V6T2 architecture (and later)
6450
     are available.  (Only a few such instructions can be written in the
6451
     `divided' syntax).
6452
 
6453
*
6454
     The `.N' and `.W' suffixes are recognized and honored.
6455
 
6456
*
6457
     All instructions set the flags if and only if they have an `s'
6458
     affix.
6459
 
6460

6461
File: as.info,  Node: ARM-Chars,  Next: ARM-Regs,  Prev: ARM-Instruction-Set,  Up: ARM Syntax
6462
 
6463
9.3.2.2 Special Characters
6464
..........................
6465
 
6466
The presence of a `@' on a line indicates the start of a comment that
6467
extends to the end of the current line.  If a `#' appears as the first
6468
character of a line, the whole line is treated as a comment.
6469
 
6470
   The `;' character can be used instead of a newline to separate
6471
statements.
6472
 
6473
   Either `#' or `$' can be used to indicate immediate operands.
6474
 
6475
   *TODO* Explain about /data modifier on symbols.
6476
 
6477

6478
File: as.info,  Node: ARM-Regs,  Next: ARM-Relocations,  Prev: ARM-Chars,  Up: ARM Syntax
6479
 
6480
9.3.2.3 Register Names
6481
......................
6482
 
6483
*TODO* Explain about ARM register naming, and the predefined names.
6484
 
6485

6486
File: as.info,  Node: ARM Floating Point,  Next: ARM Directives,  Prev: ARM Syntax,  Up: ARM-Dependent
6487
 
6488
9.3.3 Floating Point
6489
--------------------
6490
 
6491
The ARM family uses IEEE floating-point numbers.
6492
 
6493

6494
File: as.info,  Node: ARM-Relocations,  Prev: ARM-Regs,  Up: ARM Syntax
6495
 
6496
9.3.3.1 ARM relocation generation
6497
.................................
6498
 
6499
Specific data relocations can be generated by putting the relocation
6500
name in parentheses after the symbol name.  For example:
6501
 
6502
             .word foo(TARGET1)
6503
 
6504
   This will generate an `R_ARM_TARGET1' relocation against the symbol
6505
FOO.  The following relocations are supported: `GOT', `GOTOFF',
6506
`TARGET1', `TARGET2', `SBREL', `TLSGD', `TLSLDM', `TLSLDO', `GOTTPOFF'
6507
and `TPOFF'.
6508
 
6509
   For compatibility with older toolchains the assembler also accepts
6510
`(PLT)' after branch targets.  This will generate the deprecated
6511
`R_ARM_PLT32' relocation.
6512
 
6513
   Relocations for `MOVW' and `MOVT' instructions can be generated by
6514
prefixing the value with `#:lower16:' and `#:upper16' respectively.
6515
For example to load the 32-bit address of foo into r0:
6516
 
6517
             MOVW r0, #:lower16:foo
6518
             MOVT r0, #:upper16:foo
6519
 
6520

6521
File: as.info,  Node: ARM Directives,  Next: ARM Opcodes,  Prev: ARM Floating Point,  Up: ARM-Dependent
6522
 
6523
9.3.4 ARM Machine Directives
6524
----------------------------
6525
 
6526
`.2byte EXPRESSION [, EXPRESSION]*'
6527
`.4byte EXPRESSION [, EXPRESSION]*'
6528
`.8byte EXPRESSION [, EXPRESSION]*'
6529
     These directives write 2, 4 or 8 byte values to the output section.
6530
 
6531
`.align EXPRESSION [, EXPRESSION]'
6532
     This is the generic .ALIGN directive.  For the ARM however if the
6533
     first argument is zero (ie no alignment is needed) the assembler
6534
     will behave as if the argument had been 2 (ie pad to the next four
6535
     byte boundary).  This is for compatibility with ARM's own
6536
     assembler.
6537
 
6538
`.arch NAME'
6539
     Select the target architecture.  Valid values for NAME are the
6540
     same as for the `-march' commandline option.
6541
 
6542
`.arm'
6543
     This performs the same action as .CODE 32.
6544
 
6545
`.pad #COUNT'
6546
     Generate unwinder annotations for a stack adjustment of COUNT
6547
     bytes.  A positive value indicates the function prologue allocated
6548
     stack space by decrementing the stack pointer.
6549
 
6550
`.bss'
6551
     This directive switches to the `.bss' section.
6552
 
6553
`.cantunwind'
6554
     Prevents unwinding through the current function.  No personality
6555
     routine or exception table data is required or permitted.
6556
 
6557
`.code `[16|32]''
6558
     This directive selects the instruction set being generated. The
6559
     value 16 selects Thumb, with the value 32 selecting ARM.
6560
 
6561
`.cpu NAME'
6562
     Select the target processor.  Valid values for NAME are the same as
6563
     for the `-mcpu' commandline option.
6564
 
6565
`NAME .dn REGISTER NAME [.TYPE] [[INDEX]]'
6566
 
6567
`NAME .qn REGISTER NAME [.TYPE] [[INDEX]]'
6568
     The `dn' and `qn' directives are used to create typed and/or
6569
     indexed register aliases for use in Advanced SIMD Extension (Neon)
6570
     instructions.  The former should be used to create aliases of
6571
     double-precision registers, and the latter to create aliases of
6572
     quad-precision registers.
6573
 
6574
     If these directives are used to create typed aliases, those
6575
     aliases can be used in Neon instructions instead of writing types
6576
     after the mnemonic or after each operand.  For example:
6577
 
6578
                  x .dn d2.f32
6579
                  y .dn d3.f32
6580
                  z .dn d4.f32[1]
6581
                  vmul x,y,z
6582
 
6583
     This is equivalent to writing the following:
6584
 
6585
                  vmul.f32 d2,d3,d4[1]
6586
 
6587
     Aliases created using `dn' or `qn' can be destroyed using `unreq'.
6588
 
6589
`.eabi_attribute TAG, VALUE'
6590
     Set the EABI object attribute TAG to VALUE.
6591
 
6592
     The TAG is either an attribute number, or one of the following:
6593
     `Tag_CPU_raw_name', `Tag_CPU_name', `Tag_CPU_arch',
6594
     `Tag_CPU_arch_profile', `Tag_ARM_ISA_use', `Tag_THUMB_ISA_use',
6595
     `Tag_VFP_arch', `Tag_WMMX_arch', `Tag_Advanced_SIMD_arch',
6596
     `Tag_PCS_config', `Tag_ABI_PCS_R9_use', `Tag_ABI_PCS_RW_data',
6597
     `Tag_ABI_PCS_RO_data', `Tag_ABI_PCS_GOT_use',
6598
     `Tag_ABI_PCS_wchar_t', `Tag_ABI_FP_rounding',
6599
     `Tag_ABI_FP_denormal', `Tag_ABI_FP_exceptions',
6600
     `Tag_ABI_FP_user_exceptions', `Tag_ABI_FP_number_model',
6601
     `Tag_ABI_align8_needed', `Tag_ABI_align8_preserved',
6602
     `Tag_ABI_enum_size', `Tag_ABI_HardFP_use', `Tag_ABI_VFP_args',
6603
     `Tag_ABI_WMMX_args', `Tag_ABI_optimization_goals',
6604
     `Tag_ABI_FP_optimization_goals', `Tag_compatibility',
6605
     `Tag_CPU_unaligned_access', `Tag_VFP_HP_extension',
6606
     `Tag_ABI_FP_16bit_format', `Tag_nodefaults',
6607
     `Tag_also_compatible_with', `Tag_conformance', `Tag_T2EE_use',
6608
     `Tag_Virtualization_use', `Tag_MPextension_use'
6609
 
6610
     The VALUE is either a `number', `"string"', or `number, "string"'
6611
     depending on the tag.
6612
 
6613
`.even'
6614
     This directive aligns to an even-numbered address.
6615
 
6616
`.extend  EXPRESSION [, EXPRESSION]*'
6617
`.ldouble  EXPRESSION [, EXPRESSION]*'
6618
     These directives write 12byte long double floating-point values to
6619
     the output section.  These are not compatible with current ARM
6620
     processors or ABIs.
6621
 
6622
`.fnend'
6623
     Marks the end of a function with an unwind table entry.  The
6624
     unwind index table entry is created when this directive is
6625
     processed.
6626
 
6627
     If no personality routine has been specified then standard
6628
     personality routine 0 or 1 will be used, depending on the number
6629
     of unwind opcodes required.
6630
 
6631
`.fnstart'
6632
     Marks the start of a function with an unwind table entry.
6633
 
6634
`.force_thumb'
6635
     This directive forces the selection of Thumb instructions, even if
6636
     the target processor does not support those instructions
6637
 
6638
`.fpu NAME'
6639
     Select the floating-point unit to assemble for.  Valid values for
6640
     NAME are the same as for the `-mfpu' commandline option.
6641
 
6642
`.handlerdata'
6643
     Marks the end of the current function, and the start of the
6644
     exception table entry for that function.  Anything between this
6645
     directive and the `.fnend' directive will be added to the
6646
     exception table entry.
6647
 
6648
     Must be preceded by a `.personality' or `.personalityindex'
6649
     directive.
6650
 
6651
`.inst OPCODE [ , ... ]'
6652
 
6653
`.inst.n OPCODE [ , ... ]'
6654
 
6655
`.inst.w OPCODE [ , ... ]'
6656
     Generates the instruction corresponding to the numerical value
6657
     OPCODE.  `.inst.n' and `.inst.w' allow the Thumb instruction size
6658
     to be specified explicitly, overriding the normal encoding rules.
6659
 
6660
`.ldouble  EXPRESSION [, EXPRESSION]*'
6661
     See `.extend'.
6662
 
6663
`.ltorg'
6664
     This directive causes the current contents of the literal pool to
6665
     be dumped into the current section (which is assumed to be the
6666
     .text section) at the current location (aligned to a word
6667
     boundary).  `GAS' maintains a separate literal pool for each
6668
     section and each sub-section.  The `.ltorg' directive will only
6669
     affect the literal pool of the current section and sub-section.
6670
     At the end of assembly all remaining, un-empty literal pools will
6671
     automatically be dumped.
6672
 
6673
     Note - older versions of `GAS' would dump the current literal pool
6674
     any time a section change occurred.  This is no longer done, since
6675
     it prevents accurate control of the placement of literal pools.
6676
 
6677
`.movsp REG [, #OFFSET]'
6678
     Tell the unwinder that REG contains an offset from the current
6679
     stack pointer.  If OFFSET is not specified then it is assumed to be
6680
     zero.
6681
 
6682
`.object_arch NAME'
6683
     Override the architecture recorded in the EABI object attribute
6684
     section.  Valid values for NAME are the same as for the `.arch'
6685
     directive.  Typically this is useful when code uses runtime
6686
     detection of CPU features.
6687
 
6688
`.packed  EXPRESSION [, EXPRESSION]*'
6689
     This directive writes 12-byte packed floating-point values to the
6690
     output section.  These are not compatible with current ARM
6691
     processors or ABIs.
6692
 
6693
`.pad #COUNT'
6694
     Generate unwinder annotations for a stack adjustment of COUNT
6695
     bytes.  A positive value indicates the function prologue allocated
6696
     stack space by decrementing the stack pointer.
6697
 
6698
`.personality NAME'
6699
     Sets the personality routine for the current function to NAME.
6700
 
6701
`.personalityindex INDEX'
6702
     Sets the personality routine for the current function to the EABI
6703
     standard routine number INDEX
6704
 
6705
`.pool'
6706
     This is a synonym for .ltorg.
6707
 
6708
`NAME .req REGISTER NAME'
6709
     This creates an alias for REGISTER NAME called NAME.  For example:
6710
 
6711
                  foo .req r0
6712
 
6713
`.save REGLIST'
6714
     Generate unwinder annotations to restore the registers in REGLIST.
6715
     The format of REGLIST is the same as the corresponding
6716
     store-multiple instruction.
6717
 
6718
     _core registers_
6719
            .save {r4, r5, r6, lr}
6720
            stmfd sp!, {r4, r5, r6, lr}
6721
     _FPA registers_
6722
            .save f4, 2
6723
            sfmfd f4, 2, [sp]!
6724
     _VFP registers_
6725
            .save {d8, d9, d10}
6726
            fstmdx sp!, {d8, d9, d10}
6727
     _iWMMXt registers_
6728
            .save {wr10, wr11}
6729
            wstrd wr11, [sp, #-8]!
6730
            wstrd wr10, [sp, #-8]!
6731
          or
6732
            .save wr11
6733
            wstrd wr11, [sp, #-8]!
6734
            .save wr10
6735
            wstrd wr10, [sp, #-8]!
6736
 
6737
`.setfp FPREG, SPREG [, #OFFSET]'
6738
     Make all unwinder annotations relative to a frame pointer.
6739
     Without this the unwinder will use offsets from the stack pointer.
6740
 
6741
     The syntax of this directive is the same as the `sub' or `mov'
6742
     instruction used to set the frame pointer.  SPREG must be either
6743
     `sp' or mentioned in a previous `.movsp' directive.
6744
 
6745
          .movsp ip
6746
          mov ip, sp
6747
          ...
6748
          .setfp fp, ip, #4
6749
          sub fp, ip, #4
6750
 
6751
`.secrel32 EXPRESSION [, EXPRESSION]*'
6752
     This directive emits relocations that evaluate to the
6753
     section-relative offset of each expression's symbol.  This
6754
     directive is only supported for PE targets.
6755
 
6756
`.syntax [`unified' | `divided']'
6757
     This directive sets the Instruction Set Syntax as described in the
6758
     *Note ARM-Instruction-Set:: section.
6759
 
6760
`.thumb'
6761
     This performs the same action as .CODE 16.
6762
 
6763
`.thumb_func'
6764
     This directive specifies that the following symbol is the name of a
6765
     Thumb encoded function.  This information is necessary in order to
6766
     allow the assembler and linker to generate correct code for
6767
     interworking between Arm and Thumb instructions and should be used
6768
     even if interworking is not going to be performed.  The presence
6769
     of this directive also implies `.thumb'
6770
 
6771
     This directive is not neccessary when generating EABI objects.  On
6772
     these targets the encoding is implicit when generating Thumb code.
6773
 
6774
`.thumb_set'
6775
     This performs the equivalent of a `.set' directive in that it
6776
     creates a symbol which is an alias for another symbol (possibly
6777
     not yet defined).  This directive also has the added property in
6778
     that it marks the aliased symbol as being a thumb function entry
6779
     point, in the same way that the `.thumb_func' directive does.
6780
 
6781
`.unreq ALIAS-NAME'
6782
     This undefines a register alias which was previously defined using
6783
     the `req', `dn' or `qn' directives.  For example:
6784
 
6785
                  foo .req r0
6786
                  .unreq foo
6787
 
6788
     An error occurs if the name is undefined.  Note - this pseudo op
6789
     can be used to delete builtin in register name aliases (eg 'r0').
6790
     This should only be done if it is really necessary.
6791
 
6792
`.unwind_raw OFFSET, BYTE1, ...'
6793
     Insert one of more arbitary unwind opcode bytes, which are known
6794
     to adjust the stack pointer by OFFSET bytes.
6795
 
6796
     For example `.unwind_raw 4, 0xb1, 0x01' is equivalent to `.save
6797
     {r0}'
6798
 
6799
`.vsave VFP-REGLIST'
6800
     Generate unwinder annotations to restore the VFP registers in
6801
     VFP-REGLIST using FLDMD.  Also works for VFPv3 registers that are
6802
     to be restored using VLDM.  The format of VFP-REGLIST is the same
6803
     as the corresponding store-multiple instruction.
6804
 
6805
     _VFP registers_
6806
            .vsave {d8, d9, d10}
6807
            fstmdd sp!, {d8, d9, d10}
6808
     _VFPv3 registers_
6809
            .vsave {d15, d16, d17}
6810
            vstm sp!, {d15, d16, d17}
6811
 
6812
     Since FLDMX and FSTMX are now deprecated, this directive should be
6813
     used in favour of `.save' for saving VFP registers for ARMv6 and
6814
     above.
6815
 
6816
 
6817

6818
File: as.info,  Node: ARM Opcodes,  Next: ARM Mapping Symbols,  Prev: ARM Directives,  Up: ARM-Dependent
6819
 
6820
9.3.5 Opcodes
6821
-------------
6822
 
6823
`as' implements all the standard ARM opcodes.  It also implements
6824
several pseudo opcodes, including several synthetic load instructions.
6825
 
6826
`NOP'
6827
            nop
6828
 
6829
     This pseudo op will always evaluate to a legal ARM instruction
6830
     that does nothing.  Currently it will evaluate to MOV r0, r0.
6831
 
6832
`LDR'
6833
            ldr  , = 
6834
 
6835
     If expression evaluates to a numeric constant then a MOV or MVN
6836
     instruction will be used in place of the LDR instruction, if the
6837
     constant can be generated by either of these instructions.
6838
     Otherwise the constant will be placed into the nearest literal
6839
     pool (if it not already there) and a PC relative LDR instruction
6840
     will be generated.
6841
 
6842
`ADR'
6843
            adr  
6844
 
6845
     This instruction will load the address of LABEL into the indicated
6846
     register.  The instruction will evaluate to a PC relative ADD or
6847
     SUB instruction depending upon where the label is located.  If the
6848
     label is out of range, or if it is not defined in the same file
6849
     (and section) as the ADR instruction, then an error will be
6850
     generated.  This instruction will not make use of the literal pool.
6851
 
6852
`ADRL'
6853
            adrl  
6854
 
6855
     This instruction will load the address of LABEL into the indicated
6856
     register.  The instruction will evaluate to one or two PC relative
6857
     ADD or SUB instructions depending upon where the label is located.
6858
     If a second instruction is not needed a NOP instruction will be
6859
     generated in its place, so that this instruction is always 8 bytes
6860
     long.
6861
 
6862
     If the label is out of range, or if it is not defined in the same
6863
     file (and section) as the ADRL instruction, then an error will be
6864
     generated.  This instruction will not make use of the literal pool.
6865
 
6866
 
6867
   For information on the ARM or Thumb instruction sets, see `ARM
6868
Software Development Toolkit Reference Manual', Advanced RISC Machines
6869
Ltd.
6870
 
6871

6872
File: as.info,  Node: ARM Mapping Symbols,  Next: ARM Unwinding Tutorial,  Prev: ARM Opcodes,  Up: ARM-Dependent
6873
 
6874
9.3.6 Mapping Symbols
6875
---------------------
6876
 
6877
The ARM ELF specification requires that special symbols be inserted
6878
into object files to mark certain features:
6879
 
6880
`$a'
6881
     At the start of a region of code containing ARM instructions.
6882
 
6883
`$t'
6884
     At the start of a region of code containing THUMB instructions.
6885
 
6886
`$d'
6887
     At the start of a region of data.
6888
 
6889
 
6890
   The assembler will automatically insert these symbols for you - there
6891
is no need to code them yourself.  Support for tagging symbols ($b, $f,
6892
$p and $m) which is also mentioned in the current ARM ELF specification
6893
is not implemented.  This is because they have been dropped from the
6894
new EABI and so tools cannot rely upon their presence.
6895
 
6896

6897
File: as.info,  Node: ARM Unwinding Tutorial,  Prev: ARM Mapping Symbols,  Up: ARM-Dependent
6898
 
6899
9.3.7 Unwinding
6900
---------------
6901
 
6902
The ABI for the ARM Architecture specifies a standard format for
6903
exception unwind information.  This information is used when an
6904
exception is thrown to determine where control should be transferred.
6905
In particular, the unwind information is used to determine which
6906
function called the function that threw the exception, and which
6907
function called that one, and so forth.  This information is also used
6908
to restore the values of callee-saved registers in the function
6909
catching the exception.
6910
 
6911
   If you are writing functions in assembly code, and those functions
6912
call other functions that throw exceptions, you must use assembly
6913
pseudo ops to ensure that appropriate exception unwind information is
6914
generated.  Otherwise, if one of the functions called by your assembly
6915
code throws an exception, the run-time library will be unable to unwind
6916
the stack through your assembly code and your program will not behave
6917
correctly.
6918
 
6919
   To illustrate the use of these pseudo ops, we will examine the code
6920
that G++ generates for the following C++ input:
6921
 
6922
 
6923
void callee (int *);
6924
 
6925
int
6926
caller ()
6927
{
6928
  int i;
6929
  callee (&i);
6930
  return i;
6931
}
6932
 
6933
   This example does not show how to throw or catch an exception from
6934
assembly code.  That is a much more complex operation and should always
6935
be done in a high-level language, such as C++, that directly supports
6936
exceptions.
6937
 
6938
   The code generated by one particular version of G++ when compiling
6939
the example above is:
6940
 
6941
 
6942
_Z6callerv:
6943
        .fnstart
6944
.LFB2:
6945
        @ Function supports interworking.
6946
        @ args = 0, pretend = 0, frame = 8
6947
        @ frame_needed = 1, uses_anonymous_args = 0
6948
        stmfd   sp!, {fp, lr}
6949
        .save {fp, lr}
6950
.LCFI0:
6951
        .setfp fp, sp, #4
6952
        add     fp, sp, #4
6953
.LCFI1:
6954
        .pad #8
6955
        sub     sp, sp, #8
6956
.LCFI2:
6957
        sub     r3, fp, #8
6958
        mov     r0, r3
6959
        bl      _Z6calleePi
6960
        ldr     r3, [fp, #-8]
6961
        mov     r0, r3
6962
        sub     sp, fp, #4
6963
        ldmfd   sp!, {fp, lr}
6964
        bx      lr
6965
.LFE2:
6966
        .fnend
6967
 
6968
   Of course, the sequence of instructions varies based on the options
6969
you pass to GCC and on the version of GCC in use.  The exact
6970
instructions are not important since we are focusing on the pseudo ops
6971
that are used to generate unwind information.
6972
 
6973
   An important assumption made by the unwinder is that the stack frame
6974
does not change during the body of the function.  In particular, since
6975
we assume that the assembly code does not itself throw an exception,
6976
the only point where an exception can be thrown is from a call, such as
6977
the `bl' instruction above.  At each call site, the same saved
6978
registers (including `lr', which indicates the return address) must be
6979
located in the same locations relative to the frame pointer.
6980
 
6981
   The `.fnstart' (*note .fnstart pseudo op: arm_fnstart.) pseudo op
6982
appears immediately before the first instruction of the function while
6983
the `.fnend' (*note .fnend pseudo op: arm_fnend.) pseudo op appears
6984
immediately after the last instruction of the function.  These pseudo
6985
ops specify the range of the function.
6986
 
6987
   Only the order of the other pseudos ops (e.g., `.setfp' or `.pad')
6988
matters; their exact locations are irrelevant.  In the example above,
6989
the compiler emits the pseudo ops with particular instructions.  That
6990
makes it easier to understand the code, but it is not required for
6991
correctness.  It would work just as well to emit all of the pseudo ops
6992
other than `.fnend' in the same order, but immediately after `.fnstart'.
6993
 
6994
   The `.save' (*note .save pseudo op: arm_save.) pseudo op indicates
6995
registers that have been saved to the stack so that they can be
6996
restored before the function returns.  The argument to the `.save'
6997
pseudo op is a list of registers to save.  If a register is
6998
"callee-saved" (as specified by the ABI) and is modified by the
6999
function you are writing, then your code must save the value before it
7000
is modified and restore the original value before the function returns.
7001
If an exception is thrown, the run-time library restores the values of
7002
these registers from their locations on the stack before returning
7003
control to the exception handler.  (Of course, if an exception is not
7004
thrown, the function that contains the `.save' pseudo op restores these
7005
registers in the function epilogue, as is done with the `ldmfd'
7006
instruction above.)
7007
 
7008
   You do not have to save callee-saved registers at the very beginning
7009
of the function and you do not need to use the `.save' pseudo op
7010
immediately following the point at which the registers are saved.
7011
However, if you modify a callee-saved register, you must save it on the
7012
stack before modifying it and before calling any functions which might
7013
throw an exception.  And, you must use the `.save' pseudo op to
7014
indicate that you have done so.
7015
 
7016
   The `.pad' (*note .pad: arm_pad.) pseudo op indicates a modification
7017
of the stack pointer that does not save any registers.  The argument is
7018
the number of bytes (in decimal) that are subtracted from the stack
7019
pointer.  (On ARM CPUs, the stack grows downwards, so subtracting from
7020
the stack pointer increases the size of the stack.)
7021
 
7022
   The `.setfp' (*note .setfp pseudo op: arm_setfp.) pseudo op
7023
indicates the register that contains the frame pointer.  The first
7024
argument is the register that is set, which is typically `fp'.  The
7025
second argument indicates the register from which the frame pointer
7026
takes its value.  The third argument, if present, is the value (in
7027
decimal) added to the register specified by the second argument to
7028
compute the value of the frame pointer.  You should not modify the
7029
frame pointer in the body of the function.
7030
 
7031
   If you do not use a frame pointer, then you should not use the
7032
`.setfp' pseudo op.  If you do not use a frame pointer, then you should
7033
avoid modifying the stack pointer outside of the function prologue.
7034
Otherwise, the run-time library will be unable to find saved registers
7035
when it is unwinding the stack.
7036
 
7037
   The pseudo ops described above are sufficient for writing assembly
7038
code that calls functions which may throw exceptions.  If you need to
7039
know more about the object-file format used to represent unwind
7040
information, you may consult the `Exception Handling ABI for the ARM
7041
Architecture' available from `http://infocenter.arm.com'.
7042
 
7043

7044
File: as.info,  Node: AVR-Dependent,  Next: Blackfin-Dependent,  Prev: ARM-Dependent,  Up: Machine Dependencies
7045
 
7046
9.4 AVR Dependent Features
7047
==========================
7048
 
7049
* Menu:
7050
 
7051
* AVR Options::              Options
7052
* AVR Syntax::               Syntax
7053
* AVR Opcodes::              Opcodes
7054
 
7055

7056
File: as.info,  Node: AVR Options,  Next: AVR Syntax,  Up: AVR-Dependent
7057
 
7058
9.4.1 Options
7059
-------------
7060
 
7061
`-mmcu=MCU'
7062
     Specify ATMEL AVR instruction set or MCU type.
7063
 
7064
     Instruction set avr1 is for the minimal AVR core, not supported by
7065
     the C compiler, only for assembler programs (MCU types: at90s1200,
7066
     attiny11, attiny12, attiny15, attiny28).
7067
 
7068
     Instruction set avr2 (default) is for the classic AVR core with up
7069
     to 8K program memory space (MCU types: at90s2313, at90s2323,
7070
     at90s2333, at90s2343, attiny22, attiny26, at90s4414, at90s4433,
7071
     at90s4434, at90s8515, at90c8534, at90s8535).
7072
 
7073
     Instruction set avr25 is for the classic AVR core with up to 8K
7074
     program memory space plus the MOVW instruction (MCU types:
7075
     attiny13, attiny13a, attiny2313, attiny2313a, attiny24, attiny24a,
7076
     attiny4313, attiny44, attiny44a, attiny84, attiny25, attiny45,
7077
     attiny85, attiny261, attiny261a, attiny461, attiny861, attiny861a,
7078
     attiny87, attiny43u, attiny48, attiny88, at86rf401, ata6289).
7079
 
7080
     Instruction set avr3 is for the classic AVR core with up to 128K
7081
     program memory space (MCU types: at43usb355, at76c711).
7082
 
7083
     Instruction set avr31 is for the classic AVR core with exactly
7084
     128K program memory space (MCU types: atmega103, at43usb320).
7085
 
7086
     Instruction set avr35 is for classic AVR core plus MOVW, CALL, and
7087
     JMP instructions (MCU types: attiny167, attiny327, at90usb82,
7088
     at90usb162, atmega8u2, atmega16u2, atmega32u2).
7089
 
7090
     Instruction set avr4 is for the enhanced AVR core with up to 8K
7091
     program memory space (MCU types: atmega48, atmega48p,atmega8,
7092
     atmega88, atmega88p, atmega8515, atmega8535, atmega8hva,
7093
     atmega4hvd, atmega8hvd, at90pwm1, at90pwm2, at90pwm2b, at90pwm3,
7094
     at90pwm3b, at90pwm81, atmega8m1, atmega8c1).
7095
 
7096
     Instruction set avr5 is for the enhanced AVR core with up to 128K
7097
     program memory space (MCU types: atmega16, atmega161, atmega162,
7098
     atmega163, atmega164p, atmega165, atmega165p, atmega168,
7099
     atmega168p, atmega169, atmega169p, atmega16c1, atmega32,
7100
     atmega323, atmega324p, atmega325, atmega325p, atmega3250,
7101
     atmega3250p, atmega328p, atmega329, atmega329p, atmega3290,
7102
     atmega3290p, atmega406, atmega64, atmega640, atmega644,
7103
     atmega644p, atmega644pa, atmega645, atmega6450, atmega649,
7104
     atmega6490, atmega16hva, atmega16hvb, atmega32hvb, at90can32,
7105
     at90can64, at90pwm216, at90pwm316, atmega32c1, atmega64c1,
7106
     atmega16m1, atmega32m1, atmega64m1, atmega16u4, atmega32u4,
7107
     atmega32u6, at90usb646, at90usb647, at94k, at90scr100).
7108
 
7109
     Instruction set avr51 is for the enhanced AVR core with exactly
7110
     128K program memory space (MCU types: atmega128, atmega1280,
7111
     atmega1281, atmega1284p, atmega128rfa1, at90can128, at90usb1286,
7112
     at90usb1287, m3000f, m3000s, m3001b).
7113
 
7114
     Instruction set avr6 is for the enhanced AVR core with a 3-byte PC
7115
     (MCU types: atmega2560, atmega2561).
7116
 
7117
`-mall-opcodes'
7118
     Accept all AVR opcodes, even if not supported by `-mmcu'.
7119
 
7120
`-mno-skip-bug'
7121
     This option disable warnings for skipping two-word instructions.
7122
 
7123
`-mno-wrap'
7124
     This option reject `rjmp/rcall' instructions with 8K wrap-around.
7125
 
7126
 
7127

7128
File: as.info,  Node: AVR Syntax,  Next: AVR Opcodes,  Prev: AVR Options,  Up: AVR-Dependent
7129
 
7130
9.4.2 Syntax
7131
------------
7132
 
7133
* Menu:
7134
 
7135
* AVR-Chars::                Special Characters
7136
* AVR-Regs::                 Register Names
7137
* AVR-Modifiers::            Relocatable Expression Modifiers
7138
 
7139

7140
File: as.info,  Node: AVR-Chars,  Next: AVR-Regs,  Up: AVR Syntax
7141
 
7142
9.4.2.1 Special Characters
7143
..........................
7144
 
7145
The presence of a `;' on a line indicates the start of a comment that
7146
extends to the end of the current line.  If a `#' appears as the first
7147
character of a line, the whole line is treated as a comment.
7148
 
7149
   The `$' character can be used instead of a newline to separate
7150
statements.
7151
 
7152

7153
File: as.info,  Node: AVR-Regs,  Next: AVR-Modifiers,  Prev: AVR-Chars,  Up: AVR Syntax
7154
 
7155
9.4.2.2 Register Names
7156
......................
7157
 
7158
The AVR has 32 x 8-bit general purpose working registers `r0', `r1',
7159
... `r31'.  Six of the 32 registers can be used as three 16-bit
7160
indirect address register pointers for Data Space addressing. One of
7161
the these address pointers can also be used as an address pointer for
7162
look up tables in Flash program memory. These added function registers
7163
are the 16-bit `X', `Y' and `Z' - registers.
7164
 
7165
     X = r26:r27
7166
     Y = r28:r29
7167
     Z = r30:r31
7168
 
7169

7170
File: as.info,  Node: AVR-Modifiers,  Prev: AVR-Regs,  Up: AVR Syntax
7171
 
7172
9.4.2.3 Relocatable Expression Modifiers
7173
........................................
7174
 
7175
The assembler supports several modifiers when using relocatable
7176
addresses in AVR instruction operands.  The general syntax is the
7177
following:
7178
 
7179
     modifier(relocatable-expression)
7180
 
7181
`lo8'
7182
     This modifier allows you to use bits 0 through 7 of an address
7183
     expression as 8 bit relocatable expression.
7184
 
7185
`hi8'
7186
     This modifier allows you to use bits 7 through 15 of an address
7187
     expression as 8 bit relocatable expression.  This is useful with,
7188
     for example, the AVR `ldi' instruction and `lo8' modifier.
7189
 
7190
     For example
7191
 
7192
          ldi r26, lo8(sym+10)
7193
          ldi r27, hi8(sym+10)
7194
 
7195
`hh8'
7196
     This modifier allows you to use bits 16 through 23 of an address
7197
     expression as 8 bit relocatable expression.  Also, can be useful
7198
     for loading 32 bit constants.
7199
 
7200
`hlo8'
7201
     Synonym of `hh8'.
7202
 
7203
`hhi8'
7204
     This modifier allows you to use bits 24 through 31 of an
7205
     expression as 8 bit expression. This is useful with, for example,
7206
     the AVR `ldi' instruction and `lo8', `hi8', `hlo8', `hhi8',
7207
     modifier.
7208
 
7209
     For example
7210
 
7211
          ldi r26, lo8(285774925)
7212
          ldi r27, hi8(285774925)
7213
          ldi r28, hlo8(285774925)
7214
          ldi r29, hhi8(285774925)
7215
          ; r29,r28,r27,r26 = 285774925
7216
 
7217
`pm_lo8'
7218
     This modifier allows you to use bits 0 through 7 of an address
7219
     expression as 8 bit relocatable expression.  This modifier useful
7220
     for addressing data or code from Flash/Program memory. The using
7221
     of `pm_lo8' similar to `lo8'.
7222
 
7223
`pm_hi8'
7224
     This modifier allows you to use bits 8 through 15 of an address
7225
     expression as 8 bit relocatable expression.  This modifier useful
7226
     for addressing data or code from Flash/Program memory.
7227
 
7228
`pm_hh8'
7229
     This modifier allows you to use bits 15 through 23 of an address
7230
     expression as 8 bit relocatable expression.  This modifier useful
7231
     for addressing data or code from Flash/Program memory.
7232
 
7233
 
7234

7235
File: as.info,  Node: AVR Opcodes,  Prev: AVR Syntax,  Up: AVR-Dependent
7236
 
7237
9.4.3 Opcodes
7238
-------------
7239
 
7240
For detailed information on the AVR machine instruction set, see
7241
`www.atmel.com/products/AVR'.
7242
 
7243
   `as' implements all the standard AVR opcodes.  The following table
7244
summarizes the AVR opcodes, and their arguments.
7245
 
7246
     Legend:
7247
        r   any register
7248
        d   `ldi' register (r16-r31)
7249
        v   `movw' even register (r0, r2, ..., r28, r30)
7250
        a   `fmul' register (r16-r23)
7251
        w   `adiw' register (r24,r26,r28,r30)
7252
        e   pointer registers (X,Y,Z)
7253
        b   base pointer register and displacement ([YZ]+disp)
7254
        z   Z pointer register (for [e]lpm Rd,Z[+])
7255
        M   immediate value from 0 to 255
7256
        n   immediate value from 0 to 255 ( n = ~M ). Relocation impossible
7257
        s   immediate value from 0 to 7
7258
        P   Port address value from 0 to 63. (in, out)
7259
        p   Port address value from 0 to 31. (cbi, sbi, sbic, sbis)
7260
        K   immediate value from 0 to 63 (used in `adiw', `sbiw')
7261
        i   immediate value
7262
        l   signed pc relative offset from -64 to 63
7263
        L   signed pc relative offset from -2048 to 2047
7264
        h   absolute code address (call, jmp)
7265
        S   immediate value from 0 to 7 (S = s << 4)
7266
        ?   use this opcode entry if no parameters, else use next opcode entry
7267
 
7268
     1001010010001000   clc
7269
     1001010011011000   clh
7270
     1001010011111000   cli
7271
     1001010010101000   cln
7272
     1001010011001000   cls
7273
     1001010011101000   clt
7274
     1001010010111000   clv
7275
     1001010010011000   clz
7276
     1001010000001000   sec
7277
     1001010001011000   seh
7278
     1001010001111000   sei
7279
     1001010000101000   sen
7280
     1001010001001000   ses
7281
     1001010001101000   set
7282
     1001010000111000   sev
7283
     1001010000011000   sez
7284
     100101001SSS1000   bclr    S
7285
     100101000SSS1000   bset    S
7286
     1001010100001001   icall
7287
     1001010000001001   ijmp
7288
     1001010111001000   lpm     ?
7289
     1001000ddddd010+   lpm     r,z
7290
     1001010111011000   elpm    ?
7291
     1001000ddddd011+   elpm    r,z
7292
     0000000000000000   nop
7293
     1001010100001000   ret
7294
     1001010100011000   reti
7295
     1001010110001000   sleep
7296
     1001010110011000   break
7297
     1001010110101000   wdr
7298
     1001010111101000   spm
7299
     000111rdddddrrrr   adc     r,r
7300
     000011rdddddrrrr   add     r,r
7301
     001000rdddddrrrr   and     r,r
7302
     000101rdddddrrrr   cp      r,r
7303
     000001rdddddrrrr   cpc     r,r
7304
     000100rdddddrrrr   cpse    r,r
7305
     001001rdddddrrrr   eor     r,r
7306
     001011rdddddrrrr   mov     r,r
7307
     100111rdddddrrrr   mul     r,r
7308
     001010rdddddrrrr   or      r,r
7309
     000010rdddddrrrr   sbc     r,r
7310
     000110rdddddrrrr   sub     r,r
7311
     001001rdddddrrrr   clr     r
7312
     000011rdddddrrrr   lsl     r
7313
     000111rdddddrrrr   rol     r
7314
     001000rdddddrrrr   tst     r
7315
     0111KKKKddddKKKK   andi    d,M
7316
     0111KKKKddddKKKK   cbr     d,n
7317
     1110KKKKddddKKKK   ldi     d,M
7318
     11101111dddd1111   ser     d
7319
     0110KKKKddddKKKK   ori     d,M
7320
     0110KKKKddddKKKK   sbr     d,M
7321
     0011KKKKddddKKKK   cpi     d,M
7322
     0100KKKKddddKKKK   sbci    d,M
7323
     0101KKKKddddKKKK   subi    d,M
7324
     1111110rrrrr0sss   sbrc    r,s
7325
     1111111rrrrr0sss   sbrs    r,s
7326
     1111100ddddd0sss   bld     r,s
7327
     1111101ddddd0sss   bst     r,s
7328
     10110PPdddddPPPP   in      r,P
7329
     10111PPrrrrrPPPP   out     P,r
7330
     10010110KKddKKKK   adiw    w,K
7331
     10010111KKddKKKK   sbiw    w,K
7332
     10011000pppppsss   cbi     p,s
7333
     10011010pppppsss   sbi     p,s
7334
     10011001pppppsss   sbic    p,s
7335
     10011011pppppsss   sbis    p,s
7336
     111101lllllll000   brcc    l
7337
     111100lllllll000   brcs    l
7338
     111100lllllll001   breq    l
7339
     111101lllllll100   brge    l
7340
     111101lllllll101   brhc    l
7341
     111100lllllll101   brhs    l
7342
     111101lllllll111   brid    l
7343
     111100lllllll111   brie    l
7344
     111100lllllll000   brlo    l
7345
     111100lllllll100   brlt    l
7346
     111100lllllll010   brmi    l
7347
     111101lllllll001   brne    l
7348
     111101lllllll010   brpl    l
7349
     111101lllllll000   brsh    l
7350
     111101lllllll110   brtc    l
7351
     111100lllllll110   brts    l
7352
     111101lllllll011   brvc    l
7353
     111100lllllll011   brvs    l
7354
     111101lllllllsss   brbc    s,l
7355
     111100lllllllsss   brbs    s,l
7356
     1101LLLLLLLLLLLL   rcall   L
7357
     1100LLLLLLLLLLLL   rjmp    L
7358
     1001010hhhhh111h   call    h
7359
     1001010hhhhh110h   jmp     h
7360
     1001010rrrrr0101   asr     r
7361
     1001010rrrrr0000   com     r
7362
     1001010rrrrr1010   dec     r
7363
     1001010rrrrr0011   inc     r
7364
     1001010rrrrr0110   lsr     r
7365
     1001010rrrrr0001   neg     r
7366
     1001000rrrrr1111   pop     r
7367
     1001001rrrrr1111   push    r
7368
     1001010rrrrr0111   ror     r
7369
     1001010rrrrr0010   swap    r
7370
     00000001ddddrrrr   movw    v,v
7371
     00000010ddddrrrr   muls    d,d
7372
     000000110ddd0rrr   mulsu   a,a
7373
     000000110ddd1rrr   fmul    a,a
7374
     000000111ddd0rrr   fmuls   a,a
7375
     000000111ddd1rrr   fmulsu  a,a
7376
     1001001ddddd0000   sts     i,r
7377
     1001000ddddd0000   lds     r,i
7378
     10o0oo0dddddbooo   ldd     r,b
7379
     100!000dddddee-+   ld      r,e
7380
     10o0oo1rrrrrbooo   std     b,r
7381
     100!001rrrrree-+   st      e,r
7382
     1001010100011001   eicall
7383
     1001010000011001   eijmp
7384
 
7385

7386
File: as.info,  Node: Blackfin-Dependent,  Next: CR16-Dependent,  Prev: AVR-Dependent,  Up: Machine Dependencies
7387
 
7388
9.5 Blackfin Dependent Features
7389
===============================
7390
 
7391
* Menu:
7392
 
7393
* Blackfin Options::            Blackfin Options
7394
* Blackfin Syntax::             Blackfin Syntax
7395
* Blackfin Directives::         Blackfin Directives
7396
 
7397

7398
File: as.info,  Node: Blackfin Options,  Next: Blackfin Syntax,  Up: Blackfin-Dependent
7399
 
7400
9.5.1 Options
7401
-------------
7402
 
7403
`-mcpu=PROCESSOR[-SIREVISION]'
7404
     This option specifies the target processor.  The optional
7405
     SIREVISION is not used in assembler.  It's here such that GCC can
7406
     easily pass down its `-mcpu=' option.  The assembler will issue an
7407
     error message if an attempt is made to assemble an instruction
7408
     which will not execute on the target processor.  The following
7409
     processor names are recognized: `bf512', `bf514', `bf516', `bf518',
7410
     `bf522', `bf523', `bf524', `bf525', `bf526', `bf527', `bf531',
7411
     `bf532', `bf533', `bf534', `bf535' (not implemented yet), `bf536',
7412
     `bf537', `bf538', `bf539', `bf542', `bf542m', `bf544', `bf544m',
7413
     `bf547', `bf547m', `bf548', `bf548m', `bf549', `bf549m', and
7414
     `bf561'.
7415
 
7416
 
7417

7418
File: as.info,  Node: Blackfin Syntax,  Next: Blackfin Directives,  Prev: Blackfin Options,  Up: Blackfin-Dependent
7419
 
7420
9.5.2 Syntax
7421
------------
7422
 
7423
`Special Characters'
7424
     Assembler input is free format and may appear anywhere on the line.
7425
     One instruction may extend across multiple lines or more than one
7426
     instruction may appear on the same line.  White space (space, tab,
7427
     comments or newline) may appear anywhere between tokens.  A token
7428
     must not have embedded spaces.  Tokens include numbers, register
7429
     names, keywords, user identifiers, and also some multicharacter
7430
     special symbols like "+=", "/*" or "||".
7431
 
7432
`Instruction Delimiting'
7433
     A semicolon must terminate every instruction.  Sometimes a complete
7434
     instruction will consist of more than one operation.  There are two
7435
     cases where this occurs.  The first is when two general operations
7436
     are combined.  Normally a comma separates the different parts, as
7437
     in
7438
 
7439
          a0= r3.h * r2.l, a1 = r3.l * r2.h ;
7440
 
7441
     The second case occurs when a general instruction is combined with
7442
     one or two memory references for joint issue.  The latter portions
7443
     are set off by a "||" token.
7444
 
7445
          a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];
7446
 
7447
`Register Names'
7448
     The assembler treats register names and instruction keywords in a
7449
     case insensitive manner.  User identifiers are case sensitive.
7450
     Thus, R3.l, R3.L, r3.l and r3.L are all equivalent input to the
7451
     assembler.
7452
 
7453
     Register names are reserved and may not be used as program
7454
     identifiers.
7455
 
7456
     Some operations (such as "Move Register") require a register pair.
7457
     Register pairs are always data registers and are denoted using a
7458
     colon, eg., R3:2.  The larger number must be written firsts.  Note
7459
     that the hardware only supports odd-even pairs, eg., R7:6, R5:4,
7460
     R3:2, and R1:0.
7461
 
7462
     Some instructions (such as -SP (Push Multiple)) require a group of
7463
     adjacent registers.  Adjacent registers are denoted in the syntax
7464
     by the range enclosed in parentheses and separated by a colon,
7465
     eg., (R7:3).  Again, the larger number appears first.
7466
 
7467
     Portions of a particular register may be individually specified.
7468
     This is written with a dot (".") following the register name and
7469
     then a letter denoting the desired portion.  For 32-bit registers,
7470
     ".H" denotes the most significant ("High") portion.  ".L" denotes
7471
     the least-significant portion.  The subdivisions of the 40-bit
7472
     registers are described later.
7473
 
7474
`Accumulators'
7475
     The set of 40-bit registers A1 and A0 that normally contain data
7476
     that is being manipulated.  Each accumulator can be accessed in
7477
     four ways.
7478
 
7479
    `one 40-bit register'
7480
          The register will be referred to as A1 or A0.
7481
 
7482
    `one 32-bit register'
7483
          The registers are designated as A1.W or A0.W.
7484
 
7485
    `two 16-bit registers'
7486
          The registers are designated as A1.H, A1.L, A0.H or A0.L.
7487
 
7488
    `one 8-bit register'
7489
          The registers are designated as A1.X or A0.X for the bits that
7490
          extend beyond bit 31.
7491
 
7492
`Data Registers'
7493
     The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7)
7494
     that normally contain data for manipulation.  These are
7495
     abbreviated as D-register or Dreg.  Data registers can be accessed
7496
     as 32-bit registers or as two independent 16-bit registers.  The
7497
     least significant 16 bits of each register is called the "low"
7498
     half and is designated with ".L" following the register name.  The
7499
     most significant 16 bits are called the "high" half and is
7500
     designated with ".H" following the name.
7501
 
7502
             R7.L, r2.h, r4.L, R0.H
7503
 
7504
`Pointer Registers'
7505
     The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP)
7506
     that normally contain byte addresses of data structures.  These are
7507
     abbreviated as P-register or Preg.
7508
 
7509
          p2, p5, fp, sp
7510
 
7511
`Stack Pointer SP'
7512
     The stack pointer contains the 32-bit address of the last occupied
7513
     byte location in the stack.  The stack grows by decrementing the
7514
     stack pointer.
7515
 
7516
`Frame Pointer FP'
7517
     The frame pointer contains the 32-bit address of the previous frame
7518
     pointer in the stack.  It is located at the top of a frame.
7519
 
7520
`Loop Top'
7521
     LT0 and LT1.  These registers contain the 32-bit address of the
7522
     top of a zero overhead loop.
7523
 
7524
`Loop Count'
7525
     LC0 and LC1.  These registers contain the 32-bit counter of the
7526
     zero overhead loop executions.
7527
 
7528
`Loop Bottom'
7529
     LB0 and LB1.  These registers contain the 32-bit address of the
7530
     bottom of a zero overhead loop.
7531
 
7532
`Index Registers'
7533
     The set of 32-bit registers (I0, I1, I2, I3) that normally contain
7534
     byte addresses of data structures.  Abbreviated I-register or Ireg.
7535
 
7536
`Modify Registers'
7537
     The set of 32-bit registers (M0, M1, M2, M3) that normally contain
7538
     offset values that are added and subracted to one of the index
7539
     registers.  Abbreviated as Mreg.
7540
 
7541
`Length Registers'
7542
     The set of 32-bit registers (L0, L1, L2, L3) that normally contain
7543
     the length in bytes of the circular buffer.  Abbreviated as Lreg.
7544
     Clear the Lreg to disable circular addressing for the
7545
     corresponding Ireg.
7546
 
7547
`Base Registers'
7548
     The set of 32-bit registers (B0, B1, B2, B3) that normally contain
7549
     the base address in bytes of the circular buffer.  Abbreviated as
7550
     Breg.
7551
 
7552
`Floating Point'
7553
     The Blackfin family has no hardware floating point but the .float
7554
     directive generates ieee floating point numbers for use with
7555
     software floating point libraries.
7556
 
7557
`Blackfin Opcodes'
7558
     For detailed information on the Blackfin machine instruction set,
7559
     see the Blackfin(r) Processor Instruction Set Reference.
7560
 
7561
 
7562

7563
File: as.info,  Node: Blackfin Directives,  Prev: Blackfin Syntax,  Up: Blackfin-Dependent
7564
 
7565
9.5.3 Directives
7566
----------------
7567
 
7568
The following directives are provided for compatibility with the VDSP
7569
assembler.
7570
 
7571
`.byte2'
7572
     Initializes a four byte data object.
7573
 
7574
`.byte4'
7575
     Initializes a two byte data object.
7576
 
7577
`.db'
7578
     TBD
7579
 
7580
`.dd'
7581
     TBD
7582
 
7583
`.dw'
7584
     TBD
7585
 
7586
`.var'
7587
     Define and initialize a 32 bit data object.
7588
 
7589

7590
File: as.info,  Node: CR16-Dependent,  Next: CRIS-Dependent,  Prev: Blackfin-Dependent,  Up: Machine Dependencies
7591
 
7592
9.6 CR16 Dependent Features
7593
===========================
7594
 
7595
* Menu:
7596
 
7597
* CR16 Operand Qualifiers::     CR16 Machine Operand Qualifiers
7598
 
7599

7600
File: as.info,  Node: CR16 Operand Qualifiers,  Up: CR16-Dependent
7601
 
7602
9.6.1 CR16 Operand Qualifiers
7603
-----------------------------
7604
 
7605
The National Semiconductor CR16 target of `as' has a few machine
7606
dependent operand qualifiers.
7607
 
7608
   Operand expression type qualifier is an optional field in the
7609
instruction operand, to determines the type of the expression field of
7610
an operand. The `@' is required. CR16 architecture uses one of the
7611
following expression qualifiers:
7612
 
7613
`s'
7614
     - `Specifies expression operand type as small'
7615
 
7616
`m'
7617
     - `Specifies expression operand type as medium'
7618
 
7619
`l'
7620
     - `Specifies expression operand type as large'
7621
 
7622
`c'
7623
     - `Specifies the CR16 Assembler generates a relocation entry for
7624
     the operand, where pc has implied bit, the expression is adjusted
7625
     accordingly. The linker uses the relocation entry to update the
7626
     operand address at link time.'
7627
 
7628
`got/GOT'
7629
     - `Specifies the CR16 Assembler generates a relocation entry for
7630
     the operand, offset from Global Offset Table. The linker uses this
7631
     relocation entry to update the operand address at link time'
7632
 
7633
`cgot/cGOT'
7634
     - `Specifies the CompactRISC Assembler generates a relocation
7635
     entry for the operand, where pc has implied bit, the expression is
7636
     adjusted accordingly. The linker uses the relocation entry to
7637
     update the operand address at link time.'
7638
 
7639
   CR16 target operand qualifiers and its size (in bits):
7640
 
7641
`Immediate Operand'
7642
     - s --- 4 bits
7643
 
7644
`'
7645
     - m --- 16 bits, for movb and movw instructions.
7646
 
7647
`'
7648
     - m --- 20 bits, movd instructions.
7649
 
7650
`'
7651
     - l --- 32 bits
7652
 
7653
`Absolute Operand'
7654
     - s --- Illegal specifier for this operand.
7655
 
7656
`'
7657
     - m --- 20 bits, movd instructions.
7658
 
7659
`Displacement Operand'
7660
     - s --- 8 bits
7661
 
7662
`'
7663
     - m --- 16 bits
7664
 
7665
`'
7666
     - l --- 24 bits
7667
 
7668
   For example:
7669
     1   `movw $_myfun@c,r1'
7670
 
7671
         This loads the address of _myfun, shifted right by 1, into r1.
7672
 
7673
     2   `movd $_myfun@c,(r2,r1)'
7674
 
7675
         This loads the address of _myfun, shifted right by 1, into register-pair r2-r1.
7676
 
7677
     3   `_myfun_ptr:'
7678
         `.long _myfun@c'
7679
         `loadd _myfun_ptr, (r1,r0)'
7680
         `jal (r1,r0)'
7681
 
7682
         This .long directive, the address of _myfunc, shifted right by 1 at link time.
7683
 
7684
     4   `loadd  _data1@GOT(r12), (r1,r0)'
7685
 
7686
         This loads the address of _data1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r2-r1.
7687
 
7688
     5   `loadd  _myfunc@cGOT(r12), (r1,r0)'
7689
 
7690
         This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0.
7691
 
7692

7693
File: as.info,  Node: CRIS-Dependent,  Next: D10V-Dependent,  Prev: CR16-Dependent,  Up: Machine Dependencies
7694
 
7695
9.7 CRIS Dependent Features
7696
===========================
7697
 
7698
* Menu:
7699
 
7700
* CRIS-Opts::              Command-line Options
7701
* CRIS-Expand::            Instruction expansion
7702
* CRIS-Symbols::           Symbols
7703
* CRIS-Syntax::            Syntax
7704
 
7705

7706
File: as.info,  Node: CRIS-Opts,  Next: CRIS-Expand,  Up: CRIS-Dependent
7707
 
7708
9.7.1 Command-line Options
7709
--------------------------
7710
 
7711
The CRIS version of `as' has these machine-dependent command-line
7712
options.
7713
 
7714
   The format of the generated object files can be either ELF or a.out,
7715
specified by the command-line options `--emulation=crisaout' and
7716
`--emulation=criself'.  The default is ELF (criself), unless `as' has
7717
been configured specifically for a.out by using the configuration name
7718
`cris-axis-aout'.
7719
 
7720
   There are two different link-incompatible ELF object file variants
7721
for CRIS, for use in environments where symbols are expected to be
7722
prefixed by a leading `_' character and for environments without such a
7723
symbol prefix.  The variant used for GNU/Linux port has no symbol
7724
prefix.  Which variant to produce is specified by either of the options
7725
`--underscore' and `--no-underscore'.  The default is `--underscore'.
7726
Since symbols in CRIS a.out objects are expected to have a `_' prefix,
7727
specifying `--no-underscore' when generating a.out objects is an error.
7728
Besides the object format difference, the effect of this option is to
7729
parse register names differently (*note crisnous::).  The
7730
`--no-underscore' option makes a `$' register prefix mandatory.
7731
 
7732
   The option `--pic' must be passed to `as' in order to recognize the
7733
symbol syntax used for ELF (SVR4 PIC) position-independent-code (*note
7734
crispic::).  This will also affect expansion of instructions.  The
7735
expansion with `--pic' will use PC-relative rather than (slightly
7736
faster) absolute addresses in those expansions.
7737
 
7738
   The option `--march=ARCHITECTURE' specifies the recognized
7739
instruction set and recognized register names.  It also controls the
7740
architecture type of the object file.  Valid values for ARCHITECTURE
7741
are:
7742
`v0_v10'
7743
     All instructions and register names for any architecture variant
7744
     in the set v0...v10 are recognized.  This is the default if the
7745
     target is configured as cris-*.
7746
 
7747
`v10'
7748
     Only instructions and register names for CRIS v10 (as found in
7749
     ETRAX 100 LX) are recognized.  This is the default if the target
7750
     is configured as crisv10-*.
7751
 
7752
`v32'
7753
     Only instructions and register names for CRIS v32 (code name
7754
     Guinness) are recognized.  This is the default if the target is
7755
     configured as crisv32-*.  This value implies `--no-mul-bug-abort'.
7756
     (A subsequent `--mul-bug-abort' will turn it back on.)
7757
 
7758
`common_v10_v32'
7759
     Only instructions with register names and addressing modes with
7760
     opcodes common to the v10 and v32 are recognized.
7761
 
7762
   When `-N' is specified, `as' will emit a warning when a 16-bit
7763
branch instruction is expanded into a 32-bit multiple-instruction
7764
construct (*note CRIS-Expand::).
7765
 
7766
   Some versions of the CRIS v10, for example in the Etrax 100 LX,
7767
contain a bug that causes destabilizing memory accesses when a multiply
7768
instruction is executed with certain values in the first operand just
7769
before a cache-miss.  When the `--mul-bug-abort' command line option is
7770
active (the default value), `as' will refuse to assemble a file
7771
containing a multiply instruction at a dangerous offset, one that could
7772
be the last on a cache-line, or is in a section with insufficient
7773
alignment.  This placement checking does not catch any case where the
7774
multiply instruction is dangerously placed because it is located in a
7775
delay-slot.  The `--mul-bug-abort' command line option turns off the
7776
checking.
7777
 
7778

7779
File: as.info,  Node: CRIS-Expand,  Next: CRIS-Symbols,  Prev: CRIS-Opts,  Up: CRIS-Dependent
7780
 
7781
9.7.2 Instruction expansion
7782
---------------------------
7783
 
7784
`as' will silently choose an instruction that fits the operand size for
7785
`[register+constant]' operands.  For example, the offset `127' in
7786
`move.d [r3+127],r4' fits in an instruction using a signed-byte offset.
7787
Similarly, `move.d [r2+32767],r1' will generate an instruction using a
7788
16-bit offset.  For symbolic expressions and constants that do not fit
7789
in 16 bits including the sign bit, a 32-bit offset is generated.
7790
 
7791
   For branches, `as' will expand from a 16-bit branch instruction into
7792
a sequence of instructions that can reach a full 32-bit address.  Since
7793
this does not correspond to a single instruction, such expansions can
7794
optionally be warned about.  *Note CRIS-Opts::.
7795
 
7796
   If the operand is found to fit the range, a `lapc' mnemonic will
7797
translate to a `lapcq' instruction.  Use `lapc.d' to force the 32-bit
7798
`lapc' instruction.
7799
 
7800
   Similarly, the `addo' mnemonic will translate to the shortest
7801
fitting instruction of `addoq', `addo.w' and `addo.d', when used with a
7802
operand that is a constant known at assembly time.
7803
 
7804

7805
File: as.info,  Node: CRIS-Symbols,  Next: CRIS-Syntax,  Prev: CRIS-Expand,  Up: CRIS-Dependent
7806
 
7807
9.7.3 Symbols
7808
-------------
7809
 
7810
Some symbols are defined by the assembler.  They're intended to be used
7811
in conditional assembly, for example:
7812
      .if ..asm.arch.cris.v32
7813
      CODE FOR CRIS V32
7814
      .elseif ..asm.arch.cris.common_v10_v32
7815
      CODE COMMON TO CRIS V32 AND CRIS V10
7816
      .elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10
7817
      CODE FOR V10
7818
      .else
7819
      .error "Code needs to be added here."
7820
      .endif
7821
 
7822
   These symbols are defined in the assembler, reflecting command-line
7823
options, either when specified or the default.  They are always
7824
defined, to 0 or 1.
7825
`..asm.arch.cris.any_v0_v10'
7826
     This symbol is non-zero when `--march=v0_v10' is specified or the
7827
     default.
7828
 
7829
`..asm.arch.cris.common_v10_v32'
7830
     Set according to the option `--march=common_v10_v32'.
7831
 
7832
`..asm.arch.cris.v10'
7833
     Reflects the option `--march=v10'.
7834
 
7835
`..asm.arch.cris.v32'
7836
     Corresponds to `--march=v10'.
7837
 
7838
   Speaking of symbols, when a symbol is used in code, it can have a
7839
suffix modifying its value for use in position-independent code. *Note
7840
CRIS-Pic::.
7841
 
7842

7843
File: as.info,  Node: CRIS-Syntax,  Prev: CRIS-Symbols,  Up: CRIS-Dependent
7844
 
7845
9.7.4 Syntax
7846
------------
7847
 
7848
There are different aspects of the CRIS assembly syntax.
7849
 
7850
* Menu:
7851
 
7852
* CRIS-Chars::                  Special Characters
7853
* CRIS-Pic::                    Position-Independent Code Symbols
7854
* CRIS-Regs::                   Register Names
7855
* CRIS-Pseudos::                Assembler Directives
7856
 
7857

7858
File: as.info,  Node: CRIS-Chars,  Next: CRIS-Pic,  Up: CRIS-Syntax
7859
 
7860
9.7.4.1 Special Characters
7861
..........................
7862
 
7863
The character `#' is a line comment character.  It starts a comment if
7864
and only if it is placed at the beginning of a line.
7865
 
7866
   A `;' character starts a comment anywhere on the line, causing all
7867
characters up to the end of the line to be ignored.
7868
 
7869
   A `@' character is handled as a line separator equivalent to a
7870
logical new-line character (except in a comment), so separate
7871
instructions can be specified on a single line.
7872
 
7873

7874
File: as.info,  Node: CRIS-Pic,  Next: CRIS-Regs,  Prev: CRIS-Chars,  Up: CRIS-Syntax
7875
 
7876
9.7.4.2 Symbols in position-independent code
7877
............................................
7878
 
7879
When generating position-independent code (SVR4 PIC) for use in
7880
cris-axis-linux-gnu or crisv32-axis-linux-gnu shared libraries, symbol
7881
suffixes are used to specify what kind of run-time symbol lookup will
7882
be used, expressed in the object as different _relocation types_.
7883
Usually, all absolute symbol values must be located in a table, the
7884
_global offset table_, leaving the code position-independent;
7885
independent of values of global symbols and independent of the address
7886
of the code.  The suffix modifies the value of the symbol, into for
7887
example an index into the global offset table where the real symbol
7888
value is entered, or a PC-relative value, or a value relative to the
7889
start of the global offset table.  All symbol suffixes start with the
7890
character `:' (omitted in the list below).  Every symbol use in code or
7891
a read-only section must therefore have a PIC suffix to enable a useful
7892
shared library to be created.  Usually, these constructs must not be
7893
used with an additive constant offset as is usually allowed, i.e. no 4
7894
as in `symbol + 4' is allowed.  This restriction is checked at
7895
link-time, not at assembly-time.
7896
 
7897
`GOT'
7898
     Attaching this suffix to a symbol in an instruction causes the
7899
     symbol to be entered into the global offset table.  The value is a
7900
     32-bit index for that symbol into the global offset table.  The
7901
     name of the corresponding relocation is `R_CRIS_32_GOT'.  Example:
7902
     `move.d [$r0+extsym:GOT],$r9'
7903
 
7904
`GOT16'
7905
     Same as for `GOT', but the value is a 16-bit index into the global
7906
     offset table.  The corresponding relocation is `R_CRIS_16_GOT'.
7907
     Example: `move.d [$r0+asymbol:GOT16],$r10'
7908
 
7909
`PLT'
7910
     This suffix is used for function symbols.  It causes a _procedure
7911
     linkage table_, an array of code stubs, to be created at the time
7912
     the shared object is created or linked against, together with a
7913
     global offset table entry.  The value is a pc-relative offset to
7914
     the corresponding stub code in the procedure linkage table.  This
7915
     arrangement causes the run-time symbol resolver to be called to
7916
     look up and set the value of the symbol the first time the
7917
     function is called (at latest; depending environment variables).
7918
     It is only safe to leave the symbol unresolved this way if all
7919
     references are function calls.  The name of the relocation is
7920
     `R_CRIS_32_PLT_PCREL'.  Example: `add.d fnname:PLT,$pc'
7921
 
7922
`PLTG'
7923
     Like PLT, but the value is relative to the beginning of the global
7924
     offset table.  The relocation is `R_CRIS_32_PLT_GOTREL'.  Example:
7925
     `move.d fnname:PLTG,$r3'
7926
 
7927
`GOTPLT'
7928
     Similar to `PLT', but the value of the symbol is a 32-bit index
7929
     into the global offset table.  This is somewhat of a mix between
7930
     the effect of the `GOT' and the `PLT' suffix; the difference to
7931
     `GOT' is that there will be a procedure linkage table entry
7932
     created, and that the symbol is assumed to be a function entry and
7933
     will be resolved by the run-time resolver as with `PLT'.  The
7934
     relocation is `R_CRIS_32_GOTPLT'.  Example: `jsr
7935
     [$r0+fnname:GOTPLT]'
7936
 
7937
`GOTPLT16'
7938
     A variant of `GOTPLT' giving a 16-bit value.  Its relocation name
7939
     is `R_CRIS_16_GOTPLT'.  Example: `jsr [$r0+fnname:GOTPLT16]'
7940
 
7941
`GOTOFF'
7942
     This suffix must only be attached to a local symbol, but may be
7943
     used in an expression adding an offset.  The value is the address
7944
     of the symbol relative to the start of the global offset table.
7945
     The relocation name is `R_CRIS_32_GOTREL'.  Example: `move.d
7946
     [$r0+localsym:GOTOFF],r3'
7947
 
7948

7949
File: as.info,  Node: CRIS-Regs,  Next: CRIS-Pseudos,  Prev: CRIS-Pic,  Up: CRIS-Syntax
7950
 
7951
9.7.4.3 Register names
7952
......................
7953
 
7954
A `$' character may always prefix a general or special register name in
7955
an instruction operand but is mandatory when the option
7956
`--no-underscore' is specified or when the `.syntax register_prefix'
7957
directive is in effect (*note crisnous::).  Register names are
7958
case-insensitive.
7959
 
7960

7961
File: as.info,  Node: CRIS-Pseudos,  Prev: CRIS-Regs,  Up: CRIS-Syntax
7962
 
7963
9.7.4.4 Assembler Directives
7964
............................
7965
 
7966
There are a few CRIS-specific pseudo-directives in addition to the
7967
generic ones.  *Note Pseudo Ops::.  Constants emitted by
7968
pseudo-directives are in little-endian order for CRIS.  There is no
7969
support for floating-point-specific directives for CRIS.
7970
 
7971
`.dword EXPRESSIONS'
7972
     The `.dword' directive is a synonym for `.int', expecting zero or
7973
     more EXPRESSIONS, separated by commas.  For each expression, a
7974
     32-bit little-endian constant is emitted.
7975
 
7976
`.syntax ARGUMENT'
7977
     The `.syntax' directive takes as ARGUMENT one of the following
7978
     case-sensitive choices.
7979
 
7980
    `no_register_prefix'
7981
          The `.syntax no_register_prefix' directive makes a `$'
7982
          character prefix on all registers optional.  It overrides a
7983
          previous setting, including the corresponding effect of the
7984
          option `--no-underscore'.  If this directive is used when
7985
          ordinary symbols do not have a `_' character prefix, care
7986
          must be taken to avoid ambiguities whether an operand is a
7987
          register or a symbol; using symbols with names the same as
7988
          general or special registers then invoke undefined behavior.
7989
 
7990
    `register_prefix'
7991
          This directive makes a `$' character prefix on all registers
7992
          mandatory.  It overrides a previous setting, including the
7993
          corresponding effect of the option `--underscore'.
7994
 
7995
    `leading_underscore'
7996
          This is an assertion directive, emitting an error if the
7997
          `--no-underscore' option is in effect.
7998
 
7999
    `no_leading_underscore'
8000
          This is the opposite of the `.syntax leading_underscore'
8001
          directive and emits an error if the option `--underscore' is
8002
          in effect.
8003
 
8004
`.arch ARGUMENT'
8005
     This is an assertion directive, giving an error if the specified
8006
     ARGUMENT is not the same as the specified or default value for the
8007
     `--march=ARCHITECTURE' option (*note march-option::).
8008
 
8009
 
8010

8011
File: as.info,  Node: D10V-Dependent,  Next: D30V-Dependent,  Prev: CRIS-Dependent,  Up: Machine Dependencies
8012
 
8013
9.8 D10V Dependent Features
8014
===========================
8015
 
8016
* Menu:
8017
 
8018
* D10V-Opts::                   D10V Options
8019
* D10V-Syntax::                 Syntax
8020
* D10V-Float::                  Floating Point
8021
* D10V-Opcodes::                Opcodes
8022
 
8023

8024
File: as.info,  Node: D10V-Opts,  Next: D10V-Syntax,  Up: D10V-Dependent
8025
 
8026
9.8.1 D10V Options
8027
------------------
8028
 
8029
The Mitsubishi D10V version of `as' has a few machine dependent options.
8030
 
8031
`-O'
8032
     The D10V can often execute two sub-instructions in parallel. When
8033
     this option is used, `as' will attempt to optimize its output by
8034
     detecting when instructions can be executed in parallel.
8035
 
8036
`--nowarnswap'
8037
     To optimize execution performance, `as' will sometimes swap the
8038
     order of instructions. Normally this generates a warning. When
8039
     this option is used, no warning will be generated when
8040
     instructions are swapped.
8041
 
8042
`--gstabs-packing'
8043
 
8044
`--no-gstabs-packing'
8045
     `as' packs adjacent short instructions into a single packed
8046
     instruction. `--no-gstabs-packing' turns instruction packing off if
8047
     `--gstabs' is specified as well; `--gstabs-packing' (the default)
8048
     turns instruction packing on even when `--gstabs' is specified.
8049
 
8050

8051
File: as.info,  Node: D10V-Syntax,  Next: D10V-Float,  Prev: D10V-Opts,  Up: D10V-Dependent
8052
 
8053
9.8.2 Syntax
8054
------------
8055
 
8056
The D10V syntax is based on the syntax in Mitsubishi's D10V
8057
architecture manual.  The differences are detailed below.
8058
 
8059
* Menu:
8060
 
8061
* D10V-Size::                 Size Modifiers
8062
* D10V-Subs::                 Sub-Instructions
8063
* D10V-Chars::                Special Characters
8064
* D10V-Regs::                 Register Names
8065
* D10V-Addressing::           Addressing Modes
8066
* D10V-Word::                 @WORD Modifier
8067
 
8068

8069
File: as.info,  Node: D10V-Size,  Next: D10V-Subs,  Up: D10V-Syntax
8070
 
8071
9.8.2.1 Size Modifiers
8072
......................
8073
 
8074
The D10V version of `as' uses the instruction names in the D10V
8075
Architecture Manual.  However, the names in the manual are sometimes
8076
ambiguous.  There are instruction names that can assemble to a short or
8077
long form opcode.  How does the assembler pick the correct form?  `as'
8078
will always pick the smallest form if it can.  When dealing with a
8079
symbol that is not defined yet when a line is being assembled, it will
8080
always use the long form.  If you need to force the assembler to use
8081
either the short or long form of the instruction, you can append either
8082
`.s' (short) or `.l' (long) to it.  For example, if you are writing an
8083
assembly program and you want to do a branch to a symbol that is
8084
defined later in your program, you can write `bra.s   foo'.  Objdump
8085
and GDB will always append `.s' or `.l' to instructions which have both
8086
short and long forms.
8087
 
8088

8089
File: as.info,  Node: D10V-Subs,  Next: D10V-Chars,  Prev: D10V-Size,  Up: D10V-Syntax
8090
 
8091
9.8.2.2 Sub-Instructions
8092
........................
8093
 
8094
The D10V assembler takes as input a series of instructions, either
8095
one-per-line, or in the special two-per-line format described in the
8096
next section.  Some of these instructions will be short-form or
8097
sub-instructions.  These sub-instructions can be packed into a single
8098
instruction.  The assembler will do this automatically.  It will also
8099
detect when it should not pack instructions.  For example, when a label
8100
is defined, the next instruction will never be packaged with the
8101
previous one.  Whenever a branch and link instruction is called, it
8102
will not be packaged with the next instruction so the return address
8103
will be valid.  Nops are automatically inserted when necessary.
8104
 
8105
   If you do not want the assembler automatically making these
8106
decisions, you can control the packaging and execution type (parallel
8107
or sequential) with the special execution symbols described in the next
8108
section.
8109
 
8110

8111
File: as.info,  Node: D10V-Chars,  Next: D10V-Regs,  Prev: D10V-Subs,  Up: D10V-Syntax
8112
 
8113
9.8.2.3 Special Characters
8114
..........................
8115
 
8116
`;' and `#' are the line comment characters.  Sub-instructions may be
8117
executed in order, in reverse-order, or in parallel.  Instructions
8118
listed in the standard one-per-line format will be executed
8119
sequentially.  To specify the executing order, use the following
8120
symbols:
8121
`->'
8122
     Sequential with instruction on the left first.
8123
 
8124
`<-'
8125
     Sequential with instruction on the right first.
8126
 
8127
`||'
8128
     Parallel
8129
   The D10V syntax allows either one instruction per line, one
8130
instruction per line with the execution symbol, or two instructions per
8131
line.  For example
8132
`abs       a1      ->      abs     r0'
8133
     Execute these sequentially.  The instruction on the right is in
8134
     the right container and is executed second.
8135
 
8136
`abs       r0      <-      abs     a1'
8137
     Execute these reverse-sequentially.  The instruction on the right
8138
     is in the right container, and is executed first.
8139
 
8140
`ld2w    r2,@r8+         ||      mac     a0,r0,r7'
8141
     Execute these in parallel.
8142
 
8143
`ld2w    r2,@r8+         ||'
8144
`mac     a0,r0,r7'
8145
     Two-line format. Execute these in parallel.
8146
 
8147
`ld2w    r2,@r8+'
8148
`mac     a0,r0,r7'
8149
     Two-line format. Execute these sequentially.  Assembler will put
8150
     them in the proper containers.
8151
 
8152
`ld2w    r2,@r8+         ->'
8153
`mac     a0,r0,r7'
8154
     Two-line format. Execute these sequentially.  Same as above but
8155
     second instruction will always go into right container.
8156
   Since `$' has no special meaning, you may use it in symbol names.
8157
 
8158

8159
File: as.info,  Node: D10V-Regs,  Next: D10V-Addressing,  Prev: D10V-Chars,  Up: D10V-Syntax
8160
 
8161
9.8.2.4 Register Names
8162
......................
8163
 
8164
You can use the predefined symbols `r0' through `r15' to refer to the
8165
D10V registers.  You can also use `sp' as an alias for `r15'.  The
8166
accumulators are `a0' and `a1'.  There are special register-pair names
8167
that may optionally be used in opcodes that require even-numbered
8168
registers. Register names are not case sensitive.
8169
 
8170
   Register Pairs
8171
`r0-r1'
8172
 
8173
`r2-r3'
8174
 
8175
`r4-r5'
8176
 
8177
`r6-r7'
8178
 
8179
`r8-r9'
8180
 
8181
`r10-r11'
8182
 
8183
`r12-r13'
8184
 
8185
`r14-r15'
8186
 
8187
   The D10V also has predefined symbols for these control registers and
8188
status bits:
8189
`psw'
8190
     Processor Status Word
8191
 
8192
`bpsw'
8193
     Backup Processor Status Word
8194
 
8195
`pc'
8196
     Program Counter
8197
 
8198
`bpc'
8199
     Backup Program Counter
8200
 
8201
`rpt_c'
8202
     Repeat Count
8203
 
8204
`rpt_s'
8205
     Repeat Start address
8206
 
8207
`rpt_e'
8208
     Repeat End address
8209
 
8210
`mod_s'
8211
     Modulo Start address
8212
 
8213
`mod_e'
8214
     Modulo End address
8215
 
8216
`iba'
8217
     Instruction Break Address
8218
 
8219
`f0'
8220
     Flag 0
8221
 
8222
`f1'
8223
     Flag 1
8224
 
8225
`c'
8226
     Carry flag
8227
 
8228

8229
File: as.info,  Node: D10V-Addressing,  Next: D10V-Word,  Prev: D10V-Regs,  Up: D10V-Syntax
8230
 
8231
9.8.2.5 Addressing Modes
8232
........................
8233
 
8234
`as' understands the following addressing modes for the D10V.  `RN' in
8235
the following refers to any of the numbered registers, but _not_ the
8236
control registers.
8237
`RN'
8238
     Register direct
8239
 
8240
`@RN'
8241
     Register indirect
8242
 
8243
`@RN+'
8244
     Register indirect with post-increment
8245
 
8246
`@RN-'
8247
     Register indirect with post-decrement
8248
 
8249
`@-SP'
8250
     Register indirect with pre-decrement
8251
 
8252
`@(DISP, RN)'
8253
     Register indirect with displacement
8254
 
8255
`ADDR'
8256
     PC relative address (for branch or rep).
8257
 
8258
`#IMM'
8259
     Immediate data (the `#' is optional and ignored)
8260
 
8261

8262
File: as.info,  Node: D10V-Word,  Prev: D10V-Addressing,  Up: D10V-Syntax
8263
 
8264
9.8.2.6 @WORD Modifier
8265
......................
8266
 
8267
Any symbol followed by `@word' will be replaced by the symbol's value
8268
shifted right by 2.  This is used in situations such as loading a
8269
register with the address of a function (or any other code fragment).
8270
For example, if you want to load a register with the location of the
8271
function `main' then jump to that function, you could do it as follows:
8272
     ldi     r2, main@word
8273
     jmp     r2
8274
 
8275

8276
File: as.info,  Node: D10V-Float,  Next: D10V-Opcodes,  Prev: D10V-Syntax,  Up: D10V-Dependent
8277
 
8278
9.8.3 Floating Point
8279
--------------------
8280
 
8281
The D10V has no hardware floating point, but the `.float' and `.double'
8282
directives generates IEEE floating-point numbers for compatibility with
8283
other development tools.
8284
 
8285

8286
File: as.info,  Node: D10V-Opcodes,  Prev: D10V-Float,  Up: D10V-Dependent
8287
 
8288
9.8.4 Opcodes
8289
-------------
8290
 
8291
For detailed information on the D10V machine instruction set, see `D10V
8292
Architecture: A VLIW Microprocessor for Multimedia Applications'
8293
(Mitsubishi Electric Corp.).  `as' implements all the standard D10V
8294
opcodes.  The only changes are those described in the section on size
8295
modifiers
8296
 
8297

8298
File: as.info,  Node: D30V-Dependent,  Next: H8/300-Dependent,  Prev: D10V-Dependent,  Up: Machine Dependencies
8299
 
8300
9.9 D30V Dependent Features
8301
===========================
8302
 
8303
* Menu:
8304
 
8305
* D30V-Opts::                   D30V Options
8306
* D30V-Syntax::                 Syntax
8307
* D30V-Float::                  Floating Point
8308
* D30V-Opcodes::                Opcodes
8309
 
8310

8311
File: as.info,  Node: D30V-Opts,  Next: D30V-Syntax,  Up: D30V-Dependent
8312
 
8313
9.9.1 D30V Options
8314
------------------
8315
 
8316
The Mitsubishi D30V version of `as' has a few machine dependent options.
8317
 
8318
`-O'
8319
     The D30V can often execute two sub-instructions in parallel. When
8320
     this option is used, `as' will attempt to optimize its output by
8321
     detecting when instructions can be executed in parallel.
8322
 
8323
`-n'
8324
     When this option is used, `as' will issue a warning every time it
8325
     adds a nop instruction.
8326
 
8327
`-N'
8328
     When this option is used, `as' will issue a warning if it needs to
8329
     insert a nop after a 32-bit multiply before a load or 16-bit
8330
     multiply instruction.
8331
 
8332

8333
File: as.info,  Node: D30V-Syntax,  Next: D30V-Float,  Prev: D30V-Opts,  Up: D30V-Dependent
8334
 
8335
9.9.2 Syntax
8336
------------
8337
 
8338
The D30V syntax is based on the syntax in Mitsubishi's D30V
8339
architecture manual.  The differences are detailed below.
8340
 
8341
* Menu:
8342
 
8343
* D30V-Size::                 Size Modifiers
8344
* D30V-Subs::                 Sub-Instructions
8345
* D30V-Chars::                Special Characters
8346
* D30V-Guarded::              Guarded Execution
8347
* D30V-Regs::                 Register Names
8348
* D30V-Addressing::           Addressing Modes
8349
 
8350

8351
File: as.info,  Node: D30V-Size,  Next: D30V-Subs,  Up: D30V-Syntax
8352
 
8353
9.9.2.1 Size Modifiers
8354
......................
8355
 
8356
The D30V version of `as' uses the instruction names in the D30V
8357
Architecture Manual.  However, the names in the manual are sometimes
8358
ambiguous.  There are instruction names that can assemble to a short or
8359
long form opcode.  How does the assembler pick the correct form?  `as'
8360
will always pick the smallest form if it can.  When dealing with a
8361
symbol that is not defined yet when a line is being assembled, it will
8362
always use the long form.  If you need to force the assembler to use
8363
either the short or long form of the instruction, you can append either
8364
`.s' (short) or `.l' (long) to it.  For example, if you are writing an
8365
assembly program and you want to do a branch to a symbol that is
8366
defined later in your program, you can write `bra.s foo'.  Objdump and
8367
GDB will always append `.s' or `.l' to instructions which have both
8368
short and long forms.
8369
 
8370

8371
File: as.info,  Node: D30V-Subs,  Next: D30V-Chars,  Prev: D30V-Size,  Up: D30V-Syntax
8372
 
8373
9.9.2.2 Sub-Instructions
8374
........................
8375
 
8376
The D30V assembler takes as input a series of instructions, either
8377
one-per-line, or in the special two-per-line format described in the
8378
next section.  Some of these instructions will be short-form or
8379
sub-instructions.  These sub-instructions can be packed into a single
8380
instruction.  The assembler will do this automatically.  It will also
8381
detect when it should not pack instructions.  For example, when a label
8382
is defined, the next instruction will never be packaged with the
8383
previous one.  Whenever a branch and link instruction is called, it
8384
will not be packaged with the next instruction so the return address
8385
will be valid.  Nops are automatically inserted when necessary.
8386
 
8387
   If you do not want the assembler automatically making these
8388
decisions, you can control the packaging and execution type (parallel
8389
or sequential) with the special execution symbols described in the next
8390
section.
8391
 
8392

8393
File: as.info,  Node: D30V-Chars,  Next: D30V-Guarded,  Prev: D30V-Subs,  Up: D30V-Syntax
8394
 
8395
9.9.2.3 Special Characters
8396
..........................
8397
 
8398
`;' and `#' are the line comment characters.  Sub-instructions may be
8399
executed in order, in reverse-order, or in parallel.  Instructions
8400
listed in the standard one-per-line format will be executed
8401
sequentially unless you use the `-O' option.
8402
 
8403
   To specify the executing order, use the following symbols:
8404
`->'
8405
     Sequential with instruction on the left first.
8406
 
8407
`<-'
8408
     Sequential with instruction on the right first.
8409
 
8410
`||'
8411
     Parallel
8412
 
8413
   The D30V syntax allows either one instruction per line, one
8414
instruction per line with the execution symbol, or two instructions per
8415
line.  For example
8416
`abs r2,r3 -> abs r4,r5'
8417
     Execute these sequentially.  The instruction on the right is in
8418
     the right container and is executed second.
8419
 
8420
`abs r2,r3 <- abs r4,r5'
8421
     Execute these reverse-sequentially.  The instruction on the right
8422
     is in the right container, and is executed first.
8423
 
8424
`abs r2,r3 || abs r4,r5'
8425
     Execute these in parallel.
8426
 
8427
`ldw r2,@(r3,r4) ||'
8428
`mulx r6,r8,r9'
8429
     Two-line format. Execute these in parallel.
8430
 
8431
`mulx a0,r8,r9'
8432
`stw r2,@(r3,r4)'
8433
     Two-line format. Execute these sequentially unless `-O' option is
8434
     used.  If the `-O' option is used, the assembler will determine if
8435
     the instructions could be done in parallel (the above two
8436
     instructions can be done in parallel), and if so, emit them as
8437
     parallel instructions.  The assembler will put them in the proper
8438
     containers.  In the above example, the assembler will put the
8439
     `stw' instruction in left container and the `mulx' instruction in
8440
     the right container.
8441
 
8442
`stw r2,@(r3,r4) ->'
8443
`mulx a0,r8,r9'
8444
     Two-line format.  Execute the `stw' instruction followed by the
8445
     `mulx' instruction sequentially.  The first instruction goes in the
8446
     left container and the second instruction goes into right
8447
     container.  The assembler will give an error if the machine
8448
     ordering constraints are violated.
8449
 
8450
`stw r2,@(r3,r4) <-'
8451
`mulx a0,r8,r9'
8452
     Same as previous example, except that the `mulx' instruction is
8453
     executed before the `stw' instruction.
8454
 
8455
   Since `$' has no special meaning, you may use it in symbol names.
8456
 
8457

8458
File: as.info,  Node: D30V-Guarded,  Next: D30V-Regs,  Prev: D30V-Chars,  Up: D30V-Syntax
8459
 
8460
9.9.2.4 Guarded Execution
8461
.........................
8462
 
8463
`as' supports the full range of guarded execution directives for each
8464
instruction.  Just append the directive after the instruction proper.
8465
The directives are:
8466
 
8467
`/tx'
8468
     Execute the instruction if flag f0 is true.
8469
 
8470
`/fx'
8471
     Execute the instruction if flag f0 is false.
8472
 
8473
`/xt'
8474
     Execute the instruction if flag f1 is true.
8475
 
8476
`/xf'
8477
     Execute the instruction if flag f1 is false.
8478
 
8479
`/tt'
8480
     Execute the instruction if both flags f0 and f1 are true.
8481
 
8482
`/tf'
8483
     Execute the instruction if flag f0 is true and flag f1 is false.
8484
 
8485

8486
File: as.info,  Node: D30V-Regs,  Next: D30V-Addressing,  Prev: D30V-Guarded,  Up: D30V-Syntax
8487
 
8488
9.9.2.5 Register Names
8489
......................
8490
 
8491
You can use the predefined symbols `r0' through `r63' to refer to the
8492
D30V registers.  You can also use `sp' as an alias for `r63' and `link'
8493
as an alias for `r62'.  The accumulators are `a0' and `a1'.
8494
 
8495
   The D30V also has predefined symbols for these control registers and
8496
status bits:
8497
`psw'
8498
     Processor Status Word
8499
 
8500
`bpsw'
8501
     Backup Processor Status Word
8502
 
8503
`pc'
8504
     Program Counter
8505
 
8506
`bpc'
8507
     Backup Program Counter
8508
 
8509
`rpt_c'
8510
     Repeat Count
8511
 
8512
`rpt_s'
8513
     Repeat Start address
8514
 
8515
`rpt_e'
8516
     Repeat End address
8517
 
8518
`mod_s'
8519
     Modulo Start address
8520
 
8521
`mod_e'
8522
     Modulo End address
8523
 
8524
`iba'
8525
     Instruction Break Address
8526
 
8527
`f0'
8528
     Flag 0
8529
 
8530
`f1'
8531
     Flag 1
8532
 
8533
`f2'
8534
     Flag 2
8535
 
8536
`f3'
8537
     Flag 3
8538
 
8539
`f4'
8540
     Flag 4
8541
 
8542
`f5'
8543
     Flag 5
8544
 
8545
`f6'
8546
     Flag 6
8547
 
8548
`f7'
8549
     Flag 7
8550
 
8551
`s'
8552
     Same as flag 4 (saturation flag)
8553
 
8554
`v'
8555
     Same as flag 5 (overflow flag)
8556
 
8557
`va'
8558
     Same as flag 6 (sticky overflow flag)
8559
 
8560
`c'
8561
     Same as flag 7 (carry/borrow flag)
8562
 
8563
`b'
8564
     Same as flag 7 (carry/borrow flag)
8565
 
8566

8567
File: as.info,  Node: D30V-Addressing,  Prev: D30V-Regs,  Up: D30V-Syntax
8568
 
8569
9.9.2.6 Addressing Modes
8570
........................
8571
 
8572
`as' understands the following addressing modes for the D30V.  `RN' in
8573
the following refers to any of the numbered registers, but _not_ the
8574
control registers.
8575
`RN'
8576
     Register direct
8577
 
8578
`@RN'
8579
     Register indirect
8580
 
8581
`@RN+'
8582
     Register indirect with post-increment
8583
 
8584
`@RN-'
8585
     Register indirect with post-decrement
8586
 
8587
`@-SP'
8588
     Register indirect with pre-decrement
8589
 
8590
`@(DISP, RN)'
8591
     Register indirect with displacement
8592
 
8593
`ADDR'
8594
     PC relative address (for branch or rep).
8595
 
8596
`#IMM'
8597
     Immediate data (the `#' is optional and ignored)
8598
 
8599

8600
File: as.info,  Node: D30V-Float,  Next: D30V-Opcodes,  Prev: D30V-Syntax,  Up: D30V-Dependent
8601
 
8602
9.9.3 Floating Point
8603
--------------------
8604
 
8605
The D30V has no hardware floating point, but the `.float' and `.double'
8606
directives generates IEEE floating-point numbers for compatibility with
8607
other development tools.
8608
 
8609

8610
File: as.info,  Node: D30V-Opcodes,  Prev: D30V-Float,  Up: D30V-Dependent
8611
 
8612
9.9.4 Opcodes
8613
-------------
8614
 
8615
For detailed information on the D30V machine instruction set, see `D30V
8616
Architecture: A VLIW Microprocessor for Multimedia Applications'
8617
(Mitsubishi Electric Corp.).  `as' implements all the standard D30V
8618
opcodes.  The only changes are those described in the section on size
8619
modifiers
8620
 
8621

8622
File: as.info,  Node: H8/300-Dependent,  Next: HPPA-Dependent,  Prev: D30V-Dependent,  Up: Machine Dependencies
8623
 
8624
9.10 H8/300 Dependent Features
8625
==============================
8626
 
8627
* Menu:
8628
 
8629
* H8/300 Options::              Options
8630
* H8/300 Syntax::               Syntax
8631
* H8/300 Floating Point::       Floating Point
8632
* H8/300 Directives::           H8/300 Machine Directives
8633
* H8/300 Opcodes::              Opcodes
8634
 
8635

8636
File: as.info,  Node: H8/300 Options,  Next: H8/300 Syntax,  Up: H8/300-Dependent
8637
 
8638
9.10.1 Options
8639
--------------
8640
 
8641
The Renesas H8/300 version of `as' has one machine-dependent option:
8642
 
8643
`-h-tick-hex'
8644
     Support H'00 style hex constants in addition to 0x00 style.
8645
 
8646
 
8647

8648
File: as.info,  Node: H8/300 Syntax,  Next: H8/300 Floating Point,  Prev: H8/300 Options,  Up: H8/300-Dependent
8649
 
8650
9.10.2 Syntax
8651
-------------
8652
 
8653
* Menu:
8654
 
8655
* H8/300-Chars::                Special Characters
8656
* H8/300-Regs::                 Register Names
8657
* H8/300-Addressing::           Addressing Modes
8658
 
8659

8660
File: as.info,  Node: H8/300-Chars,  Next: H8/300-Regs,  Up: H8/300 Syntax
8661
 
8662
9.10.2.1 Special Characters
8663
...........................
8664
 
8665
`;' is the line comment character.
8666
 
8667
   `$' can be used instead of a newline to separate statements.
8668
Therefore _you may not use `$' in symbol names_ on the H8/300.
8669
 
8670

8671
File: as.info,  Node: H8/300-Regs,  Next: H8/300-Addressing,  Prev: H8/300-Chars,  Up: H8/300 Syntax
8672
 
8673
9.10.2.2 Register Names
8674
.......................
8675
 
8676
You can use predefined symbols of the form `rNh' and `rNl' to refer to
8677
the H8/300 registers as sixteen 8-bit general-purpose registers.  N is
8678
a digit from `0' to `7'); for instance, both `r0h' and `r7l' are valid
8679
register names.
8680
 
8681
   You can also use the eight predefined symbols `rN' to refer to the
8682
H8/300 registers as 16-bit registers (you must use this form for
8683
addressing).
8684
 
8685
   On the H8/300H, you can also use the eight predefined symbols `erN'
8686
(`er0' ... `er7') to refer to the 32-bit general purpose registers.
8687
 
8688
   The two control registers are called `pc' (program counter; a 16-bit
8689
register, except on the H8/300H where it is 24 bits) and `ccr'
8690
(condition code register; an 8-bit register).  `r7' is used as the
8691
stack pointer, and can also be called `sp'.
8692
 
8693

8694
File: as.info,  Node: H8/300-Addressing,  Prev: H8/300-Regs,  Up: H8/300 Syntax
8695
 
8696
9.10.2.3 Addressing Modes
8697
.........................
8698
 
8699
as understands the following addressing modes for the H8/300:
8700
`rN'
8701
     Register direct
8702
 
8703
`@rN'
8704
     Register indirect
8705
 
8706
`@(D, rN)'
8707
`@(D:16, rN)'
8708
`@(D:24, rN)'
8709
     Register indirect: 16-bit or 24-bit displacement D from register
8710
     N.  (24-bit displacements are only meaningful on the H8/300H.)
8711
 
8712
`@rN+'
8713
     Register indirect with post-increment
8714
 
8715
`@-rN'
8716
     Register indirect with pre-decrement
8717
 
8718
``@'AA'
8719
``@'AA:8'
8720
``@'AA:16'
8721
``@'AA:24'
8722
     Absolute address `aa'.  (The address size `:24' only makes sense
8723
     on the H8/300H.)
8724
 
8725
`#XX'
8726
`#XX:8'
8727
`#XX:16'
8728
`#XX:32'
8729
     Immediate data XX.  You may specify the `:8', `:16', or `:32' for
8730
     clarity, if you wish; but `as' neither requires this nor uses
8731
     it--the data size required is taken from context.
8732
 
8733
``@'`@'AA'
8734
``@'`@'AA:8'
8735
     Memory indirect.  You may specify the `:8' for clarity, if you
8736
     wish; but `as' neither requires this nor uses it.
8737
 
8738

8739
File: as.info,  Node: H8/300 Floating Point,  Next: H8/300 Directives,  Prev: H8/300 Syntax,  Up: H8/300-Dependent
8740
 
8741
9.10.3 Floating Point
8742
---------------------
8743
 
8744
The H8/300 family has no hardware floating point, but the `.float'
8745
directive generates IEEE floating-point numbers for compatibility with
8746
other development tools.
8747
 
8748

8749
File: as.info,  Node: H8/300 Directives,  Next: H8/300 Opcodes,  Prev: H8/300 Floating Point,  Up: H8/300-Dependent
8750
 
8751
9.10.4 H8/300 Machine Directives
8752
--------------------------------
8753
 
8754
`as' has the following machine-dependent directives for the H8/300:
8755
 
8756
`.h8300h'
8757
     Recognize and emit additional instructions for the H8/300H
8758
     variant, and also make `.int' emit 32-bit numbers rather than the
8759
     usual (16-bit) for the H8/300 family.
8760
 
8761
`.h8300s'
8762
     Recognize and emit additional instructions for the H8S variant, and
8763
     also make `.int' emit 32-bit numbers rather than the usual (16-bit)
8764
     for the H8/300 family.
8765
 
8766
`.h8300hn'
8767
     Recognize and emit additional instructions for the H8/300H variant
8768
     in normal mode, and also make `.int' emit 32-bit numbers rather
8769
     than the usual (16-bit) for the H8/300 family.
8770
 
8771
`.h8300sn'
8772
     Recognize and emit additional instructions for the H8S variant in
8773
     normal mode, and also make `.int' emit 32-bit numbers rather than
8774
     the usual (16-bit) for the H8/300 family.
8775
 
8776
   On the H8/300 family (including the H8/300H) `.word' directives
8777
generate 16-bit numbers.
8778
 
8779

8780
File: as.info,  Node: H8/300 Opcodes,  Prev: H8/300 Directives,  Up: H8/300-Dependent
8781
 
8782
9.10.5 Opcodes
8783
--------------
8784
 
8785
For detailed information on the H8/300 machine instruction set, see
8786
`H8/300 Series Programming Manual'.  For information specific to the
8787
H8/300H, see `H8/300H Series Programming Manual' (Renesas).
8788
 
8789
   `as' implements all the standard H8/300 opcodes.  No additional
8790
pseudo-instructions are needed on this family.
8791
 
8792
   The following table summarizes the H8/300 opcodes, and their
8793
arguments.  Entries marked `*' are opcodes used only on the H8/300H.
8794
 
8795
              Legend:
8796
                 Rs   source register
8797
                 Rd   destination register
8798
                 abs  absolute address
8799
                 imm  immediate data
8800
              disp:N  N-bit displacement from a register
8801
             pcrel:N  N-bit displacement relative to program counter
8802
 
8803
        add.b #imm,rd              *  andc #imm,ccr
8804
        add.b rs,rd                   band #imm,rd
8805
        add.w rs,rd                   band #imm,@rd
8806
     *  add.w #imm,rd                 band #imm,@abs:8
8807
     *  add.l rs,rd                   bra  pcrel:8
8808
     *  add.l #imm,rd              *  bra  pcrel:16
8809
        adds #imm,rd                  bt   pcrel:8
8810
        addx #imm,rd               *  bt   pcrel:16
8811
        addx rs,rd                    brn  pcrel:8
8812
        and.b #imm,rd              *  brn  pcrel:16
8813
        and.b rs,rd                   bf   pcrel:8
8814
     *  and.w rs,rd                *  bf   pcrel:16
8815
     *  and.w #imm,rd                 bhi  pcrel:8
8816
     *  and.l #imm,rd              *  bhi  pcrel:16
8817
     *  and.l rs,rd                   bls  pcrel:8
8818
 
8819
     *  bls  pcrel:16                 bld  #imm,rd
8820
        bcc  pcrel:8                  bld  #imm,@rd
8821
     *  bcc  pcrel:16                 bld  #imm,@abs:8
8822
        bhs  pcrel:8                  bnot #imm,rd
8823
     *  bhs  pcrel:16                 bnot #imm,@rd
8824
        bcs  pcrel:8                  bnot #imm,@abs:8
8825
     *  bcs  pcrel:16                 bnot rs,rd
8826
        blo  pcrel:8                  bnot rs,@rd
8827
     *  blo  pcrel:16                 bnot rs,@abs:8
8828
        bne  pcrel:8                  bor  #imm,rd
8829
     *  bne  pcrel:16                 bor  #imm,@rd
8830
        beq  pcrel:8                  bor  #imm,@abs:8
8831
     *  beq  pcrel:16                 bset #imm,rd
8832
        bvc  pcrel:8                  bset #imm,@rd
8833
     *  bvc  pcrel:16                 bset #imm,@abs:8
8834
        bvs  pcrel:8                  bset rs,rd
8835
     *  bvs  pcrel:16                 bset rs,@rd
8836
        bpl  pcrel:8                  bset rs,@abs:8
8837
     *  bpl  pcrel:16                 bsr  pcrel:8
8838
        bmi  pcrel:8                  bsr  pcrel:16
8839
     *  bmi  pcrel:16                 bst  #imm,rd
8840
        bge  pcrel:8                  bst  #imm,@rd
8841
     *  bge  pcrel:16                 bst  #imm,@abs:8
8842
        blt  pcrel:8                  btst #imm,rd
8843
     *  blt  pcrel:16                 btst #imm,@rd
8844
        bgt  pcrel:8                  btst #imm,@abs:8
8845
     *  bgt  pcrel:16                 btst rs,rd
8846
        ble  pcrel:8                  btst rs,@rd
8847
     *  ble  pcrel:16                 btst rs,@abs:8
8848
        bclr #imm,rd                  bxor #imm,rd
8849
        bclr #imm,@rd                 bxor #imm,@rd
8850
        bclr #imm,@abs:8              bxor #imm,@abs:8
8851
        bclr rs,rd                    cmp.b #imm,rd
8852
        bclr rs,@rd                   cmp.b rs,rd
8853
        bclr rs,@abs:8                cmp.w rs,rd
8854
        biand #imm,rd                 cmp.w rs,rd
8855
        biand #imm,@rd             *  cmp.w #imm,rd
8856
        biand #imm,@abs:8          *  cmp.l #imm,rd
8857
        bild #imm,rd               *  cmp.l rs,rd
8858
        bild #imm,@rd                 daa  rs
8859
        bild #imm,@abs:8              das  rs
8860
        bior #imm,rd                  dec.b rs
8861
        bior #imm,@rd              *  dec.w #imm,rd
8862
        bior #imm,@abs:8           *  dec.l #imm,rd
8863
        bist #imm,rd                  divxu.b rs,rd
8864
        bist #imm,@rd              *  divxu.w rs,rd
8865
        bist #imm,@abs:8           *  divxs.b rs,rd
8866
        bixor #imm,rd              *  divxs.w rs,rd
8867
        bixor #imm,@rd                eepmov
8868
        bixor #imm,@abs:8          *  eepmovw
8869
 
8870
     *  exts.w rd                     mov.w rs,@abs:16
8871
     *  exts.l rd                  *  mov.l #imm,rd
8872
     *  extu.w rd                  *  mov.l rs,rd
8873
     *  extu.l rd                  *  mov.l @rs,rd
8874
        inc  rs                    *  mov.l @(disp:16,rs),rd
8875
     *  inc.w #imm,rd              *  mov.l @(disp:24,rs),rd
8876
     *  inc.l #imm,rd              *  mov.l @rs+,rd
8877
        jmp  @rs                   *  mov.l @abs:16,rd
8878
        jmp  abs                   *  mov.l @abs:24,rd
8879
        jmp  @@abs:8               *  mov.l rs,@rd
8880
        jsr  @rs                   *  mov.l rs,@(disp:16,rd)
8881
        jsr  abs                   *  mov.l rs,@(disp:24,rd)
8882
        jsr  @@abs:8               *  mov.l rs,@-rd
8883
        ldc  #imm,ccr              *  mov.l rs,@abs:16
8884
        ldc  rs,ccr                *  mov.l rs,@abs:24
8885
     *  ldc  @abs:16,ccr              movfpe @abs:16,rd
8886
     *  ldc  @abs:24,ccr              movtpe rs,@abs:16
8887
     *  ldc  @(disp:16,rs),ccr        mulxu.b rs,rd
8888
     *  ldc  @(disp:24,rs),ccr     *  mulxu.w rs,rd
8889
     *  ldc  @rs+,ccr              *  mulxs.b rs,rd
8890
     *  ldc  @rs,ccr               *  mulxs.w rs,rd
8891
     *  mov.b @(disp:24,rs),rd        neg.b rs
8892
     *  mov.b rs,@(disp:24,rd)     *  neg.w rs
8893
        mov.b @abs:16,rd           *  neg.l rs
8894
        mov.b rs,rd                   nop
8895
        mov.b @abs:8,rd               not.b rs
8896
        mov.b rs,@abs:8            *  not.w rs
8897
        mov.b rs,rd                *  not.l rs
8898
        mov.b #imm,rd                 or.b #imm,rd
8899
        mov.b @rs,rd                  or.b rs,rd
8900
        mov.b @(disp:16,rs),rd     *  or.w #imm,rd
8901
        mov.b @rs+,rd              *  or.w rs,rd
8902
        mov.b @abs:8,rd            *  or.l #imm,rd
8903
        mov.b rs,@rd               *  or.l rs,rd
8904
        mov.b rs,@(disp:16,rd)        orc  #imm,ccr
8905
        mov.b rs,@-rd                 pop.w rs
8906
        mov.b rs,@abs:8            *  pop.l rs
8907
        mov.w rs,@rd                  push.w rs
8908
     *  mov.w @(disp:24,rs),rd     *  push.l rs
8909
     *  mov.w rs,@(disp:24,rd)        rotl.b rs
8910
     *  mov.w @abs:24,rd           *  rotl.w rs
8911
     *  mov.w rs,@abs:24           *  rotl.l rs
8912
        mov.w rs,rd                   rotr.b rs
8913
        mov.w #imm,rd              *  rotr.w rs
8914
        mov.w @rs,rd               *  rotr.l rs
8915
        mov.w @(disp:16,rs),rd        rotxl.b rs
8916
        mov.w @rs+,rd              *  rotxl.w rs
8917
        mov.w @abs:16,rd           *  rotxl.l rs
8918
        mov.w rs,@(disp:16,rd)        rotxr.b rs
8919
        mov.w rs,@-rd              *  rotxr.w rs
8920
 
8921
     *  rotxr.l rs                 *  stc  ccr,@(disp:24,rd)
8922
        bpt                        *  stc  ccr,@-rd
8923
        rte                        *  stc  ccr,@abs:16
8924
        rts                        *  stc  ccr,@abs:24
8925
        shal.b rs                     sub.b rs,rd
8926
     *  shal.w rs                     sub.w rs,rd
8927
     *  shal.l rs                  *  sub.w #imm,rd
8928
        shar.b rs                  *  sub.l rs,rd
8929
     *  shar.w rs                  *  sub.l #imm,rd
8930
     *  shar.l rs                     subs #imm,rd
8931
        shll.b rs                     subx #imm,rd
8932
     *  shll.w rs                     subx rs,rd
8933
     *  shll.l rs                  *  trapa #imm
8934
        shlr.b rs                     xor  #imm,rd
8935
     *  shlr.w rs                     xor  rs,rd
8936
     *  shlr.l rs                  *  xor.w #imm,rd
8937
        sleep                      *  xor.w rs,rd
8938
        stc  ccr,rd                *  xor.l #imm,rd
8939
     *  stc  ccr,@rs               *  xor.l rs,rd
8940
     *  stc  ccr,@(disp:16,rd)        xorc #imm,ccr
8941
 
8942
   Four H8/300 instructions (`add', `cmp', `mov', `sub') are defined
8943
with variants using the suffixes `.b', `.w', and `.l' to specify the
8944
size of a memory operand.  `as' supports these suffixes, but does not
8945
require them; since one of the operands is always a register, `as' can
8946
deduce the correct size.
8947
 
8948
   For example, since `r0' refers to a 16-bit register,
8949
     mov    r0,@foo
8950
is equivalent to
8951
     mov.w  r0,@foo
8952
 
8953
   If you use the size suffixes, `as' issues a warning when the suffix
8954
and the register size do not match.
8955
 
8956

8957
File: as.info,  Node: HPPA-Dependent,  Next: ESA/390-Dependent,  Prev: H8/300-Dependent,  Up: Machine Dependencies
8958
 
8959
9.11 HPPA Dependent Features
8960
============================
8961
 
8962
* Menu:
8963
 
8964
* HPPA Notes::                Notes
8965
* HPPA Options::              Options
8966
* HPPA Syntax::               Syntax
8967
* HPPA Floating Point::       Floating Point
8968
* HPPA Directives::           HPPA Machine Directives
8969
* HPPA Opcodes::              Opcodes
8970
 
8971

8972
File: as.info,  Node: HPPA Notes,  Next: HPPA Options,  Up: HPPA-Dependent
8973
 
8974
9.11.1 Notes
8975
------------
8976
 
8977
As a back end for GNU CC `as' has been throughly tested and should work
8978
extremely well.  We have tested it only minimally on hand written
8979
assembly code and no one has tested it much on the assembly output from
8980
the HP compilers.
8981
 
8982
   The format of the debugging sections has changed since the original
8983
`as' port (version 1.3X) was released; therefore, you must rebuild all
8984
HPPA objects and libraries with the new assembler so that you can debug
8985
the final executable.
8986
 
8987
   The HPPA `as' port generates a small subset of the relocations
8988
available in the SOM and ELF object file formats.  Additional relocation
8989
support will be added as it becomes necessary.
8990
 
8991

8992
File: as.info,  Node: HPPA Options,  Next: HPPA Syntax,  Prev: HPPA Notes,  Up: HPPA-Dependent
8993
 
8994
9.11.2 Options
8995
--------------
8996
 
8997
`as' has no machine-dependent command-line options for the HPPA.
8998
 
8999

9000
File: as.info,  Node: HPPA Syntax,  Next: HPPA Floating Point,  Prev: HPPA Options,  Up: HPPA-Dependent
9001
 
9002
9.11.3 Syntax
9003
-------------
9004
 
9005
The assembler syntax closely follows the HPPA instruction set reference
9006
manual; assembler directives and general syntax closely follow the HPPA
9007
assembly language reference manual, with a few noteworthy differences.
9008
 
9009
   First, a colon may immediately follow a label definition.  This is
9010
simply for compatibility with how most assembly language programmers
9011
write code.
9012
 
9013
   Some obscure expression parsing problems may affect hand written
9014
code which uses the `spop' instructions, or code which makes significant
9015
use of the `!' line separator.
9016
 
9017
   `as' is much less forgiving about missing arguments and other
9018
similar oversights than the HP assembler.  `as' notifies you of missing
9019
arguments as syntax errors; this is regarded as a feature, not a bug.
9020
 
9021
   Finally, `as' allows you to use an external symbol without
9022
explicitly importing the symbol.  _Warning:_ in the future this will be
9023
an error for HPPA targets.
9024
 
9025
   Special characters for HPPA targets include:
9026
 
9027
   `;' is the line comment character.
9028
 
9029
   `!' can be used instead of a newline to separate statements.
9030
 
9031
   Since `$' has no special meaning, you may use it in symbol names.
9032
 
9033

9034
File: as.info,  Node: HPPA Floating Point,  Next: HPPA Directives,  Prev: HPPA Syntax,  Up: HPPA-Dependent
9035
 
9036
9.11.4 Floating Point
9037
---------------------
9038
 
9039
The HPPA family uses IEEE floating-point numbers.
9040
 
9041

9042
File: as.info,  Node: HPPA Directives,  Next: HPPA Opcodes,  Prev: HPPA Floating Point,  Up: HPPA-Dependent
9043
 
9044
9.11.5 HPPA Assembler Directives
9045
--------------------------------
9046
 
9047
`as' for the HPPA supports many additional directives for compatibility
9048
with the native assembler.  This section describes them only briefly.
9049
For detailed information on HPPA-specific assembler directives, see
9050
`HP9000 Series 800 Assembly Language Reference Manual' (HP 92432-90001).
9051
 
9052
   `as' does _not_ support the following assembler directives described
9053
in the HP manual:
9054
 
9055
     .endm           .liston
9056
     .enter          .locct
9057
     .leave          .macro
9058
     .listoff
9059
 
9060
   Beyond those implemented for compatibility, `as' supports one
9061
additional assembler directive for the HPPA: `.param'.  It conveys
9062
register argument locations for static functions.  Its syntax closely
9063
follows the `.export' directive.
9064
 
9065
   These are the additional directives in `as' for the HPPA:
9066
 
9067
`.block N'
9068
`.blockz N'
9069
     Reserve N bytes of storage, and initialize them to zero.
9070
 
9071
`.call'
9072
     Mark the beginning of a procedure call.  Only the special case
9073
     with _no arguments_ is allowed.
9074
 
9075
`.callinfo [ PARAM=VALUE, ... ]  [ FLAG, ... ]'
9076
     Specify a number of parameters and flags that define the
9077
     environment for a procedure.
9078
 
9079
     PARAM may be any of `frame' (frame size), `entry_gr' (end of
9080
     general register range), `entry_fr' (end of float register range),
9081
     `entry_sr' (end of space register range).
9082
 
9083
     The values for FLAG are `calls' or `caller' (proc has
9084
     subroutines), `no_calls' (proc does not call subroutines),
9085
     `save_rp' (preserve return pointer), `save_sp' (proc preserves
9086
     stack pointer), `no_unwind' (do not unwind this proc), `hpux_int'
9087
     (proc is interrupt routine).
9088
 
9089
`.code'
9090
     Assemble into the standard section called `$TEXT$', subsection
9091
     `$CODE$'.
9092
 
9093
`.copyright "STRING"'
9094
     In the SOM object format, insert STRING into the object code,
9095
     marked as a copyright string.
9096
 
9097
`.copyright "STRING"'
9098
     In the ELF object format, insert STRING into the object code,
9099
     marked as a version string.
9100
 
9101
`.enter'
9102
     Not yet supported; the assembler rejects programs containing this
9103
     directive.
9104
 
9105
`.entry'
9106
     Mark the beginning of a procedure.
9107
 
9108
`.exit'
9109
     Mark the end of a procedure.
9110
 
9111
`.export NAME [ ,TYP ]  [ ,PARAM=R ]'
9112
     Make a procedure NAME available to callers.  TYP, if present, must
9113
     be one of `absolute', `code' (ELF only, not SOM), `data', `entry',
9114
     `data', `entry', `millicode', `plabel', `pri_prog', or `sec_prog'.
9115
 
9116
     PARAM, if present, provides either relocation information for the
9117
     procedure arguments and result, or a privilege level.  PARAM may be
9118
     `argwN' (where N ranges from `0' to `3', and indicates one of four
9119
     one-word arguments); `rtnval' (the procedure's result); or
9120
     `priv_lev' (privilege level).  For arguments or the result, R
9121
     specifies how to relocate, and must be one of `no' (not
9122
     relocatable), `gr' (argument is in general register), `fr' (in
9123
     floating point register), or `fu' (upper half of float register).
9124
     For `priv_lev', R is an integer.
9125
 
9126
`.half N'
9127
     Define a two-byte integer constant N; synonym for the portable
9128
     `as' directive `.short'.
9129
 
9130
`.import NAME [ ,TYP ]'
9131
     Converse of `.export'; make a procedure available to call.  The
9132
     arguments use the same conventions as the first two arguments for
9133
     `.export'.
9134
 
9135
`.label NAME'
9136
     Define NAME as a label for the current assembly location.
9137
 
9138
`.leave'
9139
     Not yet supported; the assembler rejects programs containing this
9140
     directive.
9141
 
9142
`.origin LC'
9143
     Advance location counter to LC. Synonym for the `as' portable
9144
     directive `.org'.
9145
 
9146
`.param NAME [ ,TYP ]  [ ,PARAM=R ]'
9147
     Similar to `.export', but used for static procedures.
9148
 
9149
`.proc'
9150
     Use preceding the first statement of a procedure.
9151
 
9152
`.procend'
9153
     Use following the last statement of a procedure.
9154
 
9155
`LABEL .reg EXPR'
9156
     Synonym for `.equ'; define LABEL with the absolute expression EXPR
9157
     as its value.
9158
 
9159
`.space SECNAME [ ,PARAMS ]'
9160
     Switch to section SECNAME, creating a new section by that name if
9161
     necessary.  You may only use PARAMS when creating a new section,
9162
     not when switching to an existing one.  SECNAME may identify a
9163
     section by number rather than by name.
9164
 
9165
     If specified, the list PARAMS declares attributes of the section,
9166
     identified by keywords.  The keywords recognized are `spnum=EXP'
9167
     (identify this section by the number EXP, an absolute expression),
9168
     `sort=EXP' (order sections according to this sort key when linking;
9169
     EXP is an absolute expression), `unloadable' (section contains no
9170
     loadable data), `notdefined' (this section defined elsewhere), and
9171
     `private' (data in this section not available to other programs).
9172
 
9173
`.spnum SECNAM'
9174
     Allocate four bytes of storage, and initialize them with the
9175
     section number of the section named SECNAM.  (You can define the
9176
     section number with the HPPA `.space' directive.)
9177
 
9178
`.string "STR"'
9179
     Copy the characters in the string STR to the object file.  *Note
9180
     Strings: Strings, for information on escape sequences you can use
9181
     in `as' strings.
9182
 
9183
     _Warning!_ The HPPA version of `.string' differs from the usual
9184
     `as' definition: it does _not_ write a zero byte after copying STR.
9185
 
9186
`.stringz "STR"'
9187
     Like `.string', but appends a zero byte after copying STR to object
9188
     file.
9189
 
9190
`.subspa NAME [ ,PARAMS ]'
9191
`.nsubspa NAME [ ,PARAMS ]'
9192
     Similar to `.space', but selects a subsection NAME within the
9193
     current section.  You may only specify PARAMS when you create a
9194
     subsection (in the first instance of `.subspa' for this NAME).
9195
 
9196
     If specified, the list PARAMS declares attributes of the
9197
     subsection, identified by keywords.  The keywords recognized are
9198
     `quad=EXPR' ("quadrant" for this subsection), `align=EXPR'
9199
     (alignment for beginning of this subsection; a power of two),
9200
     `access=EXPR' (value for "access rights" field), `sort=EXPR'
9201
     (sorting order for this subspace in link), `code_only' (subsection
9202
     contains only code), `unloadable' (subsection cannot be loaded
9203
     into memory), `comdat' (subsection is comdat), `common'
9204
     (subsection is common block), `dup_comm' (subsection may have
9205
     duplicate names), or `zero' (subsection is all zeros, do not write
9206
     in object file).
9207
 
9208
     `.nsubspa' always creates a new subspace with the given name, even
9209
     if one with the same name already exists.
9210
 
9211
     `comdat', `common' and `dup_comm' can be used to implement various
9212
     flavors of one-only support when using the SOM linker.  The SOM
9213
     linker only supports specific combinations of these flags.  The
9214
     details are not documented.  A brief description is provided here.
9215
 
9216
     `comdat' provides a form of linkonce support.  It is useful for
9217
     both code and data subspaces.  A `comdat' subspace has a key symbol
9218
     marked by the `is_comdat' flag or `ST_COMDAT'.  Only the first
9219
     subspace for any given key is selected.  The key symbol becomes
9220
     universal in shared links.  This is similar to the behavior of
9221
     `secondary_def' symbols.
9222
 
9223
     `common' provides Fortran named common support.  It is only useful
9224
     for data subspaces.  Symbols with the flag `is_common' retain this
9225
     flag in shared links.  Referencing a `is_common' symbol in a shared
9226
     library from outside the library doesn't work.  Thus, `is_common'
9227
     symbols must be output whenever they are needed.
9228
 
9229
     `common' and `dup_comm' together provide Cobol common support.
9230
     The subspaces in this case must all be the same length.
9231
     Otherwise, this support is similar to the Fortran common support.
9232
 
9233
     `dup_comm' by itself provides a type of one-only support for code.
9234
     Only the first `dup_comm' subspace is selected.  There is a rather
9235
     complex algorithm to compare subspaces.  Code symbols marked with
9236
     the `dup_common' flag are hidden.  This support was intended for
9237
     "C++ duplicate inlines".
9238
 
9239
     A simplified technique is used to mark the flags of symbols based
9240
     on the flags of their subspace.  A symbol with the scope
9241
     SS_UNIVERSAL and type ST_ENTRY, ST_CODE or ST_DATA is marked with
9242
     the corresponding settings of `comdat', `common' and `dup_comm'
9243
     from the subspace, respectively.  This avoids having to introduce
9244
     additional directives to mark these symbols.  The HP assembler
9245
     sets `is_common' from `common'.  However, it doesn't set the
9246
     `dup_common' from `dup_comm'.  It doesn't have `comdat' support.
9247
 
9248
`.version "STR"'
9249
     Write STR as version identifier in object code.
9250
 
9251

9252
File: as.info,  Node: HPPA Opcodes,  Prev: HPPA Directives,  Up: HPPA-Dependent
9253
 
9254
9.11.6 Opcodes
9255
--------------
9256
 
9257
For detailed information on the HPPA machine instruction set, see
9258
`PA-RISC Architecture and Instruction Set Reference Manual' (HP
9259
09740-90039).
9260
 
9261

9262
File: as.info,  Node: ESA/390-Dependent,  Next: i386-Dependent,  Prev: HPPA-Dependent,  Up: Machine Dependencies
9263
 
9264
9.12 ESA/390 Dependent Features
9265
===============================
9266
 
9267
* Menu:
9268
 
9269
* ESA/390 Notes::                Notes
9270
* ESA/390 Options::              Options
9271
* ESA/390 Syntax::               Syntax
9272
* ESA/390 Floating Point::       Floating Point
9273
* ESA/390 Directives::           ESA/390 Machine Directives
9274
* ESA/390 Opcodes::              Opcodes
9275
 
9276

9277
File: as.info,  Node: ESA/390 Notes,  Next: ESA/390 Options,  Up: ESA/390-Dependent
9278
 
9279
9.12.1 Notes
9280
------------
9281
 
9282
The ESA/390 `as' port is currently intended to be a back-end for the
9283
GNU CC compiler.  It is not HLASM compatible, although it does support
9284
a subset of some of the HLASM directives.  The only supported binary
9285
file format is ELF; none of the usual MVS/VM/OE/USS object file
9286
formats, such as ESD or XSD, are supported.
9287
 
9288
   When used with the GNU CC compiler, the ESA/390 `as' will produce
9289
correct, fully relocated, functional binaries, and has been used to
9290
compile and execute large projects.  However, many aspects should still
9291
be considered experimental; these include shared library support,
9292
dynamically loadable objects, and any relocation other than the 31-bit
9293
relocation.
9294
 
9295

9296
File: as.info,  Node: ESA/390 Options,  Next: ESA/390 Syntax,  Prev: ESA/390 Notes,  Up: ESA/390-Dependent
9297
 
9298
9.12.2 Options
9299
--------------
9300
 
9301
`as' has no machine-dependent command-line options for the ESA/390.
9302
 
9303

9304
File: as.info,  Node: ESA/390 Syntax,  Next: ESA/390 Floating Point,  Prev: ESA/390 Options,  Up: ESA/390-Dependent
9305
 
9306
9.12.3 Syntax
9307
-------------
9308
 
9309
The opcode/operand syntax follows the ESA/390 Principles of Operation
9310
manual; assembler directives and general syntax are loosely based on the
9311
prevailing AT&T/SVR4/ELF/Solaris style notation.  HLASM-style directives
9312
are _not_ supported for the most part, with the exception of those
9313
described herein.
9314
 
9315
   A leading dot in front of directives is optional, and the case of
9316
directives is ignored; thus for example, .using and USING have the same
9317
effect.
9318
 
9319
   A colon may immediately follow a label definition.  This is simply
9320
for compatibility with how most assembly language programmers write
9321
code.
9322
 
9323
   `#' is the line comment character.
9324
 
9325
   `;' can be used instead of a newline to separate statements.
9326
 
9327
   Since `$' has no special meaning, you may use it in symbol names.
9328
 
9329
   Registers can be given the symbolic names r0..r15, fp0, fp2, fp4,
9330
fp6.  By using thesse symbolic names, `as' can detect simple syntax
9331
errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca for
9332
r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base
9333
for r3 and rpgt or r.pgt for r4.
9334
 
9335
   `*' is the current location counter.  Unlike `.' it is always
9336
relative to the last USING directive.  Note that this means that
9337
expressions cannot use multiplication, as any occurrence of `*' will be
9338
interpreted as a location counter.
9339
 
9340
   All labels are relative to the last USING.  Thus, branches to a label
9341
always imply the use of base+displacement.
9342
 
9343
   Many of the usual forms of address constants / address literals are
9344
supported.  Thus,
9345
        .using  *,r3
9346
        L       r15,=A(some_routine)
9347
        LM      r6,r7,=V(some_longlong_extern)
9348
        A       r1,=F'12'
9349
        AH      r0,=H'42'
9350
        ME      r6,=E'3.1416'
9351
        MD      r6,=D'3.14159265358979'
9352
        O       r6,=XL4'cacad0d0'
9353
        .ltorg
9354
   should all behave as expected: that is, an entry in the literal pool
9355
will be created (or reused if it already exists), and the instruction
9356
operands will be the displacement into the literal pool using the
9357
current base register (as last declared with the `.using' directive).
9358
 
9359

9360
File: as.info,  Node: ESA/390 Floating Point,  Next: ESA/390 Directives,  Prev: ESA/390 Syntax,  Up: ESA/390-Dependent
9361
 
9362
9.12.4 Floating Point
9363
---------------------
9364
 
9365
The assembler generates only IEEE floating-point numbers.  The older
9366
floating point formats are not supported.
9367
 
9368

9369
File: as.info,  Node: ESA/390 Directives,  Next: ESA/390 Opcodes,  Prev: ESA/390 Floating Point,  Up: ESA/390-Dependent
9370
 
9371
9.12.5 ESA/390 Assembler Directives
9372
-----------------------------------
9373
 
9374
`as' for the ESA/390 supports all of the standard ELF/SVR4 assembler
9375
directives that are documented in the main part of this documentation.
9376
Several additional directives are supported in order to implement the
9377
ESA/390 addressing model.  The most important of these are `.using' and
9378
`.ltorg'
9379
 
9380
   These are the additional directives in `as' for the ESA/390:
9381
 
9382
`.dc'
9383
     A small subset of the usual DC directive is supported.
9384
 
9385
`.drop REGNO'
9386
     Stop using REGNO as the base register.  The REGNO must have been
9387
     previously declared with a `.using' directive in the same section
9388
     as the current section.
9389
 
9390
`.ebcdic STRING'
9391
     Emit the EBCDIC equivalent of the indicated string.  The emitted
9392
     string will be null terminated.  Note that the directives
9393
     `.string' etc. emit ascii strings by default.
9394
 
9395
`EQU'
9396
     The standard HLASM-style EQU directive is not supported; however,
9397
     the standard `as' directive .equ can be used to the same effect.
9398
 
9399
`.ltorg'
9400
     Dump the literal pool accumulated so far; begin a new literal pool.
9401
     The literal pool will be written in the current section; in order
9402
     to generate correct assembly, a `.using' must have been previously
9403
     specified in the same section.
9404
 
9405
`.using EXPR,REGNO'
9406
     Use REGNO as the base register for all subsequent RX, RS, and SS
9407
     form instructions. The EXPR will be evaluated to obtain the base
9408
     address; usually, EXPR will merely be `*'.
9409
 
9410
     This assembler allows two `.using' directives to be simultaneously
9411
     outstanding, one in the `.text' section, and one in another section
9412
     (typically, the `.data' section).  This feature allows dynamically
9413
     loaded objects to be implemented in a relatively straightforward
9414
     way.  A `.using' directive must always be specified in the `.text'
9415
     section; this will specify the base register that will be used for
9416
     branches in the `.text' section.  A second `.using' may be
9417
     specified in another section; this will specify the base register
9418
     that is used for non-label address literals.  When a second
9419
     `.using' is specified, then the subsequent `.ltorg' must be put in
9420
     the same section; otherwise an error will result.
9421
 
9422
     Thus, for example, the following code uses `r3' to address branch
9423
     targets and `r4' to address the literal pool, which has been
9424
     written to the `.data' section.  The is, the constants
9425
     `=A(some_routine)', `=H'42'' and `=E'3.1416'' will all appear in
9426
     the `.data' section.
9427
 
9428
          .data
9429
                .using  LITPOOL,r4
9430
          .text
9431
                BASR    r3,0
9432
                .using  *,r3
9433
                  B       START
9434
                .long   LITPOOL
9435
          START:
9436
                L       r4,4(,r3)
9437
                L       r15,=A(some_routine)
9438
                LTR     r15,r15
9439
                BNE     LABEL
9440
                AH      r0,=H'42'
9441
          LABEL:
9442
                ME      r6,=E'3.1416'
9443
          .data
9444
          LITPOOL:
9445
                .ltorg
9446
 
9447
     Note that this dual-`.using' directive semantics extends and is
9448
     not compatible with HLASM semantics.  Note that this assembler
9449
     directive does not support the full range of HLASM semantics.
9450
 
9451
 
9452

9453
File: as.info,  Node: ESA/390 Opcodes,  Prev: ESA/390 Directives,  Up: ESA/390-Dependent
9454
 
9455
9.12.6 Opcodes
9456
--------------
9457
 
9458
For detailed information on the ESA/390 machine instruction set, see
9459
`ESA/390 Principles of Operation' (IBM Publication Number DZ9AR004).
9460
 
9461

9462
File: as.info,  Node: i386-Dependent,  Next: i860-Dependent,  Prev: ESA/390-Dependent,  Up: Machine Dependencies
9463
 
9464
9.13 80386 Dependent Features
9465
=============================
9466
 
9467
   The i386 version `as' supports both the original Intel 386
9468
architecture in both 16 and 32-bit mode as well as AMD x86-64
9469
architecture extending the Intel architecture to 64-bits.
9470
 
9471
* Menu:
9472
 
9473
* i386-Options::                Options
9474
* i386-Directives::             X86 specific directives
9475
* i386-Syntax::                 AT&T Syntax versus Intel Syntax
9476
* i386-Mnemonics::              Instruction Naming
9477
* i386-Regs::                   Register Naming
9478
* i386-Prefixes::               Instruction Prefixes
9479
* i386-Memory::                 Memory References
9480
* i386-Jumps::                  Handling of Jump Instructions
9481
* i386-Float::                  Floating Point
9482
* i386-SIMD::                   Intel's MMX and AMD's 3DNow! SIMD Operations
9483
* i386-16bit::                  Writing 16-bit Code
9484
* i386-Arch::                   Specifying an x86 CPU architecture
9485
* i386-Bugs::                   AT&T Syntax bugs
9486
* i386-Notes::                  Notes
9487
 
9488

9489
File: as.info,  Node: i386-Options,  Next: i386-Directives,  Up: i386-Dependent
9490
 
9491
9.13.1 Options
9492
--------------
9493
 
9494
The i386 version of `as' has a few machine dependent options:
9495
 
9496
`--32 | --64'
9497
     Select the word size, either 32 bits or 64 bits. Selecting 32-bit
9498
     implies Intel i386 architecture, while 64-bit implies AMD x86-64
9499
     architecture.
9500
 
9501
     These options are only available with the ELF object file format,
9502
     and require that the necessary BFD support has been included (on a
9503
     32-bit platform you have to add -enable-64-bit-bfd to configure
9504
     enable 64-bit usage and use x86-64 as target platform).
9505
 
9506
`-n'
9507
     By default, x86 GAS replaces multiple nop instructions used for
9508
     alignment within code sections with multi-byte nop instructions
9509
     such as leal 0(%esi,1),%esi.  This switch disables the
9510
     optimization.
9511
 
9512
`--divide'
9513
     On SVR4-derived platforms, the character `/' is treated as a
9514
     comment character, which means that it cannot be used in
9515
     expressions.  The `--divide' option turns `/' into a normal
9516
     character.  This does not disable `/' at the beginning of a line
9517
     starting a comment, or affect using `#' for starting a comment.
9518
 
9519
`-march=CPU[+EXTENSION...]'
9520
     This option specifies the target processor.  The assembler will
9521
     issue an error message if an attempt is made to assemble an
9522
     instruction which will not execute on the target processor.  The
9523
     following processor names are recognized: `i8086', `i186', `i286',
9524
     `i386', `i486', `i586', `i686', `pentium', `pentiumpro',
9525
     `pentiumii', `pentiumiii', `pentium4', `prescott', `nocona',
9526
     `core', `core2', `corei7', `l1om', `k6', `k6_2', `athlon',
9527
     `opteron', `k8', `amdfam10', `generic32' and `generic64'.
9528
 
9529
     In addition to the basic instruction set, the assembler can be
9530
     told to accept various extension mnemonics.  For example,
9531
     `-march=i686+sse4+vmx' extends I686 with SSE4 and VMX.  The
9532
     following extensions are currently supported: `8087', `287', `387',
9533
     `no87', `mmx', `nommx', `sse', `sse2', `sse3', `ssse3', `sse4.1',
9534
     `sse4.2', `sse4', `nosse', `avx', `noavx', `vmx', `smx', `xsave',
9535
     `aes', `pclmul', `fma', `movbe', `ept', `clflush', `syscall',
9536
     `rdtscp', `3dnow', `3dnowa', `sse4a', `sse5', `svme', `abm' and
9537
     `padlock'.  Note that rather than extending a basic instruction
9538
     set, the extension mnemonics starting with `no' revoke the
9539
     respective functionality.
9540
 
9541
     When the `.arch' directive is used with `-march', the `.arch'
9542
     directive will take precedent.
9543
 
9544
`-mtune=CPU'
9545
     This option specifies a processor to optimize for. When used in
9546
     conjunction with the `-march' option, only instructions of the
9547
     processor specified by the `-march' option will be generated.
9548
 
9549
     Valid CPU values are identical to the processor list of
9550
     `-march=CPU'.
9551
 
9552
`-msse2avx'
9553
     This option specifies that the assembler should encode SSE
9554
     instructions with VEX prefix.
9555
 
9556
`-msse-check=NONE'
9557
 
9558
`-msse-check=WARNING'
9559
 
9560
`-msse-check=ERROR'
9561
     These options control if the assembler should check SSE
9562
     intructions.  `-msse-check=NONE' will make the assembler not to
9563
     check SSE instructions,  which is the default.
9564
     `-msse-check=WARNING' will make the assembler issue a warning for
9565
     any SSE intruction.  `-msse-check=ERROR' will make the assembler
9566
     issue an error for any SSE intruction.
9567
 
9568
`-mmnemonic=ATT'
9569
 
9570
`-mmnemonic=INTEL'
9571
     This option specifies instruction mnemonic for matching
9572
     instructions.  The `.att_mnemonic' and `.intel_mnemonic'
9573
     directives will take precedent.
9574
 
9575
`-msyntax=ATT'
9576
 
9577
`-msyntax=INTEL'
9578
     This option specifies instruction syntax when processing
9579
     instructions.  The `.att_syntax' and `.intel_syntax' directives
9580
     will take precedent.
9581
 
9582
`-mnaked-reg'
9583
     This opetion specifies that registers don't require a `%' prefix.
9584
     The `.att_syntax' and `.intel_syntax' directives will take
9585
     precedent.
9586
 
9587
 
9588

9589
File: as.info,  Node: i386-Directives,  Next: i386-Syntax,  Prev: i386-Options,  Up: i386-Dependent
9590
 
9591
9.13.2 x86 specific Directives
9592
------------------------------
9593
 
9594
`.lcomm SYMBOL , LENGTH[, ALIGNMENT]'
9595
     Reserve LENGTH (an absolute expression) bytes for a local common
9596
     denoted by SYMBOL.  The section and value of SYMBOL are those of
9597
     the new local common.  The addresses are allocated in the bss
9598
     section, so that at run-time the bytes start off zeroed.  Since
9599
     SYMBOL is not declared global, it is normally not visible to `ld'.
9600
     The optional third parameter, ALIGNMENT, specifies the desired
9601
     alignment of the symbol in the bss section.
9602
 
9603
     This directive is only available for COFF based x86 targets.
9604
 
9605
 
9606

9607
File: as.info,  Node: i386-Syntax,  Next: i386-Mnemonics,  Prev: i386-Directives,  Up: i386-Dependent
9608
 
9609
9.13.3 AT&T Syntax versus Intel Syntax
9610
--------------------------------------
9611
 
9612
`as' now supports assembly using Intel assembler syntax.
9613
`.intel_syntax' selects Intel mode, and `.att_syntax' switches back to
9614
the usual AT&T mode for compatibility with the output of `gcc'.  Either
9615
of these directives may have an optional argument, `prefix', or
9616
`noprefix' specifying whether registers require a `%' prefix.  AT&T
9617
System V/386 assembler syntax is quite different from Intel syntax.  We
9618
mention these differences because almost all 80386 documents use Intel
9619
syntax.  Notable differences between the two syntaxes are:
9620
 
9621
   * AT&T immediate operands are preceded by `$'; Intel immediate
9622
     operands are undelimited (Intel `push 4' is AT&T `pushl $4').
9623
     AT&T register operands are preceded by `%'; Intel register operands
9624
     are undelimited.  AT&T absolute (as opposed to PC relative)
9625
     jump/call operands are prefixed by `*'; they are undelimited in
9626
     Intel syntax.
9627
 
9628
   * AT&T and Intel syntax use the opposite order for source and
9629
     destination operands.  Intel `add eax, 4' is `addl $4, %eax'.  The
9630
     `source, dest' convention is maintained for compatibility with
9631
     previous Unix assemblers.  Note that `bound', `invlpga', and
9632
     instructions with 2 immediate operands, such as the `enter'
9633
     instruction, do _not_ have reversed order.  *Note i386-Bugs::.
9634
 
9635
   * In AT&T syntax the size of memory operands is determined from the
9636
     last character of the instruction mnemonic.  Mnemonic suffixes of
9637
     `b', `w', `l' and `q' specify byte (8-bit), word (16-bit), long
9638
     (32-bit) and quadruple word (64-bit) memory references.  Intel
9639
     syntax accomplishes this by prefixing memory operands (_not_ the
9640
     instruction mnemonics) with `byte ptr', `word ptr', `dword ptr'
9641
     and `qword ptr'.  Thus, Intel `mov al, byte ptr FOO' is `movb FOO,
9642
     %al' in AT&T syntax.
9643
 
9644
   * Immediate form long jumps and calls are `lcall/ljmp $SECTION,
9645
     $OFFSET' in AT&T syntax; the Intel syntax is `call/jmp far
9646
     SECTION:OFFSET'.  Also, the far return instruction is `lret
9647
     $STACK-ADJUST' in AT&T syntax; Intel syntax is `ret far
9648
     STACK-ADJUST'.
9649
 
9650
   * The AT&T assembler does not provide support for multiple section
9651
     programs.  Unix style systems expect all programs to be single
9652
     sections.
9653
 
9654

9655
File: as.info,  Node: i386-Mnemonics,  Next: i386-Regs,  Prev: i386-Syntax,  Up: i386-Dependent
9656
 
9657
9.13.4 Instruction Naming
9658
-------------------------
9659
 
9660
Instruction mnemonics are suffixed with one character modifiers which
9661
specify the size of operands.  The letters `b', `w', `l' and `q'
9662
specify byte, word, long and quadruple word operands.  If no suffix is
9663
specified by an instruction then `as' tries to fill in the missing
9664
suffix based on the destination register operand (the last one by
9665
convention).  Thus, `mov %ax, %bx' is equivalent to `movw %ax, %bx';
9666
also, `mov $1, %bx' is equivalent to `movw $1, bx'.  Note that this is
9667
incompatible with the AT&T Unix assembler which assumes that a missing
9668
mnemonic suffix implies long operand size.  (This incompatibility does
9669
not affect compiler output since compilers always explicitly specify
9670
the mnemonic suffix.)
9671
 
9672
   Almost all instructions have the same names in AT&T and Intel format.
9673
There are a few exceptions.  The sign extend and zero extend
9674
instructions need two sizes to specify them.  They need a size to
9675
sign/zero extend _from_ and a size to zero extend _to_.  This is
9676
accomplished by using two instruction mnemonic suffixes in AT&T syntax.
9677
Base names for sign extend and zero extend are `movs...' and `movz...'
9678
in AT&T syntax (`movsx' and `movzx' in Intel syntax).  The instruction
9679
mnemonic suffixes are tacked on to this base name, the _from_ suffix
9680
before the _to_ suffix.  Thus, `movsbl %al, %edx' is AT&T syntax for
9681
"move sign extend _from_ %al _to_ %edx."  Possible suffixes, thus, are
9682
`bl' (from byte to long), `bw' (from byte to word), `wl' (from word to
9683
long), `bq' (from byte to quadruple word), `wq' (from word to quadruple
9684
word), and `lq' (from long to quadruple word).
9685
 
9686
   Different encoding options can be specified via optional mnemonic
9687
suffix.  `.s' suffix swaps 2 register operands in encoding when moving
9688
from one register to another.
9689
 
9690
   The Intel-syntax conversion instructions
9691
 
9692
   * `cbw' -- sign-extend byte in `%al' to word in `%ax',
9693
 
9694
   * `cwde' -- sign-extend word in `%ax' to long in `%eax',
9695
 
9696
   * `cwd' -- sign-extend word in `%ax' to long in `%dx:%ax',
9697
 
9698
   * `cdq' -- sign-extend dword in `%eax' to quad in `%edx:%eax',
9699
 
9700
   * `cdqe' -- sign-extend dword in `%eax' to quad in `%rax' (x86-64
9701
     only),
9702
 
9703
   * `cqo' -- sign-extend quad in `%rax' to octuple in `%rdx:%rax'
9704
     (x86-64 only),
9705
 
9706
are called `cbtw', `cwtl', `cwtd', `cltd', `cltq', and `cqto' in AT&T
9707
naming.  `as' accepts either naming for these instructions.
9708
 
9709
   Far call/jump instructions are `lcall' and `ljmp' in AT&T syntax,
9710
but are `call far' and `jump far' in Intel convention.
9711
 
9712
9.13.5 AT&T Mnemonic versus Intel Mnemonic
9713
------------------------------------------
9714
 
9715
`as' supports assembly using Intel mnemonic.  `.intel_mnemonic' selects
9716
Intel mnemonic with Intel syntax, and `.att_mnemonic' switches back to
9717
the usual AT&T mnemonic with AT&T syntax for compatibility with the
9718
output of `gcc'.  Several x87 instructions, `fadd', `fdiv', `fdivp',
9719
`fdivr', `fdivrp', `fmul', `fsub', `fsubp', `fsubr' and `fsubrp',  are
9720
implemented in AT&T System V/386 assembler with different mnemonics
9721
from those in Intel IA32 specification.  `gcc' generates those
9722
instructions with AT&T mnemonic.
9723
 
9724

9725
File: as.info,  Node: i386-Regs,  Next: i386-Prefixes,  Prev: i386-Mnemonics,  Up: i386-Dependent
9726
 
9727
9.13.6 Register Naming
9728
----------------------
9729
 
9730
Register operands are always prefixed with `%'.  The 80386 registers
9731
consist of
9732
 
9733
   * the 8 32-bit registers `%eax' (the accumulator), `%ebx', `%ecx',
9734
     `%edx', `%edi', `%esi', `%ebp' (the frame pointer), and `%esp'
9735
     (the stack pointer).
9736
 
9737
   * the 8 16-bit low-ends of these: `%ax', `%bx', `%cx', `%dx', `%di',
9738
     `%si', `%bp', and `%sp'.
9739
 
9740
   * the 8 8-bit registers: `%ah', `%al', `%bh', `%bl', `%ch', `%cl',
9741
     `%dh', and `%dl' (These are the high-bytes and low-bytes of `%ax',
9742
     `%bx', `%cx', and `%dx')
9743
 
9744
   * the 6 section registers `%cs' (code section), `%ds' (data
9745
     section), `%ss' (stack section), `%es', `%fs', and `%gs'.
9746
 
9747
   * the 3 processor control registers `%cr0', `%cr2', and `%cr3'.
9748
 
9749
   * the 6 debug registers `%db0', `%db1', `%db2', `%db3', `%db6', and
9750
     `%db7'.
9751
 
9752
   * the 2 test registers `%tr6' and `%tr7'.
9753
 
9754
   * the 8 floating point register stack `%st' or equivalently
9755
     `%st(0)', `%st(1)', `%st(2)', `%st(3)', `%st(4)', `%st(5)',
9756
     `%st(6)', and `%st(7)'.  These registers are overloaded by 8 MMX
9757
     registers `%mm0', `%mm1', `%mm2', `%mm3', `%mm4', `%mm5', `%mm6'
9758
     and `%mm7'.
9759
 
9760
   * the 8 SSE registers registers `%xmm0', `%xmm1', `%xmm2', `%xmm3',
9761
     `%xmm4', `%xmm5', `%xmm6' and `%xmm7'.
9762
 
9763
   The AMD x86-64 architecture extends the register set by:
9764
 
9765
   * enhancing the 8 32-bit registers to 64-bit: `%rax' (the
9766
     accumulator), `%rbx', `%rcx', `%rdx', `%rdi', `%rsi', `%rbp' (the
9767
     frame pointer), `%rsp' (the stack pointer)
9768
 
9769
   * the 8 extended registers `%r8'-`%r15'.
9770
 
9771
   * the 8 32-bit low ends of the extended registers: `%r8d'-`%r15d'
9772
 
9773
   * the 8 16-bit low ends of the extended registers: `%r8w'-`%r15w'
9774
 
9775
   * the 8 8-bit low ends of the extended registers: `%r8b'-`%r15b'
9776
 
9777
   * the 4 8-bit registers: `%sil', `%dil', `%bpl', `%spl'.
9778
 
9779
   * the 8 debug registers: `%db8'-`%db15'.
9780
 
9781
   * the 8 SSE registers: `%xmm8'-`%xmm15'.
9782
 
9783

9784
File: as.info,  Node: i386-Prefixes,  Next: i386-Memory,  Prev: i386-Regs,  Up: i386-Dependent
9785
 
9786
9.13.7 Instruction Prefixes
9787
---------------------------
9788
 
9789
Instruction prefixes are used to modify the following instruction.  They
9790
are used to repeat string instructions, to provide section overrides, to
9791
perform bus lock operations, and to change operand and address sizes.
9792
(Most instructions that normally operate on 32-bit operands will use
9793
16-bit operands if the instruction has an "operand size" prefix.)
9794
Instruction prefixes are best written on the same line as the
9795
instruction they act upon. For example, the `scas' (scan string)
9796
instruction is repeated with:
9797
 
9798
             repne scas %es:(%edi),%al
9799
 
9800
   You may also place prefixes on the lines immediately preceding the
9801
instruction, but this circumvents checks that `as' does with prefixes,
9802
and will not work with all prefixes.
9803
 
9804
   Here is a list of instruction prefixes:
9805
 
9806
   * Section override prefixes `cs', `ds', `ss', `es', `fs', `gs'.
9807
     These are automatically added by specifying using the
9808
     SECTION:MEMORY-OPERAND form for memory references.
9809
 
9810
   * Operand/Address size prefixes `data16' and `addr16' change 32-bit
9811
     operands/addresses into 16-bit operands/addresses, while `data32'
9812
     and `addr32' change 16-bit ones (in a `.code16' section) into
9813
     32-bit operands/addresses.  These prefixes _must_ appear on the
9814
     same line of code as the instruction they modify. For example, in
9815
     a 16-bit `.code16' section, you might write:
9816
 
9817
                  addr32 jmpl *(%ebx)
9818
 
9819
   * The bus lock prefix `lock' inhibits interrupts during execution of
9820
     the instruction it precedes.  (This is only valid with certain
9821
     instructions; see a 80386 manual for details).
9822
 
9823
   * The wait for coprocessor prefix `wait' waits for the coprocessor to
9824
     complete the current instruction.  This should never be needed for
9825
     the 80386/80387 combination.
9826
 
9827
   * The `rep', `repe', and `repne' prefixes are added to string
9828
     instructions to make them repeat `%ecx' times (`%cx' times if the
9829
     current address size is 16-bits).
9830
 
9831
   * The `rex' family of prefixes is used by x86-64 to encode
9832
     extensions to i386 instruction set.  The `rex' prefix has four
9833
     bits -- an operand size overwrite (`64') used to change operand
9834
     size from 32-bit to 64-bit and X, Y and Z extensions bits used to
9835
     extend the register set.
9836
 
9837
     You may write the `rex' prefixes directly. The `rex64xyz'
9838
     instruction emits `rex' prefix with all the bits set.  By omitting
9839
     the `64', `x', `y' or `z' you may write other prefixes as well.
9840
     Normally, there is no need to write the prefixes explicitly, since
9841
     gas will automatically generate them based on the instruction
9842
     operands.
9843
 
9844

9845
File: as.info,  Node: i386-Memory,  Next: i386-Jumps,  Prev: i386-Prefixes,  Up: i386-Dependent
9846
 
9847
9.13.8 Memory References
9848
------------------------
9849
 
9850
An Intel syntax indirect memory reference of the form
9851
 
9852
     SECTION:[BASE + INDEX*SCALE + DISP]
9853
 
9854
is translated into the AT&T syntax
9855
 
9856
     SECTION:DISP(BASE, INDEX, SCALE)
9857
 
9858
where BASE and INDEX are the optional 32-bit base and index registers,
9859
DISP is the optional displacement, and SCALE, taking the values 1, 2,
9860
4, and 8, multiplies INDEX to calculate the address of the operand.  If
9861
no SCALE is specified, SCALE is taken to be 1.  SECTION specifies the
9862
optional section register for the memory operand, and may override the
9863
default section register (see a 80386 manual for section register
9864
defaults). Note that section overrides in AT&T syntax _must_ be
9865
preceded by a `%'.  If you specify a section override which coincides
9866
with the default section register, `as' does _not_ output any section
9867
register override prefixes to assemble the given instruction.  Thus,
9868
section overrides can be specified to emphasize which section register
9869
is used for a given memory operand.
9870
 
9871
   Here are some examples of Intel and AT&T style memory references:
9872
 
9873
AT&T: `-4(%ebp)', Intel:  `[ebp - 4]'
9874
     BASE is `%ebp'; DISP is `-4'. SECTION is missing, and the default
9875
     section is used (`%ss' for addressing with `%ebp' as the base
9876
     register).  INDEX, SCALE are both missing.
9877
 
9878
AT&T: `foo(,%eax,4)', Intel: `[foo + eax*4]'
9879
     INDEX is `%eax' (scaled by a SCALE 4); DISP is `foo'.  All other
9880
     fields are missing.  The section register here defaults to `%ds'.
9881
 
9882
AT&T: `foo(,1)'; Intel `[foo]'
9883
     This uses the value pointed to by `foo' as a memory operand.  Note
9884
     that BASE and INDEX are both missing, but there is only _one_ `,'.
9885
     This is a syntactic exception.
9886
 
9887
AT&T: `%gs:foo'; Intel `gs:foo'
9888
     This selects the contents of the variable `foo' with section
9889
     register SECTION being `%gs'.
9890
 
9891
   Absolute (as opposed to PC relative) call and jump operands must be
9892
prefixed with `*'.  If no `*' is specified, `as' always chooses PC
9893
relative addressing for jump/call labels.
9894
 
9895
   Any instruction that has a memory operand, but no register operand,
9896
_must_ specify its size (byte, word, long, or quadruple) with an
9897
instruction mnemonic suffix (`b', `w', `l' or `q', respectively).
9898
 
9899
   The x86-64 architecture adds an RIP (instruction pointer relative)
9900
addressing.  This addressing mode is specified by using `rip' as a base
9901
register.  Only constant offsets are valid. For example:
9902
 
9903
AT&T: `1234(%rip)', Intel: `[rip + 1234]'
9904
     Points to the address 1234 bytes past the end of the current
9905
     instruction.
9906
 
9907
AT&T: `symbol(%rip)', Intel: `[rip + symbol]'
9908
     Points to the `symbol' in RIP relative way, this is shorter than
9909
     the default absolute addressing.
9910
 
9911
   Other addressing modes remain unchanged in x86-64 architecture,
9912
except registers used are 64-bit instead of 32-bit.
9913
 
9914

9915
File: as.info,  Node: i386-Jumps,  Next: i386-Float,  Prev: i386-Memory,  Up: i386-Dependent
9916
 
9917
9.13.9 Handling of Jump Instructions
9918
------------------------------------
9919
 
9920
Jump instructions are always optimized to use the smallest possible
9921
displacements.  This is accomplished by using byte (8-bit) displacement
9922
jumps whenever the target is sufficiently close.  If a byte displacement
9923
is insufficient a long displacement is used.  We do not support word
9924
(16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
9925
instruction with the `data16' instruction prefix), since the 80386
9926
insists upon masking `%eip' to 16 bits after the word displacement is
9927
added. (See also *note i386-Arch::)
9928
 
9929
   Note that the `jcxz', `jecxz', `loop', `loopz', `loope', `loopnz'
9930
and `loopne' instructions only come in byte displacements, so that if
9931
you use these instructions (`gcc' does not use them) you may get an
9932
error message (and incorrect code).  The AT&T 80386 assembler tries to
9933
get around this problem by expanding `jcxz foo' to
9934
 
9935
              jcxz cx_zero
9936
              jmp cx_nonzero
9937
     cx_zero: jmp foo
9938
     cx_nonzero:
9939
 
9940

9941
File: as.info,  Node: i386-Float,  Next: i386-SIMD,  Prev: i386-Jumps,  Up: i386-Dependent
9942
 
9943
9.13.10 Floating Point
9944
----------------------
9945
 
9946
All 80387 floating point types except packed BCD are supported.  (BCD
9947
support may be added without much difficulty).  These data types are
9948
16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit),
9949
and extended (80-bit) precision floating point.  Each supported type
9950
has an instruction mnemonic suffix and a constructor associated with
9951
it.  Instruction mnemonic suffixes specify the operand's data type.
9952
Constructors build these data types into memory.
9953
 
9954
   * Floating point constructors are `.float' or `.single', `.double',
9955
     and `.tfloat' for 32-, 64-, and 80-bit formats.  These correspond
9956
     to instruction mnemonic suffixes `s', `l', and `t'. `t' stands for
9957
     80-bit (ten byte) real.  The 80387 only supports this format via
9958
     the `fldt' (load 80-bit real to stack top) and `fstpt' (store
9959
     80-bit real and pop stack) instructions.
9960
 
9961
   * Integer constructors are `.word', `.long' or `.int', and `.quad'
9962
     for the 16-, 32-, and 64-bit integer formats.  The corresponding
9963
     instruction mnemonic suffixes are `s' (single), `l' (long), and
9964
     `q' (quad).  As with the 80-bit real format, the 64-bit `q' format
9965
     is only present in the `fildq' (load quad integer to stack top)
9966
     and `fistpq' (store quad integer and pop stack) instructions.
9967
 
9968
   Register to register operations should not use instruction mnemonic
9969
suffixes.  `fstl %st, %st(1)' will give a warning, and be assembled as
9970
if you wrote `fst %st, %st(1)', since all register to register
9971
operations use 80-bit floating point operands. (Contrast this with
9972
`fstl %st, mem', which converts `%st' from 80-bit to 64-bit floating
9973
point format, then stores the result in the 4 byte location `mem')
9974
 
9975

9976
File: as.info,  Node: i386-SIMD,  Next: i386-16bit,  Prev: i386-Float,  Up: i386-Dependent
9977
 
9978
9.13.11 Intel's MMX and AMD's 3DNow! SIMD Operations
9979
----------------------------------------------------
9980
 
9981
`as' supports Intel's MMX instruction set (SIMD instructions for
9982
integer data), available on Intel's Pentium MMX processors and Pentium
9983
II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and
9984
probably others.  It also supports AMD's 3DNow!  instruction set (SIMD
9985
instructions for 32-bit floating point data) available on AMD's K6-2
9986
processor and possibly others in the future.
9987
 
9988
   Currently, `as' does not support Intel's floating point SIMD, Katmai
9989
(KNI).
9990
 
9991
   The eight 64-bit MMX operands, also used by 3DNow!, are called
9992
`%mm0', `%mm1', ... `%mm7'.  They contain eight 8-bit integers, four
9993
16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
9994
floating point values.  The MMX registers cannot be used at the same
9995
time as the floating point stack.
9996
 
9997
   See Intel and AMD documentation, keeping in mind that the operand
9998
order in instructions is reversed from the Intel syntax.
9999
 
10000

10001
File: as.info,  Node: i386-16bit,  Next: i386-Arch,  Prev: i386-SIMD,  Up: i386-Dependent
10002
 
10003
9.13.12 Writing 16-bit Code
10004
---------------------------
10005
 
10006
While `as' normally writes only "pure" 32-bit i386 code or 64-bit
10007
x86-64 code depending on the default configuration, it also supports
10008
writing code to run in real mode or in 16-bit protected mode code
10009
segments.  To do this, put a `.code16' or `.code16gcc' directive before
10010
the assembly language instructions to be run in 16-bit mode.  You can
10011
switch `as' back to writing normal 32-bit code with the `.code32'
10012
directive.
10013
 
10014
   `.code16gcc' provides experimental support for generating 16-bit
10015
code from gcc, and differs from `.code16' in that `call', `ret',
10016
`enter', `leave', `push', `pop', `pusha', `popa', `pushf', and `popf'
10017
instructions default to 32-bit size.  This is so that the stack pointer
10018
is manipulated in the same way over function calls, allowing access to
10019
function parameters at the same stack offsets as in 32-bit mode.
10020
`.code16gcc' also automatically adds address size prefixes where
10021
necessary to use the 32-bit addressing modes that gcc generates.
10022
 
10023
   The code which `as' generates in 16-bit mode will not necessarily
10024
run on a 16-bit pre-80386 processor.  To write code that runs on such a
10025
processor, you must refrain from using _any_ 32-bit constructs which
10026
require `as' to output address or operand size prefixes.
10027
 
10028
   Note that writing 16-bit code instructions by explicitly specifying a
10029
prefix or an instruction mnemonic suffix within a 32-bit code section
10030
generates different machine instructions than those generated for a
10031
16-bit code segment.  In a 32-bit code section, the following code
10032
generates the machine opcode bytes `66 6a 04', which pushes the value
10033
`4' onto the stack, decrementing `%esp' by 2.
10034
 
10035
             pushw $4
10036
 
10037
   The same code in a 16-bit code section would generate the machine
10038
opcode bytes `6a 04' (i.e., without the operand size prefix), which is
10039
correct since the processor default operand size is assumed to be 16
10040
bits in a 16-bit code section.
10041
 
10042

10043
File: as.info,  Node: i386-Bugs,  Next: i386-Notes,  Prev: i386-Arch,  Up: i386-Dependent
10044
 
10045
9.13.13 AT&T Syntax bugs
10046
------------------------
10047
 
10048
The UnixWare assembler, and probably other AT&T derived ix86 Unix
10049
assemblers, generate floating point instructions with reversed source
10050
and destination registers in certain cases.  Unfortunately, gcc and
10051
possibly many other programs use this reversed syntax, so we're stuck
10052
with it.
10053
 
10054
   For example
10055
 
10056
             fsub %st,%st(3)
10057
   results in `%st(3)' being updated to `%st - %st(3)' rather than the
10058
expected `%st(3) - %st'.  This happens with all the non-commutative
10059
arithmetic floating point operations with two register operands where
10060
the source register is `%st' and the destination register is `%st(i)'.
10061
 
10062

10063
File: as.info,  Node: i386-Arch,  Next: i386-Bugs,  Prev: i386-16bit,  Up: i386-Dependent
10064
 
10065
9.13.14 Specifying CPU Architecture
10066
-----------------------------------
10067
 
10068
`as' may be told to assemble for a particular CPU (sub-)architecture
10069
with the `.arch CPU_TYPE' directive.  This directive enables a warning
10070
when gas detects an instruction that is not supported on the CPU
10071
specified.  The choices for CPU_TYPE are:
10072
 
10073
`i8086'        `i186'         `i286'         `i386'
10074
`i486'         `i586'         `i686'         `pentium'
10075
`pentiumpro'   `pentiumii'    `pentiumiii'   `pentium4'
10076
`prescott'     `nocona'       `core'         `core2'
10077
`corei7'       `l1om'
10078
`k6'           `k6_2'         `athlon'       `k8'
10079
`amdfam10'
10080
`generic32'    `generic64'
10081
`.mmx'         `.sse'         `.sse2'        `.sse3'
10082
`.ssse3'       `.sse4.1'      `.sse4.2'      `.sse4'
10083
`.avx'         `.vmx'         `.smx'         `.xsave'
10084
`.aes'         `.pclmul'      `.fma'         `.movbe'
10085
`.ept'         `.clflush'
10086
`.3dnow'       `.3dnowa'      `.sse4a'       `.sse5'
10087
`.syscall'     `.rdtscp'      `.svme'        `.abm'
10088
`.padlock'
10089
 
10090
   Apart from the warning, there are only two other effects on `as'
10091
operation;  Firstly, if you specify a CPU other than `i486', then shift
10092
by one instructions such as `sarl $1, %eax' will automatically use a
10093
two byte opcode sequence.  The larger three byte opcode sequence is
10094
used on the 486 (and when no architecture is specified) because it
10095
executes faster on the 486.  Note that you can explicitly request the
10096
two byte opcode by writing `sarl %eax'.  Secondly, if you specify
10097
`i8086', `i186', or `i286', _and_ `.code16' or `.code16gcc' then byte
10098
offset conditional jumps will be promoted when necessary to a two
10099
instruction sequence consisting of a conditional jump of the opposite
10100
sense around an unconditional jump to the target.
10101
 
10102
   Following the CPU architecture (but not a sub-architecture, which
10103
are those starting with a dot), you may specify `jumps' or `nojumps' to
10104
control automatic promotion of conditional jumps. `jumps' is the
10105
default, and enables jump promotion;  All external jumps will be of the
10106
long variety, and file-local jumps will be promoted as necessary.
10107
(*note i386-Jumps::)  `nojumps' leaves external conditional jumps as
10108
byte offset jumps, and warns about file-local conditional jumps that
10109
`as' promotes.  Unconditional jumps are treated as for `jumps'.
10110
 
10111
   For example
10112
 
10113
      .arch i8086,nojumps
10114
 
10115

10116
File: as.info,  Node: i386-Notes,  Prev: i386-Bugs,  Up: i386-Dependent
10117
 
10118
9.13.15 Notes
10119
-------------
10120
 
10121
There is some trickery concerning the `mul' and `imul' instructions
10122
that deserves mention.  The 16-, 32-, 64- and 128-bit expanding
10123
multiplies (base opcode `0xf6'; extension 4 for `mul' and 5 for `imul')
10124
can be output only in the one operand form.  Thus, `imul %ebx, %eax'
10125
does _not_ select the expanding multiply; the expanding multiply would
10126
clobber the `%edx' register, and this would confuse `gcc' output.  Use
10127
`imul %ebx' to get the 64-bit product in `%edx:%eax'.
10128
 
10129
   We have added a two operand form of `imul' when the first operand is
10130
an immediate mode expression and the second operand is a register.
10131
This is just a shorthand, so that, multiplying `%eax' by 69, for
10132
example, can be done with `imul $69, %eax' rather than `imul $69, %eax,
10133
%eax'.
10134
 
10135

10136
File: as.info,  Node: i860-Dependent,  Next: i960-Dependent,  Prev: i386-Dependent,  Up: Machine Dependencies
10137
 
10138
9.14 Intel i860 Dependent Features
10139
==================================
10140
 
10141
* Menu:
10142
 
10143
* Notes-i860::                  i860 Notes
10144
* Options-i860::                i860 Command-line Options
10145
* Directives-i860::             i860 Machine Directives
10146
* Opcodes for i860::            i860 Opcodes
10147
 
10148

10149
File: as.info,  Node: Notes-i860,  Next: Options-i860,  Up: i860-Dependent
10150
 
10151
9.14.1 i860 Notes
10152
-----------------
10153
 
10154
This is a fairly complete i860 assembler which is compatible with the
10155
UNIX System V/860 Release 4 assembler. However, it does not currently
10156
support SVR4 PIC (i.e., `@GOT, @GOTOFF, @PLT').
10157
 
10158
   Like the SVR4/860 assembler, the output object format is ELF32.
10159
Currently, this is the only supported object format. If there is
10160
sufficient interest, other formats such as COFF may be implemented.
10161
 
10162
   Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter
10163
being the default.  One difference is that AT&T syntax requires the '%'
10164
prefix on register names while Intel syntax does not.  Another
10165
difference is in the specification of relocatable expressions.  The
10166
Intel syntax is `ha%expression' whereas the SVR4 syntax is
10167
`[expression]@ha' (and similarly for the "l" and "h" selectors).
10168
 
10169

10170
File: as.info,  Node: Options-i860,  Next: Directives-i860,  Prev: Notes-i860,  Up: i860-Dependent
10171
 
10172
9.14.2 i860 Command-line Options
10173
--------------------------------
10174
 
10175
9.14.2.1 SVR4 compatibility options
10176
...................................
10177
 
10178
`-V'
10179
     Print assembler version.
10180
 
10181
`-Qy'
10182
     Ignored.
10183
 
10184
`-Qn'
10185
     Ignored.
10186
 
10187
9.14.2.2 Other options
10188
......................
10189
 
10190
`-EL'
10191
     Select little endian output (this is the default).
10192
 
10193
`-EB'
10194
     Select big endian output. Note that the i860 always reads
10195
     instructions as little endian data, so this option only effects
10196
     data and not instructions.
10197
 
10198
`-mwarn-expand'
10199
     Emit a warning message if any pseudo-instruction expansions
10200
     occurred.  For example, a `or' instruction with an immediate
10201
     larger than 16-bits will be expanded into two instructions. This
10202
     is a very undesirable feature to rely on, so this flag can help
10203
     detect any code where it happens. One use of it, for instance, has
10204
     been to find and eliminate any place where `gcc' may emit these
10205
     pseudo-instructions.
10206
 
10207
`-mxp'
10208
     Enable support for the i860XP instructions and control registers.
10209
     By default, this option is disabled so that only the base
10210
     instruction set (i.e., i860XR) is supported.
10211
 
10212
`-mintel-syntax'
10213
     The i860 assembler defaults to AT&T/SVR4 syntax.  This option
10214
     enables the Intel syntax.
10215
 
10216

10217
File: as.info,  Node: Directives-i860,  Next: Opcodes for i860,  Prev: Options-i860,  Up: i860-Dependent
10218
 
10219
9.14.3 i860 Machine Directives
10220
------------------------------
10221
 
10222
`.dual'
10223
     Enter dual instruction mode. While this directive is supported, the
10224
     preferred way to use dual instruction mode is to explicitly code
10225
     the dual bit with the `d.' prefix.
10226
 
10227
`.enddual'
10228
     Exit dual instruction mode. While this directive is supported, the
10229
     preferred way to use dual instruction mode is to explicitly code
10230
     the dual bit with the `d.' prefix.
10231
 
10232
`.atmp'
10233
     Change the temporary register used when expanding pseudo
10234
     operations. The default register is `r31'.
10235
 
10236
   The `.dual', `.enddual', and `.atmp' directives are available only
10237
in the Intel syntax mode.
10238
 
10239
   Both syntaxes allow for the standard `.align' directive.  However,
10240
the Intel syntax additionally allows keywords for the alignment
10241
parameter: "`.align type'", where `type' is one of `.short', `.long',
10242
`.quad', `.single', `.double' representing alignments of 2, 4, 16, 4,
10243
and 8, respectively.
10244
 
10245

10246
File: as.info,  Node: Opcodes for i860,  Prev: Directives-i860,  Up: i860-Dependent
10247
 
10248
9.14.4 i860 Opcodes
10249
-------------------
10250
 
10251
All of the Intel i860XR and i860XP machine instructions are supported.
10252
Please see either _i860 Microprocessor Programmer's Reference Manual_
10253
or _i860 Microprocessor Architecture_ for more information.
10254
 
10255
9.14.4.1 Other instruction support (pseudo-instructions)
10256
........................................................
10257
 
10258
For compatibility with some other i860 assemblers, a number of
10259
pseudo-instructions are supported. While these are supported, they are
10260
a very undesirable feature that should be avoided - in particular, when
10261
they result in an expansion to multiple actual i860 instructions. Below
10262
are the pseudo-instructions that result in expansions.
10263
   * Load large immediate into general register:
10264
 
10265
     The pseudo-instruction `mov imm,%rn' (where the immediate does not
10266
     fit within a signed 16-bit field) will be expanded into:
10267
          orh large_imm@h,%r0,%rn
10268
          or large_imm@l,%rn,%rn
10269
 
10270
   * Load/store with relocatable address expression:
10271
 
10272
     For example, the pseudo-instruction `ld.b addr_exp(%rx),%rn' will
10273
     be expanded into:
10274
          orh addr_exp@ha,%rx,%r31
10275
          ld.l addr_exp@l(%r31),%rn
10276
 
10277
     The analogous expansions apply to `ld.x, st.x, fld.x, pfld.x,
10278
     fst.x', and `pst.x' as well.
10279
 
10280
   * Signed large immediate with add/subtract:
10281
 
10282
     If any of the arithmetic operations `adds, addu, subs, subu' are
10283
     used with an immediate larger than 16-bits (signed), then they
10284
     will be expanded.  For instance, the pseudo-instruction `adds
10285
     large_imm,%rx,%rn' expands to:
10286
          orh large_imm@h,%r0,%r31
10287
          or large_imm@l,%r31,%r31
10288
          adds %r31,%rx,%rn
10289
 
10290
   * Unsigned large immediate with logical operations:
10291
 
10292
     Logical operations (`or, andnot, or, xor') also result in
10293
     expansions.  The pseudo-instruction `or large_imm,%rx,%rn' results
10294
     in:
10295
          orh large_imm@h,%rx,%r31
10296
          or large_imm@l,%r31,%rn
10297
 
10298
     Similarly for the others, except for `and' which expands to:
10299
          andnot (-1 - large_imm)@h,%rx,%r31
10300
          andnot (-1 - large_imm)@l,%r31,%rn
10301
 
10302

10303
File: as.info,  Node: i960-Dependent,  Next: IA-64-Dependent,  Prev: i860-Dependent,  Up: Machine Dependencies
10304
 
10305
9.15 Intel 80960 Dependent Features
10306
===================================
10307
 
10308
* Menu:
10309
 
10310
* Options-i960::                i960 Command-line Options
10311
* Floating Point-i960::         Floating Point
10312
* Directives-i960::             i960 Machine Directives
10313
* Opcodes for i960::            i960 Opcodes
10314
 
10315

10316
File: as.info,  Node: Options-i960,  Next: Floating Point-i960,  Up: i960-Dependent
10317
 
10318
9.15.1 i960 Command-line Options
10319
--------------------------------
10320
 
10321
`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC'
10322
     Select the 80960 architecture.  Instructions or features not
10323
     supported by the selected architecture cause fatal errors.
10324
 
10325
     `-ACA' is equivalent to `-ACA_A'; `-AKC' is equivalent to `-AMC'.
10326
     Synonyms are provided for compatibility with other tools.
10327
 
10328
     If you do not specify any of these options, `as' generates code
10329
     for any instruction or feature that is supported by _some_ version
10330
     of the 960 (even if this means mixing architectures!).  In
10331
     principle, `as' attempts to deduce the minimal sufficient
10332
     processor type if none is specified; depending on the object code
10333
     format, the processor type may be recorded in the object file.  If
10334
     it is critical that the `as' output match a specific architecture,
10335
     specify that architecture explicitly.
10336
 
10337
`-b'
10338
     Add code to collect information about conditional branches taken,
10339
     for later optimization using branch prediction bits.  (The
10340
     conditional branch instructions have branch prediction bits in the
10341
     CA, CB, and CC architectures.)  If BR represents a conditional
10342
     branch instruction, the following represents the code generated by
10343
     the assembler when `-b' is specified:
10344
 
10345
                  call    INCREMENT ROUTINE
10346
                  .word   0       # pre-counter
10347
          Label:  BR
10348
                  call    INCREMENT ROUTINE
10349
                  .word   0       # post-counter
10350
 
10351
     The counter following a branch records the number of times that
10352
     branch was _not_ taken; the difference between the two counters is
10353
     the number of times the branch _was_ taken.
10354
 
10355
     A table of every such `Label' is also generated, so that the
10356
     external postprocessor `gbr960' (supplied by Intel) can locate all
10357
     the counters.  This table is always labeled `__BRANCH_TABLE__';
10358
     this is a local symbol to permit collecting statistics for many
10359
     separate object files.  The table is word aligned, and begins with
10360
     a two-word header.  The first word, initialized to 0, is used in
10361
     maintaining linked lists of branch tables.  The second word is a
10362
     count of the number of entries in the table, which follow
10363
     immediately: each is a word, pointing to one of the labels
10364
     illustrated above.
10365
 
10366
           +------------+------------+------------+ ... +------------+
10367
           |            |            |            |     |            |
10368
           |  *NEXT     |  COUNT: N  | *BRLAB 1   |     | *BRLAB N   |
10369
           |            |            |            |     |            |
10370
           +------------+------------+------------+ ... +------------+
10371
 
10372
                         __BRANCH_TABLE__ layout
10373
 
10374
     The first word of the header is used to locate multiple branch
10375
     tables, since each object file may contain one. Normally the links
10376
     are maintained with a call to an initialization routine, placed at
10377
     the beginning of each function in the file.  The GNU C compiler
10378
     generates these calls automatically when you give it a `-b' option.
10379
     For further details, see the documentation of `gbr960'.
10380
 
10381
`-no-relax'
10382
     Normally, Compare-and-Branch instructions with targets that require
10383
     displacements greater than 13 bits (or that have external targets)
10384
     are replaced with the corresponding compare (or `chkbit') and
10385
     branch instructions.  You can use the `-no-relax' option to
10386
     specify that `as' should generate errors instead, if the target
10387
     displacement is larger than 13 bits.
10388
 
10389
     This option does not affect the Compare-and-Jump instructions; the
10390
     code emitted for them is _always_ adjusted when necessary
10391
     (depending on displacement size), regardless of whether you use
10392
     `-no-relax'.
10393
 
10394

10395
File: as.info,  Node: Floating Point-i960,  Next: Directives-i960,  Prev: Options-i960,  Up: i960-Dependent
10396
 
10397
9.15.2 Floating Point
10398
---------------------
10399
 
10400
`as' generates IEEE floating-point numbers for the directives `.float',
10401
`.double', `.extended', and `.single'.
10402
 
10403

10404
File: as.info,  Node: Directives-i960,  Next: Opcodes for i960,  Prev: Floating Point-i960,  Up: i960-Dependent
10405
 
10406
9.15.3 i960 Machine Directives
10407
------------------------------
10408
 
10409
`.bss SYMBOL, LENGTH, ALIGN'
10410
     Reserve LENGTH bytes in the bss section for a local SYMBOL,
10411
     aligned to the power of two specified by ALIGN.  LENGTH and ALIGN
10412
     must be positive absolute expressions.  This directive differs
10413
     from `.lcomm' only in that it permits you to specify an alignment.
10414
     *Note `.lcomm': Lcomm.
10415
 
10416
`.extended FLONUMS'
10417
     `.extended' expects zero or more flonums, separated by commas; for
10418
     each flonum, `.extended' emits an IEEE extended-format (80-bit)
10419
     floating-point number.
10420
 
10421
`.leafproc CALL-LAB, BAL-LAB'
10422
     You can use the `.leafproc' directive in conjunction with the
10423
     optimized `callj' instruction to enable faster calls of leaf
10424
     procedures.  If a procedure is known to call no other procedures,
10425
     you may define an entry point that skips procedure prolog code
10426
     (and that does not depend on system-supplied saved context), and
10427
     declare it as the BAL-LAB using `.leafproc'.  If the procedure
10428
     also has an entry point that goes through the normal prolog, you
10429
     can specify that entry point as CALL-LAB.
10430
 
10431
     A `.leafproc' declaration is meant for use in conjunction with the
10432
     optimized call instruction `callj'; the directive records the data
10433
     needed later to choose between converting the `callj' into a `bal'
10434
     or a `call'.
10435
 
10436
     CALL-LAB is optional; if only one argument is present, or if the
10437
     two arguments are identical, the single argument is assumed to be
10438
     the `bal' entry point.
10439
 
10440
`.sysproc NAME, INDEX'
10441
     The `.sysproc' directive defines a name for a system procedure.
10442
     After you define it using `.sysproc', you can use NAME to refer to
10443
     the system procedure identified by INDEX when calling procedures
10444
     with the optimized call instruction `callj'.
10445
 
10446
     Both arguments are required; INDEX must be between 0 and 31
10447
     (inclusive).
10448
 
10449

10450
File: as.info,  Node: Opcodes for i960,  Prev: Directives-i960,  Up: i960-Dependent
10451
 
10452
9.15.4 i960 Opcodes
10453
-------------------
10454
 
10455
All Intel 960 machine instructions are supported; *note i960
10456
Command-line Options: Options-i960. for a discussion of selecting the
10457
instruction subset for a particular 960 architecture.
10458
 
10459
   Some opcodes are processed beyond simply emitting a single
10460
corresponding instruction: `callj', and Compare-and-Branch or
10461
Compare-and-Jump instructions with target displacements larger than 13
10462
bits.
10463
 
10464
* Menu:
10465
 
10466
* callj-i960::                  `callj'
10467
* Compare-and-branch-i960::     Compare-and-Branch
10468
 
10469

10470
File: as.info,  Node: callj-i960,  Next: Compare-and-branch-i960,  Up: Opcodes for i960
10471
 
10472
9.15.4.1 `callj'
10473
................
10474
 
10475
You can write `callj' to have the assembler or the linker determine the
10476
most appropriate form of subroutine call: `call', `bal', or `calls'.
10477
If the assembly source contains enough information--a `.leafproc' or
10478
`.sysproc' directive defining the operand--then `as' translates the
10479
`callj'; if not, it simply emits the `callj', leaving it for the linker
10480
to resolve.
10481
 
10482

10483
File: as.info,  Node: Compare-and-branch-i960,  Prev: callj-i960,  Up: Opcodes for i960
10484
 
10485
9.15.4.2 Compare-and-Branch
10486
...........................
10487
 
10488
The 960 architectures provide combined Compare-and-Branch instructions
10489
that permit you to store the branch target in the lower 13 bits of the
10490
instruction word itself.  However, if you specify a branch target far
10491
enough away that its address won't fit in 13 bits, the assembler can
10492
either issue an error, or convert your Compare-and-Branch instruction
10493
into separate instructions to do the compare and the branch.
10494
 
10495
   Whether `as' gives an error or expands the instruction depends on
10496
two choices you can make: whether you use the `-no-relax' option, and
10497
whether you use a "Compare and Branch" instruction or a "Compare and
10498
Jump" instruction.  The "Jump" instructions are _always_ expanded if
10499
necessary; the "Branch" instructions are expanded when necessary
10500
_unless_ you specify `-no-relax'--in which case `as' gives an error
10501
instead.
10502
 
10503
   These are the Compare-and-Branch instructions, their "Jump" variants,
10504
and the instruction pairs they may expand into:
10505
 
10506
             Compare and
10507
          Branch      Jump       Expanded to
10508
          ------    ------       ------------
10509
             bbc                 chkbit; bno
10510
             bbs                 chkbit; bo
10511
          cmpibe    cmpije       cmpi; be
10512
          cmpibg    cmpijg       cmpi; bg
10513
         cmpibge   cmpijge       cmpi; bge
10514
          cmpibl    cmpijl       cmpi; bl
10515
         cmpible   cmpijle       cmpi; ble
10516
         cmpibno   cmpijno       cmpi; bno
10517
         cmpibne   cmpijne       cmpi; bne
10518
          cmpibo    cmpijo       cmpi; bo
10519
          cmpobe    cmpoje       cmpo; be
10520
          cmpobg    cmpojg       cmpo; bg
10521
         cmpobge   cmpojge       cmpo; bge
10522
          cmpobl    cmpojl       cmpo; bl
10523
         cmpoble   cmpojle       cmpo; ble
10524
         cmpobne   cmpojne       cmpo; bne
10525
 
10526

10527
File: as.info,  Node: IA-64-Dependent,  Next: IP2K-Dependent,  Prev: i960-Dependent,  Up: Machine Dependencies
10528
 
10529
9.16 IA-64 Dependent Features
10530
=============================
10531
 
10532
* Menu:
10533
 
10534
* IA-64 Options::              Options
10535
* IA-64 Syntax::               Syntax
10536
* IA-64 Opcodes::              Opcodes
10537
 
10538

10539
File: as.info,  Node: IA-64 Options,  Next: IA-64 Syntax,  Up: IA-64-Dependent
10540
 
10541
9.16.1 Options
10542
--------------
10543
 
10544
`-mconstant-gp'
10545
     This option instructs the assembler to mark the resulting object
10546
     file as using the "constant GP" model.  With this model, it is
10547
     assumed that the entire program uses a single global pointer (GP)
10548
     value.  Note that this option does not in any fashion affect the
10549
     machine code emitted by the assembler.  All it does is turn on the
10550
     EF_IA_64_CONS_GP flag in the ELF file header.
10551
 
10552
`-mauto-pic'
10553
     This option instructs the assembler to mark the resulting object
10554
     file as using the "constant GP without function descriptor" data
10555
     model.  This model is like the "constant GP" model, except that it
10556
     additionally does away with function descriptors.  What this means
10557
     is that the address of a function refers directly to the
10558
     function's code entry-point.  Normally, such an address would
10559
     refer to a function descriptor, which contains both the code
10560
     entry-point and the GP-value needed by the function.  Note that
10561
     this option does not in any fashion affect the machine code
10562
     emitted by the assembler.  All it does is turn on the
10563
     EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header.
10564
 
10565
`-milp32'
10566
 
10567
`-milp64'
10568
 
10569
`-mlp64'
10570
 
10571
`-mp64'
10572
     These options select the data model.  The assembler defaults to
10573
     `-mlp64' (LP64 data model).
10574
 
10575
`-mle'
10576
 
10577
`-mbe'
10578
     These options select the byte order.  The `-mle' option selects
10579
     little-endian byte order (default) and `-mbe' selects big-endian
10580
     byte order.  Note that IA-64 machine code always uses
10581
     little-endian byte order.
10582
 
10583
`-mtune=itanium1'
10584
 
10585
`-mtune=itanium2'
10586
     Tune for a particular IA-64 CPU, ITANIUM1 or ITANIUM2. The default
10587
     is ITANIUM2.
10588
 
10589
`-munwind-check=warning'
10590
 
10591
`-munwind-check=error'
10592
     These options control what the assembler will do when performing
10593
     consistency checks on unwind directives.  `-munwind-check=warning'
10594
     will make the assembler issue a warning when an unwind directive
10595
     check fails.  This is the default.  `-munwind-check=error' will
10596
     make the assembler issue an error when an unwind directive check
10597
     fails.
10598
 
10599
`-mhint.b=ok'
10600
 
10601
`-mhint.b=warning'
10602
 
10603
`-mhint.b=error'
10604
     These options control what the assembler will do when the `hint.b'
10605
     instruction is used.  `-mhint.b=ok' will make the assembler accept
10606
     `hint.b'.  `-mint.b=warning' will make the assembler issue a
10607
     warning when `hint.b' is used.  `-mhint.b=error' will make the
10608
     assembler treat `hint.b' as an error, which is the default.
10609
 
10610
`-x'
10611
 
10612
`-xexplicit'
10613
     These options turn on dependency violation checking.
10614
 
10615
`-xauto'
10616
     This option instructs the assembler to automatically insert stop
10617
     bits where necessary to remove dependency violations.  This is the
10618
     default mode.
10619
 
10620
`-xnone'
10621
     This option turns off dependency violation checking.
10622
 
10623
`-xdebug'
10624
     This turns on debug output intended to help tracking down bugs in
10625
     the dependency violation checker.
10626
 
10627
`-xdebugn'
10628
     This is a shortcut for -xnone -xdebug.
10629
 
10630
`-xdebugx'
10631
     This is a shortcut for -xexplicit -xdebug.
10632
 
10633
 
10634

10635
File: as.info,  Node: IA-64 Syntax,  Next: IA-64 Opcodes,  Prev: IA-64 Options,  Up: IA-64-Dependent
10636
 
10637
9.16.2 Syntax
10638
-------------
10639
 
10640
The assembler syntax closely follows the IA-64 Assembly Language
10641
Reference Guide.
10642
 
10643
* Menu:
10644
 
10645
* IA-64-Chars::                Special Characters
10646
* IA-64-Regs::                 Register Names
10647
* IA-64-Bits::                 Bit Names
10648
 
10649

10650
File: as.info,  Node: IA-64-Chars,  Next: IA-64-Regs,  Up: IA-64 Syntax
10651
 
10652
9.16.2.1 Special Characters
10653
...........................
10654
 
10655
`//' is the line comment token.
10656
 
10657
   `;' can be used instead of a newline to separate statements.
10658
 
10659

10660
File: as.info,  Node: IA-64-Regs,  Next: IA-64-Bits,  Prev: IA-64-Chars,  Up: IA-64 Syntax
10661
 
10662
9.16.2.2 Register Names
10663
.......................
10664
 
10665
The 128 integer registers are referred to as `rN'.  The 128
10666
floating-point registers are referred to as `fN'.  The 128 application
10667
registers are referred to as `arN'.  The 128 control registers are
10668
referred to as `crN'.  The 64 one-bit predicate registers are referred
10669
to as `pN'.  The 8 branch registers are referred to as `bN'.  In
10670
addition, the assembler defines a number of aliases: `gp' (`r1'), `sp'
10671
(`r12'), `rp' (`b0'), `ret0' (`r8'), `ret1' (`r9'), `ret2' (`r10'),
10672
`ret3' (`r9'), `fargN' (`f8+N'), and `fretN' (`f8+N').
10673
 
10674
   For convenience, the assembler also defines aliases for all named
10675
application and control registers.  For example, `ar.bsp' refers to the
10676
register backing store pointer (`ar17').  Similarly, `cr.eoi' refers to
10677
the end-of-interrupt register (`cr67').
10678
 
10679

10680
File: as.info,  Node: IA-64-Bits,  Prev: IA-64-Regs,  Up: IA-64 Syntax
10681
 
10682
9.16.2.3 IA-64 Processor-Status-Register (PSR) Bit Names
10683
........................................................
10684
 
10685
The assembler defines bit masks for each of the bits in the IA-64
10686
processor status register.  For example, `psr.ic' corresponds to a
10687
value of 0x2000.  These masks are primarily intended for use with the
10688
`ssm'/`sum' and `rsm'/`rum' instructions, but they can be used anywhere
10689
else where an integer constant is expected.
10690
 
10691

10692
File: as.info,  Node: IA-64 Opcodes,  Prev: IA-64 Syntax,  Up: IA-64-Dependent
10693
 
10694
9.16.3 Opcodes
10695
--------------
10696
 
10697
For detailed information on the IA-64 machine instruction set, see the
10698
IA-64 Architecture Handbook
10699
(http://developer.intel.com/design/itanium/arch_spec.htm).
10700
 
10701

10702
File: as.info,  Node: IP2K-Dependent,  Next: LM32-Dependent,  Prev: IA-64-Dependent,  Up: Machine Dependencies
10703
 
10704
9.17 IP2K Dependent Features
10705
============================
10706
 
10707
* Menu:
10708
 
10709
* IP2K-Opts::                   IP2K Options
10710
 
10711

10712
File: as.info,  Node: IP2K-Opts,  Up: IP2K-Dependent
10713
 
10714
9.17.1 IP2K Options
10715
-------------------
10716
 
10717
The Ubicom IP2K version of `as' has a few machine dependent options:
10718
 
10719
`-mip2022ext'
10720
     `as' can assemble the extended IP2022 instructions, but it will
10721
     only do so if this is specifically allowed via this command line
10722
     option.
10723
 
10724
`-mip2022'
10725
     This option restores the assembler's default behaviour of not
10726
     permitting the extended IP2022 instructions to be assembled.
10727
 
10728
 
10729

10730
File: as.info,  Node: LM32-Dependent,  Next: M32C-Dependent,  Prev: IP2K-Dependent,  Up: Machine Dependencies
10731
 
10732
9.18 LM32 Dependent Features
10733
============================
10734
 
10735
* Menu:
10736
 
10737
* LM32 Options::              Options
10738
* LM32 Syntax::               Syntax
10739
* LM32 Opcodes::              Opcodes
10740
 
10741

10742
File: as.info,  Node: LM32 Options,  Next: LM32 Syntax,  Up: LM32-Dependent
10743
 
10744
9.18.1 Options
10745
--------------
10746
 
10747
`-mmultiply-enabled'
10748
     Enable multiply instructions.
10749
 
10750
`-mdivide-enabled'
10751
     Enable divide instructions.
10752
 
10753
`-mbarrel-shift-enabled'
10754
     Enable barrel-shift instructions.
10755
 
10756
`-msign-extend-enabled'
10757
     Enable sign extend instructions.
10758
 
10759
`-muser-enabled'
10760
     Enable user defined instructions.
10761
 
10762
`-micache-enabled'
10763
     Enable instruction cache related CSRs.
10764
 
10765
`-mdcache-enabled'
10766
     Enable data cache related CSRs.
10767
 
10768
`-mbreak-enabled'
10769
     Enable break instructions.
10770
 
10771
`-mall-enabled'
10772
     Enable all instructions and CSRs.
10773
 
10774
 
10775

10776
File: as.info,  Node: LM32 Syntax,  Next: LM32 Opcodes,  Prev: LM32 Options,  Up: LM32-Dependent
10777
 
10778
9.18.2 Syntax
10779
-------------
10780
 
10781
* Menu:
10782
 
10783
* LM32-Regs::                 Register Names
10784
* LM32-Modifiers::            Relocatable Expression Modifiers
10785
 
10786

10787
File: as.info,  Node: LM32-Regs,  Next: LM32-Modifiers,  Up: LM32 Syntax
10788
 
10789
9.18.2.1 Register Names
10790
.......................
10791
 
10792
LM32 has 32 x 32-bit general purpose registers `r0', `r1', ... `r31'.
10793
 
10794
   The following aliases are defined: `gp' - `r26', `fp' - `r27', `sp'
10795
- `r28', `ra' - `r29', `ea' - `r30', `ba' - `r31'.
10796
 
10797
   LM32 has the following Control and Status Registers (CSRs).
10798
 
10799
`IE'
10800
     Interrupt enable.
10801
 
10802
`IM'
10803
     Interrupt mask.
10804
 
10805
`IP'
10806
     Interrupt pending.
10807
 
10808
`ICC'
10809
     Instruction cache control.
10810
 
10811
`DCC'
10812
     Data cache control.
10813
 
10814
`CC'
10815
     Cycle counter.
10816
 
10817
`CFG'
10818
     Configuration.
10819
 
10820
`EBA'
10821
     Exception base address.
10822
 
10823
`DC'
10824
     Debug control.
10825
 
10826
`DEBA'
10827
     Debug exception base address.
10828
 
10829
`JTX'
10830
     JTAG transmit.
10831
 
10832
`JRX'
10833
     JTAG receive.
10834
 
10835
`BP0'
10836
     Breakpoint 0.
10837
 
10838
`BP1'
10839
     Breakpoint 1.
10840
 
10841
`BP2'
10842
     Breakpoint 2.
10843
 
10844
`BP3'
10845
     Breakpoint 3.
10846
 
10847
`WP0'
10848
     Watchpoint 0.
10849
 
10850
`WP1'
10851
     Watchpoint 1.
10852
 
10853
`WP2'
10854
     Watchpoint 2.
10855
 
10856
`WP3'
10857
     Watchpoint 3.
10858
 
10859

10860
File: as.info,  Node: LM32-Modifiers,  Prev: LM32-Regs,  Up: LM32 Syntax
10861
 
10862
9.18.2.2 Relocatable Expression Modifiers
10863
.........................................
10864
 
10865
The assembler supports several modifiers when using relocatable
10866
addresses in LM32 instruction operands.  The general syntax is the
10867
following:
10868
 
10869
     modifier(relocatable-expression)
10870
 
10871
`lo'
10872
     This modifier allows you to use bits 0 through 15 of an address
10873
     expression as 16 bit relocatable expression.
10874
 
10875
`hi'
10876
     This modifier allows you to use bits 16 through 23 of an address
10877
     expression as 16 bit relocatable expression.
10878
 
10879
     For example
10880
 
10881
          ori  r4, r4, lo(sym+10)
10882
          orhi r4, r4, hi(sym+10)
10883
 
10884
`gp'
10885
     This modified creates a 16-bit relocatable expression that is the
10886
     offset of the symbol from the global pointer.
10887
 
10888
          mva r4, gp(sym)
10889
 
10890
`got'
10891
     This modifier places a symbol in the GOT and creates a 16-bit
10892
     relocatable expression that is the offset into the GOT of this
10893
     symbol.
10894
 
10895
          lw r4, (gp+got(sym))
10896
 
10897
`gotofflo16'
10898
     This modifier allows you to use the bits 0 through 15 of an
10899
     address which is an offset from the GOT.
10900
 
10901
`gotoffhi16'
10902
     This modifier allows you to use the bits 16 through 31 of an
10903
     address which is an offset from the GOT.
10904
 
10905
          orhi r4, r4, gotoffhi16(lsym)
10906
          addi r4, r4, gotofflo16(lsym)
10907
 
10908
 
10909

10910
File: as.info,  Node: LM32 Opcodes,  Prev: LM32 Syntax,  Up: LM32-Dependent
10911
 
10912
9.18.3 Opcodes
10913
--------------
10914
 
10915
For detailed information on the LM32 machine instruction set, see
10916
`http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/'.
10917
 
10918
   `as' implements all the standard LM32 opcodes.
10919
 
10920

10921
File: as.info,  Node: M32C-Dependent,  Next: M32R-Dependent,  Prev: LM32-Dependent,  Up: Machine Dependencies
10922
 
10923
9.19 M32C Dependent Features
10924
============================
10925
 
10926
   `as' can assemble code for several different members of the Renesas
10927
M32C family.  Normally the default is to assemble code for the M16C
10928
microprocessor.  The `-m32c' option may be used to change the default
10929
to the M32C microprocessor.
10930
 
10931
* Menu:
10932
 
10933
* M32C-Opts::                   M32C Options
10934
* M32C-Modifiers::              Symbolic Operand Modifiers
10935
 
10936

10937
File: as.info,  Node: M32C-Opts,  Next: M32C-Modifiers,  Up: M32C-Dependent
10938
 
10939
9.19.1 M32C Options
10940
-------------------
10941
 
10942
The Renesas M32C version of `as' has these machine-dependent options:
10943
 
10944
`-m32c'
10945
     Assemble M32C instructions.
10946
 
10947
`-m16c'
10948
     Assemble M16C instructions (default).
10949
 
10950
`-relax'
10951
     Enable support for link-time relaxations.
10952
 
10953
`-h-tick-hex'
10954
     Support H'00 style hex constants in addition to 0x00 style.
10955
 
10956
 
10957

10958
File: as.info,  Node: M32C-Modifiers,  Prev: M32C-Opts,  Up: M32C-Dependent
10959
 
10960
9.19.2 Symbolic Operand Modifiers
10961
---------------------------------
10962
 
10963
The assembler supports several modifiers when using symbol addresses in
10964
M32C instruction operands.  The general syntax is the following:
10965
 
10966
     %modifier(symbol)
10967
 
10968
`%dsp8'
10969
`%dsp16'
10970
     These modifiers override the assembler's assumptions about how big
10971
     a symbol's address is.  Normally, when it sees an operand like
10972
     `sym[a0]' it assumes `sym' may require the widest displacement
10973
     field (16 bits for `-m16c', 24 bits for `-m32c').  These modifiers
10974
     tell it to assume the address will fit in an 8 or 16 bit
10975
     (respectively) unsigned displacement.  Note that, of course, if it
10976
     doesn't actually fit you will get linker errors.  Example:
10977
 
10978
          mov.w %dsp8(sym)[a0],r1
10979
          mov.b #0,%dsp8(sym)[a0]
10980
 
10981
`%hi8'
10982
     This modifier allows you to load bits 16 through 23 of a 24 bit
10983
     address into an 8 bit register.  This is useful with, for example,
10984
     the M16C `smovf' instruction, which expects a 20 bit address in
10985
     `r1h' and `a0'.  Example:
10986
 
10987
          mov.b #%hi8(sym),r1h
10988
          mov.w #%lo16(sym),a0
10989
          smovf.b
10990
 
10991
`%lo16'
10992
     Likewise, this modifier allows you to load bits 0 through 15 of a
10993
     24 bit address into a 16 bit register.
10994
 
10995
`%hi16'
10996
     This modifier allows you to load bits 16 through 31 of a 32 bit
10997
     address into a 16 bit register.  While the M32C family only has 24
10998
     bits of address space, it does support addresses in pairs of 16 bit
10999
     registers (like `a1a0' for the `lde' instruction).  This modifier
11000
     is for loading the upper half in such cases.  Example:
11001
 
11002
          mov.w #%hi16(sym),a1
11003
          mov.w #%lo16(sym),a0
11004
          ...
11005
          lde.w [a1a0],r1
11006
 
11007
 
11008

11009
File: as.info,  Node: M32R-Dependent,  Next: M68K-Dependent,  Prev: M32C-Dependent,  Up: Machine Dependencies
11010
 
11011
9.20 M32R Dependent Features
11012
============================
11013
 
11014
* Menu:
11015
 
11016
* M32R-Opts::                   M32R Options
11017
* M32R-Directives::             M32R Directives
11018
* M32R-Warnings::               M32R Warnings
11019
 
11020

11021
File: as.info,  Node: M32R-Opts,  Next: M32R-Directives,  Up: M32R-Dependent
11022
 
11023
9.20.1 M32R Options
11024
-------------------
11025
 
11026
The Renease M32R version of `as' has a few machine dependent options:
11027
 
11028
`-m32rx'
11029
     `as' can assemble code for several different members of the
11030
     Renesas M32R family.  Normally the default is to assemble code for
11031
     the M32R microprocessor.  This option may be used to change the
11032
     default to the M32RX microprocessor, which adds some more
11033
     instructions to the basic M32R instruction set, and some
11034
     additional parameters to some of the original instructions.
11035
 
11036
`-m32r2'
11037
     This option changes the target processor to the the M32R2
11038
     microprocessor.
11039
 
11040
`-m32r'
11041
     This option can be used to restore the assembler's default
11042
     behaviour of assembling for the M32R microprocessor.  This can be
11043
     useful if the default has been changed by a previous command line
11044
     option.
11045
 
11046
`-little'
11047
     This option tells the assembler to produce little-endian code and
11048
     data.  The default is dependent upon how the toolchain was
11049
     configured.
11050
 
11051
`-EL'
11052
     This is a synonym for _-little_.
11053
 
11054
`-big'
11055
     This option tells the assembler to produce big-endian code and
11056
     data.
11057
 
11058
`-EB'
11059
     This is a synonum for _-big_.
11060
 
11061
`-KPIC'
11062
     This option specifies that the output of the assembler should be
11063
     marked as position-independent code (PIC).
11064
 
11065
`-parallel'
11066
     This option tells the assembler to attempts to combine two
11067
     sequential instructions into a single, parallel instruction, where
11068
     it is legal to do so.
11069
 
11070
`-no-parallel'
11071
     This option disables a previously enabled _-parallel_ option.
11072
 
11073
`-no-bitinst'
11074
     This option disables the support for the extended bit-field
11075
     instructions provided by the M32R2.  If this support needs to be
11076
     re-enabled the _-bitinst_ switch can be used to restore it.
11077
 
11078
`-O'
11079
     This option tells the assembler to attempt to optimize the
11080
     instructions that it produces.  This includes filling delay slots
11081
     and converting sequential instructions into parallel ones.  This
11082
     option implies _-parallel_.
11083
 
11084
`-warn-explicit-parallel-conflicts'
11085
     Instructs `as' to produce warning messages when questionable
11086
     parallel instructions are encountered.  This option is enabled by
11087
     default, but `gcc' disables it when it invokes `as' directly.
11088
     Questionable instructions are those whose behaviour would be
11089
     different if they were executed sequentially.  For example the
11090
     code fragment `mv r1, r2 || mv r3, r1' produces a different result
11091
     from `mv r1, r2 \n mv r3, r1' since the former moves r1 into r3
11092
     and then r2 into r1, whereas the later moves r2 into r1 and r3.
11093
 
11094
`-Wp'
11095
     This is a shorter synonym for the
11096
     _-warn-explicit-parallel-conflicts_ option.
11097
 
11098
`-no-warn-explicit-parallel-conflicts'
11099
     Instructs `as' not to produce warning messages when questionable
11100
     parallel instructions are encountered.
11101
 
11102
`-Wnp'
11103
     This is a shorter synonym for the
11104
     _-no-warn-explicit-parallel-conflicts_ option.
11105
 
11106
`-ignore-parallel-conflicts'
11107
     This option tells the assembler's to stop checking parallel
11108
     instructions for constraint violations.  This ability is provided
11109
     for hardware vendors testing chip designs and should not be used
11110
     under normal circumstances.
11111
 
11112
`-no-ignore-parallel-conflicts'
11113
     This option restores the assembler's default behaviour of checking
11114
     parallel instructions to detect constraint violations.
11115
 
11116
`-Ip'
11117
     This is a shorter synonym for the _-ignore-parallel-conflicts_
11118
     option.
11119
 
11120
`-nIp'
11121
     This is a shorter synonym for the _-no-ignore-parallel-conflicts_
11122
     option.
11123
 
11124
`-warn-unmatched-high'
11125
     This option tells the assembler to produce a warning message if a
11126
     `.high' pseudo op is encountered without a matching `.low' pseudo
11127
     op.  The presence of such an unmatched pseudo op usually indicates
11128
     a programming error.
11129
 
11130
`-no-warn-unmatched-high'
11131
     Disables a previously enabled _-warn-unmatched-high_ option.
11132
 
11133
`-Wuh'
11134
     This is a shorter synonym for the _-warn-unmatched-high_ option.
11135
 
11136
`-Wnuh'
11137
     This is a shorter synonym for the _-no-warn-unmatched-high_ option.
11138
 
11139
 
11140

11141
File: as.info,  Node: M32R-Directives,  Next: M32R-Warnings,  Prev: M32R-Opts,  Up: M32R-Dependent
11142
 
11143
9.20.2 M32R Directives
11144
----------------------
11145
 
11146
The Renease M32R version of `as' has a few architecture specific
11147
directives:
11148
 
11149
`low EXPRESSION'
11150
     The `low' directive computes the value of its expression and
11151
     places the lower 16-bits of the result into the immediate-field of
11152
     the instruction.  For example:
11153
 
11154
             or3   r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678
11155
             add3, r0, r0, #low(fred)   ; compute r0 = r0 + low 16-bits of address of fred
11156
 
11157
`high EXPRESSION'
11158
     The `high' directive computes the value of its expression and
11159
     places the upper 16-bits of the result into the immediate-field of
11160
     the instruction.  For example:
11161
 
11162
             seth  r0, #high(0x12345678) ; compute r0 = 0x12340000
11163
             seth, r0, #high(fred)       ; compute r0 = upper 16-bits of address of fred
11164
 
11165
`shigh EXPRESSION'
11166
     The `shigh' directive is very similar to the `high' directive.  It
11167
     also computes the value of its expression and places the upper
11168
     16-bits of the result into the immediate-field of the instruction.
11169
     The difference is that `shigh' also checks to see if the lower
11170
     16-bits could be interpreted as a signed number, and if so it
11171
     assumes that a borrow will occur from the upper-16 bits.  To
11172
     compensate for this the `shigh' directive pre-biases the upper 16
11173
     bit value by adding one to it.  For example:
11174
 
11175
     For example:
11176
 
11177
             seth  r0, #shigh(0x12345678) ; compute r0 = 0x12340000
11178
             seth  r0, #shigh(0x00008000) ; compute r0 = 0x00010000
11179
 
11180
     In the second example the lower 16-bits are 0x8000.  If these are
11181
     treated as a signed value and sign extended to 32-bits then the
11182
     value becomes 0xffff8000.  If this value is then added to
11183
     0x00010000 then the result is 0x00008000.
11184
 
11185
     This behaviour is to allow for the different semantics of the
11186
     `or3' and `add3' instructions.  The `or3' instruction treats its
11187
     16-bit immediate argument as unsigned whereas the `add3' treats
11188
     its 16-bit immediate as a signed value.  So for example:
11189
 
11190
             seth  r0, #shigh(0x00008000)
11191
             add3  r0, r0, #low(0x00008000)
11192
 
11193
     Produces the correct result in r0, whereas:
11194
 
11195
             seth  r0, #shigh(0x00008000)
11196
             or3   r0, r0, #low(0x00008000)
11197
 
11198
     Stores 0xffff8000 into r0.
11199
 
11200
     Note - the `shigh' directive does not know where in the assembly
11201
     source code the lower 16-bits of the value are going set, so it
11202
     cannot check to make sure that an `or3' instruction is being used
11203
     rather than an `add3' instruction.  It is up to the programmer to
11204
     make sure that correct directives are used.
11205
 
11206
`.m32r'
11207
     The directive performs a similar thing as the _-m32r_ command line
11208
     option.  It tells the assembler to only accept M32R instructions
11209
     from now on.  An instructions from later M32R architectures are
11210
     refused.
11211
 
11212
`.m32rx'
11213
     The directive performs a similar thing as the _-m32rx_ command
11214
     line option.  It tells the assembler to start accepting the extra
11215
     instructions in the M32RX ISA as well as the ordinary M32R ISA.
11216
 
11217
`.m32r2'
11218
     The directive performs a similar thing as the _-m32r2_ command
11219
     line option.  It tells the assembler to start accepting the extra
11220
     instructions in the M32R2 ISA as well as the ordinary M32R ISA.
11221
 
11222
`.little'
11223
     The directive performs a similar thing as the _-little_ command
11224
     line option.  It tells the assembler to start producing
11225
     little-endian code and data.  This option should be used with care
11226
     as producing mixed-endian binary files is fraught with danger.
11227
 
11228
`.big'
11229
     The directive performs a similar thing as the _-big_ command line
11230
     option.  It tells the assembler to start producing big-endian code
11231
     and data.  This option should be used with care as producing
11232
     mixed-endian binary files is fraught with danger.
11233
 
11234
 
11235

11236
File: as.info,  Node: M32R-Warnings,  Prev: M32R-Directives,  Up: M32R-Dependent
11237
 
11238
9.20.3 M32R Warnings
11239
--------------------
11240
 
11241
There are several warning and error messages that can be produced by
11242
`as' which are specific to the M32R:
11243
 
11244
`output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?'
11245
     This message is only produced if warnings for explicit parallel
11246
     conflicts have been enabled.  It indicates that the assembler has
11247
     encountered a parallel instruction in which the destination
11248
     register of the left hand instruction is used as an input register
11249
     in the right hand instruction.  For example in this code fragment
11250
     `mv r1, r2 || neg r3, r1' register r1 is the destination of the
11251
     move instruction and the input to the neg instruction.
11252
 
11253
`output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?'
11254
     This message is only produced if warnings for explicit parallel
11255
     conflicts have been enabled.  It indicates that the assembler has
11256
     encountered a parallel instruction in which the destination
11257
     register of the right hand instruction is used as an input
11258
     register in the left hand instruction.  For example in this code
11259
     fragment `mv r1, r2 || neg r2, r3' register r2 is the destination
11260
     of the neg instruction and the input to the move instruction.
11261
 
11262
`instruction `...' is for the M32RX only'
11263
     This message is produced when the assembler encounters an
11264
     instruction which is only supported by the M32Rx processor, and
11265
     the `-m32rx' command line flag has not been specified to allow
11266
     assembly of such instructions.
11267
 
11268
`unknown instruction `...''
11269
     This message is produced when the assembler encounters an
11270
     instruction which it does not recognize.
11271
 
11272
`only the NOP instruction can be issued in parallel on the m32r'
11273
     This message is produced when the assembler encounters a parallel
11274
     instruction which does not involve a NOP instruction and the
11275
     `-m32rx' command line flag has not been specified.  Only the M32Rx
11276
     processor is able to execute two instructions in parallel.
11277
 
11278
`instruction `...' cannot be executed in parallel.'
11279
     This message is produced when the assembler encounters a parallel
11280
     instruction which is made up of one or two instructions which
11281
     cannot be executed in parallel.
11282
 
11283
`Instructions share the same execution pipeline'
11284
     This message is produced when the assembler encounters a parallel
11285
     instruction whoes components both use the same execution pipeline.
11286
 
11287
`Instructions write to the same destination register.'
11288
     This message is produced when the assembler encounters a parallel
11289
     instruction where both components attempt to modify the same
11290
     register.  For example these code fragments will produce this
11291
     message: `mv r1, r2 || neg r1, r3' `jl r0 || mv r14, r1' `st r2,
11292
     @-r1 || mv r1, r3' `mv r1, r2 || ld r0, @r1+' `cmp r1, r2 || addx
11293
     r3, r4' (Both write to the condition bit)
11294
 
11295
 
11296

11297
File: as.info,  Node: M68K-Dependent,  Next: M68HC11-Dependent,  Prev: M32R-Dependent,  Up: Machine Dependencies
11298
 
11299
9.21 M680x0 Dependent Features
11300
==============================
11301
 
11302
* Menu:
11303
 
11304
* M68K-Opts::                   M680x0 Options
11305
* M68K-Syntax::                 Syntax
11306
* M68K-Moto-Syntax::            Motorola Syntax
11307
* M68K-Float::                  Floating Point
11308
* M68K-Directives::             680x0 Machine Directives
11309
* M68K-opcodes::                Opcodes
11310
 
11311

11312
File: as.info,  Node: M68K-Opts,  Next: M68K-Syntax,  Up: M68K-Dependent
11313
 
11314
9.21.1 M680x0 Options
11315
---------------------
11316
 
11317
The Motorola 680x0 version of `as' has a few machine dependent options:
11318
 
11319
`-march=ARCHITECTURE'
11320
     This option specifies a target architecture.  The following
11321
     architectures are recognized: `68000', `68010', `68020', `68030',
11322
     `68040', `68060', `cpu32', `isaa', `isaaplus', `isab', `isac' and
11323
     `cfv4e'.
11324
 
11325
`-mcpu=CPU'
11326
     This option specifies a target cpu.  When used in conjunction with
11327
     the `-march' option, the cpu must be within the specified
11328
     architecture.  Also, the generic features of the architecture are
11329
     used for instruction generation, rather than those of the specific
11330
     chip.
11331
 
11332
`-m[no-]68851'
11333
 
11334
`-m[no-]68881'
11335
 
11336
`-m[no-]div'
11337
 
11338
`-m[no-]usp'
11339
 
11340
`-m[no-]float'
11341
 
11342
`-m[no-]mac'
11343
 
11344
`-m[no-]emac'
11345
     Enable or disable various architecture specific features.  If a
11346
     chip or architecture by default supports an option (for instance
11347
     `-march=isaaplus' includes the `-mdiv' option), explicitly
11348
     disabling the option will override the default.
11349
 
11350
`-l'
11351
     You can use the `-l' option to shorten the size of references to
11352
     undefined symbols.  If you do not use the `-l' option, references
11353
     to undefined symbols are wide enough for a full `long' (32 bits).
11354
     (Since `as' cannot know where these symbols end up, `as' can only
11355
     allocate space for the linker to fill in later.  Since `as' does
11356
     not know how far away these symbols are, it allocates as much
11357
     space as it can.)  If you use this option, the references are only
11358
     one word wide (16 bits).  This may be useful if you want the
11359
     object file to be as small as possible, and you know that the
11360
     relevant symbols are always less than 17 bits away.
11361
 
11362
`--register-prefix-optional'
11363
     For some configurations, especially those where the compiler
11364
     normally does not prepend an underscore to the names of user
11365
     variables, the assembler requires a `%' before any use of a
11366
     register name.  This is intended to let the assembler distinguish
11367
     between C variables and functions named `a0' through `a7', and so
11368
     on.  The `%' is always accepted, but is not required for certain
11369
     configurations, notably `sun3'.  The `--register-prefix-optional'
11370
     option may be used to permit omitting the `%' even for
11371
     configurations for which it is normally required.  If this is
11372
     done, it will generally be impossible to refer to C variables and
11373
     functions with the same names as register names.
11374
 
11375
`--bitwise-or'
11376
     Normally the character `|' is treated as a comment character, which
11377
     means that it can not be used in expressions.  The `--bitwise-or'
11378
     option turns `|' into a normal character.  In this mode, you must
11379
     either use C style comments, or start comments with a `#' character
11380
     at the beginning of a line.
11381
 
11382
`--base-size-default-16  --base-size-default-32'
11383
     If you use an addressing mode with a base register without
11384
     specifying the size, `as' will normally use the full 32 bit value.
11385
     For example, the addressing mode `%a0@(%d0)' is equivalent to
11386
     `%a0@(%d0:l)'.  You may use the `--base-size-default-16' option to
11387
     tell `as' to default to using the 16 bit value.  In this case,
11388
     `%a0@(%d0)' is equivalent to `%a0@(%d0:w)'.  You may use the
11389
     `--base-size-default-32' option to restore the default behaviour.
11390
 
11391
`--disp-size-default-16  --disp-size-default-32'
11392
     If you use an addressing mode with a displacement, and the value
11393
     of the displacement is not known, `as' will normally assume that
11394
     the value is 32 bits.  For example, if the symbol `disp' has not
11395
     been defined, `as' will assemble the addressing mode
11396
     `%a0@(disp,%d0)' as though `disp' is a 32 bit value.  You may use
11397
     the `--disp-size-default-16' option to tell `as' to instead assume
11398
     that the displacement is 16 bits.  In this case, `as' will
11399
     assemble `%a0@(disp,%d0)' as though `disp' is a 16 bit value.  You
11400
     may use the `--disp-size-default-32' option to restore the default
11401
     behaviour.
11402
 
11403
`--pcrel'
11404
     Always keep branches PC-relative.  In the M680x0 architecture all
11405
     branches are defined as PC-relative.  However, on some processors
11406
     they are limited to word displacements maximum.  When `as' needs a
11407
     long branch that is not available, it normally emits an absolute
11408
     jump instead.  This option disables this substitution.  When this
11409
     option is given and no long branches are available, only word
11410
     branches will be emitted.  An error message will be generated if a
11411
     word branch cannot reach its target.  This option has no effect on
11412
     68020 and other processors that have long branches.  *note Branch
11413
     Improvement: M68K-Branch.
11414
 
11415
`-m68000'
11416
     `as' can assemble code for several different members of the
11417
     Motorola 680x0 family.  The default depends upon how `as' was
11418
     configured when it was built; normally, the default is to assemble
11419
     code for the 68020 microprocessor.  The following options may be
11420
     used to change the default.  These options control which
11421
     instructions and addressing modes are permitted.  The members of
11422
     the 680x0 family are very similar.  For detailed information about
11423
     the differences, see the Motorola manuals.
11424
 
11425
    `-m68000'
11426
    `-m68ec000'
11427
    `-m68hc000'
11428
    `-m68hc001'
11429
    `-m68008'
11430
    `-m68302'
11431
    `-m68306'
11432
    `-m68307'
11433
    `-m68322'
11434
    `-m68356'
11435
          Assemble for the 68000. `-m68008', `-m68302', and so on are
11436
          synonyms for `-m68000', since the chips are the same from the
11437
          point of view of the assembler.
11438
 
11439
    `-m68010'
11440
          Assemble for the 68010.
11441
 
11442
    `-m68020'
11443
    `-m68ec020'
11444
          Assemble for the 68020.  This is normally the default.
11445
 
11446
    `-m68030'
11447
    `-m68ec030'
11448
          Assemble for the 68030.
11449
 
11450
    `-m68040'
11451
    `-m68ec040'
11452
          Assemble for the 68040.
11453
 
11454
    `-m68060'
11455
    `-m68ec060'
11456
          Assemble for the 68060.
11457
 
11458
    `-mcpu32'
11459
    `-m68330'
11460
    `-m68331'
11461
    `-m68332'
11462
    `-m68333'
11463
    `-m68334'
11464
    `-m68336'
11465
    `-m68340'
11466
    `-m68341'
11467
    `-m68349'
11468
    `-m68360'
11469
          Assemble for the CPU32 family of chips.
11470
 
11471
    `-m5200'
11472
 
11473
    `-m5202'
11474
 
11475
    `-m5204'
11476
 
11477
    `-m5206'
11478
 
11479
    `-m5206e'
11480
 
11481
    `-m521x'
11482
 
11483
    `-m5249'
11484
 
11485
    `-m528x'
11486
 
11487
    `-m5307'
11488
 
11489
    `-m5407'
11490
 
11491
    `-m547x'
11492
 
11493
    `-m548x'
11494
 
11495
    `-mcfv4'
11496
 
11497
    `-mcfv4e'
11498
          Assemble for the ColdFire family of chips.
11499
 
11500
    `-m68881'
11501
    `-m68882'
11502
          Assemble 68881 floating point instructions.  This is the
11503
          default for the 68020, 68030, and the CPU32.  The 68040 and
11504
          68060 always support floating point instructions.
11505
 
11506
    `-mno-68881'
11507
          Do not assemble 68881 floating point instructions.  This is
11508
          the default for 68000 and the 68010.  The 68040 and 68060
11509
          always support floating point instructions, even if this
11510
          option is used.
11511
 
11512
    `-m68851'
11513
          Assemble 68851 MMU instructions.  This is the default for the
11514
          68020, 68030, and 68060.  The 68040 accepts a somewhat
11515
          different set of MMU instructions; `-m68851' and `-m68040'
11516
          should not be used together.
11517
 
11518
    `-mno-68851'
11519
          Do not assemble 68851 MMU instructions.  This is the default
11520
          for the 68000, 68010, and the CPU32.  The 68040 accepts a
11521
          somewhat different set of MMU instructions.
11522
 
11523

11524
File: as.info,  Node: M68K-Syntax,  Next: M68K-Moto-Syntax,  Prev: M68K-Opts,  Up: M68K-Dependent
11525
 
11526
9.21.2 Syntax
11527
-------------
11528
 
11529
This syntax for the Motorola 680x0 was developed at MIT.
11530
 
11531
   The 680x0 version of `as' uses instructions names and syntax
11532
compatible with the Sun assembler.  Intervening periods are ignored;
11533
for example, `movl' is equivalent to `mov.l'.
11534
 
11535
   In the following table APC stands for any of the address registers
11536
(`%a0' through `%a7'), the program counter (`%pc'), the zero-address
11537
relative to the program counter (`%zpc'), a suppressed address register
11538
(`%za0' through `%za7'), or it may be omitted entirely.  The use of
11539
SIZE means one of `w' or `l', and it may be omitted, along with the
11540
leading colon, unless a scale is also specified.  The use of SCALE
11541
means one of `1', `2', `4', or `8', and it may always be omitted along
11542
with the leading colon.
11543
 
11544
   The following addressing modes are understood:
11545
"Immediate"
11546
     `#NUMBER'
11547
 
11548
"Data Register"
11549
     `%d0' through `%d7'
11550
 
11551
"Address Register"
11552
     `%a0' through `%a7'
11553
     `%a7' is also known as `%sp', i.e., the Stack Pointer.  `%a6' is
11554
     also known as `%fp', the Frame Pointer.
11555
 
11556
"Address Register Indirect"
11557
     `%a0@' through `%a7@'
11558
 
11559
"Address Register Postincrement"
11560
     `%a0@+' through `%a7@+'
11561
 
11562
"Address Register Predecrement"
11563
     `%a0@-' through `%a7@-'
11564
 
11565
"Indirect Plus Offset"
11566
     `APC@(NUMBER)'
11567
 
11568
"Index"
11569
     `APC@(NUMBER,REGISTER:SIZE:SCALE)'
11570
 
11571
     The NUMBER may be omitted.
11572
 
11573
"Postindex"
11574
     `APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)'
11575
 
11576
     The ONUMBER or the REGISTER, but not both, may be omitted.
11577
 
11578
"Preindex"
11579
     `APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)'
11580
 
11581
     The NUMBER may be omitted.  Omitting the REGISTER produces the
11582
     Postindex addressing mode.
11583
 
11584
"Absolute"
11585
     `SYMBOL', or `DIGITS', optionally followed by `:b', `:w', or `:l'.
11586
 
11587

11588
File: as.info,  Node: M68K-Moto-Syntax,  Next: M68K-Float,  Prev: M68K-Syntax,  Up: M68K-Dependent
11589
 
11590
9.21.3 Motorola Syntax
11591
----------------------
11592
 
11593
The standard Motorola syntax for this chip differs from the syntax
11594
already discussed (*note Syntax: M68K-Syntax.).  `as' can accept
11595
Motorola syntax for operands, even if MIT syntax is used for other
11596
operands in the same instruction.  The two kinds of syntax are fully
11597
compatible.
11598
 
11599
   In the following table APC stands for any of the address registers
11600
(`%a0' through `%a7'), the program counter (`%pc'), the zero-address
11601
relative to the program counter (`%zpc'), or a suppressed address
11602
register (`%za0' through `%za7').  The use of SIZE means one of `w' or
11603
`l', and it may always be omitted along with the leading dot.  The use
11604
of SCALE means one of `1', `2', `4', or `8', and it may always be
11605
omitted along with the leading asterisk.
11606
 
11607
   The following additional addressing modes are understood:
11608
 
11609
"Address Register Indirect"
11610
     `(%a0)' through `(%a7)'
11611
     `%a7' is also known as `%sp', i.e., the Stack Pointer.  `%a6' is
11612
     also known as `%fp', the Frame Pointer.
11613
 
11614
"Address Register Postincrement"
11615
     `(%a0)+' through `(%a7)+'
11616
 
11617
"Address Register Predecrement"
11618
     `-(%a0)' through `-(%a7)'
11619
 
11620
"Indirect Plus Offset"
11621
     `NUMBER(%A0)' through `NUMBER(%A7)', or `NUMBER(%PC)'.
11622
 
11623
     The NUMBER may also appear within the parentheses, as in
11624
     `(NUMBER,%A0)'.  When used with the PC, the NUMBER may be omitted
11625
     (with an address register, omitting the NUMBER produces Address
11626
     Register Indirect mode).
11627
 
11628
"Index"
11629
     `NUMBER(APC,REGISTER.SIZE*SCALE)'
11630
 
11631
     The NUMBER may be omitted, or it may appear within the
11632
     parentheses.  The APC may be omitted.  The REGISTER and the APC
11633
     may appear in either order.  If both APC and REGISTER are address
11634
     registers, and the SIZE and SCALE are omitted, then the first
11635
     register is taken as the base register, and the second as the
11636
     index register.
11637
 
11638
"Postindex"
11639
     `([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)'
11640
 
11641
     The ONUMBER, or the REGISTER, or both, may be omitted.  Either the
11642
     NUMBER or the APC may be omitted, but not both.
11643
 
11644
"Preindex"
11645
     `([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)'
11646
 
11647
     The NUMBER, or the APC, or the REGISTER, or any two of them, may
11648
     be omitted.  The ONUMBER may be omitted.  The REGISTER and the APC
11649
     may appear in either order.  If both APC and REGISTER are address
11650
     registers, and the SIZE and SCALE are omitted, then the first
11651
     register is taken as the base register, and the second as the
11652
     index register.
11653
 
11654

11655
File: as.info,  Node: M68K-Float,  Next: M68K-Directives,  Prev: M68K-Moto-Syntax,  Up: M68K-Dependent
11656
 
11657
9.21.4 Floating Point
11658
---------------------
11659
 
11660
Packed decimal (P) format floating literals are not supported.  Feel
11661
free to add the code!
11662
 
11663
   The floating point formats generated by directives are these.
11664
 
11665
`.float'
11666
     `Single' precision floating point constants.
11667
 
11668
`.double'
11669
     `Double' precision floating point constants.
11670
 
11671
`.extend'
11672
`.ldouble'
11673
     `Extended' precision (`long double') floating point constants.
11674
 
11675

11676
File: as.info,  Node: M68K-Directives,  Next: M68K-opcodes,  Prev: M68K-Float,  Up: M68K-Dependent
11677
 
11678
9.21.5 680x0 Machine Directives
11679
-------------------------------
11680
 
11681
In order to be compatible with the Sun assembler the 680x0 assembler
11682
understands the following directives.
11683
 
11684
`.data1'
11685
     This directive is identical to a `.data 1' directive.
11686
 
11687
`.data2'
11688
     This directive is identical to a `.data 2' directive.
11689
 
11690
`.even'
11691
     This directive is a special case of the `.align' directive; it
11692
     aligns the output to an even byte boundary.
11693
 
11694
`.skip'
11695
     This directive is identical to a `.space' directive.
11696
 
11697
`.arch NAME'
11698
     Select the target architecture and extension features.  Valid
11699
     values for NAME are the same as for the `-march' command line
11700
     option.  This directive cannot be specified after any instructions
11701
     have been assembled.  If it is given multiple times, or in
11702
     conjunction with the `-march' option, all uses must be for the
11703
     same architecture and extension set.
11704
 
11705
`.cpu NAME'
11706
     Select the target cpu.  Valid valuse for NAME are the same as for
11707
     the `-mcpu' command line option.  This directive cannot be
11708
     specified after any instructions have been assembled.  If it is
11709
     given multiple times, or in conjunction with the `-mopt' option,
11710
     all uses must be for the same cpu.
11711
 
11712
 
11713

11714
File: as.info,  Node: M68K-opcodes,  Prev: M68K-Directives,  Up: M68K-Dependent
11715
 
11716
9.21.6 Opcodes
11717
--------------
11718
 
11719
* Menu:
11720
 
11721
* M68K-Branch::                 Branch Improvement
11722
* M68K-Chars::                  Special Characters
11723
 
11724

11725
File: as.info,  Node: M68K-Branch,  Next: M68K-Chars,  Up: M68K-opcodes
11726
 
11727
9.21.6.1 Branch Improvement
11728
...........................
11729
 
11730
Certain pseudo opcodes are permitted for branch instructions.  They
11731
expand to the shortest branch instruction that reach the target.
11732
Generally these mnemonics are made by substituting `j' for `b' at the
11733
start of a Motorola mnemonic.
11734
 
11735
   The following table summarizes the pseudo-operations.  A `*' flags
11736
cases that are more fully described after the table:
11737
 
11738
               Displacement
11739
               +------------------------------------------------------------
11740
               |                68020           68000/10, not PC-relative OK
11741
     Pseudo-Op |BYTE    WORD    LONG            ABSOLUTE LONG JUMP    **
11742
               +------------------------------------------------------------
11743
          jbsr |bsrs    bsrw    bsrl            jsr
11744
           jra |bras    braw    bral            jmp
11745
     *     jXX |bXXs    bXXw    bXXl            bNXs;jmp
11746
     *    dbXX | N/A    dbXXw   dbXX;bras;bral  dbXX;bras;jmp
11747
          fjXX | N/A    fbXXw   fbXXl            N/A
11748
 
11749
     XX: condition
11750
     NX: negative of condition XX
11751
                       `*'--see full description below
11752
         `**'--this expansion mode is disallowed by `--pcrel'
11753
 
11754
`jbsr'
11755
`jra'
11756
     These are the simplest jump pseudo-operations; they always map to
11757
     one particular machine instruction, depending on the displacement
11758
     to the branch target.  This instruction will be a byte or word
11759
     branch is that is sufficient.  Otherwise, a long branch will be
11760
     emitted if available.  If no long branches are available and the
11761
     `--pcrel' option is not given, an absolute long jump will be
11762
     emitted instead.  If no long branches are available, the `--pcrel'
11763
     option is given, and a word branch cannot reach the target, an
11764
     error message is generated.
11765
 
11766
     In addition to standard branch operands, `as' allows these
11767
     pseudo-operations to have all operands that are allowed for jsr
11768
     and jmp, substituting these instructions if the operand given is
11769
     not valid for a branch instruction.
11770
 
11771
`jXX'
11772
     Here, `jXX' stands for an entire family of pseudo-operations,
11773
     where XX is a conditional branch or condition-code test.  The full
11774
     list of pseudo-ops in this family is:
11775
           jhi   jls   jcc   jcs   jne   jeq   jvc
11776
           jvs   jpl   jmi   jge   jlt   jgt   jle
11777
 
11778
     Usually, each of these pseudo-operations expands to a single branch
11779
     instruction.  However, if a word branch is not sufficient, no long
11780
     branches are available, and the `--pcrel' option is not given, `as'
11781
     issues a longer code fragment in terms of NX, the opposite
11782
     condition to XX.  For example, under these conditions:
11783
              jXX foo
11784
     gives
11785
               bNXs oof
11786
               jmp foo
11787
           oof:
11788
 
11789
`dbXX'
11790
     The full family of pseudo-operations covered here is
11791
           dbhi   dbls   dbcc   dbcs   dbne   dbeq   dbvc
11792
           dbvs   dbpl   dbmi   dbge   dblt   dbgt   dble
11793
           dbf    dbra   dbt
11794
 
11795
     Motorola `dbXX' instructions allow word displacements only.  When
11796
     a word displacement is sufficient, each of these pseudo-operations
11797
     expands to the corresponding Motorola instruction.  When a word
11798
     displacement is not sufficient and long branches are available,
11799
     when the source reads `dbXX foo', `as' emits
11800
               dbXX oo1
11801
               bras oo2
11802
           oo1:bral foo
11803
           oo2:
11804
 
11805
     If, however, long branches are not available and the `--pcrel'
11806
     option is not given, `as' emits
11807
               dbXX oo1
11808
               bras oo2
11809
           oo1:jmp foo
11810
           oo2:
11811
 
11812
`fjXX'
11813
     This family includes
11814
           fjne   fjeq   fjge   fjlt   fjgt   fjle   fjf
11815
           fjt    fjgl   fjgle  fjnge  fjngl  fjngle fjngt
11816
           fjnle  fjnlt  fjoge  fjogl  fjogt  fjole  fjolt
11817
           fjor   fjseq  fjsf   fjsne  fjst   fjueq  fjuge
11818
           fjugt  fjule  fjult  fjun
11819
 
11820
     Each of these pseudo-operations always expands to a single Motorola
11821
     coprocessor branch instruction, word or long.  All Motorola
11822
     coprocessor branch instructions allow both word and long
11823
     displacements.
11824
 
11825
 
11826

11827
File: as.info,  Node: M68K-Chars,  Prev: M68K-Branch,  Up: M68K-opcodes
11828
 
11829
9.21.6.2 Special Characters
11830
...........................
11831
 
11832
The immediate character is `#' for Sun compatibility.  The line-comment
11833
character is `|' (unless the `--bitwise-or' option is used).  If a `#'
11834
appears at the beginning of a line, it is treated as a comment unless
11835
it looks like `# line file', in which case it is treated normally.
11836
 
11837

11838
File: as.info,  Node: M68HC11-Dependent,  Next: MicroBlaze-Dependent,  Prev: M68K-Dependent,  Up: Machine Dependencies
11839
 
11840
9.22 M68HC11 and M68HC12 Dependent Features
11841
===========================================
11842
 
11843
* Menu:
11844
 
11845
* M68HC11-Opts::                   M68HC11 and M68HC12 Options
11846
* M68HC11-Syntax::                 Syntax
11847
* M68HC11-Modifiers::              Symbolic Operand Modifiers
11848
* M68HC11-Directives::             Assembler Directives
11849
* M68HC11-Float::                  Floating Point
11850
* M68HC11-opcodes::                Opcodes
11851
 
11852

11853
File: as.info,  Node: M68HC11-Opts,  Next: M68HC11-Syntax,  Up: M68HC11-Dependent
11854
 
11855
9.22.1 M68HC11 and M68HC12 Options
11856
----------------------------------
11857
 
11858
The Motorola 68HC11 and 68HC12 version of `as' have a few machine
11859
dependent options.
11860
 
11861
`-m68hc11'
11862
     This option switches the assembler in the M68HC11 mode. In this
11863
     mode, the assembler only accepts 68HC11 operands and mnemonics. It
11864
     produces code for the 68HC11.
11865
 
11866
`-m68hc12'
11867
     This option switches the assembler in the M68HC12 mode. In this
11868
     mode, the assembler also accepts 68HC12 operands and mnemonics. It
11869
     produces code for the 68HC12. A few 68HC11 instructions are
11870
     replaced by some 68HC12 instructions as recommended by Motorola
11871
     specifications.
11872
 
11873
`-m68hcs12'
11874
     This option switches the assembler in the M68HCS12 mode.  This
11875
     mode is similar to `-m68hc12' but specifies to assemble for the
11876
     68HCS12 series.  The only difference is on the assembling of the
11877
     `movb' and `movw' instruction when a PC-relative operand is used.
11878
 
11879
`-mshort'
11880
     This option controls the ABI and indicates to use a 16-bit integer
11881
     ABI.  It has no effect on the assembled instructions.  This is the
11882
     default.
11883
 
11884
`-mlong'
11885
     This option controls the ABI and indicates to use a 32-bit integer
11886
     ABI.
11887
 
11888
`-mshort-double'
11889
     This option controls the ABI and indicates to use a 32-bit float
11890
     ABI.  This is the default.
11891
 
11892
`-mlong-double'
11893
     This option controls the ABI and indicates to use a 64-bit float
11894
     ABI.
11895
 
11896
`--strict-direct-mode'
11897
     You can use the `--strict-direct-mode' option to disable the
11898
     automatic translation of direct page mode addressing into extended
11899
     mode when the instruction does not support direct mode.  For
11900
     example, the `clr' instruction does not support direct page mode
11901
     addressing. When it is used with the direct page mode, `as' will
11902
     ignore it and generate an absolute addressing.  This option
11903
     prevents `as' from doing this, and the wrong usage of the direct
11904
     page mode will raise an error.
11905
 
11906
`--short-branches'
11907
     The `--short-branches' option turns off the translation of
11908
     relative branches into absolute branches when the branch offset is
11909
     out of range. By default `as' transforms the relative branch
11910
     (`bsr', `bgt', `bge', `beq', `bne', `ble', `blt', `bhi', `bcc',
11911
     `bls', `bcs', `bmi', `bvs', `bvs', `bra') into an absolute branch
11912
     when the offset is out of the -128 .. 127 range.  In that case,
11913
     the `bsr' instruction is translated into a `jsr', the `bra'
11914
     instruction is translated into a `jmp' and the conditional
11915
     branches instructions are inverted and followed by a `jmp'. This
11916
     option disables these translations and `as' will generate an error
11917
     if a relative branch is out of range. This option does not affect
11918
     the optimization associated to the `jbra', `jbsr' and `jbXX'
11919
     pseudo opcodes.
11920
 
11921
`--force-long-branches'
11922
     The `--force-long-branches' option forces the translation of
11923
     relative branches into absolute branches. This option does not
11924
     affect the optimization associated to the `jbra', `jbsr' and
11925
     `jbXX' pseudo opcodes.
11926
 
11927
`--print-insn-syntax'
11928
     You can use the `--print-insn-syntax' option to obtain the syntax
11929
     description of the instruction when an error is detected.
11930
 
11931
`--print-opcodes'
11932
     The `--print-opcodes' option prints the list of all the
11933
     instructions with their syntax. The first item of each line
11934
     represents the instruction name and the rest of the line indicates
11935
     the possible operands for that instruction. The list is printed in
11936
     alphabetical order. Once the list is printed `as' exits.
11937
 
11938
`--generate-example'
11939
     The `--generate-example' option is similar to `--print-opcodes'
11940
     but it generates an example for each instruction instead.
11941
 
11942

11943
File: as.info,  Node: M68HC11-Syntax,  Next: M68HC11-Modifiers,  Prev: M68HC11-Opts,  Up: M68HC11-Dependent
11944
 
11945
9.22.2 Syntax
11946
-------------
11947
 
11948
In the M68HC11 syntax, the instruction name comes first and it may be
11949
followed by one or several operands (up to three). Operands are
11950
separated by comma (`,'). In the normal mode, `as' will complain if too
11951
many operands are specified for a given instruction. In the MRI mode
11952
(turned on with `-M' option), it will treat them as comments. Example:
11953
 
11954
     inx
11955
     lda  #23
11956
     bset 2,x #4
11957
     brclr *bot #8 foo
11958
 
11959
   The following addressing modes are understood for 68HC11 and 68HC12:
11960
"Immediate"
11961
     `#NUMBER'
11962
 
11963
"Address Register"
11964
     `NUMBER,X', `NUMBER,Y'
11965
 
11966
     The NUMBER may be omitted in which case 0 is assumed.
11967
 
11968
"Direct Addressing mode"
11969
     `*SYMBOL', or `*DIGITS'
11970
 
11971
"Absolute"
11972
     `SYMBOL', or `DIGITS'
11973
 
11974
   The M68HC12 has other more complex addressing modes. All of them are
11975
supported and they are represented below:
11976
 
11977
"Constant Offset Indexed Addressing Mode"
11978
     `NUMBER,REG'
11979
 
11980
     The NUMBER may be omitted in which case 0 is assumed.  The
11981
     register can be either `X', `Y', `SP' or `PC'.  The assembler will
11982
     use the smaller post-byte definition according to the constant
11983
     value (5-bit constant offset, 9-bit constant offset or 16-bit
11984
     constant offset).  If the constant is not known by the assembler
11985
     it will use the 16-bit constant offset post-byte and the value
11986
     will be resolved at link time.
11987
 
11988
"Offset Indexed Indirect"
11989
     `[NUMBER,REG]'
11990
 
11991
     The register can be either `X', `Y', `SP' or `PC'.
11992
 
11993
"Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement"
11994
     `NUMBER,-REG' `NUMBER,+REG' `NUMBER,REG-' `NUMBER,REG+'
11995
 
11996
     The number must be in the range `-8'..`+8' and must not be 0.  The
11997
     register can be either `X', `Y', `SP' or `PC'.
11998
 
11999
"Accumulator Offset"
12000
     `ACC,REG'
12001
 
12002
     The accumulator register can be either `A', `B' or `D'.  The
12003
     register can be either `X', `Y', `SP' or `PC'.
12004
 
12005
"Accumulator D offset indexed-indirect"
12006
     `[D,REG]'
12007
 
12008
     The register can be either `X', `Y', `SP' or `PC'.
12009
 
12010
 
12011
   For example:
12012
 
12013
     ldab 1024,sp
12014
     ldd [10,x]
12015
     orab 3,+x
12016
     stab -2,y-
12017
     ldx a,pc
12018
     sty [d,sp]
12019
 
12020

12021
File: as.info,  Node: M68HC11-Modifiers,  Next: M68HC11-Directives,  Prev: M68HC11-Syntax,  Up: M68HC11-Dependent
12022
 
12023
9.22.3 Symbolic Operand Modifiers
12024
---------------------------------
12025
 
12026
The assembler supports several modifiers when using symbol addresses in
12027
68HC11 and 68HC12 instruction operands.  The general syntax is the
12028
following:
12029
 
12030
     %modifier(symbol)
12031
 
12032
`%addr'
12033
     This modifier indicates to the assembler and linker to use the
12034
     16-bit physical address corresponding to the symbol.  This is
12035
     intended to be used on memory window systems to map a symbol in
12036
     the memory bank window.  If the symbol is in a memory expansion
12037
     part, the physical address corresponds to the symbol address
12038
     within the memory bank window.  If the symbol is not in a memory
12039
     expansion part, this is the symbol address (using or not using the
12040
     %addr modifier has no effect in that case).
12041
 
12042
`%page'
12043
     This modifier indicates to use the memory page number corresponding
12044
     to the symbol.  If the symbol is in a memory expansion part, its
12045
     page number is computed by the linker as a number used to map the
12046
     page containing the symbol in the memory bank window.  If the
12047
     symbol is not in a memory expansion part, the page number is 0.
12048
 
12049
`%hi'
12050
     This modifier indicates to use the 8-bit high part of the physical
12051
     address of the symbol.
12052
 
12053
`%lo'
12054
     This modifier indicates to use the 8-bit low part of the physical
12055
     address of the symbol.
12056
 
12057
 
12058
   For example a 68HC12 call to a function `foo_example' stored in
12059
memory expansion part could be written as follows:
12060
 
12061
     call %addr(foo_example),%page(foo_example)
12062
 
12063
   and this is equivalent to
12064
 
12065
     call foo_example
12066
 
12067
   And for 68HC11 it could be written as follows:
12068
 
12069
     ldab #%page(foo_example)
12070
     stab _page_switch
12071
     jsr  %addr(foo_example)
12072
 
12073

12074
File: as.info,  Node: M68HC11-Directives,  Next: M68HC11-Float,  Prev: M68HC11-Modifiers,  Up: M68HC11-Dependent
12075
 
12076
9.22.4 Assembler Directives
12077
---------------------------
12078
 
12079
The 68HC11 and 68HC12 version of `as' have the following specific
12080
assembler directives:
12081
 
12082
`.relax'
12083
     The relax directive is used by the `GNU Compiler' to emit a
12084
     specific relocation to mark a group of instructions for linker
12085
     relaxation.  The sequence of instructions within the group must be
12086
     known to the linker so that relaxation can be performed.
12087
 
12088
`.mode [mshort|mlong|mshort-double|mlong-double]'
12089
     This directive specifies the ABI.  It overrides the `-mshort',
12090
     `-mlong', `-mshort-double' and `-mlong-double' options.
12091
 
12092
`.far SYMBOL'
12093
     This directive marks the symbol as a `far' symbol meaning that it
12094
     uses a `call/rtc' calling convention as opposed to `jsr/rts'.
12095
     During a final link, the linker will identify references to the
12096
     `far' symbol and will verify the proper calling convention.
12097
 
12098
`.interrupt SYMBOL'
12099
     This directive marks the symbol as an interrupt entry point.  This
12100
     information is then used by the debugger to correctly unwind the
12101
     frame across interrupts.
12102
 
12103
`.xrefb SYMBOL'
12104
     This directive is defined for compatibility with the
12105
     `Specification for Motorola 8 and 16-Bit Assembly Language Input
12106
     Standard' and is ignored.
12107
 
12108
 
12109

12110
File: as.info,  Node: M68HC11-Float,  Next: M68HC11-opcodes,  Prev: M68HC11-Directives,  Up: M68HC11-Dependent
12111
 
12112
9.22.5 Floating Point
12113
---------------------
12114
 
12115
Packed decimal (P) format floating literals are not supported.  Feel
12116
free to add the code!
12117
 
12118
   The floating point formats generated by directives are these.
12119
 
12120
`.float'
12121
     `Single' precision floating point constants.
12122
 
12123
`.double'
12124
     `Double' precision floating point constants.
12125
 
12126
`.extend'
12127
`.ldouble'
12128
     `Extended' precision (`long double') floating point constants.
12129
 
12130

12131
File: as.info,  Node: M68HC11-opcodes,  Prev: M68HC11-Float,  Up: M68HC11-Dependent
12132
 
12133
9.22.6 Opcodes
12134
--------------
12135
 
12136
* Menu:
12137
 
12138
* M68HC11-Branch::                 Branch Improvement
12139
 
12140

12141
File: as.info,  Node: M68HC11-Branch,  Up: M68HC11-opcodes
12142
 
12143
9.22.6.1 Branch Improvement
12144
...........................
12145
 
12146
Certain pseudo opcodes are permitted for branch instructions.  They
12147
expand to the shortest branch instruction that reach the target.
12148
Generally these mnemonics are made by prepending `j' to the start of
12149
Motorola mnemonic. These pseudo opcodes are not affected by the
12150
`--short-branches' or `--force-long-branches' options.
12151
 
12152
   The following table summarizes the pseudo-operations.
12153
 
12154
                             Displacement Width
12155
          +-------------------------------------------------------------+
12156
          |                     Options                                 |
12157
          |    --short-branches           --force-long-branches         |
12158
          +--------------------------+----------------------------------+
12159
       Op |BYTE             WORD     | BYTE          WORD               |
12160
          +--------------------------+----------------------------------+
12161
      bsr | bsr       |               jsr           |
12162
      bra | bra       |               jmp           |
12163
     jbsr | bsr    jsr  | bsr   jsr           |
12164
     jbra | bra    jmp  | bra   jmp           |
12165
      bXX | bXX       |               bNX +3; jmp   |
12166
     jbXX | bXX    bNX +3;   | bXX   bNX +3; jmp   |
12167
          |                jmp  |                                  |
12168
          +--------------------------+----------------------------------+
12169
     XX: condition
12170
     NX: negative of condition XX
12171
 
12172
`jbsr'
12173
`jbra'
12174
     These are the simplest jump pseudo-operations; they always map to
12175
     one particular machine instruction, depending on the displacement
12176
     to the branch target.
12177
 
12178
`jbXX'
12179
     Here, `jbXX' stands for an entire family of pseudo-operations,
12180
     where XX is a conditional branch or condition-code test.  The full
12181
     list of pseudo-ops in this family is:
12182
           jbcc   jbeq   jbge   jbgt   jbhi   jbvs   jbpl  jblo
12183
           jbcs   jbne   jblt   jble   jbls   jbvc   jbmi
12184
 
12185
     For the cases of non-PC relative displacements and long
12186
     displacements, `as' issues a longer code fragment in terms of NX,
12187
     the opposite condition to XX.  For example, for the non-PC
12188
     relative case:
12189
              jbXX foo
12190
     gives
12191
               bNXs oof
12192
               jmp foo
12193
           oof:
12194
 
12195
 
12196

12197
File: as.info,  Node: MicroBlaze-Dependent,  Next: MIPS-Dependent,  Prev: M68HC11-Dependent,  Up: Machine Dependencies
12198
 
12199
9.23 MicroBlaze Dependent Features
12200
==================================
12201
 
12202
   The Xilinx MicroBlaze processor family includes several variants,
12203
all using the same core instruction set.  This chapter covers features
12204
of the GNU assembler that are specific to the MicroBlaze architecture.
12205
For details about the MicroBlaze instruction set, please see the
12206
`MicroBlaze Processor Reference Guide (UG081)' available at
12207
www.xilinx.com.
12208
 
12209
* Menu:
12210
 
12211
* MicroBlaze Directives::           Directives for MicroBlaze Processors.
12212
 
12213

12214
File: as.info,  Node: MicroBlaze Directives,  Up: MicroBlaze-Dependent
12215
 
12216
9.23.1 Directives
12217
-----------------
12218
 
12219
A number of assembler directives are available for MicroBlaze.
12220
 
12221
`.data8 EXPRESSION,...'
12222
     This directive is an alias for `.byte'. Each expression is
12223
     assembled into an eight-bit value.
12224
 
12225
`.data16 EXPRESSION,...'
12226
     This directive is an alias for `.hword'. Each expression is
12227
     assembled into an 16-bit value.
12228
 
12229
`.data32 EXPRESSION,...'
12230
     This directive is an alias for `.word'. Each expression is
12231
     assembled into an 32-bit value.
12232
 
12233
`.ent NAME[,LABEL]'
12234
     This directive is an alias for `.func' denoting the start of
12235
     function NAME at (optional) LABEL.
12236
 
12237
`.end NAME[,LABEL]'
12238
     This directive is an alias for `.endfunc' denoting the end of
12239
     function NAME.
12240
 
12241
`.gpword LABEL,...'
12242
     This directive is an alias for `.rva'.  The resolved address of
12243
     LABEL is stored in the data section.
12244
 
12245
`.weakext LABEL'
12246
     Declare that LABEL is a weak external symbol.
12247
 
12248
`.rodata'
12249
     Switch to .rodata section. Equivalent to `.section .rodata'
12250
 
12251
`.sdata2'
12252
     Switch to .sdata2 section. Equivalent to `.section .sdata2'
12253
 
12254
`.sdata'
12255
     Switch to .sdata section. Equivalent to `.section .sdata'
12256
 
12257
`.bss'
12258
     Switch to .bss section. Equivalent to `.section .bss'
12259
 
12260
`.sbss'
12261
     Switch to .sbss section. Equivalent to `.section .sbss'
12262
 
12263

12264
File: as.info,  Node: MIPS-Dependent,  Next: MMIX-Dependent,  Prev: MicroBlaze-Dependent,  Up: Machine Dependencies
12265
 
12266
9.24 MIPS Dependent Features
12267
============================
12268
 
12269
   GNU `as' for MIPS architectures supports several different MIPS
12270
processors, and MIPS ISA levels I through V, MIPS32, and MIPS64.  For
12271
information about the MIPS instruction set, see `MIPS RISC
12272
Architecture', by Kane and Heindrich (Prentice-Hall).  For an overview
12273
of MIPS assembly conventions, see "Appendix D: Assembly Language
12274
Programming" in the same work.
12275
 
12276
* Menu:
12277
 
12278
* MIPS Opts::           Assembler options
12279
* MIPS Object::         ECOFF object code
12280
* MIPS Stabs::          Directives for debugging information
12281
* MIPS ISA::            Directives to override the ISA level
12282
* MIPS symbol sizes::   Directives to override the size of symbols
12283
* MIPS autoextend::     Directives for extending MIPS 16 bit instructions
12284
* MIPS insn::           Directive to mark data as an instruction
12285
* MIPS option stack::   Directives to save and restore options
12286
* MIPS ASE instruction generation overrides:: Directives to control
12287
                        generation of MIPS ASE instructions
12288
* MIPS floating-point:: Directives to override floating-point options
12289
 
12290

12291
File: as.info,  Node: MIPS Opts,  Next: MIPS Object,  Up: MIPS-Dependent
12292
 
12293
9.24.1 Assembler options
12294
------------------------
12295
 
12296
The MIPS configurations of GNU `as' support these special options:
12297
 
12298
`-G NUM'
12299
     This option sets the largest size of an object that can be
12300
     referenced implicitly with the `gp' register.  It is only accepted
12301
     for targets that use ECOFF format.  The default value is 8.
12302
 
12303
`-EB'
12304
`-EL'
12305
     Any MIPS configuration of `as' can select big-endian or
12306
     little-endian output at run time (unlike the other GNU development
12307
     tools, which must be configured for one or the other).  Use `-EB'
12308
     to select big-endian output, and `-EL' for little-endian.
12309
 
12310
`-KPIC'
12311
     Generate SVR4-style PIC.  This option tells the assembler to
12312
     generate SVR4-style position-independent macro expansions.  It
12313
     also tells the assembler to mark the output file as PIC.
12314
 
12315
`-mvxworks-pic'
12316
     Generate VxWorks PIC.  This option tells the assembler to generate
12317
     VxWorks-style position-independent macro expansions.
12318
 
12319
`-mips1'
12320
`-mips2'
12321
`-mips3'
12322
`-mips4'
12323
`-mips5'
12324
`-mips32'
12325
`-mips32r2'
12326
`-mips64'
12327
`-mips64r2'
12328
     Generate code for a particular MIPS Instruction Set Architecture
12329
     level.  `-mips1' corresponds to the R2000 and R3000 processors,
12330
     `-mips2' to the R6000 processor, `-mips3' to the R4000 processor,
12331
     and `-mips4' to the R8000 and R10000 processors.  `-mips5',
12332
     `-mips32', `-mips32r2', `-mips64', and `-mips64r2' correspond to
12333
     generic MIPS V, MIPS32, MIPS32 RELEASE 2, MIPS64, and MIPS64
12334
     RELEASE 2 ISA processors, respectively.  You can also switch
12335
     instruction sets during the assembly; see *Note Directives to
12336
     override the ISA level: MIPS ISA.
12337
 
12338
`-mgp32'
12339
`-mfp32'
12340
     Some macros have different expansions for 32-bit and 64-bit
12341
     registers.  The register sizes are normally inferred from the ISA
12342
     and ABI, but these flags force a certain group of registers to be
12343
     treated as 32 bits wide at all times.  `-mgp32' controls the size
12344
     of general-purpose registers and `-mfp32' controls the size of
12345
     floating-point registers.
12346
 
12347
     The `.set gp=32' and `.set fp=32' directives allow the size of
12348
     registers to be changed for parts of an object. The default value
12349
     is restored by `.set gp=default' and `.set fp=default'.
12350
 
12351
     On some MIPS variants there is a 32-bit mode flag; when this flag
12352
     is set, 64-bit instructions generate a trap.  Also, some 32-bit
12353
     OSes only save the 32-bit registers on a context switch, so it is
12354
     essential never to use the 64-bit registers.
12355
 
12356
`-mgp64'
12357
`-mfp64'
12358
     Assume that 64-bit registers are available.  This is provided in
12359
     the interests of symmetry with `-mgp32' and `-mfp32'.
12360
 
12361
     The `.set gp=64' and `.set fp=64' directives allow the size of
12362
     registers to be changed for parts of an object. The default value
12363
     is restored by `.set gp=default' and `.set fp=default'.
12364
 
12365
`-mips16'
12366
`-no-mips16'
12367
     Generate code for the MIPS 16 processor.  This is equivalent to
12368
     putting `.set mips16' at the start of the assembly file.
12369
     `-no-mips16' turns off this option.
12370
 
12371
`-msmartmips'
12372
`-mno-smartmips'
12373
     Enables the SmartMIPS extensions to the MIPS32 instruction set,
12374
     which provides a number of new instructions which target smartcard
12375
     and cryptographic applications.  This is equivalent to putting
12376
     `.set smartmips' at the start of the assembly file.
12377
     `-mno-smartmips' turns off this option.
12378
 
12379
`-mips3d'
12380
`-no-mips3d'
12381
     Generate code for the MIPS-3D Application Specific Extension.
12382
     This tells the assembler to accept MIPS-3D instructions.
12383
     `-no-mips3d' turns off this option.
12384
 
12385
`-mdmx'
12386
`-no-mdmx'
12387
     Generate code for the MDMX Application Specific Extension.  This
12388
     tells the assembler to accept MDMX instructions.  `-no-mdmx' turns
12389
     off this option.
12390
 
12391
`-mdsp'
12392
`-mno-dsp'
12393
     Generate code for the DSP Release 1 Application Specific Extension.
12394
     This tells the assembler to accept DSP Release 1 instructions.
12395
     `-mno-dsp' turns off this option.
12396
 
12397
`-mdspr2'
12398
`-mno-dspr2'
12399
     Generate code for the DSP Release 2 Application Specific Extension.
12400
     This option implies -mdsp.  This tells the assembler to accept DSP
12401
     Release 2 instructions.  `-mno-dspr2' turns off this option.
12402
 
12403
`-mmt'
12404
`-mno-mt'
12405
     Generate code for the MT Application Specific Extension.  This
12406
     tells the assembler to accept MT instructions.  `-mno-mt' turns
12407
     off this option.
12408
 
12409
`-mfix7000'
12410
`-mno-fix7000'
12411
     Cause nops to be inserted if the read of the destination register
12412
     of an mfhi or mflo instruction occurs in the following two
12413
     instructions.
12414
 
12415
`-mfix-vr4120'
12416
`-no-mfix-vr4120'
12417
     Insert nops to work around certain VR4120 errata.  This option is
12418
     intended to be used on GCC-generated code: it is not designed to
12419
     catch all problems in hand-written assembler code.
12420
 
12421
`-mfix-vr4130'
12422
`-no-mfix-vr4130'
12423
     Insert nops to work around the VR4130 `mflo'/`mfhi' errata.
12424
 
12425
`-mfix-24k'
12426
`-no-mfix-24k'
12427
     Insert nops to work around the 24K `eret'/`deret' errata.
12428
 
12429
`-m4010'
12430
`-no-m4010'
12431
     Generate code for the LSI R4010 chip.  This tells the assembler to
12432
     accept the R4010 specific instructions (`addciu', `ffc', etc.),
12433
     and to not schedule `nop' instructions around accesses to the `HI'
12434
     and `LO' registers.  `-no-m4010' turns off this option.
12435
 
12436
`-m4650'
12437
`-no-m4650'
12438
     Generate code for the MIPS R4650 chip.  This tells the assembler
12439
     to accept the `mad' and `madu' instruction, and to not schedule
12440
     `nop' instructions around accesses to the `HI' and `LO' registers.
12441
     `-no-m4650' turns off this option.
12442
 
12443
`-m3900'
12444
`-no-m3900'
12445
`-m4100'
12446
`-no-m4100'
12447
     For each option `-mNNNN', generate code for the MIPS RNNNN chip.
12448
     This tells the assembler to accept instructions specific to that
12449
     chip, and to schedule for that chip's hazards.
12450
 
12451
`-march=CPU'
12452
     Generate code for a particular MIPS cpu.  It is exactly equivalent
12453
     to `-mCPU', except that there are more value of CPU understood.
12454
     Valid CPU value are:
12455
 
12456
          2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130,
12457
          vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231,
12458
          rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000,
12459
          10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem,
12460
          4kep, 4ksd, m4k, m4kp, 24kc, 24kf2_1, 24kf, 24kf1_1, 24kec,
12461
          24kef2_1, 24kef, 24kef1_1, 34kc, 34kf2_1, 34kf, 34kf1_1, 74kc,
12462
          74kf2_1, 74kf, 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf,
12463
          1004kf1_1, 5kc, 5kf, 20kc, 25kf, sb1, sb1a, loongson2e,
12464
          loongson2f, octeon, xlr
12465
 
12466
     For compatibility reasons, `Nx' and `Bfx' are accepted as synonyms
12467
     for `Nf1_1'.  These values are deprecated.
12468
 
12469
`-mtune=CPU'
12470
     Schedule and tune for a particular MIPS cpu.  Valid CPU values are
12471
     identical to `-march=CPU'.
12472
 
12473
`-mabi=ABI'
12474
     Record which ABI the source code uses.  The recognized arguments
12475
     are: `32', `n32', `o64', `64' and `eabi'.
12476
 
12477
`-msym32'
12478
`-mno-sym32'
12479
     Equivalent to adding `.set sym32' or `.set nosym32' to the
12480
     beginning of the assembler input.  *Note MIPS symbol sizes::.
12481
 
12482
`-nocpp'
12483
     This option is ignored.  It is accepted for command-line
12484
     compatibility with other assemblers, which use it to turn off C
12485
     style preprocessing.  With GNU `as', there is no need for
12486
     `-nocpp', because the GNU assembler itself never runs the C
12487
     preprocessor.
12488
 
12489
`-msoft-float'
12490
`-mhard-float'
12491
     Disable or enable floating-point instructions.  Note that by
12492
     default floating-point instructions are always allowed even with
12493
     CPU targets that don't have support for these instructions.
12494
 
12495
`-msingle-float'
12496
`-mdouble-float'
12497
     Disable or enable double-precision floating-point operations.  Note
12498
     that by default double-precision floating-point operations are
12499
     always allowed even with CPU targets that don't have support for
12500
     these operations.
12501
 
12502
`--construct-floats'
12503
`--no-construct-floats'
12504
     The `--no-construct-floats' option disables the construction of
12505
     double width floating point constants by loading the two halves of
12506
     the value into the two single width floating point registers that
12507
     make up the double width register.  This feature is useful if the
12508
     processor support the FR bit in its status  register, and this bit
12509
     is known (by the programmer) to be set.  This bit prevents the
12510
     aliasing of the double width register by the single width
12511
     registers.
12512
 
12513
     By default `--construct-floats' is selected, allowing construction
12514
     of these floating point constants.
12515
 
12516
`--trap'
12517
`--no-break'
12518
     `as' automatically macro expands certain division and
12519
     multiplication instructions to check for overflow and division by
12520
     zero.  This option causes `as' to generate code to take a trap
12521
     exception rather than a break exception when an error is detected.
12522
     The trap instructions are only supported at Instruction Set
12523
     Architecture level 2 and higher.
12524
 
12525
`--break'
12526
`--no-trap'
12527
     Generate code to take a break exception rather than a trap
12528
     exception when an error is detected.  This is the default.
12529
 
12530
`-mpdr'
12531
`-mno-pdr'
12532
     Control generation of `.pdr' sections.  Off by default on IRIX, on
12533
     elsewhere.
12534
 
12535
`-mshared'
12536
`-mno-shared'
12537
     When generating code using the Unix calling conventions (selected
12538
     by `-KPIC' or `-mcall_shared'), gas will normally generate code
12539
     which can go into a shared library.  The `-mno-shared' option
12540
     tells gas to generate code which uses the calling convention, but
12541
     can not go into a shared library.  The resulting code is slightly
12542
     more efficient.  This option only affects the handling of the
12543
     `.cpload' and `.cpsetup' pseudo-ops.
12544
 
12545

12546
File: as.info,  Node: MIPS Object,  Next: MIPS Stabs,  Prev: MIPS Opts,  Up: MIPS-Dependent
12547
 
12548
9.24.2 MIPS ECOFF object code
12549
-----------------------------
12550
 
12551
Assembling for a MIPS ECOFF target supports some additional sections
12552
besides the usual `.text', `.data' and `.bss'.  The additional sections
12553
are `.rdata', used for read-only data, `.sdata', used for small data,
12554
and `.sbss', used for small common objects.
12555
 
12556
   When assembling for ECOFF, the assembler uses the `$gp' (`$28')
12557
register to form the address of a "small object".  Any object in the
12558
`.sdata' or `.sbss' sections is considered "small" in this sense.  For
12559
external objects, or for objects in the `.bss' section, you can use the
12560
`gcc' `-G' option to control the size of objects addressed via `$gp';
12561
the default value is 8, meaning that a reference to any object eight
12562
bytes or smaller uses `$gp'.  Passing `-G 0' to `as' prevents it from
12563
using the `$gp' register on the basis of object size (but the assembler
12564
uses `$gp' for objects in `.sdata' or `sbss' in any case).  The size of
12565
an object in the `.bss' section is set by the `.comm' or `.lcomm'
12566
directive that defines it.  The size of an external object may be set
12567
with the `.extern' directive.  For example, `.extern sym,4' declares
12568
that the object at `sym' is 4 bytes in length, whie leaving `sym'
12569
otherwise undefined.
12570
 
12571
   Using small ECOFF objects requires linker support, and assumes that
12572
the `$gp' register is correctly initialized (normally done
12573
automatically by the startup code).  MIPS ECOFF assembly code must not
12574
modify the `$gp' register.
12575
 
12576

12577
File: as.info,  Node: MIPS Stabs,  Next: MIPS ISA,  Prev: MIPS Object,  Up: MIPS-Dependent
12578
 
12579
9.24.3 Directives for debugging information
12580
-------------------------------------------
12581
 
12582
MIPS ECOFF `as' supports several directives used for generating
12583
debugging information which are not support by traditional MIPS
12584
assemblers.  These are `.def', `.endef', `.dim', `.file', `.scl',
12585
`.size', `.tag', `.type', `.val', `.stabd', `.stabn', and `.stabs'.
12586
The debugging information generated by the three `.stab' directives can
12587
only be read by GDB, not by traditional MIPS debuggers (this
12588
enhancement is required to fully support C++ debugging).  These
12589
directives are primarily used by compilers, not assembly language
12590
programmers!
12591
 
12592

12593
File: as.info,  Node: MIPS symbol sizes,  Next: MIPS autoextend,  Prev: MIPS ISA,  Up: MIPS-Dependent
12594
 
12595
9.24.4 Directives to override the size of symbols
12596
-------------------------------------------------
12597
 
12598
The n64 ABI allows symbols to have any 64-bit value.  Although this
12599
provides a great deal of flexibility, it means that some macros have
12600
much longer expansions than their 32-bit counterparts.  For example,
12601
the non-PIC expansion of `dla $4,sym' is usually:
12602
 
12603
     lui     $4,%highest(sym)
12604
     lui     $1,%hi(sym)
12605
     daddiu  $4,$4,%higher(sym)
12606
     daddiu  $1,$1,%lo(sym)
12607
     dsll32  $4,$4,0
12608
     daddu   $4,$4,$1
12609
 
12610
   whereas the 32-bit expansion is simply:
12611
 
12612
     lui     $4,%hi(sym)
12613
     daddiu  $4,$4,%lo(sym)
12614
 
12615
   n64 code is sometimes constructed in such a way that all symbolic
12616
constants are known to have 32-bit values, and in such cases, it's
12617
preferable to use the 32-bit expansion instead of the 64-bit expansion.
12618
 
12619
   You can use the `.set sym32' directive to tell the assembler that,
12620
from this point on, all expressions of the form `SYMBOL' or `SYMBOL +
12621
OFFSET' have 32-bit values.  For example:
12622
 
12623
     .set sym32
12624
     dla     $4,sym
12625
     lw      $4,sym+16
12626
     sw      $4,sym+0x8000($4)
12627
 
12628
   will cause the assembler to treat `sym', `sym+16' and `sym+0x8000'
12629
as 32-bit values.  The handling of non-symbolic addresses is not
12630
affected.
12631
 
12632
   The directive `.set nosym32' ends a `.set sym32' block and reverts
12633
to the normal behavior.  It is also possible to change the symbol size
12634
using the command-line options `-msym32' and `-mno-sym32'.
12635
 
12636
   These options and directives are always accepted, but at present,
12637
they have no effect for anything other than n64.
12638
 
12639

12640
File: as.info,  Node: MIPS ISA,  Next: MIPS symbol sizes,  Prev: MIPS Stabs,  Up: MIPS-Dependent
12641
 
12642
9.24.5 Directives to override the ISA level
12643
-------------------------------------------
12644
 
12645
GNU `as' supports an additional directive to change the MIPS
12646
Instruction Set Architecture level on the fly: `.set mipsN'.  N should
12647
be a number from 0 to 5, or 32, 32r2, 64 or 64r2.  The values other
12648
than 0 make the assembler accept instructions for the corresponding ISA
12649
level, from that point on in the assembly.  `.set mipsN' affects not
12650
only which instructions are permitted, but also how certain macros are
12651
expanded.  `.set mips0' restores the ISA level to its original level:
12652
either the level you selected with command line options, or the default
12653
for your configuration.  You can use this feature to permit specific
12654
MIPS3 instructions while assembling in 32 bit mode.  Use this directive
12655
with care!
12656
 
12657
   The `.set arch=CPU' directive provides even finer control.  It
12658
changes the effective CPU target and allows the assembler to use
12659
instructions specific to a particular CPU.  All CPUs supported by the
12660
`-march' command line option are also selectable by this directive.
12661
The original value is restored by `.set arch=default'.
12662
 
12663
   The directive `.set mips16' puts the assembler into MIPS 16 mode, in
12664
which it will assemble instructions for the MIPS 16 processor.  Use
12665
`.set nomips16' to return to normal 32 bit mode.
12666
 
12667
   Traditional MIPS assemblers do not support this directive.
12668
 
12669

12670
File: as.info,  Node: MIPS autoextend,  Next: MIPS insn,  Prev: MIPS symbol sizes,  Up: MIPS-Dependent
12671
 
12672
9.24.6 Directives for extending MIPS 16 bit instructions
12673
--------------------------------------------------------
12674
 
12675
By default, MIPS 16 instructions are automatically extended to 32 bits
12676
when necessary.  The directive `.set noautoextend' will turn this off.
12677
When `.set noautoextend' is in effect, any 32 bit instruction must be
12678
explicitly extended with the `.e' modifier (e.g., `li.e $4,1000').  The
12679
directive `.set autoextend' may be used to once again automatically
12680
extend instructions when necessary.
12681
 
12682
   This directive is only meaningful when in MIPS 16 mode.  Traditional
12683
MIPS assemblers do not support this directive.
12684
 
12685

12686
File: as.info,  Node: MIPS insn,  Next: MIPS option stack,  Prev: MIPS autoextend,  Up: MIPS-Dependent
12687
 
12688
9.24.7 Directive to mark data as an instruction
12689
-----------------------------------------------
12690
 
12691
The `.insn' directive tells `as' that the following data is actually
12692
instructions.  This makes a difference in MIPS 16 mode: when loading
12693
the address of a label which precedes instructions, `as' automatically
12694
adds 1 to the value, so that jumping to the loaded address will do the
12695
right thing.
12696
 
12697
   The `.global' and `.globl' directives supported by `as' will by
12698
default mark the symbol as pointing to a region of data not code.  This
12699
means that, for example, any instructions following such a symbol will
12700
not be disassembled by `objdump' as it will regard them as data.  To
12701
change this behaviour an optional section name can be placed after the
12702
symbol name in the `.global' directive.  If this section exists and is
12703
known to be a code section, then the symbol will be marked as poiting at
12704
code not data.  Ie the syntax for the directive is:
12705
 
12706
   `.global SYMBOL[ SECTION][, SYMBOL[ SECTION]] ...',
12707
 
12708
   Here is a short example:
12709
 
12710
             .global foo .text, bar, baz .data
12711
     foo:
12712
             nop
12713
     bar:
12714
             .word 0x0
12715
     baz:
12716
             .word 0x1
12717
 
12718

12719
File: as.info,  Node: MIPS option stack,  Next: MIPS ASE instruction generation overrides,  Prev: MIPS insn,  Up: MIPS-Dependent
12720
 
12721
9.24.8 Directives to save and restore options
12722
---------------------------------------------
12723
 
12724
The directives `.set push' and `.set pop' may be used to save and
12725
restore the current settings for all the options which are controlled
12726
by `.set'.  The `.set push' directive saves the current settings on a
12727
stack.  The `.set pop' directive pops the stack and restores the
12728
settings.
12729
 
12730
   These directives can be useful inside an macro which must change an
12731
option such as the ISA level or instruction reordering but does not want
12732
to change the state of the code which invoked the macro.
12733
 
12734
   Traditional MIPS assemblers do not support these directives.
12735
 
12736

12737
File: as.info,  Node: MIPS ASE instruction generation overrides,  Next: MIPS floating-point,  Prev: MIPS option stack,  Up: MIPS-Dependent
12738
 
12739
9.24.9 Directives to control generation of MIPS ASE instructions
12740
----------------------------------------------------------------
12741
 
12742
The directive `.set mips3d' makes the assembler accept instructions
12743
from the MIPS-3D Application Specific Extension from that point on in
12744
the assembly.  The `.set nomips3d' directive prevents MIPS-3D
12745
instructions from being accepted.
12746
 
12747
   The directive `.set smartmips' makes the assembler accept
12748
instructions from the SmartMIPS Application Specific Extension to the
12749
MIPS32 ISA from that point on in the assembly.  The `.set nosmartmips'
12750
directive prevents SmartMIPS instructions from being accepted.
12751
 
12752
   The directive `.set mdmx' makes the assembler accept instructions
12753
from the MDMX Application Specific Extension from that point on in the
12754
assembly.  The `.set nomdmx' directive prevents MDMX instructions from
12755
being accepted.
12756
 
12757
   The directive `.set dsp' makes the assembler accept instructions
12758
from the DSP Release 1 Application Specific Extension from that point
12759
on in the assembly.  The `.set nodsp' directive prevents DSP Release 1
12760
instructions from being accepted.
12761
 
12762
   The directive `.set dspr2' makes the assembler accept instructions
12763
from the DSP Release 2 Application Specific Extension from that point
12764
on in the assembly.  This dirctive implies `.set dsp'.  The `.set
12765
nodspr2' directive prevents DSP Release 2 instructions from being
12766
accepted.
12767
 
12768
   The directive `.set mt' makes the assembler accept instructions from
12769
the MT Application Specific Extension from that point on in the
12770
assembly.  The `.set nomt' directive prevents MT instructions from
12771
being accepted.
12772
 
12773
   Traditional MIPS assemblers do not support these directives.
12774
 
12775

12776
File: as.info,  Node: MIPS floating-point,  Prev: MIPS ASE instruction generation overrides,  Up: MIPS-Dependent
12777
 
12778
9.24.10 Directives to override floating-point options
12779
-----------------------------------------------------
12780
 
12781
The directives `.set softfloat' and `.set hardfloat' provide finer
12782
control of disabling and enabling float-point instructions.  These
12783
directives always override the default (that hard-float instructions
12784
are accepted) or the command-line options (`-msoft-float' and
12785
`-mhard-float').
12786
 
12787
   The directives `.set singlefloat' and `.set doublefloat' provide
12788
finer control of disabling and enabling double-precision float-point
12789
operations.  These directives always override the default (that
12790
double-precision operations are accepted) or the command-line options
12791
(`-msingle-float' and `-mdouble-float').
12792
 
12793
   Traditional MIPS assemblers do not support these directives.
12794
 
12795

12796
File: as.info,  Node: MMIX-Dependent,  Next: MSP430-Dependent,  Prev: MIPS-Dependent,  Up: Machine Dependencies
12797
 
12798
9.25 MMIX Dependent Features
12799
============================
12800
 
12801
* Menu:
12802
 
12803
* MMIX-Opts::              Command-line Options
12804
* MMIX-Expand::            Instruction expansion
12805
* MMIX-Syntax::            Syntax
12806
* MMIX-mmixal::            Differences to `mmixal' syntax and semantics
12807
 
12808

12809
File: as.info,  Node: MMIX-Opts,  Next: MMIX-Expand,  Up: MMIX-Dependent
12810
 
12811
9.25.1 Command-line Options
12812
---------------------------
12813
 
12814
The MMIX version of `as' has some machine-dependent options.
12815
 
12816
   When `--fixed-special-register-names' is specified, only the register
12817
names specified in *Note MMIX-Regs:: are recognized in the instructions
12818
`PUT' and `GET'.
12819
 
12820
   You can use the `--globalize-symbols' to make all symbols global.
12821
This option is useful when splitting up a `mmixal' program into several
12822
files.
12823
 
12824
   The `--gnu-syntax' turns off most syntax compatibility with
12825
`mmixal'.  Its usability is currently doubtful.
12826
 
12827
   The `--relax' option is not fully supported, but will eventually make
12828
the object file prepared for linker relaxation.
12829
 
12830
   If you want to avoid inadvertently calling a predefined symbol and
12831
would rather get an error, for example when using `as' with a compiler
12832
or other machine-generated code, specify `--no-predefined-syms'.  This
12833
turns off built-in predefined definitions of all such symbols,
12834
including rounding-mode symbols, segment symbols, `BIT' symbols, and
12835
`TRAP' symbols used in `mmix' "system calls".  It also turns off
12836
predefined special-register names, except when used in `PUT' and `GET'
12837
instructions.
12838
 
12839
   By default, some instructions are expanded to fit the size of the
12840
operand or an external symbol (*note MMIX-Expand::).  By passing
12841
`--no-expand', no such expansion will be done, instead causing errors
12842
at link time if the operand does not fit.
12843
 
12844
   The `mmixal' documentation (*note mmixsite::) specifies that global
12845
registers allocated with the `GREG' directive (*note MMIX-greg::) and
12846
initialized to the same non-zero value, will refer to the same global
12847
register.  This isn't strictly enforceable in `as' since the final
12848
addresses aren't known until link-time, but it will do an effort unless
12849
the `--no-merge-gregs' option is specified.  (Register merging isn't
12850
yet implemented in `ld'.)
12851
 
12852
   `as' will warn every time it expands an instruction to fit an
12853
operand unless the option `-x' is specified.  It is believed that this
12854
behaviour is more useful than just mimicking `mmixal''s behaviour, in
12855
which instructions are only expanded if the `-x' option is specified,
12856
and assembly fails otherwise, when an instruction needs to be expanded.
12857
It needs to be kept in mind that `mmixal' is both an assembler and
12858
linker, while `as' will expand instructions that at link stage can be
12859
contracted.  (Though linker relaxation isn't yet implemented in `ld'.)
12860
The option `-x' also imples `--linker-allocated-gregs'.
12861
 
12862
   If instruction expansion is enabled, `as' can expand a `PUSHJ'
12863
instruction into a series of instructions.  The shortest expansion is
12864
to not expand it, but just mark the call as redirectable to a stub,
12865
which `ld' creates at link-time, but only if the original `PUSHJ'
12866
instruction is found not to reach the target.  The stub consists of the
12867
necessary instructions to form a jump to the target.  This happens if
12868
`as' can assert that the `PUSHJ' instruction can reach such a stub.
12869
The option `--no-pushj-stubs' disables this shorter expansion, and the
12870
longer series of instructions is then created at assembly-time.  The
12871
option `--no-stubs' is a synonym, intended for compatibility with
12872
future releases, where generation of stubs for other instructions may
12873
be implemented.
12874
 
12875
   Usually a two-operand-expression (*note GREG-base::) without a
12876
matching `GREG' directive is treated as an error by `as'.  When the
12877
option `--linker-allocated-gregs' is in effect, they are instead passed
12878
through to the linker, which will allocate as many global registers as
12879
is needed.
12880
 
12881

12882
File: as.info,  Node: MMIX-Expand,  Next: MMIX-Syntax,  Prev: MMIX-Opts,  Up: MMIX-Dependent
12883
 
12884
9.25.2 Instruction expansion
12885
----------------------------
12886
 
12887
When `as' encounters an instruction with an operand that is either not
12888
known or does not fit the operand size of the instruction, `as' (and
12889
`ld') will expand the instruction into a sequence of instructions
12890
semantically equivalent to the operand fitting the instruction.
12891
Expansion will take place for the following instructions:
12892
 
12893
`GETA'
12894
     Expands to a sequence of four instructions: `SETL', `INCML',
12895
     `INCMH' and `INCH'.  The operand must be a multiple of four.
12896
 
12897
Conditional branches
12898
     A branch instruction is turned into a branch with the complemented
12899
     condition and prediction bit over five instructions; four
12900
     instructions setting `$255' to the operand value, which like with
12901
     `GETA' must be a multiple of four, and a final `GO $255,$255,0'.
12902
 
12903
`PUSHJ'
12904
     Similar to expansion for conditional branches; four instructions
12905
     set `$255' to the operand value, followed by a `PUSHGO
12906
     $255,$255,0'.
12907
 
12908
`JMP'
12909
     Similar to conditional branches and `PUSHJ'.  The final instruction
12910
     is `GO $255,$255,0'.
12911
 
12912
   The linker `ld' is expected to shrink these expansions for code
12913
assembled with `--relax' (though not currently implemented).
12914
 
12915

12916
File: as.info,  Node: MMIX-Syntax,  Next: MMIX-mmixal,  Prev: MMIX-Expand,  Up: MMIX-Dependent
12917
 
12918
9.25.3 Syntax
12919
-------------
12920
 
12921
The assembly syntax is supposed to be upward compatible with that
12922
described in Sections 1.3 and 1.4 of `The Art of Computer Programming,
12923
Volume 1'.  Draft versions of those chapters as well as other MMIX
12924
information is located at
12925
`http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html'.  Most code
12926
examples from the mmixal package located there should work unmodified
12927
when assembled and linked as single files, with a few noteworthy
12928
exceptions (*note MMIX-mmixal::).
12929
 
12930
   Before an instruction is emitted, the current location is aligned to
12931
the next four-byte boundary.  If a label is defined at the beginning of
12932
the line, its value will be the aligned value.
12933
 
12934
   In addition to the traditional hex-prefix `0x', a hexadecimal number
12935
can also be specified by the prefix character `#'.
12936
 
12937
   After all operands to an MMIX instruction or directive have been
12938
specified, the rest of the line is ignored, treated as a comment.
12939
 
12940
* Menu:
12941
 
12942
* MMIX-Chars::                  Special Characters
12943
* MMIX-Symbols::                Symbols
12944
* MMIX-Regs::                   Register Names
12945
* MMIX-Pseudos::                Assembler Directives
12946
 
12947

12948
File: as.info,  Node: MMIX-Chars,  Next: MMIX-Symbols,  Up: MMIX-Syntax
12949
 
12950
9.25.3.1 Special Characters
12951
...........................
12952
 
12953
The characters `*' and `#' are line comment characters; each start a
12954
comment at the beginning of a line, but only at the beginning of a
12955
line.  A `#' prefixes a hexadecimal number if found elsewhere on a line.
12956
 
12957
   Two other characters, `%' and `!', each start a comment anywhere on
12958
the line.  Thus you can't use the `modulus' and `not' operators in
12959
expressions normally associated with these two characters.
12960
 
12961
   A `;' is a line separator, treated as a new-line, so separate
12962
instructions can be specified on a single line.
12963
 
12964

12965
File: as.info,  Node: MMIX-Symbols,  Next: MMIX-Regs,  Prev: MMIX-Chars,  Up: MMIX-Syntax
12966
 
12967
9.25.3.2 Symbols
12968
................
12969
 
12970
The character `:' is permitted in identifiers.  There are two
12971
exceptions to it being treated as any other symbol character: if a
12972
symbol begins with `:', it means that the symbol is in the global
12973
namespace and that the current prefix should not be prepended to that
12974
symbol (*note MMIX-prefix::).  The `:' is then not considered part of
12975
the symbol.  For a symbol in the label position (first on a line), a `:'
12976
at the end of a symbol is silently stripped off.  A label is permitted,
12977
but not required, to be followed by a `:', as with many other assembly
12978
formats.
12979
 
12980
   The character `@' in an expression, is a synonym for `.', the
12981
current location.
12982
 
12983
   In addition to the common forward and backward local symbol formats
12984
(*note Symbol Names::), they can be specified with upper-case `B' and
12985
`F', as in `8B' and `9F'.  A local label defined for the current
12986
position is written with a `H' appended to the number:
12987
     3H LDB $0,$1,2
12988
   This and traditional local-label formats cannot be mixed: a label
12989
must be defined and referred to using the same format.
12990
 
12991
   There's a minor caveat: just as for the ordinary local symbols, the
12992
local symbols are translated into ordinary symbols using control
12993
characters are to hide the ordinal number of the symbol.
12994
Unfortunately, these symbols are not translated back in error messages.
12995
Thus you may see confusing error messages when local symbols are used.
12996
Control characters `\003' (control-C) and `\004' (control-D) are used
12997
for the MMIX-specific local-symbol syntax.
12998
 
12999
   The symbol `Main' is handled specially; it is always global.
13000
 
13001
   By defining the symbols `__.MMIX.start..text' and
13002
`__.MMIX.start..data', the address of respectively the `.text' and
13003
`.data' segments of the final program can be defined, though when
13004
linking more than one object file, the code or data in the object file
13005
containing the symbol is not guaranteed to be start at that position;
13006
just the final executable.  *Note MMIX-loc::.
13007
 
13008

13009
File: as.info,  Node: MMIX-Regs,  Next: MMIX-Pseudos,  Prev: MMIX-Symbols,  Up: MMIX-Syntax
13010
 
13011
9.25.3.3 Register names
13012
.......................
13013
 
13014
Local and global registers are specified as `$0' to `$255'.  The
13015
recognized special register names are `rJ', `rA', `rB', `rC', `rD',
13016
`rE', `rF', `rG', `rH', `rI', `rK', `rL', `rM', `rN', `rO', `rP', `rQ',
13017
`rR', `rS', `rT', `rU', `rV', `rW', `rX', `rY', `rZ', `rBB', `rTT',
13018
`rWW', `rXX', `rYY' and `rZZ'.  A leading `:' is optional for special
13019
register names.
13020
 
13021
   Local and global symbols can be equated to register names and used in
13022
place of ordinary registers.
13023
 
13024
   Similarly for special registers, local and global symbols can be
13025
used.  Also, symbols equated from numbers and constant expressions are
13026
allowed in place of a special register, except when either of the
13027
options `--no-predefined-syms' and `--fixed-special-register-names' are
13028
specified.  Then only the special register names above are allowed for
13029
the instructions having a special register operand; `GET' and `PUT'.
13030
 
13031

13032
File: as.info,  Node: MMIX-Pseudos,  Prev: MMIX-Regs,  Up: MMIX-Syntax
13033
 
13034
9.25.3.4 Assembler Directives
13035
.............................
13036
 
13037
`LOC'
13038
     The `LOC' directive sets the current location to the value of the
13039
     operand field, which may include changing sections.  If the
13040
     operand is a constant, the section is set to either `.data' if the
13041
     value is `0x2000000000000000' or larger, else it is set to `.text'.
13042
     Within a section, the current location may only be changed to
13043
     monotonically higher addresses.  A LOC expression must be a
13044
     previously defined symbol or a "pure" constant.
13045
 
13046
     An example, which sets the label PREV to the current location, and
13047
     updates the current location to eight bytes forward:
13048
          prev LOC @+8
13049
 
13050
     When a LOC has a constant as its operand, a symbol
13051
     `__.MMIX.start..text' or `__.MMIX.start..data' is defined
13052
     depending on the address as mentioned above.  Each such symbol is
13053
     interpreted as special by the linker, locating the section at that
13054
     address.  Note that if multiple files are linked, the first object
13055
     file with that section will be mapped to that address (not
13056
     necessarily the file with the LOC definition).
13057
 
13058
`LOCAL'
13059
     Example:
13060
           LOCAL external_symbol
13061
           LOCAL 42
13062
           .local asymbol
13063
 
13064
     This directive-operation generates a link-time assertion that the
13065
     operand does not correspond to a global register.  The operand is
13066
     an expression that at link-time resolves to a register symbol or a
13067
     number.  A number is treated as the register having that number.
13068
     There is one restriction on the use of this directive: the
13069
     pseudo-directive must be placed in a section with contents, code
13070
     or data.
13071
 
13072
`IS'
13073
     The `IS' directive:
13074
          asymbol IS an_expression
13075
     sets the symbol `asymbol' to `an_expression'.  A symbol may not be
13076
     set more than once using this directive.  Local labels may be set
13077
     using this directive, for example:
13078
          5H IS @+4
13079
 
13080
`GREG'
13081
     This directive reserves a global register, gives it an initial
13082
     value and optionally gives it a symbolic name.  Some examples:
13083
 
13084
          areg GREG
13085
          breg GREG data_value
13086
               GREG data_buffer
13087
               .greg creg, another_data_value
13088
 
13089
     The symbolic register name can be used in place of a (non-special)
13090
     register.  If a value isn't provided, it defaults to zero.  Unless
13091
     the option `--no-merge-gregs' is specified, non-zero registers
13092
     allocated with this directive may be eliminated by `as'; another
13093
     register with the same value used in its place.  Any of the
13094
     instructions `CSWAP', `GO', `LDA', `LDBU', `LDB', `LDHT', `LDOU',
13095
     `LDO', `LDSF', `LDTU', `LDT', `LDUNC', `LDVTS', `LDWU', `LDW',
13096
     `PREGO', `PRELD', `PREST', `PUSHGO', `STBU', `STB', `STCO', `STHT',
13097
     `STOU', `STSF', `STTU', `STT', `STUNC', `SYNCD', `SYNCID', can
13098
     have a value nearby an initial value in place of its second and
13099
     third operands.  Here, "nearby" is defined as within the range
13100
     0...255 from the initial value of such an allocated register.
13101
 
13102
          buffer1 BYTE 0,0,0,0,0
13103
          buffer2 BYTE 0,0,0,0,0
13104
           ...
13105
           GREG buffer1
13106
           LDOU $42,buffer2
13107
     In the example above, the `Y' field of the `LDOUI' instruction
13108
     (LDOU with a constant Z) will be replaced with the global register
13109
     allocated for `buffer1', and the `Z' field will have the value 5,
13110
     the offset from `buffer1' to `buffer2'.  The result is equivalent
13111
     to this code:
13112
          buffer1 BYTE 0,0,0,0,0
13113
          buffer2 BYTE 0,0,0,0,0
13114
           ...
13115
          tmpreg GREG buffer1
13116
           LDOU $42,tmpreg,(buffer2-buffer1)
13117
 
13118
     Global registers allocated with this directive are allocated in
13119
     order higher-to-lower within a file.  Other than that, the exact
13120
     order of register allocation and elimination is undefined.  For
13121
     example, the order is undefined when more than one file with such
13122
     directives are linked together.  With the options `-x' and
13123
     `--linker-allocated-gregs', `GREG' directives for two-operand
13124
     cases like the one mentioned above can be omitted.  Sufficient
13125
     global registers will then be allocated by the linker.
13126
 
13127
`BYTE'
13128
     The `BYTE' directive takes a series of operands separated by a
13129
     comma.  If an operand is a string (*note Strings::), each
13130
     character of that string is emitted as a byte.  Other operands
13131
     must be constant expressions without forward references, in the
13132
     range 0...255.  If you need operands having expressions with
13133
     forward references, use `.byte' (*note Byte::).  An operand can be
13134
     omitted, defaulting to a zero value.
13135
 
13136
`WYDE'
13137
`TETRA'
13138
`OCTA'
13139
     The directives `WYDE', `TETRA' and `OCTA' emit constants of two,
13140
     four and eight bytes size respectively.  Before anything else
13141
     happens for the directive, the current location is aligned to the
13142
     respective constant-size boundary.  If a label is defined at the
13143
     beginning of the line, its value will be that after the alignment.
13144
     A single operand can be omitted, defaulting to a zero value
13145
     emitted for the directive.  Operands can be expressed as strings
13146
     (*note Strings::), in which case each character in the string is
13147
     emitted as a separate constant of the size indicated by the
13148
     directive.
13149
 
13150
`PREFIX'
13151
     The `PREFIX' directive sets a symbol name prefix to be prepended to
13152
     all symbols (except local symbols, *note MMIX-Symbols::), that are
13153
     not prefixed with `:', until the next `PREFIX' directive.  Such
13154
     prefixes accumulate.  For example,
13155
           PREFIX a
13156
           PREFIX b
13157
          c IS 0
13158
     defines a symbol `abc' with the value 0.
13159
 
13160
`BSPEC'
13161
`ESPEC'
13162
     A pair of `BSPEC' and `ESPEC' directives delimit a section of
13163
     special contents (without specified semantics).  Example:
13164
           BSPEC 42
13165
           TETRA 1,2,3
13166
           ESPEC
13167
     The single operand to `BSPEC' must be number in the range 0...255.
13168
     The `BSPEC' number 80 is used by the GNU binutils implementation.
13169
 
13170

13171
File: as.info,  Node: MMIX-mmixal,  Prev: MMIX-Syntax,  Up: MMIX-Dependent
13172
 
13173
9.25.4 Differences to `mmixal'
13174
------------------------------
13175
 
13176
The binutils `as' and `ld' combination has a few differences in
13177
function compared to `mmixal' (*note mmixsite::).
13178
 
13179
   The replacement of a symbol with a GREG-allocated register (*note
13180
GREG-base::) is not handled the exactly same way in `as' as in
13181
`mmixal'.  This is apparent in the `mmixal' example file `inout.mms',
13182
where different registers with different offsets, eventually yielding
13183
the same address, are used in the first instruction.  This type of
13184
difference should however not affect the function of any program unless
13185
it has specific assumptions about the allocated register number.
13186
 
13187
   Line numbers (in the `mmo' object format) are currently not
13188
supported.
13189
 
13190
   Expression operator precedence is not that of mmixal: operator
13191
precedence is that of the C programming language.  It's recommended to
13192
use parentheses to explicitly specify wanted operator precedence
13193
whenever more than one type of operators are used.
13194
 
13195
   The serialize unary operator `&', the fractional division operator
13196
`//', the logical not operator `!' and the modulus operator `%' are not
13197
available.
13198
 
13199
   Symbols are not global by default, unless the option
13200
`--globalize-symbols' is passed.  Use the `.global' directive to
13201
globalize symbols (*note Global::).
13202
 
13203
   Operand syntax is a bit stricter with `as' than `mmixal'.  For
13204
example, you can't say `addu 1,2,3', instead you must write `addu
13205
$1,$2,3'.
13206
 
13207
   You can't LOC to a lower address than those already visited (i.e.,
13208
"backwards").
13209
 
13210
   A LOC directive must come before any emitted code.
13211
 
13212
   Predefined symbols are visible as file-local symbols after use.  (In
13213
the ELF file, that is--the linked mmo file has no notion of a file-local
13214
symbol.)
13215
 
13216
   Some mapping of constant expressions to sections in LOC expressions
13217
is attempted, but that functionality is easily confused and should be
13218
avoided unless compatibility with `mmixal' is required.  A LOC
13219
expression to `0x2000000000000000' or higher, maps to the `.data'
13220
section and lower addresses map to the `.text' section (*note
13221
MMIX-loc::).
13222
 
13223
   The code and data areas are each contiguous.  Sparse programs with
13224
far-away LOC directives will take up the same amount of space as a
13225
contiguous program with zeros filled in the gaps between the LOC
13226
directives.  If you need sparse programs, you might try and get the
13227
wanted effect with a linker script and splitting up the code parts into
13228
sections (*note Section::).  Assembly code for this, to be compatible
13229
with `mmixal', would look something like:
13230
      .if 0
13231
      LOC away_expression
13232
      .else
13233
      .section away,"ax"
13234
      .fi
13235
   `as' will not execute the LOC directive and `mmixal' ignores the
13236
lines with `.'.  This construct can be used generally to help
13237
compatibility.
13238
 
13239
   Symbols can't be defined twice-not even to the same value.
13240
 
13241
   Instruction mnemonics are recognized case-insensitive, though the
13242
`IS' and `GREG' pseudo-operations must be specified in upper-case
13243
characters.
13244
 
13245
   There's no unicode support.
13246
 
13247
   The following is a list of programs in `mmix.tar.gz', available at
13248
`http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html', last
13249
checked with the version dated 2001-08-25 (md5sum
13250
c393470cfc86fac040487d22d2bf0172) that assemble with `mmixal' but do
13251
not assemble with `as':
13252
 
13253
`silly.mms'
13254
     LOC to a previous address.
13255
 
13256
`sim.mms'
13257
     Redefines symbol `Done'.
13258
 
13259
`test.mms'
13260
     Uses the serial operator `&'.
13261
 
13262

13263
File: as.info,  Node: MSP430-Dependent,  Next: SH-Dependent,  Prev: MMIX-Dependent,  Up: Machine Dependencies
13264
 
13265
9.26 MSP 430 Dependent Features
13266
===============================
13267
 
13268
* Menu:
13269
 
13270
* MSP430 Options::              Options
13271
* MSP430 Syntax::               Syntax
13272
* MSP430 Floating Point::       Floating Point
13273
* MSP430 Directives::           MSP 430 Machine Directives
13274
* MSP430 Opcodes::              Opcodes
13275
* MSP430 Profiling Capability:: Profiling Capability
13276
 
13277

13278
File: as.info,  Node: MSP430 Options,  Next: MSP430 Syntax,  Up: MSP430-Dependent
13279
 
13280
9.26.1 Options
13281
--------------
13282
 
13283
`-m'
13284
     select the mpu arch. Currently has no effect.
13285
 
13286
`-mP'
13287
     enables polymorph instructions handler.
13288
 
13289
`-mQ'
13290
     enables relaxation at assembly time. DANGEROUS!
13291
 
13292
 
13293

13294
File: as.info,  Node: MSP430 Syntax,  Next: MSP430 Floating Point,  Prev: MSP430 Options,  Up: MSP430-Dependent
13295
 
13296
9.26.2 Syntax
13297
-------------
13298
 
13299
* Menu:
13300
 
13301
* MSP430-Macros::               Macros
13302
* MSP430-Chars::                Special Characters
13303
* MSP430-Regs::                 Register Names
13304
* MSP430-Ext::                  Assembler Extensions
13305
 
13306

13307
File: as.info,  Node: MSP430-Macros,  Next: MSP430-Chars,  Up: MSP430 Syntax
13308
 
13309
9.26.2.1 Macros
13310
...............
13311
 
13312
The macro syntax used on the MSP 430 is like that described in the MSP
13313
430 Family Assembler Specification.  Normal `as' macros should still
13314
work.
13315
 
13316
   Additional built-in macros are:
13317
 
13318
`llo(exp)'
13319
     Extracts least significant word from 32-bit expression 'exp'.
13320
 
13321
`lhi(exp)'
13322
     Extracts most significant word from 32-bit expression 'exp'.
13323
 
13324
`hlo(exp)'
13325
     Extracts 3rd word from 64-bit expression 'exp'.
13326
 
13327
`hhi(exp)'
13328
     Extracts 4rd word from 64-bit expression 'exp'.
13329
 
13330
 
13331
   They normally being used as an immediate source operand.
13332
         mov    #llo(1), r10    ;       == mov  #1, r10
13333
         mov    #lhi(1), r10    ;       == mov  #0, r10
13334
 
13335

13336
File: as.info,  Node: MSP430-Chars,  Next: MSP430-Regs,  Prev: MSP430-Macros,  Up: MSP430 Syntax
13337
 
13338
9.26.2.2 Special Characters
13339
...........................
13340
 
13341
`;' is the line comment character.
13342
 
13343
   The character `$' in jump instructions indicates current location and
13344
implemented only for TI syntax compatibility.
13345
 
13346

13347
File: as.info,  Node: MSP430-Regs,  Next: MSP430-Ext,  Prev: MSP430-Chars,  Up: MSP430 Syntax
13348
 
13349
9.26.2.3 Register Names
13350
.......................
13351
 
13352
General-purpose registers are represented by predefined symbols of the
13353
form `rN' (for global registers), where N represents a number between
13354
`0' and `15'.  The leading letters may be in either upper or lower
13355
case; for example, `r13' and `R7' are both valid register names.
13356
 
13357
   Register names `PC', `SP' and `SR' cannot be used as register names
13358
and will be treated as variables. Use `r0', `r1', and `r2' instead.
13359
 
13360

13361
File: as.info,  Node: MSP430-Ext,  Prev: MSP430-Regs,  Up: MSP430 Syntax
13362
 
13363
9.26.2.4 Assembler Extensions
13364
.............................
13365
 
13366
`@rN'
13367
     As destination operand being treated as `0(rn)'
13368
 
13369
`0(rN)'
13370
     As source operand being treated as `@rn'
13371
 
13372
`jCOND +N'
13373
     Skips next N bytes followed by jump instruction and equivalent to
13374
     `jCOND $+N+2'
13375
 
13376
 
13377
   Also, there are some instructions, which cannot be found in other
13378
assemblers.  These are branch instructions, which has different opcodes
13379
upon jump distance.  They all got PC relative addressing mode.
13380
 
13381
`beq label'
13382
     A polymorph instruction which is `jeq label' in case if jump
13383
     distance within allowed range for cpu's jump instruction. If not,
13384
     this unrolls into a sequence of
13385
            jne $+6
13386
            br  label
13387
 
13388
`bne label'
13389
     A polymorph instruction which is `jne label' or `jeq +4; br label'
13390
 
13391
`blt label'
13392
     A polymorph instruction which is `jl label' or `jge +4; br label'
13393
 
13394
`bltn label'
13395
     A polymorph instruction which is `jn label' or `jn +2; jmp +4; br
13396
     label'
13397
 
13398
`bltu label'
13399
     A polymorph instruction which is `jlo label' or `jhs +2; br label'
13400
 
13401
`bge label'
13402
     A polymorph instruction which is `jge label' or `jl +4; br label'
13403
 
13404
`bgeu label'
13405
     A polymorph instruction which is `jhs label' or `jlo +4; br label'
13406
 
13407
`bgt label'
13408
     A polymorph instruction which is `jeq +2; jge label' or `jeq +6;
13409
     jl  +4; br label'
13410
 
13411
`bgtu label'
13412
     A polymorph instruction which is `jeq +2; jhs label' or `jeq +6;
13413
     jlo +4; br label'
13414
 
13415
`bleu label'
13416
     A polymorph instruction which is `jeq label; jlo label' or `jeq
13417
     +2; jhs +4; br label'
13418
 
13419
`ble label'
13420
     A polymorph instruction which is `jeq label; jl  label' or `jeq
13421
     +2; jge +4; br label'
13422
 
13423
`jump label'
13424
     A polymorph instruction which is `jmp label' or `br label'
13425
 
13426

13427
File: as.info,  Node: MSP430 Floating Point,  Next: MSP430 Directives,  Prev: MSP430 Syntax,  Up: MSP430-Dependent
13428
 
13429
9.26.3 Floating Point
13430
---------------------
13431
 
13432
The MSP 430 family uses IEEE 32-bit floating-point numbers.
13433
 
13434

13435
File: as.info,  Node: MSP430 Directives,  Next: MSP430 Opcodes,  Prev: MSP430 Floating Point,  Up: MSP430-Dependent
13436
 
13437
9.26.4 MSP 430 Machine Directives
13438
---------------------------------
13439
 
13440
`.file'
13441
     This directive is ignored; it is accepted for compatibility with
13442
     other MSP 430 assemblers.
13443
 
13444
          _Warning:_ in other versions of the GNU assembler, `.file' is
13445
          used for the directive called `.app-file' in the MSP 430
13446
          support.
13447
 
13448
`.line'
13449
     This directive is ignored; it is accepted for compatibility with
13450
     other MSP 430 assemblers.
13451
 
13452
`.arch'
13453
     Currently this directive is ignored; it is accepted for
13454
     compatibility with other MSP 430 assemblers.
13455
 
13456
`.profiler'
13457
     This directive instructs assembler to add new profile entry to the
13458
     object file.
13459
 
13460
 
13461

13462
File: as.info,  Node: MSP430 Opcodes,  Next: MSP430 Profiling Capability,  Prev: MSP430 Directives,  Up: MSP430-Dependent
13463
 
13464
9.26.5 Opcodes
13465
--------------
13466
 
13467
`as' implements all the standard MSP 430 opcodes.  No additional
13468
pseudo-instructions are needed on this family.
13469
 
13470
   For information on the 430 machine instruction set, see `MSP430
13471
User's Manual, document slau049d', Texas Instrument, Inc.
13472
 
13473

13474
File: as.info,  Node: MSP430 Profiling Capability,  Prev: MSP430 Opcodes,  Up: MSP430-Dependent
13475
 
13476
9.26.6 Profiling Capability
13477
---------------------------
13478
 
13479
It is a performance hit to use gcc's profiling approach for this tiny
13480
target.  Even more - jtag hardware facility does not perform any
13481
profiling functions.  However we've got gdb's built-in simulator where
13482
we can do anything.
13483
 
13484
   We define new section `.profiler' which holds all profiling
13485
information.  We define new pseudo operation `.profiler' which will
13486
instruct assembler to add new profile entry to the object file. Profile
13487
should take place at the present address.
13488
 
13489
   Pseudo operation format:
13490
 
13491
   `.profiler flags,function_to_profile [, cycle_corrector, extra]'
13492
 
13493
   where:
13494
 
13495
          `flags' is a combination of the following characters:
13496
 
13497
    `s'
13498
          function entry
13499
 
13500
    `x'
13501
          function exit
13502
 
13503
    `i'
13504
          function is in init section
13505
 
13506
    `f'
13507
          function is in fini section
13508
 
13509
    `l'
13510
          library call
13511
 
13512
    `c'
13513
          libc standard call
13514
 
13515
    `d'
13516
          stack value demand
13517
 
13518
    `I'
13519
          interrupt service routine
13520
 
13521
    `P'
13522
          prologue start
13523
 
13524
    `p'
13525
          prologue end
13526
 
13527
    `E'
13528
          epilogue start
13529
 
13530
    `e'
13531
          epilogue end
13532
 
13533
    `j'
13534
          long jump / sjlj unwind
13535
 
13536
    `a'
13537
          an arbitrary code fragment
13538
 
13539
    `t'
13540
          extra parameter saved (a constant value like frame size)
13541
 
13542
`function_to_profile'
13543
     a function address
13544
 
13545
`cycle_corrector'
13546
     a value which should be added to the cycle counter, zero if
13547
     omitted.
13548
 
13549
`extra'
13550
     any extra parameter, zero if omitted.
13551
 
13552
 
13553
   For example:
13554
     .global fxx
13555
     .type fxx,@function
13556
     fxx:
13557
     .LFrameOffset_fxx=0x08
13558
     .profiler "scdP", fxx     ; function entry.
13559
                          ; we also demand stack value to be saved
13560
       push r11
13561
       push r10
13562
       push r9
13563
       push r8
13564
     .profiler "cdpt",fxx,0, .LFrameOffset_fxx  ; check stack value at this point
13565
                                          ; (this is a prologue end)
13566
                                          ; note, that spare var filled with
13567
                                          ; the farme size
13568
       mov r15,r8
13569
     ...
13570
     .profiler cdE,fxx         ; check stack
13571
       pop r8
13572
       pop r9
13573
       pop r10
13574
       pop r11
13575
     .profiler xcde,fxx,3      ; exit adds 3 to the cycle counter
13576
       ret                     ; cause 'ret' insn takes 3 cycles
13577
 
13578

13579
File: as.info,  Node: PDP-11-Dependent,  Next: PJ-Dependent,  Prev: SH64-Dependent,  Up: Machine Dependencies
13580
 
13581
9.27 PDP-11 Dependent Features
13582
==============================
13583
 
13584
* Menu:
13585
 
13586
* PDP-11-Options::              Options
13587
* PDP-11-Pseudos::              Assembler Directives
13588
* PDP-11-Syntax::               DEC Syntax versus BSD Syntax
13589
* PDP-11-Mnemonics::            Instruction Naming
13590
* PDP-11-Synthetic::            Synthetic Instructions
13591
 
13592

13593
File: as.info,  Node: PDP-11-Options,  Next: PDP-11-Pseudos,  Up: PDP-11-Dependent
13594
 
13595
9.27.1 Options
13596
--------------
13597
 
13598
The PDP-11 version of `as' has a rich set of machine dependent options.
13599
 
13600
9.27.1.1 Code Generation Options
13601
................................
13602
 
13603
`-mpic | -mno-pic'
13604
     Generate position-independent (or position-dependent) code.
13605
 
13606
     The default is to generate position-independent code.
13607
 
13608
9.27.1.2 Instruction Set Extension Options
13609
..........................................
13610
 
13611
These options enables or disables the use of extensions over the base
13612
line instruction set as introduced by the first PDP-11 CPU: the KA11.
13613
Most options come in two variants: a `-m'EXTENSION that enables
13614
EXTENSION, and a `-mno-'EXTENSION that disables EXTENSION.
13615
 
13616
   The default is to enable all extensions.
13617
 
13618
`-mall | -mall-extensions'
13619
     Enable all instruction set extensions.
13620
 
13621
`-mno-extensions'
13622
     Disable all instruction set extensions.
13623
 
13624
`-mcis | -mno-cis'
13625
     Enable (or disable) the use of the commercial instruction set,
13626
     which consists of these instructions: `ADDNI', `ADDN', `ADDPI',
13627
     `ADDP', `ASHNI', `ASHN', `ASHPI', `ASHP', `CMPCI', `CMPC',
13628
     `CMPNI', `CMPN', `CMPPI', `CMPP', `CVTLNI', `CVTLN', `CVTLPI',
13629
     `CVTLP', `CVTNLI', `CVTNL', `CVTNPI', `CVTNP', `CVTPLI', `CVTPL',
13630
     `CVTPNI', `CVTPN', `DIVPI', `DIVP', `L2DR', `L3DR', `LOCCI',
13631
     `LOCC', `MATCI', `MATC', `MOVCI', `MOVC', `MOVRCI', `MOVRC',
13632
     `MOVTCI', `MOVTC', `MULPI', `MULP', `SCANCI', `SCANC', `SKPCI',
13633
     `SKPC', `SPANCI', `SPANC', `SUBNI', `SUBN', `SUBPI', and `SUBP'.
13634
 
13635
`-mcsm | -mno-csm'
13636
     Enable (or disable) the use of the `CSM' instruction.
13637
 
13638
`-meis | -mno-eis'
13639
     Enable (or disable) the use of the extended instruction set, which
13640
     consists of these instructions: `ASHC', `ASH', `DIV', `MARK',
13641
     `MUL', `RTT', `SOB' `SXT', and `XOR'.
13642
 
13643
`-mfis | -mkev11'
13644
`-mno-fis | -mno-kev11'
13645
     Enable (or disable) the use of the KEV11 floating-point
13646
     instructions: `FADD', `FDIV', `FMUL', and `FSUB'.
13647
 
13648
`-mfpp | -mfpu | -mfp-11'
13649
`-mno-fpp | -mno-fpu | -mno-fp-11'
13650
     Enable (or disable) the use of FP-11 floating-point instructions:
13651
     `ABSF', `ADDF', `CFCC', `CLRF', `CMPF', `DIVF', `LDCFF', `LDCIF',
13652
     `LDEXP', `LDF', `LDFPS', `MODF', `MULF', `NEGF', `SETD', `SETF',
13653
     `SETI', `SETL', `STCFF', `STCFI', `STEXP', `STF', `STFPS', `STST',
13654
     `SUBF', and `TSTF'.
13655
 
13656
`-mlimited-eis | -mno-limited-eis'
13657
     Enable (or disable) the use of the limited extended instruction
13658
     set: `MARK', `RTT', `SOB', `SXT', and `XOR'.
13659
 
13660
     The -mno-limited-eis options also implies -mno-eis.
13661
 
13662
`-mmfpt | -mno-mfpt'
13663
     Enable (or disable) the use of the `MFPT' instruction.
13664
 
13665
`-mmultiproc | -mno-multiproc'
13666
     Enable (or disable) the use of multiprocessor instructions:
13667
     `TSTSET' and `WRTLCK'.
13668
 
13669
`-mmxps | -mno-mxps'
13670
     Enable (or disable) the use of the `MFPS' and `MTPS' instructions.
13671
 
13672
`-mspl | -mno-spl'
13673
     Enable (or disable) the use of the `SPL' instruction.
13674
 
13675
     Enable (or disable) the use of the microcode instructions: `LDUB',
13676
     `MED', and `XFC'.
13677
 
13678
9.27.1.3 CPU Model Options
13679
..........................
13680
 
13681
These options enable the instruction set extensions supported by a
13682
particular CPU, and disables all other extensions.
13683
 
13684
`-mka11'
13685
     KA11 CPU.  Base line instruction set only.
13686
 
13687
`-mkb11'
13688
     KB11 CPU.  Enable extended instruction set and `SPL'.
13689
 
13690
`-mkd11a'
13691
     KD11-A CPU.  Enable limited extended instruction set.
13692
 
13693
`-mkd11b'
13694
     KD11-B CPU.  Base line instruction set only.
13695
 
13696
`-mkd11d'
13697
     KD11-D CPU.  Base line instruction set only.
13698
 
13699
`-mkd11e'
13700
     KD11-E CPU.  Enable extended instruction set, `MFPS', and `MTPS'.
13701
 
13702
`-mkd11f | -mkd11h | -mkd11q'
13703
     KD11-F, KD11-H, or KD11-Q CPU.  Enable limited extended
13704
     instruction set, `MFPS', and `MTPS'.
13705
 
13706
`-mkd11k'
13707
     KD11-K CPU.  Enable extended instruction set, `LDUB', `MED',
13708
     `MFPS', `MFPT', `MTPS', and `XFC'.
13709
 
13710
`-mkd11z'
13711
     KD11-Z CPU.  Enable extended instruction set, `CSM', `MFPS',
13712
     `MFPT', `MTPS', and `SPL'.
13713
 
13714
`-mf11'
13715
     F11 CPU.  Enable extended instruction set, `MFPS', `MFPT', and
13716
     `MTPS'.
13717
 
13718
`-mj11'
13719
     J11 CPU.  Enable extended instruction set, `CSM', `MFPS', `MFPT',
13720
     `MTPS', `SPL', `TSTSET', and `WRTLCK'.
13721
 
13722
`-mt11'
13723
     T11 CPU.  Enable limited extended instruction set, `MFPS', and
13724
     `MTPS'.
13725
 
13726
9.27.1.4 Machine Model Options
13727
..............................
13728
 
13729
These options enable the instruction set extensions supported by a
13730
particular machine model, and disables all other extensions.
13731
 
13732
`-m11/03'
13733
     Same as `-mkd11f'.
13734
 
13735
`-m11/04'
13736
     Same as `-mkd11d'.
13737
 
13738
`-m11/05 | -m11/10'
13739
     Same as `-mkd11b'.
13740
 
13741
`-m11/15 | -m11/20'
13742
     Same as `-mka11'.
13743
 
13744
`-m11/21'
13745
     Same as `-mt11'.
13746
 
13747
`-m11/23 | -m11/24'
13748
     Same as `-mf11'.
13749
 
13750
`-m11/34'
13751
     Same as `-mkd11e'.
13752
 
13753
`-m11/34a'
13754
     Ame as `-mkd11e' `-mfpp'.
13755
 
13756
`-m11/35 | -m11/40'
13757
     Same as `-mkd11a'.
13758
 
13759
`-m11/44'
13760
     Same as `-mkd11z'.
13761
 
13762
`-m11/45 | -m11/50 | -m11/55 | -m11/70'
13763
     Same as `-mkb11'.
13764
 
13765
`-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94'
13766
     Same as `-mj11'.
13767
 
13768
`-m11/60'
13769
     Same as `-mkd11k'.
13770
 
13771

13772
File: as.info,  Node: PDP-11-Pseudos,  Next: PDP-11-Syntax,  Prev: PDP-11-Options,  Up: PDP-11-Dependent
13773
 
13774
9.27.2 Assembler Directives
13775
---------------------------
13776
 
13777
The PDP-11 version of `as' has a few machine dependent assembler
13778
directives.
13779
 
13780
`.bss'
13781
     Switch to the `bss' section.
13782
 
13783
`.even'
13784
     Align the location counter to an even number.
13785
 
13786

13787
File: as.info,  Node: PDP-11-Syntax,  Next: PDP-11-Mnemonics,  Prev: PDP-11-Pseudos,  Up: PDP-11-Dependent
13788
 
13789
9.27.3 PDP-11 Assembly Language Syntax
13790
--------------------------------------
13791
 
13792
`as' supports both DEC syntax and BSD syntax.  The only difference is
13793
that in DEC syntax, a `#' character is used to denote an immediate
13794
constants, while in BSD syntax the character for this purpose is `$'.
13795
 
13796
   general-purpose registers are named `r0' through `r7'.  Mnemonic
13797
alternatives for `r6' and `r7' are `sp' and `pc', respectively.
13798
 
13799
   Floating-point registers are named `ac0' through `ac3', or
13800
alternatively `fr0' through `fr3'.
13801
 
13802
   Comments are started with a `#' or a `/' character, and extend to
13803
the end of the line.  (FIXME: clash with immediates?)
13804
 
13805

13806
File: as.info,  Node: PDP-11-Mnemonics,  Next: PDP-11-Synthetic,  Prev: PDP-11-Syntax,  Up: PDP-11-Dependent
13807
 
13808
9.27.4 Instruction Naming
13809
-------------------------
13810
 
13811
Some instructions have alternative names.
13812
 
13813
`BCC'
13814
     `BHIS'
13815
 
13816
`BCS'
13817
     `BLO'
13818
 
13819
`L2DR'
13820
     `L2D'
13821
 
13822
`L3DR'
13823
     `L3D'
13824
 
13825
`SYS'
13826
     `TRAP'
13827
 
13828

13829
File: as.info,  Node: PDP-11-Synthetic,  Prev: PDP-11-Mnemonics,  Up: PDP-11-Dependent
13830
 
13831
9.27.5 Synthetic Instructions
13832
-----------------------------
13833
 
13834
The `JBR' and `J'CC synthetic instructions are not supported yet.
13835
 
13836

13837
File: as.info,  Node: PJ-Dependent,  Next: PPC-Dependent,  Prev: PDP-11-Dependent,  Up: Machine Dependencies
13838
 
13839
9.28 picoJava Dependent Features
13840
================================
13841
 
13842
* Menu:
13843
 
13844
* PJ Options::              Options
13845
 
13846

13847
File: as.info,  Node: PJ Options,  Up: PJ-Dependent
13848
 
13849
9.28.1 Options
13850
--------------
13851
 
13852
`as' has two additional command-line options for the picoJava
13853
architecture.
13854
`-ml'
13855
     This option selects little endian data output.
13856
 
13857
`-mb'
13858
     This option selects big endian data output.
13859
 
13860

13861
File: as.info,  Node: PPC-Dependent,  Next: S/390-Dependent,  Prev: PJ-Dependent,  Up: Machine Dependencies
13862
 
13863
9.29 PowerPC Dependent Features
13864
===============================
13865
 
13866
* Menu:
13867
 
13868
* PowerPC-Opts::                Options
13869
* PowerPC-Pseudo::              PowerPC Assembler Directives
13870
 
13871

13872
File: as.info,  Node: PowerPC-Opts,  Next: PowerPC-Pseudo,  Up: PPC-Dependent
13873
 
13874
9.29.1 Options
13875
--------------
13876
 
13877
The PowerPC chip family includes several successive levels, using the
13878
same core instruction set, but including a few additional instructions
13879
at each level.  There are exceptions to this however.  For details on
13880
what instructions each variant supports, please see the chip's
13881
architecture reference manual.
13882
 
13883
   The following table lists all available PowerPC options.
13884
 
13885
`-mpwrx | -mpwr2'
13886
     Generate code for POWER/2 (RIOS2).
13887
 
13888
`-mpwr'
13889
     Generate code for POWER (RIOS1)
13890
 
13891
`-m601'
13892
     Generate code for PowerPC 601.
13893
 
13894
`-mppc, -mppc32, -m603, -m604'
13895
     Generate code for PowerPC 603/604.
13896
 
13897
`-m403, -m405'
13898
     Generate code for PowerPC 403/405.
13899
 
13900
`-m440'
13901
     Generate code for PowerPC 440.  BookE and some 405 instructions.
13902
 
13903
`-m476'
13904
     Generate code for PowerPC 476.
13905
 
13906
`-m7400, -m7410, -m7450, -m7455'
13907
     Generate code for PowerPC 7400/7410/7450/7455.
13908
 
13909
`-m750cl'
13910
     Generate code for PowerPC 750CL.
13911
 
13912
`-mppc64, -m620'
13913
     Generate code for PowerPC 620/625/630.
13914
 
13915
`-me500, -me500x2'
13916
     Generate code for Motorola e500 core complex.
13917
 
13918
`-mspe'
13919
     Generate code for Motorola SPE instructions.
13920
 
13921
`-mppc64bridge'
13922
     Generate code for PowerPC 64, including bridge insns.
13923
 
13924
`-mbooke'
13925
     Generate code for 32-bit BookE.
13926
 
13927
`-ma2'
13928
     Generate code for A2 architecture.
13929
 
13930
`-me300'
13931
     Generate code for PowerPC e300 family.
13932
 
13933
`-maltivec'
13934
     Generate code for processors with AltiVec instructions.
13935
 
13936
`-mvsx'
13937
     Generate code for processors with Vector-Scalar (VSX) instructions.
13938
 
13939
`-mpower4'
13940
     Generate code for Power4 architecture.
13941
 
13942
`-mpower5'
13943
     Generate code for Power5 architecture.
13944
 
13945
`-mpower6'
13946
     Generate code for Power6 architecture.
13947
 
13948
`-mpower7'
13949
     Generate code for Power7 architecture.
13950
 
13951
`-mcell'
13952
     Generate code for Cell Broadband Engine architecture.
13953
 
13954
`-mcom'
13955
     Generate code Power/PowerPC common instructions.
13956
 
13957
`-many'
13958
     Generate code for any architecture (PWR/PWRX/PPC).
13959
 
13960
`-mregnames'
13961
     Allow symbolic names for registers.
13962
 
13963
`-mno-regnames'
13964
     Do not allow symbolic names for registers.
13965
 
13966
`-mrelocatable'
13967
     Support for GCC's -mrelocatable option.
13968
 
13969
`-mrelocatable-lib'
13970
     Support for GCC's -mrelocatable-lib option.
13971
 
13972
`-memb'
13973
     Set PPC_EMB bit in ELF flags.
13974
 
13975
`-mlittle, -mlittle-endian'
13976
     Generate code for a little endian machine.
13977
 
13978
`-mbig, -mbig-endian'
13979
     Generate code for a big endian machine.
13980
 
13981
`-msolaris'
13982
     Generate code for Solaris.
13983
 
13984
`-mno-solaris'
13985
     Do not generate code for Solaris.
13986
 
13987

13988
File: as.info,  Node: PowerPC-Pseudo,  Prev: PowerPC-Opts,  Up: PPC-Dependent
13989
 
13990
9.29.2 PowerPC Assembler Directives
13991
-----------------------------------
13992
 
13993
A number of assembler directives are available for PowerPC.  The
13994
following table is far from complete.
13995
 
13996
`.machine "string"'
13997
     This directive allows you to change the machine for which code is
13998
     generated.  `"string"' may be any of the -m cpu selection options
13999
     (without the -m) enclosed in double quotes, `"push"', or `"pop"'.
14000
     `.machine "push"' saves the currently selected cpu, which may be
14001
     restored with `.machine "pop"'.
14002
 
14003

14004
File: as.info,  Node: S/390-Dependent,  Next: SCORE-Dependent,  Prev: PPC-Dependent,  Up: Machine Dependencies
14005
 
14006
9.30 IBM S/390 Dependent Features
14007
=================================
14008
 
14009
   The s390 version of `as' supports two architectures modes and seven
14010
chip levels. The architecture modes are the Enterprise System
14011
Architecture (ESA) and the newer z/Architecture mode. The chip levels
14012
are g5, g6, z900, z990, z9-109, z9-ec and z10.
14013
 
14014
* Menu:
14015
 
14016
* s390 Options::                Command-line Options.
14017
* s390 Characters::             Special Characters.
14018
* s390 Syntax::                 Assembler Instruction syntax.
14019
* s390 Directives::             Assembler Directives.
14020
* s390 Floating Point::         Floating Point.
14021
 
14022

14023
File: as.info,  Node: s390 Options,  Next: s390 Characters,  Up: S/390-Dependent
14024
 
14025
9.30.1 Options
14026
--------------
14027
 
14028
The following table lists all available s390 specific options:
14029
 
14030
`-m31 | -m64'
14031
     Select 31- or 64-bit ABI implying a word size of 32- or 64-bit.
14032
 
14033
     These options are only available with the ELF object file format,
14034
     and require that the necessary BFD support has been included (on a
14035
     31-bit platform you must add -enable-64-bit-bfd on the call to the
14036
     configure script to enable 64-bit usage and use s390x as target
14037
     platform).
14038
 
14039
`-mesa | -mzarch'
14040
     Select the architecture mode, either the Enterprise System
14041
     Architecture (esa) mode or the z/Architecture mode (zarch).
14042
 
14043
     The 64-bit instructions are only available with the z/Architecture
14044
     mode.  The combination of `-m64' and `-mesa' results in a warning
14045
     message.
14046
 
14047
`-march=CPU'
14048
     This option specifies the target processor. The following
14049
     processor names are recognized: `g5', `g6', `z900', `z990',
14050
     `z9-109', `z9-ec' and `z10'.  Assembling an instruction that is
14051
     not supported on the target processor results in an error message.
14052
     Do not specify `g5' or `g6' with `-mzarch'.
14053
 
14054
`-mregnames'
14055
     Allow symbolic names for registers.
14056
 
14057
`-mno-regnames'
14058
     Do not allow symbolic names for registers.
14059
 
14060
`-mwarn-areg-zero'
14061
     Warn whenever the operand for a base or index register has been
14062
     specified but evaluates to zero. This can indicate the misuse of
14063
     general purpose register 0 as an address register.
14064
 
14065
 
14066

14067
File: as.info,  Node: s390 Characters,  Next: s390 Syntax,  Prev: s390 Options,  Up: S/390-Dependent
14068
 
14069
9.30.2 Special Characters
14070
-------------------------
14071
 
14072
`#' is the line comment character.
14073
 
14074

14075
File: as.info,  Node: s390 Syntax,  Next: s390 Directives,  Prev: s390 Characters,  Up: S/390-Dependent
14076
 
14077
9.30.3 Instruction syntax
14078
-------------------------
14079
 
14080
The assembler syntax closely follows the syntax outlined in Enterprise
14081
Systems Architecture/390 Principles of Operation (SA22-7201) and the
14082
z/Architecture Principles of Operation (SA22-7832).
14083
 
14084
   Each instruction has two major parts, the instruction mnemonic and
14085
the instruction operands. The instruction format varies.
14086
 
14087
* Menu:
14088
 
14089
* s390 Register::               Register Naming
14090
* s390 Mnemonics::              Instruction Mnemonics
14091
* s390 Operands::               Instruction Operands
14092
* s390 Formats::                Instruction Formats
14093
* s390 Aliases::                Instruction Aliases
14094
* s390 Operand Modifier::       Instruction Operand Modifier
14095
* s390 Instruction Marker::     Instruction Marker
14096
* s390 Literal Pool Entries::   Literal Pool Entries
14097
 
14098

14099
File: as.info,  Node: s390 Register,  Next: s390 Mnemonics,  Up: s390 Syntax
14100
 
14101
9.30.3.1 Register naming
14102
........................
14103
 
14104
The `as' recognizes a number of predefined symbols for the various
14105
processor registers. A register specification in one of the instruction
14106
formats is an unsigned integer between 0 and 15. The specific
14107
instruction and the position of the register in the instruction format
14108
denotes the type of the register. The register symbols are prefixed with
14109
`%':
14110
 
14111
     %rN   the 16 general purpose registers, 0 <= N <= 15
14112
     %fN   the 16 floating point registers, 0 <= N <= 15
14113
     %aN   the 16 access registers, 0 <= N <= 15
14114
     %cN   the 16 control registers, 0 <= N <= 15
14115
     %lit  an alias for the general purpose register %r13
14116
     %sp   an alias for the general purpose register %r15
14117
 
14118

14119
File: as.info,  Node: s390 Mnemonics,  Next: s390 Operands,  Prev: s390 Register,  Up: s390 Syntax
14120
 
14121
9.30.3.2 Instruction Mnemonics
14122
..............................
14123
 
14124
All instructions documented in the Principles of Operation are supported
14125
with the mnemonic and order of operands as described.  The instruction
14126
mnemonic identifies the instruction format (*Note s390 Formats::) and
14127
the specific operation code for the instruction.  For example, the `lr'
14128
mnemonic denotes the instruction format `RR' with the operation code
14129
`0x18'.
14130
 
14131
   The definition of the various mnemonics follows a scheme, where the
14132
first character usually hint at the type of the instruction:
14133
 
14134
     a          add instruction, for example `al' for add logical 32-bit
14135
     b          branch instruction, for example `bc' for branch on condition
14136
     c          compare or convert instruction, for example `cr' for compare
14137
                register 32-bit
14138
     d          divide instruction, for example `dlr' devide logical register
14139
                64-bit to 32-bit
14140
     i          insert instruction, for example `ic' insert character
14141
     l          load instruction, for example `ltr' load and test register
14142
     mv         move instruction, for example `mvc' move character
14143
     m          multiply instruction, for example `mh' multiply halfword
14144
     n          and instruction, for example `ni' and immediate
14145
     o          or instruction, for example `oc' or character
14146
     sla, sll   shift left single instruction
14147
     sra, srl   shift right single instruction
14148
     st         store instruction, for example `stm' store multiple
14149
     s          subtract instruction, for example `slr' subtract
14150
                logical 32-bit
14151
     t          test or translate instruction, of example `tm' test under mask
14152
     x          exclusive or instruction, for example `xc' exclusive or
14153
                character
14154
 
14155
   Certain characters at the end of the mnemonic may describe a property
14156
of the instruction:
14157
 
14158
     c   the instruction uses a 8-bit character operand
14159
     f   the instruction extends a 32-bit operand to 64 bit
14160
     g   the operands are treated as 64-bit values
14161
     h   the operand uses a 16-bit halfword operand
14162
     i   the instruction uses an immediate operand
14163
     l   the instruction uses unsigned, logical operands
14164
     m   the instruction uses a mask or operates on multiple values
14165
     r   if r is the last character, the instruction operates on registers
14166
     y   the instruction uses 20-bit displacements
14167
 
14168
   There are many exceptions to the scheme outlined in the above lists,
14169
in particular for the priviledged instructions. For non-priviledged
14170
instruction it works quite well, for example the instruction `clgfr' c:
14171
compare instruction, l: unsigned operands, g: 64-bit operands, f: 32-
14172
to 64-bit extension, r: register operands. The instruction compares an
14173
64-bit value in a register with the zero extended 32-bit value from a
14174
second register.  For a complete list of all mnemonics see appendix B
14175
in the Principles of Operation.
14176
 
14177

14178
File: as.info,  Node: s390 Operands,  Next: s390 Formats,  Prev: s390 Mnemonics,  Up: s390 Syntax
14179
 
14180
9.30.3.3 Instruction Operands
14181
.............................
14182
 
14183
Instruction operands can be grouped into three classes, operands located
14184
in registers, immediate operands, and operands in storage.
14185
 
14186
   A register operand can be located in general, floating-point, access,
14187
or control register. The register is identified by a four-bit field.
14188
The field containing the register operand is called the R field.
14189
 
14190
   Immediate operands are contained within the instruction and can have
14191
8, 16 or 32 bits. The field containing the immediate operand is called
14192
the I field. Dependent on the instruction the I field is either signed
14193
or unsigned.
14194
 
14195
   A storage operand consists of an address and a length. The address
14196
of a storage operands can be specified in any of these ways:
14197
 
14198
   * The content of a single general R
14199
 
14200
   * The sum of the content of a general register called the base
14201
     register B plus the content of a displacement field D
14202
 
14203
   * The sum of the contents of two general registers called the index
14204
     register X and the base register B plus the content of a
14205
     displacement field
14206
 
14207
   * The sum of the current instruction address and a 32-bit signed
14208
     immediate field multiplied by two.
14209
 
14210
   The length of a storage operand can be:
14211
 
14212
   * Implied by the instruction
14213
 
14214
   * Specified by a bitmask
14215
 
14216
   * Specified by a four-bit or eight-bit length field L
14217
 
14218
   * Specified by the content of a general register
14219
 
14220
   The notation for storage operand addresses formed from multiple
14221
fields is as follows:
14222
 
14223
`Dn(Bn)'
14224
     the address for operand number n is formed from the content of
14225
     general register Bn called the base register and the displacement
14226
     field Dn.
14227
 
14228
`Dn(Xn,Bn)'
14229
     the address for operand number n is formed from the content of
14230
     general register Xn called the index register, general register Bn
14231
     called the base register and the displacement field Dn.
14232
 
14233
`Dn(Ln,Bn)'
14234
     the address for operand number n is formed from the content of
14235
     general regiser Bn called the base register and the displacement
14236
     field Dn.  The length of the operand n is specified by the field
14237
     Ln.
14238
 
14239
   The base registers Bn and the index registers Xn of a storage
14240
operand can be skipped. If Bn and Xn are skipped, a zero will be stored
14241
to the operand field. The notation changes as follows:
14242
 
14243
     full notation        short notation
14244
     ------------------------------------------
14245
     Dn(0,Bn)             Dn(Bn)
14246
     Dn(0,0)              Dn
14247
     Dn(0)                Dn
14248
     Dn(Ln,0)             Dn(Ln)
14249
 
14250

14251
File: as.info,  Node: s390 Formats,  Next: s390 Aliases,  Prev: s390 Operands,  Up: s390 Syntax
14252
 
14253
9.30.3.4 Instruction Formats
14254
............................
14255
 
14256
The Principles of Operation manuals lists 26 instruction formats where
14257
some of the formats have multiple variants. For the `.insn' pseudo
14258
directive the assembler recognizes some of the formats.  Typically, the
14259
most general variant of the instruction format is used by the `.insn'
14260
directive.
14261
 
14262
   The following table lists the abbreviations used in the table of
14263
instruction formats:
14264
 
14265
     OpCode / OpCd   Part of the op code.
14266
     Bx              Base register number for operand x.
14267
     Dx              Displacement for operand x.
14268
     DLx             Displacement lower 12 bits for operand x.
14269
     DHx             Displacement higher 8-bits for operand x.
14270
     Rx              Register number for operand x.
14271
     Xx              Index register number for operand x.
14272
     Ix              Signed immediate for operand x.
14273
     Ux              Unsigned immediate for operand x.
14274
 
14275
   An instruction is two, four, or six bytes in length and must be
14276
aligned on a 2 byte boundary. The first two bits of the instruction
14277
specify the length of the instruction, 00 indicates a two byte
14278
instruction, 01 and 10 indicates a four byte instruction, and 11
14279
indicates a six byte instruction.
14280
 
14281
   The following table lists the s390 instruction formats that are
14282
available with the `.insn' pseudo directive:
14283
 
14284
`E format'
14285
 
14286
     +-------------+
14287
     |    OpCode   |
14288
     +-------------+
14289
 
14290
 
14291
`RI format:  R1,I2'
14292
 
14293
     +--------+----+----+------------------+
14294
     | OpCode | R1 |OpCd|        I2        |
14295
     +--------+----+----+------------------+
14296
 
14297
 
14298
`RIE format:  R1,R3,I2'
14299
 
14300
     +--------+----+----+------------------+--------+--------+
14301
     | OpCode | R1 | R3 |        I2        |////////| OpCode |
14302
     +--------+----+----+------------------+--------+--------+
14303
 
14304
 
14305
`RIL format:  R1,I2'
14306
 
14307
     +--------+----+----+------------------------------------+
14308
     | OpCode | R1 |OpCd|                  I2                |
14309
     +--------+----+----+------------------------------------+
14310
 
14311
 
14312
`RILU format:  R1,U2'
14313
 
14314
     +--------+----+----+------------------------------------+
14315
     | OpCode | R1 |OpCd|                  U2                |
14316
     +--------+----+----+------------------------------------+
14317
 
14318
 
14319
`RIS format:  R1,I2,M3,D4(B4)'
14320
 
14321
     +--------+----+----+----+-------------+--------+--------+
14322
     | OpCode | R1 | M3 | B4 |     D4      |   I2   | Opcode |
14323
     +--------+----+----+----+-------------+--------+--------+
14324
 
14325
 
14326
`RR format:  R1,R2'
14327
 
14328
     +--------+----+----+
14329
     | OpCode | R1 | R2 |
14330
     +--------+----+----+
14331
 
14332
 
14333
`RRE format:  R1,R2'
14334
 
14335
     +------------------+--------+----+----+
14336
     |      OpCode      |////////| R1 | R2 |
14337
     +------------------+--------+----+----+
14338
 
14339
 
14340
`RRF format:  R1,R2,R3,M4'
14341
 
14342
     +------------------+----+----+----+----+
14343
     |      OpCode      | R3 | M4 | R1 | R2 |
14344
     +------------------+----+----+----+----+
14345
 
14346
 
14347
`RRS format:  R1,R2,M3,D4(B4)'
14348
 
14349
     +--------+----+----+----+-------------+----+----+--------+
14350
     | OpCode | R1 | R3 | B4 |     D4      | M3 |////| OpCode |
14351
     +--------+----+----+----+-------------+----+----+--------+
14352
 
14353
 
14354
`RS format:  R1,R3,D2(B2)'
14355
 
14356
     +--------+----+----+----+-------------+
14357
     | OpCode | R1 | R3 | B2 |     D2      |
14358
     +--------+----+----+----+-------------+
14359
 
14360
 
14361
`RSE format:  R1,R3,D2(B2)'
14362
 
14363
     +--------+----+----+----+-------------+--------+--------+
14364
     | OpCode | R1 | R3 | B2 |     D2      |////////| OpCode |
14365
     +--------+----+----+----+-------------+--------+--------+
14366
 
14367
 
14368
`RSI format:  R1,R3,I2'
14369
 
14370
     +--------+----+----+------------------------------------+
14371
     | OpCode | R1 | R3 |                  I2                |
14372
     +--------+----+----+------------------------------------+
14373
 
14374
 
14375
`RSY format:  R1,R3,D2(B2)'
14376
 
14377
     +--------+----+----+----+-------------+--------+--------+
14378
     | OpCode | R1 | R3 | B2 |    DL2      |  DH2   | OpCode |
14379
     +--------+----+----+----+-------------+--------+--------+
14380
 
14381
 
14382
`RX format:  R1,D2(X2,B2)'
14383
 
14384
     +--------+----+----+----+-------------+
14385
     | OpCode | R1 | X2 | B2 |     D2      |
14386
     +--------+----+----+----+-------------+
14387
 
14388
 
14389
`RXE format:  R1,D2(X2,B2)'
14390
 
14391
     +--------+----+----+----+-------------+--------+--------+
14392
     | OpCode | R1 | X2 | B2 |     D2      |////////| OpCode |
14393
     +--------+----+----+----+-------------+--------+--------+
14394
 
14395
 
14396
`RXF format:  R1,R3,D2(X2,B2)'
14397
 
14398
     +--------+----+----+----+-------------+----+---+--------+
14399
     | OpCode | R3 | X2 | B2 |     D2      | R1 |///| OpCode |
14400
     +--------+----+----+----+-------------+----+---+--------+
14401
 
14402
 
14403
`RXY format:  R1,D2(X2,B2)'
14404
 
14405
     +--------+----+----+----+-------------+--------+--------+
14406
     | OpCode | R1 | X2 | B2 |     DL2     |   DH2  | OpCode |
14407
     +--------+----+----+----+-------------+--------+--------+
14408
 
14409
 
14410
`S format:  D2(B2)'
14411
 
14412
     +------------------+----+-------------+
14413
     |      OpCode      | B2 |     D2      |
14414
     +------------------+----+-------------+
14415
 
14416
 
14417
`SI format:  D1(B1),I2'
14418
 
14419
     +--------+---------+----+-------------+
14420
     | OpCode |   I2    | B1 |     D1      |
14421
     +--------+---------+----+-------------+
14422
 
14423
 
14424
`SIY format:  D1(B1),U2'
14425
 
14426
     +--------+---------+----+-------------+--------+--------+
14427
     | OpCode |   I2    | B1 |     DL1     |  DH1   | OpCode |
14428
     +--------+---------+----+-------------+--------+--------+
14429
 
14430
 
14431
`SIL format:  D1(B1),I2'
14432
 
14433
     +------------------+----+-------------+-----------------+
14434
     |      OpCode      | B1 |      D1     |       I2        |
14435
     +------------------+----+-------------+-----------------+
14436
 
14437
 
14438
`SS format:  D1(R1,B1),D2(B3),R3'
14439
 
14440
     +--------+----+----+----+-------------+----+------------+
14441
     | OpCode | R1 | R3 | B1 |     D1      | B2 |     D2     |
14442
     +--------+----+----+----+-------------+----+------------+
14443
 
14444
 
14445
`SSE format:  D1(B1),D2(B2)'
14446
 
14447
     +------------------+----+-------------+----+------------+
14448
     |      OpCode      | B1 |     D1      | B2 |     D2     |
14449
     +------------------+----+-------------+----+------------+
14450
 
14451
 
14452
`SSF format:  D1(B1),D2(B2),R3'
14453
 
14454
     +--------+----+----+----+-------------+----+------------+
14455
     | OpCode | R3 |OpCd| B1 |     D1      | B2 |     D2     |
14456
     +--------+----+----+----+-------------+----+------------+
14457
 
14458
 
14459
 
14460
   For the complete list of all instruction format variants see the
14461
Principles of Operation manuals.
14462
 
14463

14464
File: as.info,  Node: s390 Aliases,  Next: s390 Operand Modifier,  Prev: s390 Formats,  Up: s390 Syntax
14465
 
14466
9.30.3.5 Instruction Aliases
14467
............................
14468
 
14469
A specific bit pattern can have multiple mnemonics, for example the bit
14470
pattern `0xa7000000' has the mnemonics `tmh' and `tmlh'. In addition,
14471
there are a number of mnemonics recognized by `as' that are not present
14472
in the Principles of Operation.  These are the short forms of the
14473
branch instructions, where the condition code mask operand is encoded
14474
in the mnemonic. This is relevant for the branch instructions, the
14475
compare and branch instructions, and the compare and trap instructions.
14476
 
14477
   For the branch instructions there are 20 condition code strings that
14478
can be used as part of the mnemonic in place of a mask operand in the
14479
instruction format:
14480
 
14481
     instruction          short form
14482
     ------------------------------------------
14483
     bcr   M1,R2          br  R2
14484
     bc    M1,D2(X2,B2)   b   D2(X2,B2)
14485
     brc   M1,I2          j   I2
14486
     brcl  M1,I2          jg  I2
14487
 
14488
   In the mnemonic for a branch instruction the condition code string
14489
 can be any of the following:
14490
 
14491
     o     jump on overflow / if ones
14492
     h     jump on A high
14493
     p     jump on plus
14494
     nle   jump on not low or equal
14495
     l     jump on A low
14496
     m     jump on minus
14497
     nhe   jump on not high or equal
14498
     lh    jump on low or high
14499
     ne    jump on A not equal B
14500
     nz    jump on not zero / if not zeros
14501
     e     jump on A equal B
14502
     z     jump on zero / if zeroes
14503
     nlh   jump on not low or high
14504
     he    jump on high or equal
14505
     nl    jump on A not low
14506
     nm    jump on not minus / if not mixed
14507
     le    jump on low or equal
14508
     nh    jump on A not high
14509
     np    jump on not plus
14510
     no    jump on not overflow / if not ones
14511
 
14512
   For the compare and branch, and compare and trap instructions there
14513
are 12 condition code strings that can be used as part of the mnemonic
14514
in place of a mask operand in the instruction format:
14515
 
14516
     instruction                 short form
14517
     --------------------------------------------------------
14518
     crb    R1,R2,M3,D4(B4)      crb    R1,R2,D4(B4)
14519
     cgrb   R1,R2,M3,D4(B4)      cgrb   R1,R2,D4(B4)
14520
     crj    R1,R2,M3,I4          crj    R1,R2,I4
14521
     cgrj   R1,R2,M3,I4          cgrj   R1,R2,I4
14522
     cib    R1,I2,M3,D4(B4)      cib    R1,I2,D4(B4)
14523
     cgib   R1,I2,M3,D4(B4)      cgib   R1,I2,D4(B4)
14524
     cij    R1,I2,M3,I4          cij    R1,I2,I4
14525
     cgij   R1,I2,M3,I4          cgij   R1,I2,I4
14526
     crt    R1,R2,M3             crt    R1,R2
14527
     cgrt   R1,R2,M3             cgrt   R1,R2
14528
     cit    R1,I2,M3             cit    R1,I2
14529
     cgit   R1,I2,M3             cgit   R1,I2
14530
     clrb   R1,R2,M3,D4(B4)      clrb   R1,R2,D4(B4)
14531
     clgrb  R1,R2,M3,D4(B4)      clgrb  R1,R2,D4(B4)
14532
     clrj   R1,R2,M3,I4          clrj   R1,R2,I4
14533
     clgrj  R1,R2,M3,I4          clgrj  R1,R2,I4
14534
     clib   R1,I2,M3,D4(B4)      clib   R1,I2,D4(B4)
14535
     clgib  R1,I2,M3,D4(B4)      clgib  R1,I2,D4(B4)
14536
     clij   R1,I2,M3,I4          clij   R1,I2,I4
14537
     clgij  R1,I2,M3,I4          clgij  R1,I2,I4
14538
     clrt   R1,R2,M3             clrt   R1,R2
14539
     clgrt  R1,R2,M3             clgrt  R1,R2
14540
     clfit  R1,I2,M3             clfit  R1,I2
14541
     clgit  R1,I2,M3             clgit  R1,I2
14542
 
14543
   In the mnemonic for a compare and branch and compare and trap
14544
instruction the condition code string  can be any of the following:
14545
 
14546
     h     jump on A high
14547
     nle   jump on not low or equal
14548
     l     jump on A low
14549
     nhe   jump on not high or equal
14550
     ne    jump on A not equal B
14551
     lh    jump on low or high
14552
     e     jump on A equal B
14553
     nlh   jump on not low or high
14554
     nl    jump on A not low
14555
     he    jump on high or equal
14556
     nh    jump on A not high
14557
     le    jump on low or equal
14558
 
14559

14560
File: as.info,  Node: s390 Operand Modifier,  Next: s390 Instruction Marker,  Prev: s390 Aliases,  Up: s390 Syntax
14561
 
14562
9.30.3.6 Instruction Operand Modifier
14563
.....................................
14564
 
14565
If a symbol modifier is attached to a symbol in an expression for an
14566
instruction operand field, the symbol term is replaced with a reference
14567
to an object in the global offset table (GOT) or the procedure linkage
14568
table (PLT). The following expressions are allowed: `symbol@modifier +
14569
constant', `symbol@modifier + label + constant', and `symbol@modifier -
14570
label + constant'.  The term `symbol' is the symbol that will be
14571
entered into the GOT or PLT, `label' is a local label, and `constant'
14572
is an arbitrary expression that the assembler can evaluate to a
14573
constant value.
14574
 
14575
   The term `(symbol + constant1)@modifier +/- label + constant2' is
14576
also accepted but a warning message is printed and the term is
14577
converted to `symbol@modifier +/- label + constant1 + constant2'.
14578
 
14579
`@got'
14580
`@got12'
14581
     The @got modifier can be used for displacement fields, 16-bit
14582
     immediate fields and 32-bit pc-relative immediate fields. The
14583
     @got12 modifier is synonym to @got. The symbol is added to the
14584
     GOT. For displacement fields and 16-bit immediate fields the
14585
     symbol term is replaced with the offset from the start of the GOT
14586
     to the GOT slot for the symbol.  For a 32-bit pc-relative field
14587
     the pc-relative offset to the GOT slot from the current
14588
     instruction address is used.
14589
 
14590
`@gotent'
14591
     The @gotent modifier can be used for 32-bit pc-relative immediate
14592
     fields.  The symbol is added to the GOT and the symbol term is
14593
     replaced with the pc-relative offset from the current instruction
14594
     to the GOT slot for the symbol.
14595
 
14596
`@gotoff'
14597
     The @gotoff modifier can be used for 16-bit immediate fields. The
14598
     symbol term is replaced with the offset from the start of the GOT
14599
     to the address of the symbol.
14600
 
14601
`@gotplt'
14602
     The @gotplt modifier can be used for displacement fields, 16-bit
14603
     immediate fields, and 32-bit pc-relative immediate fields. A
14604
     procedure linkage table entry is generated for the symbol and a
14605
     jump slot for the symbol is added to the GOT. For displacement
14606
     fields and 16-bit immediate fields the symbol term is replaced
14607
     with the offset from the start of the GOT to the jump slot for the
14608
     symbol. For a 32-bit pc-relative field the pc-relative offset to
14609
     the jump slot from the current instruction address is used.
14610
 
14611
`@plt'
14612
     The @plt modifier can be used for 16-bit and 32-bit pc-relative
14613
     immediate fields. A procedure linkage table entry is generated for
14614
     the symbol.  The symbol term is replaced with the relative offset
14615
     from the current instruction to the PLT entry for the symbol.
14616
 
14617
`@pltoff'
14618
     The @pltoff modifier can be used for 16-bit immediate fields. The
14619
     symbol term is replaced with the offset from the start of the PLT
14620
     to the address of the symbol.
14621
 
14622
`@gotntpoff'
14623
     The @gotntpoff modifier can be used for displacement fields. The
14624
     symbol is added to the static TLS block and the negated offset to
14625
     the symbol in the static TLS block is added to the GOT. The symbol
14626
     term is replaced with the offset to the GOT slot from the start of
14627
     the GOT.
14628
 
14629
`@indntpoff'
14630
     The @indntpoff modifier can be used for 32-bit pc-relative
14631
     immediate fields. The symbol is added to the static TLS block and
14632
     the negated offset to the symbol in the static TLS block is added
14633
     to the GOT. The symbol term is replaced with the pc-relative
14634
     offset to the GOT slot from the current instruction address.
14635
 
14636
   For more information about the thread local storage modifiers
14637
`gotntpoff' and `indntpoff' see the ELF extension documentation `ELF
14638
Handling For Thread-Local Storage'.
14639
 
14640

14641
File: as.info,  Node: s390 Instruction Marker,  Next: s390 Literal Pool Entries,  Prev: s390 Operand Modifier,  Up: s390 Syntax
14642
 
14643
9.30.3.7 Instruction Marker
14644
...........................
14645
 
14646
The thread local storage instruction markers are used by the linker to
14647
perform code optimization.
14648
 
14649
`:tls_load'
14650
     The :tls_load marker is used to flag the load instruction in the
14651
     initial exec TLS model that retrieves the offset from the thread
14652
     pointer to a thread local storage variable from the GOT.
14653
 
14654
`:tls_gdcall'
14655
     The :tls_gdcall marker is used to flag the branch-and-save
14656
     instruction to the __tls_get_offset function in the global dynamic
14657
     TLS model.
14658
 
14659
`:tls_ldcall'
14660
     The :tls_ldcall marker is used to flag the branch-and-save
14661
     instruction to the __tls_get_offset function in the local dynamic
14662
     TLS model.
14663
 
14664
   For more information about the thread local storage instruction
14665
marker and the linker optimizations see the ELF extension documentation
14666
`ELF Handling For Thread-Local Storage'.
14667
 
14668

14669
File: as.info,  Node: s390 Literal Pool Entries,  Prev: s390 Instruction Marker,  Up: s390 Syntax
14670
 
14671
9.30.3.8 Literal Pool Entries
14672
.............................
14673
 
14674
A literal pool is a collection of values. To access the values a pointer
14675
to the literal pool is loaded to a register, the literal pool register.
14676
Usually, register %r13 is used as the literal pool register (*Note s390
14677
Register::). Literal pool entries are created by adding the suffix
14678
:lit1, :lit2, :lit4, or :lit8 to the end of an expression for an
14679
instruction operand. The expression is added to the literal pool and the
14680
operand is replaced with the offset to the literal in the literal pool.
14681
 
14682
`:lit1'
14683
     The literal pool entry is created as an 8-bit value. An operand
14684
     modifier must not be used for the original expression.
14685
 
14686
`:lit2'
14687
     The literal pool entry is created as a 16 bit value. The operand
14688
     modifier @got may be used in the original expression. The term
14689
     `x@got:lit2' will put the got offset for the global symbol x to
14690
     the literal pool as 16 bit value.
14691
 
14692
`:lit4'
14693
     The literal pool entry is created as a 32-bit value. The operand
14694
     modifier @got and @plt may be used in the original expression. The
14695
     term `x@got:lit4' will put the got offset for the global symbol x
14696
     to the literal pool as a 32-bit value. The term `x@plt:lit4' will
14697
     put the plt offset for the global symbol x to the literal pool as
14698
     a 32-bit value.
14699
 
14700
`:lit8'
14701
     The literal pool entry is created as a 64-bit value. The operand
14702
     modifier @got and @plt may be used in the original expression. The
14703
     term `x@got:lit8' will put the got offset for the global symbol x
14704
     to the literal pool as a 64-bit value. The term `x@plt:lit8' will
14705
     put the plt offset for the global symbol x to the literal pool as
14706
     a 64-bit value.
14707
 
14708
   The assembler directive `.ltorg' is used to emit all literal pool
14709
entries to the current position.
14710
 
14711

14712
File: as.info,  Node: s390 Directives,  Next: s390 Floating Point,  Prev: s390 Syntax,  Up: S/390-Dependent
14713
 
14714
9.30.4 Assembler Directives
14715
---------------------------
14716
 
14717
`as' for s390 supports all of the standard ELF assembler directives as
14718
outlined in the main part of this document.  Some directives have been
14719
extended and there are some additional directives, which are only
14720
available for the s390 `as'.
14721
 
14722
`.insn'
14723
     This directive permits the numeric representation of an
14724
     instructions and makes the assembler insert the operands according
14725
     to one of the instructions formats for `.insn' (*Note s390
14726
     Formats::).  For example, the instruction `l %r1,24(%r15)' could
14727
     be written as `.insn rx,0x58000000,%r1,24(%r15)'.
14728
 
14729
`.short'
14730
`.long'
14731
`.quad'
14732
     This directive places one or more 16-bit (.short), 32-bit (.long),
14733
     or 64-bit (.quad) values into the current section. If an ELF or
14734
     TLS modifier is used only the following expressions are allowed:
14735
     `symbol@modifier + constant', `symbol@modifier + label +
14736
     constant', and `symbol@modifier - label + constant'.  The
14737
     following modifiers are available:
14738
    `@got'
14739
    `@got12'
14740
          The @got modifier can be used for .short, .long and .quad.
14741
          The @got12 modifier is synonym to @got. The symbol is added
14742
          to the GOT. The symbol term is replaced with offset from the
14743
          start of the GOT to the GOT slot for the symbol.
14744
 
14745
    `@gotoff'
14746
          The @gotoff modifier can be used for .short, .long and .quad.
14747
          The symbol term is replaced with the offset from the start of
14748
          the GOT to the address of the symbol.
14749
 
14750
    `@gotplt'
14751
          The @gotplt modifier can be used for .long and .quad. A
14752
          procedure linkage table entry is generated for the symbol and
14753
          a jump slot for the symbol is added to the GOT. The symbol
14754
          term is replaced with the offset from the start of the GOT to
14755
          the jump slot for the symbol.
14756
 
14757
    `@plt'
14758
          The @plt modifier can be used for .long and .quad. A
14759
          procedure linkage table entry us generated for the symbol.
14760
          The symbol term is replaced with the address of the PLT entry
14761
          for the symbol.
14762
 
14763
    `@pltoff'
14764
          The @pltoff modifier can be used for .short, .long and .quad.
14765
          The symbol term is replaced with the offset from the start of
14766
          the PLT to the address of the symbol.
14767
 
14768
    `@tlsgd'
14769
    `@tlsldm'
14770
          The @tlsgd and @tlsldm modifier can be used for .long and
14771
          .quad. A tls_index structure for the symbol is added to the
14772
          GOT. The symbol term is replaced with the offset from the
14773
          start of the GOT to the tls_index structure.
14774
 
14775
    `@gotntpoff'
14776
    `@indntpoff'
14777
          The @gotntpoff and @indntpoff modifier can be used for .long
14778
          and .quad.  The symbol is added to the static TLS block and
14779
          the negated offset to the symbol in the static TLS block is
14780
          added to the GOT. For @gotntpoff the symbol term is replaced
14781
          with the offset from the start of the GOT to the GOT slot,
14782
          for @indntpoff the symbol term is replaced with the address
14783
          of the GOT slot.
14784
 
14785
    `@dtpoff'
14786
          The @dtpoff modifier can be used for .long and .quad. The
14787
          symbol term is replaced with the offset of the symbol
14788
          relative to the start of the TLS block it is contained in.
14789
 
14790
    `@ntpoff'
14791
          The @ntpoff modifier can be used for .long and .quad. The
14792
          symbol term is replaced with the offset of the symbol
14793
          relative to the TCB pointer.
14794
 
14795
     For more information about the thread local storage modifiers see
14796
     the ELF extension documentation `ELF Handling For Thread-Local
14797
     Storage'.
14798
 
14799
`.ltorg'
14800
     This directive causes the current contents of the literal pool to
14801
     be dumped to the current location (*Note s390 Literal Pool
14802
     Entries::).
14803
 
14804

14805
File: as.info,  Node: s390 Floating Point,  Prev: s390 Directives,  Up: S/390-Dependent
14806
 
14807
9.30.5 Floating Point
14808
---------------------
14809
 
14810
The assembler recognizes both the IEEE floating-point instruction and
14811
the hexadecimal floating-point instructions. The floating-point
14812
constructors `.float', `.single', and `.double' always emit the IEEE
14813
format. To assemble hexadecimal floating-point constants the `.long'
14814
and `.quad' directives must be used.
14815
 
14816

14817
File: as.info,  Node: SCORE-Dependent,  Next: Sparc-Dependent,  Prev: S/390-Dependent,  Up: Machine Dependencies
14818
 
14819
9.31 SCORE Dependent Features
14820
=============================
14821
 
14822
* Menu:
14823
 
14824
* SCORE-Opts::          Assembler options
14825
* SCORE-Pseudo::        SCORE Assembler Directives
14826
 
14827

14828
File: as.info,  Node: SCORE-Opts,  Next: SCORE-Pseudo,  Up: SCORE-Dependent
14829
 
14830
9.31.1 Options
14831
--------------
14832
 
14833
The following table lists all available SCORE options.
14834
 
14835
`-G NUM'
14836
     This option sets the largest size of an object that can be
14837
     referenced implicitly with the `gp' register. The default value is
14838
     8.
14839
 
14840
`-EB'
14841
     Assemble code for a big-endian cpu
14842
 
14843
`-EL'
14844
     Assemble code for a little-endian cpu
14845
 
14846
`-FIXDD'
14847
     Assemble code for fix data dependency
14848
 
14849
`-NWARN'
14850
     Assemble code for no warning message for fix data dependency
14851
 
14852
`-SCORE5'
14853
     Assemble code for target is SCORE5
14854
 
14855
`-SCORE5U'
14856
     Assemble code for target is SCORE5U
14857
 
14858
`-SCORE7'
14859
     Assemble code for target is SCORE7, this is default setting
14860
 
14861
`-SCORE3'
14862
     Assemble code for target is SCORE3
14863
 
14864
`-march=score7'
14865
     Assemble code for target is SCORE7, this is default setting
14866
 
14867
`-march=score3'
14868
     Assemble code for target is SCORE3
14869
 
14870
`-USE_R1'
14871
     Assemble code for no warning message when using temp register r1
14872
 
14873
`-KPIC'
14874
     Generate code for PIC.  This option tells the assembler to generate
14875
     score position-independent macro expansions.  It also tells the
14876
     assembler to mark the output file as PIC.
14877
 
14878
`-O0'
14879
     Assembler will not perform any optimizations
14880
 
14881
`-V'
14882
     Sunplus release version
14883
 
14884
 
14885

14886
File: as.info,  Node: SCORE-Pseudo,  Prev: SCORE-Opts,  Up: SCORE-Dependent
14887
 
14888
9.31.2 SCORE Assembler Directives
14889
---------------------------------
14890
 
14891
A number of assembler directives are available for SCORE.  The
14892
following table is far from complete.
14893
 
14894
`.set nwarn'
14895
     Let the assembler not to generate warnings if the source machine
14896
     language instructions happen data dependency.
14897
 
14898
`.set fixdd'
14899
     Let the assembler to insert bubbles (32 bit nop instruction / 16
14900
     bit nop! Instruction) if the source machine language instructions
14901
     happen data dependency.
14902
 
14903
`.set nofixdd'
14904
     Let the assembler to generate warnings if the source machine
14905
     language instructions happen data dependency. (Default)
14906
 
14907
`.set r1'
14908
     Let the assembler not to generate warnings if the source program
14909
     uses r1. allow user to use r1
14910
 
14911
`set nor1'
14912
     Let the assembler to generate warnings if the source program uses
14913
     r1. (Default)
14914
 
14915
`.sdata'
14916
     Tell the assembler to add subsequent data into the sdata section
14917
 
14918
`.rdata'
14919
     Tell the assembler to add subsequent data into the rdata section
14920
 
14921
`.frame "frame-register", "offset", "return-pc-register"'
14922
     Describe a stack frame. "frame-register" is the frame register,
14923
     "offset" is the distance from the frame register to the virtual
14924
     frame pointer, "return-pc-register" is the return program register.
14925
     You must use ".ent" before ".frame" and only one ".frame" can be
14926
     used per ".ent".
14927
 
14928
`.mask "bitmask", "frameoffset"'
14929
     Indicate which of the integer registers are saved in the current
14930
     function's stack frame, this is for the debugger to explain the
14931
     frame chain.
14932
 
14933
`.ent "proc-name"'
14934
     Set the beginning of the procedure "proc_name". Use this directive
14935
     when you want to generate information for the debugger.
14936
 
14937
`.end proc-name'
14938
     Set the end of a procedure. Use this directive to generate
14939
     information for the debugger.
14940
 
14941
`.bss'
14942
     Switch the destination of following statements into the bss
14943
     section, which is used for data that is uninitialized anywhere.
14944
 
14945
 
14946

14947
File: as.info,  Node: SH-Dependent,  Next: SH64-Dependent,  Prev: MSP430-Dependent,  Up: Machine Dependencies
14948
 
14949
9.32 Renesas / SuperH SH Dependent Features
14950
===========================================
14951
 
14952
* Menu:
14953
 
14954
* SH Options::              Options
14955
* SH Syntax::               Syntax
14956
* SH Floating Point::       Floating Point
14957
* SH Directives::           SH Machine Directives
14958
* SH Opcodes::              Opcodes
14959
 
14960

14961
File: as.info,  Node: SH Options,  Next: SH Syntax,  Up: SH-Dependent
14962
 
14963
9.32.1 Options
14964
--------------
14965
 
14966
`as' has following command-line options for the Renesas (formerly
14967
Hitachi) / SuperH SH family.
14968
 
14969
`--little'
14970
     Generate little endian code.
14971
 
14972
`--big'
14973
     Generate big endian code.
14974
 
14975
`--relax'
14976
     Alter jump instructions for long displacements.
14977
 
14978
`--small'
14979
     Align sections to 4 byte boundaries, not 16.
14980
 
14981
`--dsp'
14982
     Enable sh-dsp insns, and disable sh3e / sh4 insns.
14983
 
14984
`--renesas'
14985
     Disable optimization with section symbol for compatibility with
14986
     Renesas assembler.
14987
 
14988
`--allow-reg-prefix'
14989
     Allow '$' as a register name prefix.
14990
 
14991
`--isa=sh4 | sh4a'
14992
     Specify the sh4 or sh4a instruction set.
14993
 
14994
`--isa=dsp'
14995
     Enable sh-dsp insns, and disable sh3e / sh4 insns.
14996
 
14997
`--isa=fp'
14998
     Enable sh2e, sh3e, sh4, and sh4a insn sets.
14999
 
15000
`--isa=all'
15001
     Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
15002
 
15003
`-h-tick-hex'
15004
     Support H'00 style hex constants in addition to 0x00 style.
15005
 
15006
 
15007

15008
File: as.info,  Node: SH Syntax,  Next: SH Floating Point,  Prev: SH Options,  Up: SH-Dependent
15009
 
15010
9.32.2 Syntax
15011
-------------
15012
 
15013
* Menu:
15014
 
15015
* SH-Chars::                Special Characters
15016
* SH-Regs::                 Register Names
15017
* SH-Addressing::           Addressing Modes
15018
 
15019

15020
File: as.info,  Node: SH-Chars,  Next: SH-Regs,  Up: SH Syntax
15021
 
15022
9.32.2.1 Special Characters
15023
...........................
15024
 
15025
`!' is the line comment character.
15026
 
15027
   You can use `;' instead of a newline to separate statements.
15028
 
15029
   Since `$' has no special meaning, you may use it in symbol names.
15030
 
15031

15032
File: as.info,  Node: SH-Regs,  Next: SH-Addressing,  Prev: SH-Chars,  Up: SH Syntax
15033
 
15034
9.32.2.2 Register Names
15035
.......................
15036
 
15037
You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', `r5',
15038
`r6', `r7', `r8', `r9', `r10', `r11', `r12', `r13', `r14', and `r15' to
15039
refer to the SH registers.
15040
 
15041
   The SH also has these control registers:
15042
 
15043
`pr'
15044
     procedure register (holds return address)
15045
 
15046
`pc'
15047
     program counter
15048
 
15049
`mach'
15050
`macl'
15051
     high and low multiply accumulator registers
15052
 
15053
`sr'
15054
     status register
15055
 
15056
`gbr'
15057
     global base register
15058
 
15059
`vbr'
15060
     vector base register (for interrupt vectors)
15061
 
15062

15063
File: as.info,  Node: SH-Addressing,  Prev: SH-Regs,  Up: SH Syntax
15064
 
15065
9.32.2.3 Addressing Modes
15066
.........................
15067
 
15068
`as' understands the following addressing modes for the SH.  `RN' in
15069
the following refers to any of the numbered registers, but _not_ the
15070
control registers.
15071
 
15072
`RN'
15073
     Register direct
15074
 
15075
`@RN'
15076
     Register indirect
15077
 
15078
`@-RN'
15079
     Register indirect with pre-decrement
15080
 
15081
`@RN+'
15082
     Register indirect with post-increment
15083
 
15084
`@(DISP, RN)'
15085
     Register indirect with displacement
15086
 
15087
`@(R0, RN)'
15088
     Register indexed
15089
 
15090
`@(DISP, GBR)'
15091
     `GBR' offset
15092
 
15093
`@(R0, GBR)'
15094
     GBR indexed
15095
 
15096
`ADDR'
15097
`@(DISP, PC)'
15098
     PC relative address (for branch or for addressing memory).  The
15099
     `as' implementation allows you to use the simpler form ADDR
15100
     anywhere a PC relative address is called for; the alternate form
15101
     is supported for compatibility with other assemblers.
15102
 
15103
`#IMM'
15104
     Immediate data
15105
 
15106

15107
File: as.info,  Node: SH Floating Point,  Next: SH Directives,  Prev: SH Syntax,  Up: SH-Dependent
15108
 
15109
9.32.3 Floating Point
15110
---------------------
15111
 
15112
SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
15113
SH groups can use `.float' directive to generate IEEE floating-point
15114
numbers.
15115
 
15116
   SH2E and SH3E support single-precision floating point calculations as
15117
well as entirely PCAPI compatible emulation of double-precision
15118
floating point calculations. SH2E and SH3E instructions are a subset of
15119
the floating point calculations conforming to the IEEE754 standard.
15120
 
15121
   In addition to single-precision and double-precision floating-point
15122
operation capability, the on-chip FPU of SH4 has a 128-bit graphic
15123
engine that enables 32-bit floating-point data to be processed 128 bits
15124
at a time. It also supports 4 * 4 array operations and inner product
15125
operations. Also, a superscalar architecture is employed that enables
15126
simultaneous execution of two instructions (including FPU
15127
instructions), providing performance of up to twice that of
15128
conventional architectures at the same frequency.
15129
 
15130

15131
File: as.info,  Node: SH Directives,  Next: SH Opcodes,  Prev: SH Floating Point,  Up: SH-Dependent
15132
 
15133
9.32.4 SH Machine Directives
15134
----------------------------
15135
 
15136
`uaword'
15137
`ualong'
15138
     `as' will issue a warning when a misaligned `.word' or `.long'
15139
     directive is used.  You may use `.uaword' or `.ualong' to indicate
15140
     that the value is intentionally misaligned.
15141
 
15142

15143
File: as.info,  Node: SH Opcodes,  Prev: SH Directives,  Up: SH-Dependent
15144
 
15145
9.32.5 Opcodes
15146
--------------
15147
 
15148
For detailed information on the SH machine instruction set, see
15149
`SH-Microcomputer User's Manual' (Renesas) or `SH-4 32-bit CPU Core
15150
Architecture' (SuperH) and `SuperH (SH) 64-Bit RISC Series' (SuperH).
15151
 
15152
   `as' implements all the standard SH opcodes.  No additional
15153
pseudo-instructions are needed on this family.  Note, however, that
15154
because `as' supports a simpler form of PC-relative addressing, you may
15155
simply write (for example)
15156
 
15157
     mov.l  bar,r0
15158
 
15159
where other assemblers might require an explicit displacement to `bar'
15160
from the program counter:
15161
 
15162
     mov.l  @(DISP, PC)
15163
 
15164
   Here is a summary of SH opcodes:
15165
 
15166
     Legend:
15167
     Rn        a numbered register
15168
     Rm        another numbered register
15169
     #imm      immediate data
15170
     disp      displacement
15171
     disp8     8-bit displacement
15172
     disp12    12-bit displacement
15173
 
15174
     add #imm,Rn                    lds.l @Rn+,PR
15175
     add Rm,Rn                      mac.w @Rm+,@Rn+
15176
     addc Rm,Rn                     mov #imm,Rn
15177
     addv Rm,Rn                     mov Rm,Rn
15178
     and #imm,R0                    mov.b Rm,@(R0,Rn)
15179
     and Rm,Rn                      mov.b Rm,@-Rn
15180
     and.b #imm,@(R0,GBR)           mov.b Rm,@Rn
15181
     bf disp8                       mov.b @(disp,Rm),R0
15182
     bra disp12                     mov.b @(disp,GBR),R0
15183
     bsr disp12                     mov.b @(R0,Rm),Rn
15184
     bt disp8                       mov.b @Rm+,Rn
15185
     clrmac                         mov.b @Rm,Rn
15186
     clrt                           mov.b R0,@(disp,Rm)
15187
     cmp/eq #imm,R0                 mov.b R0,@(disp,GBR)
15188
     cmp/eq Rm,Rn                   mov.l Rm,@(disp,Rn)
15189
     cmp/ge Rm,Rn                   mov.l Rm,@(R0,Rn)
15190
     cmp/gt Rm,Rn                   mov.l Rm,@-Rn
15191
     cmp/hi Rm,Rn                   mov.l Rm,@Rn
15192
     cmp/hs Rm,Rn                   mov.l @(disp,Rn),Rm
15193
     cmp/pl Rn                      mov.l @(disp,GBR),R0
15194
     cmp/pz Rn                      mov.l @(disp,PC),Rn
15195
     cmp/str Rm,Rn                  mov.l @(R0,Rm),Rn
15196
     div0s Rm,Rn                    mov.l @Rm+,Rn
15197
     div0u                          mov.l @Rm,Rn
15198
     div1 Rm,Rn                     mov.l R0,@(disp,GBR)
15199
     exts.b Rm,Rn                   mov.w Rm,@(R0,Rn)
15200
     exts.w Rm,Rn                   mov.w Rm,@-Rn
15201
     extu.b Rm,Rn                   mov.w Rm,@Rn
15202
     extu.w Rm,Rn                   mov.w @(disp,Rm),R0
15203
     jmp @Rn                        mov.w @(disp,GBR),R0
15204
     jsr @Rn                        mov.w @(disp,PC),Rn
15205
     ldc Rn,GBR                     mov.w @(R0,Rm),Rn
15206
     ldc Rn,SR                      mov.w @Rm+,Rn
15207
     ldc Rn,VBR                     mov.w @Rm,Rn
15208
     ldc.l @Rn+,GBR                 mov.w R0,@(disp,Rm)
15209
     ldc.l @Rn+,SR                  mov.w R0,@(disp,GBR)
15210
     ldc.l @Rn+,VBR                 mova @(disp,PC),R0
15211
     lds Rn,MACH                    movt Rn
15212
     lds Rn,MACL                    muls Rm,Rn
15213
     lds Rn,PR                      mulu Rm,Rn
15214
     lds.l @Rn+,MACH                neg Rm,Rn
15215
     lds.l @Rn+,MACL                negc Rm,Rn
15216
 
15217
     nop                            stc VBR,Rn
15218
     not Rm,Rn                      stc.l GBR,@-Rn
15219
     or #imm,R0                     stc.l SR,@-Rn
15220
     or Rm,Rn                       stc.l VBR,@-Rn
15221
     or.b #imm,@(R0,GBR)            sts MACH,Rn
15222
     rotcl Rn                       sts MACL,Rn
15223
     rotcr Rn                       sts PR,Rn
15224
     rotl Rn                        sts.l MACH,@-Rn
15225
     rotr Rn                        sts.l MACL,@-Rn
15226
     rte                            sts.l PR,@-Rn
15227
     rts                            sub Rm,Rn
15228
     sett                           subc Rm,Rn
15229
     shal Rn                        subv Rm,Rn
15230
     shar Rn                        swap.b Rm,Rn
15231
     shll Rn                        swap.w Rm,Rn
15232
     shll16 Rn                      tas.b @Rn
15233
     shll2 Rn                       trapa #imm
15234
     shll8 Rn                       tst #imm,R0
15235
     shlr Rn                        tst Rm,Rn
15236
     shlr16 Rn                      tst.b #imm,@(R0,GBR)
15237
     shlr2 Rn                       xor #imm,R0
15238
     shlr8 Rn                       xor Rm,Rn
15239
     sleep                          xor.b #imm,@(R0,GBR)
15240
     stc GBR,Rn                     xtrct Rm,Rn
15241
     stc SR,Rn
15242
 
15243

15244
File: as.info,  Node: SH64-Dependent,  Next: PDP-11-Dependent,  Prev: SH-Dependent,  Up: Machine Dependencies
15245
 
15246
9.33 SuperH SH64 Dependent Features
15247
===================================
15248
 
15249
* Menu:
15250
 
15251
* SH64 Options::              Options
15252
* SH64 Syntax::               Syntax
15253
* SH64 Directives::           SH64 Machine Directives
15254
* SH64 Opcodes::              Opcodes
15255
 
15256

15257
File: as.info,  Node: SH64 Options,  Next: SH64 Syntax,  Up: SH64-Dependent
15258
 
15259
9.33.1 Options
15260
--------------
15261
 
15262
`-isa=sh4 | sh4a'
15263
     Specify the sh4 or sh4a instruction set.
15264
 
15265
`-isa=dsp'
15266
     Enable sh-dsp insns, and disable sh3e / sh4 insns.
15267
 
15268
`-isa=fp'
15269
     Enable sh2e, sh3e, sh4, and sh4a insn sets.
15270
 
15271
`-isa=all'
15272
     Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
15273
 
15274
`-isa=shmedia | -isa=shcompact'
15275
     Specify the default instruction set.  `SHmedia' specifies the
15276
     32-bit opcodes, and `SHcompact' specifies the 16-bit opcodes
15277
     compatible with previous SH families.  The default depends on the
15278
     ABI selected; the default for the 64-bit ABI is SHmedia, and the
15279
     default for the 32-bit ABI is SHcompact.  If neither the ABI nor
15280
     the ISA is specified, the default is 32-bit SHcompact.
15281
 
15282
     Note that the `.mode' pseudo-op is not permitted if the ISA is not
15283
     specified on the command line.
15284
 
15285
`-abi=32 | -abi=64'
15286
     Specify the default ABI.  If the ISA is specified and the ABI is
15287
     not, the default ABI depends on the ISA, with SHmedia defaulting
15288
     to 64-bit and SHcompact defaulting to 32-bit.
15289
 
15290
     Note that the `.abi' pseudo-op is not permitted if the ABI is not
15291
     specified on the command line.  When the ABI is specified on the
15292
     command line, any `.abi' pseudo-ops in the source must match it.
15293
 
15294
`-shcompact-const-crange'
15295
     Emit code-range descriptors for constants in SHcompact code
15296
     sections.
15297
 
15298
`-no-mix'
15299
     Disallow SHmedia code in the same section as constants and
15300
     SHcompact code.
15301
 
15302
`-no-expand'
15303
     Do not expand MOVI, PT, PTA or PTB instructions.
15304
 
15305
`-expand-pt32'
15306
     With -abi=64, expand PT, PTA and PTB instructions to 32 bits only.
15307
 
15308
`-h-tick-hex'
15309
     Support H'00 style hex constants in addition to 0x00 style.
15310
 
15311
 
15312

15313
File: as.info,  Node: SH64 Syntax,  Next: SH64 Directives,  Prev: SH64 Options,  Up: SH64-Dependent
15314
 
15315
9.33.2 Syntax
15316
-------------
15317
 
15318
* Menu:
15319
 
15320
* SH64-Chars::                Special Characters
15321
* SH64-Regs::                 Register Names
15322
* SH64-Addressing::           Addressing Modes
15323
 
15324

15325
File: as.info,  Node: SH64-Chars,  Next: SH64-Regs,  Up: SH64 Syntax
15326
 
15327
9.33.2.1 Special Characters
15328
...........................
15329
 
15330
`!' is the line comment character.
15331
 
15332
   You can use `;' instead of a newline to separate statements.
15333
 
15334
   Since `$' has no special meaning, you may use it in symbol names.
15335
 
15336

15337
File: as.info,  Node: SH64-Regs,  Next: SH64-Addressing,  Prev: SH64-Chars,  Up: SH64 Syntax
15338
 
15339
9.33.2.2 Register Names
15340
.......................
15341
 
15342
You can use the predefined symbols `r0' through `r63' to refer to the
15343
SH64 general registers, `cr0' through `cr63' for control registers,
15344
`tr0' through `tr7' for target address registers, `fr0' through `fr63'
15345
for single-precision floating point registers, `dr0' through `dr62'
15346
(even numbered registers only) for double-precision floating point
15347
registers, `fv0' through `fv60' (multiples of four only) for
15348
single-precision floating point vectors, `fp0' through `fp62' (even
15349
numbered registers only) for single-precision floating point pairs,
15350
`mtrx0' through `mtrx48' (multiples of 16 only) for 4x4 matrices of
15351
single-precision floating point registers, `pc' for the program
15352
counter, and `fpscr' for the floating point status and control register.
15353
 
15354
   You can also refer to the control registers by the mnemonics `sr',
15355
`ssr', `pssr', `intevt', `expevt', `pexpevt', `tra', `spc', `pspc',
15356
`resvec', `vbr', `tea', `dcr', `kcr0', `kcr1', `ctc', and `usr'.
15357
 
15358

15359
File: as.info,  Node: SH64-Addressing,  Prev: SH64-Regs,  Up: SH64 Syntax
15360
 
15361
9.33.2.3 Addressing Modes
15362
.........................
15363
 
15364
SH64 operands consist of either a register or immediate value.  The
15365
immediate value can be a constant or label reference (or portion of a
15366
label reference), as in this example:
15367
 
15368
        movi    4,r2
15369
        pt      function, tr4
15370
        movi    (function >> 16) & 65535,r0
15371
        shori   function & 65535, r0
15372
        ld.l    r0,4,r0
15373
 
15374
   Instruction label references can reference labels in either SHmedia
15375
or SHcompact.  To differentiate between the two, labels in SHmedia
15376
sections will always have the least significant bit set (i.e. they will
15377
be odd), which SHcompact labels will have the least significant bit
15378
reset (i.e. they will be even).  If you need to reference the actual
15379
address of a label, you can use the `datalabel' modifier, as in this
15380
example:
15381
 
15382
        .long   function
15383
        .long   datalabel function
15384
 
15385
   In that example, the first longword may or may not have the least
15386
significant bit set depending on whether the label is an SHmedia label
15387
or an SHcompact label.  The second longword will be the actual address
15388
of the label, regardless of what type of label it is.
15389
 
15390

15391
File: as.info,  Node: SH64 Directives,  Next: SH64 Opcodes,  Prev: SH64 Syntax,  Up: SH64-Dependent
15392
 
15393
9.33.3 SH64 Machine Directives
15394
------------------------------
15395
 
15396
In addition to the SH directives, the SH64 provides the following
15397
directives:
15398
 
15399
`.mode [shmedia|shcompact]'
15400
`.isa [shmedia|shcompact]'
15401
     Specify the ISA for the following instructions (the two directives
15402
     are equivalent).  Note that programs such as `objdump' rely on
15403
     symbolic labels to determine when such mode switches occur (by
15404
     checking the least significant bit of the label's address), so
15405
     such mode/isa changes should always be followed by a label (in
15406
     practice, this is true anyway).  Note that you cannot use these
15407
     directives if you didn't specify an ISA on the command line.
15408
 
15409
`.abi [32|64]'
15410
     Specify the ABI for the following instructions.  Note that you
15411
     cannot use this directive unless you specified an ABI on the
15412
     command line, and the ABIs specified must match.
15413
 
15414
`.uaquad'
15415
     Like .uaword and .ualong, this allows you to specify an
15416
     intentionally unaligned quadword (64 bit word).
15417
 
15418
 
15419

15420
File: as.info,  Node: SH64 Opcodes,  Prev: SH64 Directives,  Up: SH64-Dependent
15421
 
15422
9.33.4 Opcodes
15423
--------------
15424
 
15425
For detailed information on the SH64 machine instruction set, see
15426
`SuperH 64 bit RISC Series Architecture Manual' (SuperH, Inc.).
15427
 
15428
   `as' implements all the standard SH64 opcodes.  In addition, the
15429
following pseudo-opcodes may be expanded into one or more alternate
15430
opcodes:
15431
 
15432
`movi'
15433
     If the value doesn't fit into a standard `movi' opcode, `as' will
15434
     replace the `movi' with a sequence of `movi' and `shori' opcodes.
15435
 
15436
`pt'
15437
     This expands to a sequence of `movi' and `shori' opcode, followed
15438
     by a `ptrel' opcode, or to a `pta' or `ptb' opcode, depending on
15439
     the label referenced.
15440
 
15441
 
15442

15443
File: as.info,  Node: Sparc-Dependent,  Next: TIC54X-Dependent,  Prev: SCORE-Dependent,  Up: Machine Dependencies
15444
 
15445
9.34 SPARC Dependent Features
15446
=============================
15447
 
15448
* Menu:
15449
 
15450
* Sparc-Opts::                  Options
15451
* Sparc-Aligned-Data::          Option to enforce aligned data
15452
* Sparc-Syntax::                Syntax
15453
* Sparc-Float::                 Floating Point
15454
* Sparc-Directives::            Sparc Machine Directives
15455
 
15456

15457
File: as.info,  Node: Sparc-Opts,  Next: Sparc-Aligned-Data,  Up: Sparc-Dependent
15458
 
15459
9.34.1 Options
15460
--------------
15461
 
15462
The SPARC chip family includes several successive versions, using the
15463
same core instruction set, but including a few additional instructions
15464
at each version.  There are exceptions to this however.  For details on
15465
what instructions each variant supports, please see the chip's
15466
architecture reference manual.
15467
 
15468
   By default, `as' assumes the core instruction set (SPARC v6), but
15469
"bumps" the architecture level as needed: it switches to successively
15470
higher architectures as it encounters instructions that only exist in
15471
the higher levels.
15472
 
15473
   If not configured for SPARC v9 (`sparc64-*-*') GAS will not bump
15474
past sparclite by default, an option must be passed to enable the v9
15475
instructions.
15476
 
15477
   GAS treats sparclite as being compatible with v8, unless an
15478
architecture is explicitly requested.  SPARC v9 is always incompatible
15479
with sparclite.
15480
 
15481
`-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite'
15482
`-Av8plus | -Av8plusa | -Av9 | -Av9a'
15483
     Use one of the `-A' options to select one of the SPARC
15484
     architectures explicitly.  If you select an architecture
15485
     explicitly, `as' reports a fatal error if it encounters an
15486
     instruction or feature requiring an incompatible or higher level.
15487
 
15488
     `-Av8plus' and `-Av8plusa' select a 32 bit environment.
15489
 
15490
     `-Av9' and `-Av9a' select a 64 bit environment and are not
15491
     available unless GAS is explicitly configured with 64 bit
15492
     environment support.
15493
 
15494
     `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with
15495
     UltraSPARC extensions.
15496
 
15497
`-xarch=v8plus | -xarch=v8plusa'
15498
     For compatibility with the SunOS v9 assembler.  These options are
15499
     equivalent to -Av8plus and -Av8plusa, respectively.
15500
 
15501
`-bump'
15502
     Warn whenever it is necessary to switch to another level.  If an
15503
     architecture level is explicitly requested, GAS will not issue
15504
     warnings until that level is reached, and will then bump the level
15505
     as required (except between incompatible levels).
15506
 
15507
`-32 | -64'
15508
     Select the word size, either 32 bits or 64 bits.  These options
15509
     are only available with the ELF object file format, and require
15510
     that the necessary BFD support has been included.
15511
 
15512

15513
File: as.info,  Node: Sparc-Aligned-Data,  Next: Sparc-Syntax,  Prev: Sparc-Opts,  Up: Sparc-Dependent
15514
 
15515
9.34.2 Enforcing aligned data
15516
-----------------------------
15517
 
15518
SPARC GAS normally permits data to be misaligned.  For example, it
15519
permits the `.long' pseudo-op to be used on a byte boundary.  However,
15520
the native SunOS assemblers issue an error when they see misaligned
15521
data.
15522
 
15523
   You can use the `--enforce-aligned-data' option to make SPARC GAS
15524
also issue an error about misaligned data, just as the SunOS assemblers
15525
do.
15526
 
15527
   The `--enforce-aligned-data' option is not the default because gcc
15528
issues misaligned data pseudo-ops when it initializes certain packed
15529
data structures (structures defined using the `packed' attribute).  You
15530
may have to assemble with GAS in order to initialize packed data
15531
structures in your own code.
15532
 
15533

15534
File: as.info,  Node: Sparc-Syntax,  Next: Sparc-Float,  Prev: Sparc-Aligned-Data,  Up: Sparc-Dependent
15535
 
15536
9.34.3 Sparc Syntax
15537
-------------------
15538
 
15539
The assembler syntax closely follows The Sparc Architecture Manual,
15540
versions 8 and 9, as well as most extensions defined by Sun for their
15541
UltraSPARC and Niagara line of processors.
15542
 
15543
* Menu:
15544
 
15545
* Sparc-Chars::                Special Characters
15546
* Sparc-Regs::                 Register Names
15547
* Sparc-Constants::            Constant Names
15548
* Sparc-Relocs::               Relocations
15549
* Sparc-Size-Translations::    Size Translations
15550
 
15551

15552
File: as.info,  Node: Sparc-Chars,  Next: Sparc-Regs,  Up: Sparc-Syntax
15553
 
15554
9.34.3.1 Special Characters
15555
...........................
15556
 
15557
`#' is the line comment character.
15558
 
15559
   `;' can be used instead of a newline to separate statements.
15560
 
15561

15562
File: as.info,  Node: Sparc-Regs,  Next: Sparc-Constants,  Prev: Sparc-Chars,  Up: Sparc-Syntax
15563
 
15564
9.34.3.2 Register Names
15565
.......................
15566
 
15567
The Sparc integer register file is broken down into global, outgoing,
15568
local, and incoming.
15569
 
15570
   * The 8 global registers are referred to as `%gN'.
15571
 
15572
   * The 8 outgoing registers are referred to as `%oN'.
15573
 
15574
   * The 8 local registers are referred to as `%lN'.
15575
 
15576
   * The 8 incoming registers are referred to as `%iN'.
15577
 
15578
   * The frame pointer register `%i6' can be referenced using the alias
15579
     `%fp'.
15580
 
15581
   * The stack pointer register `%o6' can be referenced using the alias
15582
     `%sp'.
15583
 
15584
   Floating point registers are simply referred to as `%fN'.  When
15585
assembling for pre-V9, only 32 floating point registers are available.
15586
For V9 and later there are 64, but there are restrictions when
15587
referencing the upper 32 registers.  They can only be accessed as
15588
double or quad, and thus only even or quad numbered accesses are
15589
allowed.  For example, `%f34' is a legal floating point register, but
15590
`%f35' is not.
15591
 
15592
   Certain V9 instructions allow access to ancillary state registers.
15593
Most simply they can be referred to as `%asrN' where N can be from 16
15594
to 31.  However, there are some aliases defined to reference ASR
15595
registers defined for various UltraSPARC processors:
15596
 
15597
   * The tick compare register is referred to as `%tick_cmpr'.
15598
 
15599
   * The system tick register is referred to as `%stick'.  An alias,
15600
     `%sys_tick', exists but is deprecated and should not be used by
15601
     new software.
15602
 
15603
   * The system tick compare register is referred to as `%stick_cmpr'.
15604
     An alias, `%sys_tick_cmpr', exists but is deprecated and should
15605
     not be used by new software.
15606
 
15607
   * The software interrupt register is referred to as `%softint'.
15608
 
15609
   * The set software interrupt register is referred to as
15610
     `%set_softint'.  The mnemonic `%softint_set' is provided as an
15611
     alias.
15612
 
15613
   * The clear software interrupt register is referred to as
15614
     `%clear_softint'.  The mnemonic `%softint_clear' is provided as an
15615
     alias.
15616
 
15617
   * The performance instrumentation counters register is referred to as
15618
     `%pic'.
15619
 
15620
   * The performance control register is referred to as `%pcr'.
15621
 
15622
   * The graphics status register is referred to as `%gsr'.
15623
 
15624
   * The V9 dispatch control register is referred to as `%dcr'.
15625
 
15626
   Various V9 branch and conditional move instructions allow
15627
specification of which set of integer condition codes to test.  These
15628
are referred to as `%xcc' and `%icc'.
15629
 
15630
   In V9, there are 4 sets of floating point condition codes which are
15631
referred to as `%fccN'.
15632
 
15633
   Several special privileged and non-privileged registers exist:
15634
 
15635
   * The V9 address space identifier register is referred to as `%asi'.
15636
 
15637
   * The V9 restorable windows register is referred to as `%canrestore'.
15638
 
15639
   * The V9 savable windows register is referred to as `%cansave'.
15640
 
15641
   * The V9 clean windows register is referred to as `%cleanwin'.
15642
 
15643
   * The V9 current window pointer register is referred to as `%cwp'.
15644
 
15645
   * The floating-point queue register is referred to as `%fq'.
15646
 
15647
   * The V8 co-processor queue register is referred to as `%cq'.
15648
 
15649
   * The floating point status register is referred to as `%fsr'.
15650
 
15651
   * The other windows register is referred to as `%otherwin'.
15652
 
15653
   * The V9 program counter register is referred to as `%pc'.
15654
 
15655
   * The V9 next program counter register is referred to as `%npc'.
15656
 
15657
   * The V9 processor interrupt level register is referred to as `%pil'.
15658
 
15659
   * The V9 processor state register is referred to as `%pstate'.
15660
 
15661
   * The trap base address register is referred to as `%tba'.
15662
 
15663
   * The V9 tick register is referred to as `%tick'.
15664
 
15665
   * The V9 trap level is referred to as `%tl'.
15666
 
15667
   * The V9 trap program counter is referred to as `%tpc'.
15668
 
15669
   * The V9 trap next program counter is referred to as `%tnpc'.
15670
 
15671
   * The V9 trap state is referred to as `%tstate'.
15672
 
15673
   * The V9 trap type is referred to as `%tt'.
15674
 
15675
   * The V9 condition codes is referred to as `%ccr'.
15676
 
15677
   * The V9 floating-point registers state is referred to as `%fprs'.
15678
 
15679
   * The V9 version register is referred to as `%ver'.
15680
 
15681
   * The V9 window state register is referred to as `%wstate'.
15682
 
15683
   * The Y register is referred to as `%y'.
15684
 
15685
   * The V8 window invalid mask register is referred to as `%wim'.
15686
 
15687
   * The V8 processor state register is referred to as `%psr'.
15688
 
15689
   * The V9 global register level register is referred to as `%gl'.
15690
 
15691
   Several special register names exist for hypervisor mode code:
15692
 
15693
   * The hyperprivileged processor state register is referred to as
15694
     `%hpstate'.
15695
 
15696
   * The hyperprivileged trap state register is referred to as
15697
     `%htstate'.
15698
 
15699
   * The hyperprivileged interrupt pending register is referred to as
15700
     `%hintp'.
15701
 
15702
   * The hyperprivileged trap base address register is referred to as
15703
     `%htba'.
15704
 
15705
   * The hyperprivileged implementation version register is referred to
15706
     as `%hver'.
15707
 
15708
   * The hyperprivileged system tick compare register is referred to as
15709
     `%hstick_cmpr'.  Note that there is no `%hstick' register, the
15710
     normal `%stick' is used.
15711
 
15712

15713
File: as.info,  Node: Sparc-Constants,  Next: Sparc-Relocs,  Prev: Sparc-Regs,  Up: Sparc-Syntax
15714
 
15715
9.34.3.3 Constants
15716
..................
15717
 
15718
Several Sparc instructions take an immediate operand field for which
15719
mnemonic names exist.  Two such examples are `membar' and `prefetch'.
15720
Another example are the set of V9 memory access instruction that allow
15721
specification of an address space identifier.
15722
 
15723
   The `membar' instruction specifies a memory barrier that is the
15724
defined by the operand which is a bitmask.  The supported mask
15725
mnemonics are:
15726
 
15727
   * `#Sync' requests that all operations (including nonmemory
15728
     reference operations) appearing prior to the `membar' must have
15729
     been performed and the effects of any exceptions become visible
15730
     before any instructions after the `membar' may be initiated.  This
15731
     corresponds to `membar' cmask field bit 2.
15732
 
15733
   * `#MemIssue' requests that all memory reference operations
15734
     appearing prior to the `membar' must have been performed before
15735
     any memory operation after the `membar' may be initiated.  This
15736
     corresponds to `membar' cmask field bit 1.
15737
 
15738
   * `#Lookaside' requests that a store appearing prior to the `membar'
15739
     must complete before any load following the `membar' referencing
15740
     the same address can be initiated.  This corresponds to `membar'
15741
     cmask field bit 0.
15742
 
15743
   * `#StoreStore' defines that the effects of all stores appearing
15744
     prior to the `membar' instruction must be visible to all
15745
     processors before the effect of any stores following the `membar'.
15746
     Equivalent to the deprecated `stbar' instruction.  This
15747
     corresponds to `membar' mmask field bit 3.
15748
 
15749
   * `#LoadStore' defines all loads appearing prior to the `membar'
15750
     instruction must have been performed before the effect of any
15751
     stores following the `membar' is visible to any other processor.
15752
     This corresponds to `membar' mmask field bit 2.
15753
 
15754
   * `#StoreLoad' defines that the effects of all stores appearing
15755
     prior to the `membar' instruction must be visible to all
15756
     processors before loads following the `membar' may be performed.
15757
     This corresponds to `membar' mmask field bit 1.
15758
 
15759
   * `#LoadLoad' defines that all loads appearing prior to the `membar'
15760
     instruction must have been performed before any loads following
15761
     the `membar' may be performed.  This corresponds to `membar' mmask
15762
     field bit 0.
15763
 
15764
 
15765
   These values can be ored together, for example:
15766
 
15767
     membar #Sync
15768
     membar #StoreLoad | #LoadLoad
15769
     membar #StoreLoad | #StoreStore
15770
 
15771
   The `prefetch' and `prefetcha' instructions take a prefetch function
15772
code.  The following prefetch function code constant mnemonics are
15773
available:
15774
 
15775
   * `#n_reads' requests a prefetch for several reads, and corresponds
15776
     to a prefetch function code of 0.
15777
 
15778
     `#one_read' requests a prefetch for one read, and corresponds to a
15779
     prefetch function code of 1.
15780
 
15781
     `#n_writes' requests a prefetch for several writes (and possibly
15782
     reads), and corresponds to a prefetch function code of 2.
15783
 
15784
     `#one_write' requests a prefetch for one write, and corresponds to
15785
     a prefetch function code of 3.
15786
 
15787
     `#page' requests a prefetch page, and corresponds to a prefetch
15788
     function code of 4.
15789
 
15790
     `#invalidate' requests a prefetch invalidate, and corresponds to a
15791
     prefetch function code of 16.
15792
 
15793
     `#unified' requests a prefetch to the nearest unified cache, and
15794
     corresponds to a prefetch function code of 17.
15795
 
15796
     `#n_reads_strong' requests a strong prefetch for several reads,
15797
     and corresponds to a prefetch function code of 20.
15798
 
15799
     `#one_read_strong' requests a strong prefetch for one read, and
15800
     corresponds to a prefetch function code of 21.
15801
 
15802
     `#n_writes_strong' requests a strong prefetch for several writes,
15803
     and corresponds to a prefetch function code of 22.
15804
 
15805
     `#one_write_strong' requests a strong prefetch for one write, and
15806
     corresponds to a prefetch function code of 23.
15807
 
15808
     Onle one prefetch code may be specified.  Here are some examples:
15809
 
15810
          prefetch  [%l0 + %l2], #one_read
15811
          prefetch  [%g2 + 8], #n_writes
15812
          prefetcha [%g1] 0x8, #unified
15813
          prefetcha [%o0 + 0x10] %asi, #n_reads
15814
 
15815
     The actual behavior of a given prefetch function code is processor
15816
     specific.  If a processor does not implement a given prefetch
15817
     function code, it will treat the prefetch instruction as a nop.
15818
 
15819
     For instructions that accept an immediate address space identifier,
15820
     `as' provides many mnemonics corresponding to V9 defined as well
15821
     as UltraSPARC and Niagara extended values.  For example, `#ASI_P'
15822
     and `#ASI_BLK_INIT_QUAD_LDD_AIUS'.  See the V9 and processor
15823
     specific manuals for details.
15824
 
15825
 
15826

15827
File: as.info,  Node: Sparc-Relocs,  Next: Sparc-Size-Translations,  Prev: Sparc-Constants,  Up: Sparc-Syntax
15828
 
15829
9.34.3.4 Relocations
15830
....................
15831
 
15832
ELF relocations are available as defined in the 32-bit and 64-bit Sparc
15833
ELF specifications.
15834
 
15835
   `R_SPARC_HI22' is obtained using `%hi' and `R_SPARC_LO10' is
15836
obtained using `%lo'.  Likewise `R_SPARC_HIX22' is obtained from `%hix'
15837
and `R_SPARC_LOX10' is obtained using `%lox'.  For example:
15838
 
15839
     sethi %hi(symbol), %g1
15840
     or    %g1, %lo(symbol), %g1
15841
 
15842
     sethi %hix(symbol), %g1
15843
     xor   %g1, %lox(symbol), %g1
15844
 
15845
   These "high" mnemonics extract bits 31:10 of their operand, and the
15846
"low" mnemonics extract bits 9:0 of their operand.
15847
 
15848
   V9 code model relocations can be requested as follows:
15849
 
15850
   * `R_SPARC_HH22' is requested using `%hh'.  It can also be generated
15851
     using `%uhi'.
15852
 
15853
   * `R_SPARC_HM10' is requested using `%hm'.  It can also be generated
15854
     using `%ulo'.
15855
 
15856
   * `R_SPARC_LM22' is requested using `%lm'.
15857
 
15858
   * `R_SPARC_H44' is requested using `%h44'.
15859
 
15860
   * `R_SPARC_M44' is requested using `%m44'.
15861
 
15862
   * `R_SPARC_L44' is requested using `%l44'.
15863
 
15864
   The PC relative relocation `R_SPARC_PC22' can be obtained by
15865
enclosing an operand inside of `%pc22'.  Likewise, the `R_SPARC_PC10'
15866
relocation can be obtained using `%pc10'.  These are mostly used when
15867
assembling PIC code.  For example, the standard PIC sequence on Sparc
15868
to get the base of the global offset table, PC relative, into a
15869
register, can be performed as:
15870
 
15871
     sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7
15872
     add   %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7
15873
 
15874
   Several relocations exist to allow the link editor to potentially
15875
optimize GOT data references.  The `R_SPARC_GOTDATA_OP_HIX22'
15876
relocation can obtained by enclosing an operand inside of
15877
`%gdop_hix22'.  The `R_SPARC_GOTDATA_OP_LOX10' relocation can obtained
15878
by enclosing an operand inside of `%gdop_lox10'.  Likewise,
15879
`R_SPARC_GOTDATA_OP' can be obtained by enclosing an operand inside of
15880
`%gdop'.  For example, assuming the GOT base is in register `%l7':
15881
 
15882
     sethi %gdop_hix22(symbol), %l1
15883
     xor   %l1, %gdop_lox10(symbol), %l1
15884
     ld    [%l7 + %l1], %l2, %gdop(symbol)
15885
 
15886
   There are many relocations that can be requested for access to
15887
thread local storage variables.  All of the Sparc TLS mnemonics are
15888
supported:
15889
 
15890
   * `R_SPARC_TLS_GD_HI22' is requested using `%tgd_hi22'.
15891
 
15892
   * `R_SPARC_TLS_GD_LO10' is requested using `%tgd_lo10'.
15893
 
15894
   * `R_SPARC_TLS_GD_ADD' is requested using `%tgd_add'.
15895
 
15896
   * `R_SPARC_TLS_GD_CALL' is requested using `%tgd_call'.
15897
 
15898
   * `R_SPARC_TLS_LDM_HI22' is requested using `%tldm_hi22'.
15899
 
15900
   * `R_SPARC_TLS_LDM_LO10' is requested using `%tldm_lo10'.
15901
 
15902
   * `R_SPARC_TLS_LDM_ADD' is requested using `%tldm_add'.
15903
 
15904
   * `R_SPARC_TLS_LDM_CALL' is requested using `%tldm_call'.
15905
 
15906
   * `R_SPARC_TLS_LDO_HIX22' is requested using `%tldo_hix22'.
15907
 
15908
   * `R_SPARC_TLS_LDO_LOX10' is requested using `%tldo_lox10'.
15909
 
15910
   * `R_SPARC_TLS_LDO_ADD' is requested using `%tldo_add'.
15911
 
15912
   * `R_SPARC_TLS_IE_HI22' is requested using `%tie_hi22'.
15913
 
15914
   * `R_SPARC_TLS_IE_LO10' is requested using `%tie_lo10'.
15915
 
15916
   * `R_SPARC_TLS_IE_LD' is requested using `%tie_ld'.
15917
 
15918
   * `R_SPARC_TLS_IE_LDX' is requested using `%tie_ldx'.
15919
 
15920
   * `R_SPARC_TLS_IE_ADD' is requested using `%tie_add'.
15921
 
15922
   * `R_SPARC_TLS_LE_HIX22' is requested using `%tle_hix22'.
15923
 
15924
   * `R_SPARC_TLS_LE_LOX10' is requested using `%tle_lox10'.
15925
 
15926
   Here are some example TLS model sequences.
15927
 
15928
   First, General Dynamic:
15929
 
15930
     sethi  %tgd_hi22(symbol), %l1
15931
     add    %l1, %tgd_lo10(symbol), %l1
15932
     add    %l7, %l1, %o0, %tgd_add(symbol)
15933
     call   __tls_get_addr, %tgd_call(symbol)
15934
     nop
15935
 
15936
   Local Dynamic:
15937
 
15938
     sethi  %tldm_hi22(symbol), %l1
15939
     add    %l1, %tldm_lo10(symbol), %l1
15940
     add    %l7, %l1, %o0, %tldm_add(symbol)
15941
     call   __tls_get_addr, %tldm_call(symbol)
15942
     nop
15943
 
15944
     sethi  %tldo_hix22(symbol), %l1
15945
     xor    %l1, %tldo_lox10(symbol), %l1
15946
     add    %o0, %l1, %l1, %tldo_add(symbol)
15947
 
15948
   Initial Exec:
15949
 
15950
     sethi  %tie_hi22(symbol), %l1
15951
     add    %l1, %tie_lo10(symbol), %l1
15952
     ld     [%l7 + %l1], %o0, %tie_ld(symbol)
15953
     add    %g7, %o0, %o0, %tie_add(symbol)
15954
 
15955
     sethi  %tie_hi22(symbol), %l1
15956
     add    %l1, %tie_lo10(symbol), %l1
15957
     ldx    [%l7 + %l1], %o0, %tie_ldx(symbol)
15958
     add    %g7, %o0, %o0, %tie_add(symbol)
15959
 
15960
   And finally, Local Exec:
15961
 
15962
     sethi  %tle_hix22(symbol), %l1
15963
     add    %l1, %tle_lox10(symbol), %l1
15964
     add    %g7, %l1, %l1
15965
 
15966
   When assembling for 64-bit, and a secondary constant addend is
15967
specified in an address expression that would normally generate an
15968
`R_SPARC_LO10' relocation, the assembler will emit an `R_SPARC_OLO10'
15969
instead.
15970
 
15971

15972
File: as.info,  Node: Sparc-Size-Translations,  Prev: Sparc-Relocs,  Up: Sparc-Syntax
15973
 
15974
9.34.3.5 Size Translations
15975
..........................
15976
 
15977
Often it is desirable to write code in an operand size agnostic manner.
15978
`as' provides support for this via operand size opcode translations.
15979
Translations are supported for loads, stores, shifts, compare-and-swap
15980
atomics, and the `clr' synthetic instruction.
15981
 
15982
   If generating 32-bit code, `as' will generate the 32-bit opcode.
15983
Whereas if 64-bit code is being generated, the 64-bit opcode will be
15984
emitted.  For example `ldn' will be transformed into `ld' for 32-bit
15985
code and `ldx' for 64-bit code.
15986
 
15987
   Here is an example meant to demonstrate all the supported opcode
15988
translations:
15989
 
15990
     ldn   [%o0], %o1
15991
     ldna  [%o0] %asi, %o2
15992
     stn   %o1, [%o0]
15993
     stna  %o2, [%o0] %asi
15994
     slln  %o3, 3, %o3
15995
     srln  %o4, 8, %o4
15996
     sran  %o5, 12, %o5
15997
     casn  [%o0], %o1, %o2
15998
     casna [%o0] %asi, %o1, %o2
15999
     clrn  %g1
16000
 
16001
   In 32-bit mode `as' will emit:
16002
 
16003
     ld   [%o0], %o1
16004
     lda  [%o0] %asi, %o2
16005
     st   %o1, [%o0]
16006
     sta  %o2, [%o0] %asi
16007
     sll  %o3, 3, %o3
16008
     srl  %o4, 8, %o4
16009
     sra  %o5, 12, %o5
16010
     cas  [%o0], %o1, %o2
16011
     casa [%o0] %asi, %o1, %o2
16012
     clr  %g1
16013
 
16014
   And in 64-bit mode `as' will emit:
16015
 
16016
     ldx   [%o0], %o1
16017
     ldxa  [%o0] %asi, %o2
16018
     stx   %o1, [%o0]
16019
     stxa  %o2, [%o0] %asi
16020
     sllx  %o3, 3, %o3
16021
     srlx  %o4, 8, %o4
16022
     srax  %o5, 12, %o5
16023
     casx  [%o0], %o1, %o2
16024
     casxa [%o0] %asi, %o1, %o2
16025
     clrx  %g1
16026
 
16027
   Finally, the `.nword' translating directive is supported as well.
16028
It is documented in the section on Sparc machine directives.
16029
 
16030

16031
File: as.info,  Node: Sparc-Float,  Next: Sparc-Directives,  Prev: Sparc-Syntax,  Up: Sparc-Dependent
16032
 
16033
9.34.4 Floating Point
16034
---------------------
16035
 
16036
The Sparc uses IEEE floating-point numbers.
16037
 
16038

16039
File: as.info,  Node: Sparc-Directives,  Prev: Sparc-Float,  Up: Sparc-Dependent
16040
 
16041
9.34.5 Sparc Machine Directives
16042
-------------------------------
16043
 
16044
The Sparc version of `as' supports the following additional machine
16045
directives:
16046
 
16047
`.align'
16048
     This must be followed by the desired alignment in bytes.
16049
 
16050
`.common'
16051
     This must be followed by a symbol name, a positive number, and
16052
     `"bss"'.  This behaves somewhat like `.comm', but the syntax is
16053
     different.
16054
 
16055
`.half'
16056
     This is functionally identical to `.short'.
16057
 
16058
`.nword'
16059
     On the Sparc, the `.nword' directive produces native word sized
16060
     value, ie. if assembling with -32 it is equivalent to `.word', if
16061
     assembling with -64 it is equivalent to `.xword'.
16062
 
16063
`.proc'
16064
     This directive is ignored.  Any text following it on the same line
16065
     is also ignored.
16066
 
16067
`.register'
16068
     This directive declares use of a global application or system
16069
     register.  It must be followed by a register name %g2, %g3, %g6 or
16070
     %g7, comma and the symbol name for that register.  If symbol name
16071
     is `#scratch', it is a scratch register, if it is `#ignore', it
16072
     just suppresses any errors about using undeclared global register,
16073
     but does not emit any information about it into the object file.
16074
     This can be useful e.g. if you save the register before use and
16075
     restore it after.
16076
 
16077
`.reserve'
16078
     This must be followed by a symbol name, a positive number, and
16079
     `"bss"'.  This behaves somewhat like `.lcomm', but the syntax is
16080
     different.
16081
 
16082
`.seg'
16083
     This must be followed by `"text"', `"data"', or `"data1"'.  It
16084
     behaves like `.text', `.data', or `.data 1'.
16085
 
16086
`.skip'
16087
     This is functionally identical to the `.space' directive.
16088
 
16089
`.word'
16090
     On the Sparc, the `.word' directive produces 32 bit values,
16091
     instead of the 16 bit values it produces on many other machines.
16092
 
16093
`.xword'
16094
     On the Sparc V9 processor, the `.xword' directive produces 64 bit
16095
     values.
16096
 
16097

16098
File: as.info,  Node: TIC54X-Dependent,  Next: V850-Dependent,  Prev: Sparc-Dependent,  Up: Machine Dependencies
16099
 
16100
9.35 TIC54X Dependent Features
16101
==============================
16102
 
16103
* Menu:
16104
 
16105
* TIC54X-Opts::              Command-line Options
16106
* TIC54X-Block::             Blocking
16107
* TIC54X-Env::               Environment Settings
16108
* TIC54X-Constants::         Constants Syntax
16109
* TIC54X-Subsyms::           String Substitution
16110
* TIC54X-Locals::            Local Label Syntax
16111
* TIC54X-Builtins::          Builtin Assembler Math Functions
16112
* TIC54X-Ext::               Extended Addressing Support
16113
* TIC54X-Directives::        Directives
16114
* TIC54X-Macros::            Macro Features
16115
* TIC54X-MMRegs::            Memory-mapped Registers
16116
 
16117

16118
File: as.info,  Node: TIC54X-Opts,  Next: TIC54X-Block,  Up: TIC54X-Dependent
16119
 
16120
9.35.1 Options
16121
--------------
16122
 
16123
The TMS320C54X version of `as' has a few machine-dependent options.
16124
 
16125
   You can use the `-mfar-mode' option to enable extended addressing
16126
mode.  All addresses will be assumed to be > 16 bits, and the
16127
appropriate relocation types will be used.  This option is equivalent
16128
to using the `.far_mode' directive in the assembly code.  If you do not
16129
use the `-mfar-mode' option, all references will be assumed to be 16
16130
bits.  This option may be abbreviated to `-mf'.
16131
 
16132
   You can use the `-mcpu' option to specify a particular CPU.  This
16133
option is equivalent to using the `.version' directive in the assembly
16134
code.  For recognized CPU codes, see *Note `.version':
16135
TIC54X-Directives.  The default CPU version is `542'.
16136
 
16137
   You can use the `-merrors-to-file' option to redirect error output
16138
to a file (this provided for those deficient environments which don't
16139
provide adequate output redirection).  This option may be abbreviated to
16140
`-me'.
16141
 
16142

16143
File: as.info,  Node: TIC54X-Block,  Next: TIC54X-Env,  Prev: TIC54X-Opts,  Up: TIC54X-Dependent
16144
 
16145
9.35.2 Blocking
16146
---------------
16147
 
16148
A blocked section or memory block is guaranteed not to cross the
16149
blocking boundary (usually a page, or 128 words) if it is smaller than
16150
the blocking size, or to start on a page boundary if it is larger than
16151
the blocking size.
16152
 
16153

16154
File: as.info,  Node: TIC54X-Env,  Next: TIC54X-Constants,  Prev: TIC54X-Block,  Up: TIC54X-Dependent
16155
 
16156
9.35.3 Environment Settings
16157
---------------------------
16158
 
16159
`C54XDSP_DIR' and `A_DIR' are semicolon-separated paths which are added
16160
to the list of directories normally searched for source and include
16161
files.  `C54XDSP_DIR' will override `A_DIR'.
16162
 
16163

16164
File: as.info,  Node: TIC54X-Constants,  Next: TIC54X-Subsyms,  Prev: TIC54X-Env,  Up: TIC54X-Dependent
16165
 
16166
9.35.4 Constants Syntax
16167
-----------------------
16168
 
16169
The TIC54X version of `as' allows the following additional constant
16170
formats, using a suffix to indicate the radix:
16171
 
16172
     Binary                  `000000B, 011000b'
16173
     Octal                   `10Q, 224q'
16174
     Hexadecimal             `45h, 0FH'
16175
 
16176

16177
File: as.info,  Node: TIC54X-Subsyms,  Next: TIC54X-Locals,  Prev: TIC54X-Constants,  Up: TIC54X-Dependent
16178
 
16179
9.35.5 String Substitution
16180
--------------------------
16181
 
16182
A subset of allowable symbols (which we'll call subsyms) may be assigned
16183
arbitrary string values.  This is roughly equivalent to C preprocessor
16184
#define macros.  When `as' encounters one of these symbols, the symbol
16185
is replaced in the input stream by its string value.  Subsym names
16186
*must* begin with a letter.
16187
 
16188
   Subsyms may be defined using the `.asg' and `.eval' directives
16189
(*Note `.asg': TIC54X-Directives, *Note `.eval': TIC54X-Directives.
16190
 
16191
   Expansion is recursive until a previously encountered symbol is
16192
seen, at which point substitution stops.
16193
 
16194
   In this example, x is replaced with SYM2; SYM2 is replaced with
16195
SYM1, and SYM1 is replaced with x.  At this point, x has already been
16196
encountered and the substitution stops.
16197
 
16198
      .asg   "x",SYM1
16199
      .asg   "SYM1",SYM2
16200
      .asg   "SYM2",x
16201
      add    x,a             ; final code assembled is "add  x, a"
16202
 
16203
   Macro parameters are converted to subsyms; a side effect of this is
16204
the normal `as' '\ARG' dereferencing syntax is unnecessary.  Subsyms
16205
defined within a macro will have global scope, unless the `.var'
16206
directive is used to identify the subsym as a local macro variable
16207
*note `.var': TIC54X-Directives.
16208
 
16209
   Substitution may be forced in situations where replacement might be
16210
ambiguous by placing colons on either side of the subsym.  The following
16211
code:
16212
 
16213
      .eval  "10",x
16214
     LAB:X:  add     #x, a
16215
 
16216
   When assembled becomes:
16217
 
16218
     LAB10  add     #10, a
16219
 
16220
   Smaller parts of the string assigned to a subsym may be accessed with
16221
the following syntax:
16222
 
16223
``:SYMBOL(CHAR_INDEX):''
16224
     Evaluates to a single-character string, the character at
16225
     CHAR_INDEX.
16226
 
16227
``:SYMBOL(START,LENGTH):''
16228
     Evaluates to a substring of SYMBOL beginning at START with length
16229
     LENGTH.
16230
 
16231

16232
File: as.info,  Node: TIC54X-Locals,  Next: TIC54X-Builtins,  Prev: TIC54X-Subsyms,  Up: TIC54X-Dependent
16233
 
16234
9.35.6 Local Labels
16235
-------------------
16236
 
16237
Local labels may be defined in two ways:
16238
 
16239
   * $N, where N is a decimal number between 0 and 9
16240
 
16241
   * LABEL?, where LABEL is any legal symbol name.
16242
 
16243
   Local labels thus defined may be redefined or automatically
16244
generated.  The scope of a local label is based on when it may be
16245
undefined or reset.  This happens when one of the following situations
16246
is encountered:
16247
 
16248
   * .newblock directive *note `.newblock': TIC54X-Directives.
16249
 
16250
   * The current section is changed (.sect, .text, or .data)
16251
 
16252
   * Entering or leaving an included file
16253
 
16254
   * The macro scope where the label was defined is exited
16255
 
16256

16257
File: as.info,  Node: TIC54X-Builtins,  Next: TIC54X-Ext,  Prev: TIC54X-Locals,  Up: TIC54X-Dependent
16258
 
16259
9.35.7 Math Builtins
16260
--------------------
16261
 
16262
The following built-in functions may be used to generate a
16263
floating-point value.  All return a floating-point value except `$cvi',
16264
`$int', and `$sgn', which return an integer value.
16265
 
16266
``$acos(EXPR)''
16267
     Returns the floating point arccosine of EXPR.
16268
 
16269
``$asin(EXPR)''
16270
     Returns the floating point arcsine of EXPR.
16271
 
16272
``$atan(EXPR)''
16273
     Returns the floating point arctangent of EXPR.
16274
 
16275
``$atan2(EXPR1,EXPR2)''
16276
     Returns the floating point arctangent of EXPR1 / EXPR2.
16277
 
16278
``$ceil(EXPR)''
16279
     Returns the smallest integer not less than EXPR as floating point.
16280
 
16281
``$cosh(EXPR)''
16282
     Returns the floating point hyperbolic cosine of EXPR.
16283
 
16284
``$cos(EXPR)''
16285
     Returns the floating point cosine of EXPR.
16286
 
16287
``$cvf(EXPR)''
16288
     Returns the integer value EXPR converted to floating-point.
16289
 
16290
``$cvi(EXPR)''
16291
     Returns the floating point value EXPR converted to integer.
16292
 
16293
``$exp(EXPR)''
16294
     Returns the floating point value e ^ EXPR.
16295
 
16296
``$fabs(EXPR)''
16297
     Returns the floating point absolute value of EXPR.
16298
 
16299
``$floor(EXPR)''
16300
     Returns the largest integer that is not greater than EXPR as
16301
     floating point.
16302
 
16303
``$fmod(EXPR1,EXPR2)''
16304
     Returns the floating point remainder of EXPR1 / EXPR2.
16305
 
16306
``$int(EXPR)''
16307
     Returns 1 if EXPR evaluates to an integer, zero otherwise.
16308
 
16309
``$ldexp(EXPR1,EXPR2)''
16310
     Returns the floating point value EXPR1 * 2 ^ EXPR2.
16311
 
16312
``$log10(EXPR)''
16313
     Returns the base 10 logarithm of EXPR.
16314
 
16315
``$log(EXPR)''
16316
     Returns the natural logarithm of EXPR.
16317
 
16318
``$max(EXPR1,EXPR2)''
16319
     Returns the floating point maximum of EXPR1 and EXPR2.
16320
 
16321
``$min(EXPR1,EXPR2)''
16322
     Returns the floating point minimum of EXPR1 and EXPR2.
16323
 
16324
``$pow(EXPR1,EXPR2)''
16325
     Returns the floating point value EXPR1 ^ EXPR2.
16326
 
16327
``$round(EXPR)''
16328
     Returns the nearest integer to EXPR as a floating point number.
16329
 
16330
``$sgn(EXPR)''
16331
     Returns -1, 0, or 1 based on the sign of EXPR.
16332
 
16333
``$sin(EXPR)''
16334
     Returns the floating point sine of EXPR.
16335
 
16336
``$sinh(EXPR)''
16337
     Returns the floating point hyperbolic sine of EXPR.
16338
 
16339
``$sqrt(EXPR)''
16340
     Returns the floating point square root of EXPR.
16341
 
16342
``$tan(EXPR)''
16343
     Returns the floating point tangent of EXPR.
16344
 
16345
``$tanh(EXPR)''
16346
     Returns the floating point hyperbolic tangent of EXPR.
16347
 
16348
``$trunc(EXPR)''
16349
     Returns the integer value of EXPR truncated towards zero as
16350
     floating point.
16351
 
16352
 
16353

16354
File: as.info,  Node: TIC54X-Ext,  Next: TIC54X-Directives,  Prev: TIC54X-Builtins,  Up: TIC54X-Dependent
16355
 
16356
9.35.8 Extended Addressing
16357
--------------------------
16358
 
16359
The `LDX' pseudo-op is provided for loading the extended addressing bits
16360
of a label or address.  For example, if an address `_label' resides in
16361
extended program memory, the value of `_label' may be loaded as follows:
16362
      ldx     #_label,16,a    ; loads extended bits of _label
16363
      or      #_label,a       ; loads lower 16 bits of _label
16364
      bacc    a               ; full address is in accumulator A
16365
 
16366

16367
File: as.info,  Node: TIC54X-Directives,  Next: TIC54X-Macros,  Prev: TIC54X-Ext,  Up: TIC54X-Dependent
16368
 
16369
9.35.9 Directives
16370
-----------------
16371
 
16372
`.align [SIZE]'
16373
`.even'
16374
     Align the section program counter on the next boundary, based on
16375
     SIZE.  SIZE may be any power of 2.  `.even' is equivalent to
16376
     `.align' with a SIZE of 2.
16377
    `1'
16378
          Align SPC to word boundary
16379
 
16380
    `2'
16381
          Align SPC to longword boundary (same as .even)
16382
 
16383
    `128'
16384
          Align SPC to page boundary
16385
 
16386
`.asg STRING, NAME'
16387
     Assign NAME the string STRING.  String replacement is performed on
16388
     STRING before assignment.
16389
 
16390
`.eval STRING, NAME'
16391
     Evaluate the contents of string STRING and assign the result as a
16392
     string to the subsym NAME.  String replacement is performed on
16393
     STRING before assignment.
16394
 
16395
`.bss SYMBOL, SIZE [, [BLOCKING_FLAG] [,ALIGNMENT_FLAG]]'
16396
     Reserve space for SYMBOL in the .bss section.  SIZE is in words.
16397
     If present, BLOCKING_FLAG indicates the allocated space should be
16398
     aligned on a page boundary if it would otherwise cross a page
16399
     boundary.  If present, ALIGNMENT_FLAG causes the assembler to
16400
     allocate SIZE on a long word boundary.
16401
 
16402
`.byte VALUE [,...,VALUE_N]'
16403
`.ubyte VALUE [,...,VALUE_N]'
16404
`.char VALUE [,...,VALUE_N]'
16405
`.uchar VALUE [,...,VALUE_N]'
16406
     Place one or more bytes into consecutive words of the current
16407
     section.  The upper 8 bits of each word is zero-filled.  If a
16408
     label is used, it points to the word allocated for the first byte
16409
     encountered.
16410
 
16411
`.clink ["SECTION_NAME"]'
16412
     Set STYP_CLINK flag for this section, which indicates to the
16413
     linker that if no symbols from this section are referenced, the
16414
     section should not be included in the link.  If SECTION_NAME is
16415
     omitted, the current section is used.
16416
 
16417
`.c_mode'
16418
     TBD.
16419
 
16420
`.copy "FILENAME" | FILENAME'
16421
`.include "FILENAME" | FILENAME'
16422
     Read source statements from FILENAME.  The normal include search
16423
     path is used.  Normally .copy will cause statements from the
16424
     included file to be printed in the assembly listing and .include
16425
     will not, but this distinction is not currently implemented.
16426
 
16427
`.data'
16428
     Begin assembling code into the .data section.
16429
 
16430
`.double VALUE [,...,VALUE_N]'
16431
`.ldouble VALUE [,...,VALUE_N]'
16432
`.float VALUE [,...,VALUE_N]'
16433
`.xfloat VALUE [,...,VALUE_N]'
16434
     Place an IEEE single-precision floating-point representation of
16435
     one or more floating-point values into the current section.  All
16436
     but `.xfloat' align the result on a longword boundary.  Values are
16437
     stored most-significant word first.
16438
 
16439
`.drlist'
16440
`.drnolist'
16441
     Control printing of directives to the listing file.  Ignored.
16442
 
16443
`.emsg STRING'
16444
`.mmsg STRING'
16445
`.wmsg STRING'
16446
     Emit a user-defined error, message, or warning, respectively.
16447
 
16448
`.far_mode'
16449
     Use extended addressing when assembling statements.  This should
16450
     appear only once per file, and is equivalent to the -mfar-mode
16451
     option *note `-mfar-mode': TIC54X-Opts.
16452
 
16453
`.fclist'
16454
`.fcnolist'
16455
     Control printing of false conditional blocks to the listing file.
16456
 
16457
`.field VALUE [,SIZE]'
16458
     Initialize a bitfield of SIZE bits in the current section.  If
16459
     VALUE is relocatable, then SIZE must be 16.  SIZE defaults to 16
16460
     bits.  If VALUE does not fit into SIZE bits, the value will be
16461
     truncated.  Successive `.field' directives will pack starting at
16462
     the current word, filling the most significant bits first, and
16463
     aligning to the start of the next word if the field size does not
16464
     fit into the space remaining in the current word.  A `.align'
16465
     directive with an operand of 1 will force the next `.field'
16466
     directive to begin packing into a new word.  If a label is used, it
16467
     points to the word that contains the specified field.
16468
 
16469
`.global SYMBOL [,...,SYMBOL_N]'
16470
`.def SYMBOL [,...,SYMBOL_N]'
16471
`.ref SYMBOL [,...,SYMBOL_N]'
16472
     `.def' nominally identifies a symbol defined in the current file
16473
     and available to other files.  `.ref' identifies a symbol used in
16474
     the current file but defined elsewhere.  Both map to the standard
16475
     `.global' directive.
16476
 
16477
`.half VALUE [,...,VALUE_N]'
16478
`.uhalf VALUE [,...,VALUE_N]'
16479
`.short VALUE [,...,VALUE_N]'
16480
`.ushort VALUE [,...,VALUE_N]'
16481
`.int VALUE [,...,VALUE_N]'
16482
`.uint VALUE [,...,VALUE_N]'
16483
`.word VALUE [,...,VALUE_N]'
16484
`.uword VALUE [,...,VALUE_N]'
16485
     Place one or more values into consecutive words of the current
16486
     section.  If a label is used, it points to the word allocated for
16487
     the first value encountered.
16488
 
16489
`.label SYMBOL'
16490
     Define a special SYMBOL to refer to the load time address of the
16491
     current section program counter.
16492
 
16493
`.length'
16494
`.width'
16495
     Set the page length and width of the output listing file.  Ignored.
16496
 
16497
`.list'
16498
`.nolist'
16499
     Control whether the source listing is printed.  Ignored.
16500
 
16501
`.long VALUE [,...,VALUE_N]'
16502
`.ulong VALUE [,...,VALUE_N]'
16503
`.xlong VALUE [,...,VALUE_N]'
16504
     Place one or more 32-bit values into consecutive words in the
16505
     current section.  The most significant word is stored first.
16506
     `.long' and `.ulong' align the result on a longword boundary;
16507
     `xlong' does not.
16508
 
16509
`.loop [COUNT]'
16510
`.break [CONDITION]'
16511
`.endloop'
16512
     Repeatedly assemble a block of code.  `.loop' begins the block, and
16513
     `.endloop' marks its termination.  COUNT defaults to 1024, and
16514
     indicates the number of times the block should be repeated.
16515
     `.break' terminates the loop so that assembly begins after the
16516
     `.endloop' directive.  The optional CONDITION will cause the loop
16517
     to terminate only if it evaluates to zero.
16518
 
16519
`MACRO_NAME .macro [PARAM1][,...PARAM_N]'
16520
`[.mexit]'
16521
`.endm'
16522
     See the section on macros for more explanation (*Note
16523
     TIC54X-Macros::.
16524
 
16525
`.mlib "FILENAME" | FILENAME'
16526
     Load the macro library FILENAME.  FILENAME must be an archived
16527
     library (BFD ar-compatible) of text files, expected to contain
16528
     only macro definitions.   The standard include search path is used.
16529
 
16530
`.mlist'
16531
 
16532
`.mnolist'
16533
     Control whether to include macro and loop block expansions in the
16534
     listing output.  Ignored.
16535
 
16536
`.mmregs'
16537
     Define global symbolic names for the 'c54x registers.  Supposedly
16538
     equivalent to executing `.set' directives for each register with
16539
     its memory-mapped value, but in reality is provided only for
16540
     compatibility and does nothing.
16541
 
16542
`.newblock'
16543
     This directive resets any TIC54X local labels currently defined.
16544
     Normal `as' local labels are unaffected.
16545
 
16546
`.option OPTION_LIST'
16547
     Set listing options.  Ignored.
16548
 
16549
`.sblock "SECTION_NAME" | SECTION_NAME [,"NAME_N" | NAME_N]'
16550
     Designate SECTION_NAME for blocking.  Blocking guarantees that a
16551
     section will start on a page boundary (128 words) if it would
16552
     otherwise cross a page boundary.  Only initialized sections may be
16553
     designated with this directive.  See also *Note TIC54X-Block::.
16554
 
16555
`.sect "SECTION_NAME"'
16556
     Define a named initialized section and make it the current section.
16557
 
16558
`SYMBOL .set "VALUE"'
16559
`SYMBOL .equ "VALUE"'
16560
     Equate a constant VALUE to a SYMBOL, which is placed in the symbol
16561
     table.  SYMBOL may not be previously defined.
16562
 
16563
`.space SIZE_IN_BITS'
16564
`.bes SIZE_IN_BITS'
16565
     Reserve the given number of bits in the current section and
16566
     zero-fill them.  If a label is used with `.space', it points to the
16567
     *first* word reserved.  With `.bes', the label points to the
16568
     *last* word reserved.
16569
 
16570
`.sslist'
16571
`.ssnolist'
16572
     Controls the inclusion of subsym replacement in the listing
16573
     output.  Ignored.
16574
 
16575
`.string "STRING" [,...,"STRING_N"]'
16576
`.pstring "STRING" [,...,"STRING_N"]'
16577
     Place 8-bit characters from STRING into the current section.
16578
     `.string' zero-fills the upper 8 bits of each word, while
16579
     `.pstring' puts two characters into each word, filling the
16580
     most-significant bits first.  Unused space is zero-filled.  If a
16581
     label is used, it points to the first word initialized.
16582
 
16583
`[STAG] .struct [OFFSET]'
16584
`[NAME_1] element [COUNT_1]'
16585
`[NAME_2] element [COUNT_2]'
16586
`[TNAME] .tag STAGX [TCOUNT]'
16587
`...'
16588
`[NAME_N] element [COUNT_N]'
16589
`[SSIZE] .endstruct'
16590
`LABEL .tag [STAG]'
16591
     Assign symbolic offsets to the elements of a structure.  STAG
16592
     defines a symbol to use to reference the structure.  OFFSET
16593
     indicates a starting value to use for the first element
16594
     encountered; otherwise it defaults to zero.  Each element can have
16595
     a named offset, NAME, which is a symbol assigned the value of the
16596
     element's offset into the structure.  If STAG is missing, these
16597
     become global symbols.  COUNT adjusts the offset that many times,
16598
     as if `element' were an array.  `element' may be one of `.byte',
16599
     `.word', `.long', `.float', or any equivalent of those, and the
16600
     structure offset is adjusted accordingly.  `.field' and `.string'
16601
     are also allowed; the size of `.field' is one bit, and `.string'
16602
     is considered to be one word in size.  Only element descriptors,
16603
     structure/union tags, `.align' and conditional assembly directives
16604
     are allowed within `.struct'/`.endstruct'.  `.align' aligns member
16605
     offsets to word boundaries only.  SSIZE, if provided, will always
16606
     be assigned the size of the structure.
16607
 
16608
     The `.tag' directive, in addition to being used to define a
16609
     structure/union element within a structure, may be used to apply a
16610
     structure to a symbol.  Once applied to LABEL, the individual
16611
     structure elements may be applied to LABEL to produce the desired
16612
     offsets using LABEL as the structure base.
16613
 
16614
`.tab'
16615
     Set the tab size in the output listing.  Ignored.
16616
 
16617
`[UTAG] .union'
16618
`[NAME_1] element [COUNT_1]'
16619
`[NAME_2] element [COUNT_2]'
16620
`[TNAME] .tag UTAGX[,TCOUNT]'
16621
`...'
16622
`[NAME_N] element [COUNT_N]'
16623
`[USIZE] .endstruct'
16624
`LABEL .tag [UTAG]'
16625
     Similar to `.struct', but the offset after each element is reset to
16626
     zero, and the USIZE is set to the maximum of all defined elements.
16627
     Starting offset for the union is always zero.
16628
 
16629
`[SYMBOL] .usect "SECTION_NAME", SIZE, [,[BLOCKING_FLAG] [,ALIGNMENT_FLAG]]'
16630
     Reserve space for variables in a named, uninitialized section
16631
     (similar to .bss).  `.usect' allows definitions sections
16632
     independent of .bss.  SYMBOL points to the first location reserved
16633
     by this allocation.  The symbol may be used as a variable name.
16634
     SIZE is the allocated size in words.  BLOCKING_FLAG indicates
16635
     whether to block this section on a page boundary (128 words)
16636
     (*note TIC54X-Block::).  ALIGNMENT FLAG indicates whether the
16637
     section should be longword-aligned.
16638
 
16639
`.var SYM[,..., SYM_N]'
16640
     Define a subsym to be a local variable within a macro.  See *Note
16641
     TIC54X-Macros::.
16642
 
16643
`.version VERSION'
16644
     Set which processor to build instructions for.  Though the
16645
     following values are accepted, the op is ignored.
16646
    `541'
16647
    `542'
16648
    `543'
16649
    `545'
16650
    `545LP'
16651
    `546LP'
16652
    `548'
16653
    `549'
16654
 
16655

16656
File: as.info,  Node: TIC54X-Macros,  Next: TIC54X-MMRegs,  Prev: TIC54X-Directives,  Up: TIC54X-Dependent
16657
 
16658
9.35.10 Macros
16659
--------------
16660
 
16661
Macros do not require explicit dereferencing of arguments (i.e., \ARG).
16662
 
16663
   During macro expansion, the macro parameters are converted to
16664
subsyms.  If the number of arguments passed the macro invocation
16665
exceeds the number of parameters defined, the last parameter is
16666
assigned the string equivalent of all remaining arguments.  If fewer
16667
arguments are given than parameters, the missing parameters are
16668
assigned empty strings.  To include a comma in an argument, you must
16669
enclose the argument in quotes.
16670
 
16671
   The following built-in subsym functions allow examination of the
16672
string value of subsyms (or ordinary strings).  The arguments are
16673
strings unless otherwise indicated (subsyms passed as args will be
16674
replaced by the strings they represent).
16675
``$symlen(STR)''
16676
     Returns the length of STR.
16677
 
16678
``$symcmp(STR1,STR2)''
16679
     Returns 0 if STR1 == STR2, non-zero otherwise.
16680
 
16681
``$firstch(STR,CH)''
16682
     Returns index of the first occurrence of character constant CH in
16683
     STR.
16684
 
16685
``$lastch(STR,CH)''
16686
     Returns index of the last occurrence of character constant CH in
16687
     STR.
16688
 
16689
``$isdefed(SYMBOL)''
16690
     Returns zero if the symbol SYMBOL is not in the symbol table,
16691
     non-zero otherwise.
16692
 
16693
``$ismember(SYMBOL,LIST)''
16694
     Assign the first member of comma-separated string LIST to SYMBOL;
16695
     LIST is reassigned the remainder of the list.  Returns zero if
16696
     LIST is a null string.  Both arguments must be subsyms.
16697
 
16698
``$iscons(EXPR)''
16699
     Returns 1 if string EXPR is binary, 2 if octal, 3 if hexadecimal,
16700
     4 if a character, 5 if decimal, and zero if not an integer.
16701
 
16702
``$isname(NAME)''
16703
     Returns 1 if NAME is a valid symbol name, zero otherwise.
16704
 
16705
``$isreg(REG)''
16706
     Returns 1 if REG is a valid predefined register name (AR0-AR7
16707
     only).
16708
 
16709
``$structsz(STAG)''
16710
     Returns the size of the structure or union represented by STAG.
16711
 
16712
``$structacc(STAG)''
16713
     Returns the reference point of the structure or union represented
16714
     by STAG.   Always returns zero.
16715
 
16716
 
16717

16718
File: as.info,  Node: TIC54X-MMRegs,  Prev: TIC54X-Macros,  Up: TIC54X-Dependent
16719
 
16720
9.35.11 Memory-mapped Registers
16721
-------------------------------
16722
 
16723
The following symbols are recognized as memory-mapped registers:
16724
 
16725
 
16726

16727
File: as.info,  Node: Z80-Dependent,  Next: Z8000-Dependent,  Prev: Xtensa-Dependent,  Up: Machine Dependencies
16728
 
16729
9.36 Z80 Dependent Features
16730
===========================
16731
 
16732
* Menu:
16733
 
16734
* Z80 Options::              Options
16735
* Z80 Syntax::               Syntax
16736
* Z80 Floating Point::       Floating Point
16737
* Z80 Directives::           Z80 Machine Directives
16738
* Z80 Opcodes::              Opcodes
16739
 
16740

16741
File: as.info,  Node: Z80 Options,  Next: Z80 Syntax,  Up: Z80-Dependent
16742
 
16743
9.36.1 Options
16744
--------------
16745
 
16746
The Zilog Z80 and Ascii R800 version of `as' have a few machine
16747
dependent options.
16748
`-z80'
16749
     Produce code for the Z80 processor. There are additional options to
16750
     request warnings and error messages for undocumented instructions.
16751
 
16752
`-ignore-undocumented-instructions'
16753
`-Wnud'
16754
     Silently assemble undocumented Z80-instructions that have been
16755
     adopted as documented R800-instructions.
16756
 
16757
`-ignore-unportable-instructions'
16758
`-Wnup'
16759
     Silently assemble all undocumented Z80-instructions.
16760
 
16761
`-warn-undocumented-instructions'
16762
`-Wud'
16763
     Issue warnings for undocumented Z80-instructions that work on
16764
     R800, do not assemble other undocumented instructions without
16765
     warning.
16766
 
16767
`-warn-unportable-instructions'
16768
`-Wup'
16769
     Issue warnings for other undocumented Z80-instructions, do not
16770
     treat any undocumented instructions as errors.
16771
 
16772
`-forbid-undocumented-instructions'
16773
`-Fud'
16774
     Treat all undocumented z80-instructions as errors.
16775
 
16776
`-forbid-unportable-instructions'
16777
`-Fup'
16778
     Treat undocumented z80-instructions that do not work on R800 as
16779
     errors.
16780
 
16781
`-r800'
16782
     Produce code for the R800 processor. The assembler does not support
16783
     undocumented instructions for the R800.  In line with common
16784
     practice, `as' uses Z80 instruction names for the R800 processor,
16785
     as far as they exist.
16786
 
16787

16788
File: as.info,  Node: Z80 Syntax,  Next: Z80 Floating Point,  Prev: Z80 Options,  Up: Z80-Dependent
16789
 
16790
9.36.2 Syntax
16791
-------------
16792
 
16793
The assembler syntax closely follows the 'Z80 family CPU User Manual' by
16794
Zilog.  In expressions a single `=' may be used as "is equal to"
16795
comparison operator.
16796
 
16797
   Suffices can be used to indicate the radix of integer constants; `H'
16798
or `h' for hexadecimal, `D' or `d' for decimal, `Q', `O', `q' or `o'
16799
for octal, and `B' for binary.
16800
 
16801
   The suffix `b' denotes a backreference to local label.
16802
 
16803
* Menu:
16804
 
16805
* Z80-Chars::                Special Characters
16806
* Z80-Regs::                 Register Names
16807
* Z80-Case::                 Case Sensitivity
16808
 
16809

16810
File: as.info,  Node: Z80-Chars,  Next: Z80-Regs,  Up: Z80 Syntax
16811
 
16812
9.36.2.1 Special Characters
16813
...........................
16814
 
16815
The semicolon `;' is the line comment character;
16816
 
16817
   The dollar sign `$' can be used as a prefix for hexadecimal numbers
16818
and as a symbol denoting the current location counter.
16819
 
16820
   A backslash `\' is an ordinary character for the Z80 assembler.
16821
 
16822
   The single quote `'' must be followed by a closing quote. If there
16823
is one character in between, it is a character constant, otherwise it is
16824
a string constant.
16825
 
16826

16827
File: as.info,  Node: Z80-Regs,  Next: Z80-Case,  Prev: Z80-Chars,  Up: Z80 Syntax
16828
 
16829
9.36.2.2 Register Names
16830
.......................
16831
 
16832
The registers are referred to with the letters assigned to them by
16833
Zilog. In addition `as' recognizes `ixl' and `ixh' as the least and
16834
most significant octet in `ix', and similarly `iyl' and  `iyh' as parts
16835
of `iy'.
16836
 
16837

16838
File: as.info,  Node: Z80-Case,  Prev: Z80-Regs,  Up: Z80 Syntax
16839
 
16840
9.36.2.3 Case Sensitivity
16841
.........................
16842
 
16843
Upper and lower case are equivalent in register names, opcodes,
16844
condition codes  and assembler directives.  The case of letters is
16845
significant in labels and symbol names. The case is also important to
16846
distinguish the suffix `b' for a backward reference to a local label
16847
from the suffix `B' for a number in binary notation.
16848
 
16849

16850
File: as.info,  Node: Z80 Floating Point,  Next: Z80 Directives,  Prev: Z80 Syntax,  Up: Z80-Dependent
16851
 
16852
9.36.3 Floating Point
16853
---------------------
16854
 
16855
Floating-point numbers are not supported.
16856
 
16857

16858
File: as.info,  Node: Z80 Directives,  Next: Z80 Opcodes,  Prev: Z80 Floating Point,  Up: Z80-Dependent
16859
 
16860
9.36.4 Z80 Assembler Directives
16861
-------------------------------
16862
 
16863
`as' for the Z80 supports some additional directives for compatibility
16864
with other assemblers.
16865
 
16866
   These are the additional directives in `as' for the Z80:
16867
 
16868
`db EXPRESSION|STRING[,EXPRESSION|STRING...]'
16869
`defb EXPRESSION|STRING[,EXPRESSION|STRING...]'
16870
     For each STRING the characters are copied to the object file, for
16871
     each other EXPRESSION the value is stored in one byte.  A warning
16872
     is issued in case of an overflow.
16873
 
16874
`dw EXPRESSION[,EXPRESSION...]'
16875
`defw EXPRESSION[,EXPRESSION...]'
16876
     For each EXPRESSION the value is stored in two bytes, ignoring
16877
     overflow.
16878
 
16879
`d24 EXPRESSION[,EXPRESSION...]'
16880
`def24 EXPRESSION[,EXPRESSION...]'
16881
     For each EXPRESSION the value is stored in three bytes, ignoring
16882
     overflow.
16883
 
16884
`d32 EXPRESSION[,EXPRESSION...]'
16885
`def32 EXPRESSION[,EXPRESSION...]'
16886
     For each EXPRESSION the value is stored in four bytes, ignoring
16887
     overflow.
16888
 
16889
`ds COUNT[, VALUE]'
16890
`defs COUNT[, VALUE]'
16891
     Fill COUNT bytes in the object file with VALUE, if VALUE is
16892
     omitted it defaults to zero.
16893
 
16894
`SYMBOL equ EXPRESSION'
16895
`SYMBOL defl EXPRESSION'
16896
     These directives set the value of SYMBOL to EXPRESSION. If `equ'
16897
     is used, it is an error if SYMBOL is already defined.  Symbols
16898
     defined with `equ' are not protected from redefinition.
16899
 
16900
`set'
16901
     This is a normal instruction on Z80, and not an assembler
16902
     directive.
16903
 
16904
`psect NAME'
16905
     A synonym for *Note Section::, no second argument should be given.
16906
 
16907
 
16908

16909
File: as.info,  Node: Z80 Opcodes,  Prev: Z80 Directives,  Up: Z80-Dependent
16910
 
16911
9.36.5 Opcodes
16912
--------------
16913
 
16914
In line with common practice, Z80 mnemonics are used for both the Z80
16915
and the R800.
16916
 
16917
   In many instructions it is possible to use one of the half index
16918
registers (`ixl',`ixh',`iyl',`iyh') in stead of an 8-bit general
16919
purpose register. This yields instructions that are documented on the
16920
R800 and undocumented on the Z80.  Similarly `in f,(c)' is documented
16921
on the R800 and undocumented on the Z80.
16922
 
16923
   The assembler also supports the following undocumented
16924
Z80-instructions, that have not been adopted in the R800 instruction
16925
set:
16926
`out (c),0'
16927
     Sends zero to the port pointed to by register c.
16928
 
16929
`sli M'
16930
     Equivalent to `M = (M<<1)+1', the operand M can be any operand
16931
     that is valid for `sla'. One can use `sll' as a synonym for `sli'.
16932
 
16933
`OP (ix+D), R'
16934
     This is equivalent to
16935
 
16936
          ld R, (ix+D)
16937
          OPC R
16938
          ld (ix+D), R
16939
 
16940
     The operation `OPC' may be any of `res B,', `set B,', `rl', `rlc',
16941
     `rr', `rrc', `sla', `sli', `sra' and `srl', and the register `R'
16942
     may be any of `a', `b', `c', `d', `e', `h' and `l'.
16943
 
16944
`OPC (iy+D), R'
16945
     As above, but with `iy' instead of `ix'.
16946
 
16947
   The web site at `http://www.z80.info' is a good starting place to
16948
find more information on programming the Z80.
16949
 
16950

16951
File: as.info,  Node: Z8000-Dependent,  Next: Vax-Dependent,  Prev: Z80-Dependent,  Up: Machine Dependencies
16952
 
16953
9.37 Z8000 Dependent Features
16954
=============================
16955
 
16956
   The Z8000 as supports both members of the Z8000 family: the
16957
unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with
16958
24 bit addresses.
16959
 
16960
   When the assembler is in unsegmented mode (specified with the
16961
`unsegm' directive), an address takes up one word (16 bit) sized
16962
register.  When the assembler is in segmented mode (specified with the
16963
`segm' directive), a 24-bit address takes up a long (32 bit) register.
16964
*Note Assembler Directives for the Z8000: Z8000 Directives, for a list
16965
of other Z8000 specific assembler directives.
16966
 
16967
* Menu:
16968
 
16969
* Z8000 Options::               Command-line options for the Z8000
16970
* Z8000 Syntax::                Assembler syntax for the Z8000
16971
* Z8000 Directives::            Special directives for the Z8000
16972
* Z8000 Opcodes::               Opcodes
16973
 
16974

16975
File: as.info,  Node: Z8000 Options,  Next: Z8000 Syntax,  Up: Z8000-Dependent
16976
 
16977
9.37.1 Options
16978
--------------
16979
 
16980
`-z8001'
16981
     Generate segmented code by default.
16982
 
16983
`-z8002'
16984
     Generate unsegmented code by default.
16985
 
16986

16987
File: as.info,  Node: Z8000 Syntax,  Next: Z8000 Directives,  Prev: Z8000 Options,  Up: Z8000-Dependent
16988
 
16989
9.37.2 Syntax
16990
-------------
16991
 
16992
* Menu:
16993
 
16994
* Z8000-Chars::                Special Characters
16995
* Z8000-Regs::                 Register Names
16996
* Z8000-Addressing::           Addressing Modes
16997
 
16998

16999
File: as.info,  Node: Z8000-Chars,  Next: Z8000-Regs,  Up: Z8000 Syntax
17000
 
17001
9.37.2.1 Special Characters
17002
...........................
17003
 
17004
`!' is the line comment character.
17005
 
17006
   You can use `;' instead of a newline to separate statements.
17007
 
17008

17009
File: as.info,  Node: Z8000-Regs,  Next: Z8000-Addressing,  Prev: Z8000-Chars,  Up: Z8000 Syntax
17010
 
17011
9.37.2.2 Register Names
17012
.......................
17013
 
17014
The Z8000 has sixteen 16 bit registers, numbered 0 to 15.  You can refer
17015
to different sized groups of registers by register number, with the
17016
prefix `r' for 16 bit registers, `rr' for 32 bit registers and `rq' for
17017
64 bit registers.  You can also refer to the contents of the first
17018
eight (of the sixteen 16 bit registers) by bytes.  They are named `rlN'
17019
and `rhN'.
17020
 
17021
_byte registers_
17022
     rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3
17023
     rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7
17024
 
17025
_word registers_
17026
     r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
17027
 
17028
_long word registers_
17029
     rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14
17030
 
17031
_quad word registers_
17032
     rq0 rq4 rq8 rq12
17033
 
17034

17035
File: as.info,  Node: Z8000-Addressing,  Prev: Z8000-Regs,  Up: Z8000 Syntax
17036
 
17037
9.37.2.3 Addressing Modes
17038
.........................
17039
 
17040
as understands the following addressing modes for the Z8000:
17041
 
17042
`rlN'
17043
`rhN'
17044
`rN'
17045
`rrN'
17046
`rqN'
17047
     Register direct:  8bit, 16bit, 32bit, and 64bit registers.
17048
 
17049
`@rN'
17050
`@rrN'
17051
     Indirect register:  @rrN in segmented mode, @rN in unsegmented
17052
     mode.
17053
 
17054
`ADDR'
17055
     Direct: the 16 bit or 24 bit address (depending on whether the
17056
     assembler is in segmented or unsegmented mode) of the operand is
17057
     in the instruction.
17058
 
17059
`address(rN)'
17060
     Indexed: the 16 or 24 bit address is added to the 16 bit register
17061
     to produce the final address in memory of the operand.
17062
 
17063
`rN(#IMM)'
17064
`rrN(#IMM)'
17065
     Base Address: the 16 or 24 bit register is added to the 16 bit sign
17066
     extended immediate displacement to produce the final address in
17067
     memory of the operand.
17068
 
17069
`rN(rM)'
17070
`rrN(rM)'
17071
     Base Index: the 16 or 24 bit register rN or rrN is added to the
17072
     sign extended 16 bit index register rM to produce the final
17073
     address in memory of the operand.
17074
 
17075
`#XX'
17076
     Immediate data XX.
17077
 
17078

17079
File: as.info,  Node: Z8000 Directives,  Next: Z8000 Opcodes,  Prev: Z8000 Syntax,  Up: Z8000-Dependent
17080
 
17081
9.37.3 Assembler Directives for the Z8000
17082
-----------------------------------------
17083
 
17084
The Z8000 port of as includes additional assembler directives, for
17085
compatibility with other Z8000 assemblers.  These do not begin with `.'
17086
(unlike the ordinary as directives).
17087
 
17088
`segm'
17089
`.z8001'
17090
     Generate code for the segmented Z8001.
17091
 
17092
`unsegm'
17093
`.z8002'
17094
     Generate code for the unsegmented Z8002.
17095
 
17096
`name'
17097
     Synonym for `.file'
17098
 
17099
`global'
17100
     Synonym for `.global'
17101
 
17102
`wval'
17103
     Synonym for `.word'
17104
 
17105
`lval'
17106
     Synonym for `.long'
17107
 
17108
`bval'
17109
     Synonym for `.byte'
17110
 
17111
`sval'
17112
     Assemble a string.  `sval' expects one string literal, delimited by
17113
     single quotes.  It assembles each byte of the string into
17114
     consecutive addresses.  You can use the escape sequence `%XX'
17115
     (where XX represents a two-digit hexadecimal number) to represent
17116
     the character whose ASCII value is XX.  Use this feature to
17117
     describe single quote and other characters that may not appear in
17118
     string literals as themselves.  For example, the C statement
17119
     `char *a = "he said \"it's 50% off\"";' is represented in Z8000
17120
     assembly language (shown with the assembler output in hex at the
17121
     left) as
17122
 
17123
          68652073    sval    'he said %22it%27s 50%25 off%22%00'
17124
          61696420
17125
          22697427
17126
          73203530
17127
          25206F66
17128
          662200
17129
 
17130
`rsect'
17131
     synonym for `.section'
17132
 
17133
`block'
17134
     synonym for `.space'
17135
 
17136
`even'
17137
     special case of `.align'; aligns output to even byte boundary.
17138
 
17139

17140
File: as.info,  Node: Z8000 Opcodes,  Prev: Z8000 Directives,  Up: Z8000-Dependent
17141
 
17142
9.37.4 Opcodes
17143
--------------
17144
 
17145
For detailed information on the Z8000 machine instruction set, see
17146
`Z8000 Technical Manual'.
17147
 
17148
   The following table summarizes the opcodes and their arguments:
17149
 
17150
                 rs   16 bit source register
17151
                 rd   16 bit destination register
17152
                 rbs   8 bit source register
17153
                 rbd   8 bit destination register
17154
                 rrs   32 bit source register
17155
                 rrd   32 bit destination register
17156
                 rqs   64 bit source register
17157
                 rqd   64 bit destination register
17158
                 addr 16/24 bit address
17159
                 imm  immediate data
17160
 
17161
     adc rd,rs               clrb addr               cpsir @rd,@rs,rr,cc
17162
     adcb rbd,rbs            clrb addr(rd)           cpsirb @rd,@rs,rr,cc
17163
     add rd,@rs              clrb rbd                dab rbd
17164
     add rd,addr             com @rd                 dbjnz rbd,disp7
17165
     add rd,addr(rs)         com addr                dec @rd,imm4m1
17166
     add rd,imm16            com addr(rd)            dec addr(rd),imm4m1
17167
     add rd,rs               com rd                  dec addr,imm4m1
17168
     addb rbd,@rs            comb @rd                dec rd,imm4m1
17169
     addb rbd,addr           comb addr               decb @rd,imm4m1
17170
     addb rbd,addr(rs)       comb addr(rd)           decb addr(rd),imm4m1
17171
     addb rbd,imm8           comb rbd                decb addr,imm4m1
17172
     addb rbd,rbs            comflg flags            decb rbd,imm4m1
17173
     addl rrd,@rs            cp @rd,imm16            di i2
17174
     addl rrd,addr           cp addr(rd),imm16       div rrd,@rs
17175
     addl rrd,addr(rs)       cp addr,imm16           div rrd,addr
17176
     addl rrd,imm32          cp rd,@rs               div rrd,addr(rs)
17177
     addl rrd,rrs            cp rd,addr              div rrd,imm16
17178
     and rd,@rs              cp rd,addr(rs)          div rrd,rs
17179
     and rd,addr             cp rd,imm16             divl rqd,@rs
17180
     and rd,addr(rs)         cp rd,rs                divl rqd,addr
17181
     and rd,imm16            cpb @rd,imm8            divl rqd,addr(rs)
17182
     and rd,rs               cpb addr(rd),imm8       divl rqd,imm32
17183
     andb rbd,@rs            cpb addr,imm8           divl rqd,rrs
17184
     andb rbd,addr           cpb rbd,@rs             djnz rd,disp7
17185
     andb rbd,addr(rs)       cpb rbd,addr            ei i2
17186
     andb rbd,imm8           cpb rbd,addr(rs)        ex rd,@rs
17187
     andb rbd,rbs            cpb rbd,imm8            ex rd,addr
17188
     bit @rd,imm4            cpb rbd,rbs             ex rd,addr(rs)
17189
     bit addr(rd),imm4       cpd rd,@rs,rr,cc        ex rd,rs
17190
     bit addr,imm4           cpdb rbd,@rs,rr,cc      exb rbd,@rs
17191
     bit rd,imm4             cpdr rd,@rs,rr,cc       exb rbd,addr
17192
     bit rd,rs               cpdrb rbd,@rs,rr,cc     exb rbd,addr(rs)
17193
     bitb @rd,imm4           cpi rd,@rs,rr,cc        exb rbd,rbs
17194
     bitb addr(rd),imm4      cpib rbd,@rs,rr,cc      ext0e imm8
17195
     bitb addr,imm4          cpir rd,@rs,rr,cc       ext0f imm8
17196
     bitb rbd,imm4           cpirb rbd,@rs,rr,cc     ext8e imm8
17197
     bitb rbd,rs             cpl rrd,@rs             ext8f imm8
17198
     bpt                     cpl rrd,addr            exts rrd
17199
     call @rd                cpl rrd,addr(rs)        extsb rd
17200
     call addr               cpl rrd,imm32           extsl rqd
17201
     call addr(rd)           cpl rrd,rrs             halt
17202
     calr disp12             cpsd @rd,@rs,rr,cc      in rd,@rs
17203
     clr @rd                 cpsdb @rd,@rs,rr,cc     in rd,imm16
17204
     clr addr                cpsdr @rd,@rs,rr,cc     inb rbd,@rs
17205
     clr addr(rd)            cpsdrb @rd,@rs,rr,cc    inb rbd,imm16
17206
     clr rd                  cpsi @rd,@rs,rr,cc      inc @rd,imm4m1
17207
     clrb @rd                cpsib @rd,@rs,rr,cc     inc addr(rd),imm4m1
17208
     inc addr,imm4m1         ldb rbd,rs(rx)          mult rrd,addr(rs)
17209
     inc rd,imm4m1           ldb rd(imm16),rbs       mult rrd,imm16
17210
     incb @rd,imm4m1         ldb rd(rx),rbs          mult rrd,rs
17211
     incb addr(rd),imm4m1    ldctl ctrl,rs           multl rqd,@rs
17212
     incb addr,imm4m1        ldctl rd,ctrl           multl rqd,addr
17213
     incb rbd,imm4m1         ldd @rs,@rd,rr          multl rqd,addr(rs)
17214
     ind @rd,@rs,ra          lddb @rs,@rd,rr         multl rqd,imm32
17215
     indb @rd,@rs,rba        lddr @rs,@rd,rr         multl rqd,rrs
17216
     inib @rd,@rs,ra         lddrb @rs,@rd,rr        neg @rd
17217
     inibr @rd,@rs,ra        ldi @rd,@rs,rr          neg addr
17218
     iret                    ldib @rd,@rs,rr         neg addr(rd)
17219
     jp cc,@rd               ldir @rd,@rs,rr         neg rd
17220
     jp cc,addr              ldirb @rd,@rs,rr        negb @rd
17221
     jp cc,addr(rd)          ldk rd,imm4             negb addr
17222
     jr cc,disp8             ldl @rd,rrs             negb addr(rd)
17223
     ld @rd,imm16            ldl addr(rd),rrs        negb rbd
17224
     ld @rd,rs               ldl addr,rrs            nop
17225
     ld addr(rd),imm16       ldl rd(imm16),rrs       or rd,@rs
17226
     ld addr(rd),rs          ldl rd(rx),rrs          or rd,addr
17227
     ld addr,imm16           ldl rrd,@rs             or rd,addr(rs)
17228
     ld addr,rs              ldl rrd,addr            or rd,imm16
17229
     ld rd(imm16),rs         ldl rrd,addr(rs)        or rd,rs
17230
     ld rd(rx),rs            ldl rrd,imm32           orb rbd,@rs
17231
     ld rd,@rs               ldl rrd,rrs             orb rbd,addr
17232
     ld rd,addr              ldl rrd,rs(imm16)       orb rbd,addr(rs)
17233
     ld rd,addr(rs)          ldl rrd,rs(rx)          orb rbd,imm8
17234
     ld rd,imm16             ldm @rd,rs,n            orb rbd,rbs
17235
     ld rd,rs                ldm addr(rd),rs,n       out @rd,rs
17236
     ld rd,rs(imm16)         ldm addr,rs,n           out imm16,rs
17237
     ld rd,rs(rx)            ldm rd,@rs,n            outb @rd,rbs
17238
     lda rd,addr             ldm rd,addr(rs),n       outb imm16,rbs
17239
     lda rd,addr(rs)         ldm rd,addr,n           outd @rd,@rs,ra
17240
     lda rd,rs(imm16)        ldps @rs                outdb @rd,@rs,rba
17241
     lda rd,rs(rx)           ldps addr               outib @rd,@rs,ra
17242
     ldar rd,disp16          ldps addr(rs)           outibr @rd,@rs,ra
17243
     ldb @rd,imm8            ldr disp16,rs           pop @rd,@rs
17244
     ldb @rd,rbs             ldr rd,disp16           pop addr(rd),@rs
17245
     ldb addr(rd),imm8       ldrb disp16,rbs         pop addr,@rs
17246
     ldb addr(rd),rbs        ldrb rbd,disp16         pop rd,@rs
17247
     ldb addr,imm8           ldrl disp16,rrs         popl @rd,@rs
17248
     ldb addr,rbs            ldrl rrd,disp16         popl addr(rd),@rs
17249
     ldb rbd,@rs             mbit                    popl addr,@rs
17250
     ldb rbd,addr            mreq rd                 popl rrd,@rs
17251
     ldb rbd,addr(rs)        mres                    push @rd,@rs
17252
     ldb rbd,imm8            mset                    push @rd,addr
17253
     ldb rbd,rbs             mult rrd,@rs            push @rd,addr(rs)
17254
     ldb rbd,rs(imm16)       mult rrd,addr           push @rd,imm16
17255
     push @rd,rs             set addr,imm4           subl rrd,imm32
17256
     pushl @rd,@rs           set rd,imm4             subl rrd,rrs
17257
     pushl @rd,addr          set rd,rs               tcc cc,rd
17258
     pushl @rd,addr(rs)      setb @rd,imm4           tccb cc,rbd
17259
     pushl @rd,rrs           setb addr(rd),imm4      test @rd
17260
     res @rd,imm4            setb addr,imm4          test addr
17261
     res addr(rd),imm4       setb rbd,imm4           test addr(rd)
17262
     res addr,imm4           setb rbd,rs             test rd
17263
     res rd,imm4             setflg imm4             testb @rd
17264
     res rd,rs               sinb rbd,imm16          testb addr
17265
     resb @rd,imm4           sinb rd,imm16           testb addr(rd)
17266
     resb addr(rd),imm4      sind @rd,@rs,ra         testb rbd
17267
     resb addr,imm4          sindb @rd,@rs,rba       testl @rd
17268
     resb rbd,imm4           sinib @rd,@rs,ra        testl addr
17269
     resb rbd,rs             sinibr @rd,@rs,ra       testl addr(rd)
17270
     resflg imm4             sla rd,imm8             testl rrd
17271
     ret cc                  slab rbd,imm8           trdb @rd,@rs,rba
17272
     rl rd,imm1or2           slal rrd,imm8           trdrb @rd,@rs,rba
17273
     rlb rbd,imm1or2         sll rd,imm8             trib @rd,@rs,rbr
17274
     rlc rd,imm1or2          sllb rbd,imm8           trirb @rd,@rs,rbr
17275
     rlcb rbd,imm1or2        slll rrd,imm8           trtdrb @ra,@rb,rbr
17276
     rldb rbb,rba            sout imm16,rs           trtib @ra,@rb,rr
17277
     rr rd,imm1or2           soutb imm16,rbs         trtirb @ra,@rb,rbr
17278
     rrb rbd,imm1or2         soutd @rd,@rs,ra        trtrb @ra,@rb,rbr
17279
     rrc rd,imm1or2          soutdb @rd,@rs,rba      tset @rd
17280
     rrcb rbd,imm1or2        soutib @rd,@rs,ra       tset addr
17281
     rrdb rbb,rba            soutibr @rd,@rs,ra      tset addr(rd)
17282
     rsvd36                  sra rd,imm8             tset rd
17283
     rsvd38                  srab rbd,imm8           tsetb @rd
17284
     rsvd78                  sral rrd,imm8           tsetb addr
17285
     rsvd7e                  srl rd,imm8             tsetb addr(rd)
17286
     rsvd9d                  srlb rbd,imm8           tsetb rbd
17287
     rsvd9f                  srll rrd,imm8           xor rd,@rs
17288
     rsvdb9                  sub rd,@rs              xor rd,addr
17289
     rsvdbf                  sub rd,addr             xor rd,addr(rs)
17290
     sbc rd,rs               sub rd,addr(rs)         xor rd,imm16
17291
     sbcb rbd,rbs            sub rd,imm16            xor rd,rs
17292
     sc imm8                 sub rd,rs               xorb rbd,@rs
17293
     sda rd,rs               subb rbd,@rs            xorb rbd,addr
17294
     sdab rbd,rs             subb rbd,addr           xorb rbd,addr(rs)
17295
     sdal rrd,rs             subb rbd,addr(rs)       xorb rbd,imm8
17296
     sdl rd,rs               subb rbd,imm8           xorb rbd,rbs
17297
     sdlb rbd,rs             subb rbd,rbs            xorb rbd,rbs
17298
     sdll rrd,rs             subl rrd,@rs
17299
     set @rd,imm4            subl rrd,addr
17300
     set addr(rd),imm4       subl rrd,addr(rs)
17301
 
17302

17303
File: as.info,  Node: Vax-Dependent,  Prev: Z8000-Dependent,  Up: Machine Dependencies
17304
 
17305
9.38 VAX Dependent Features
17306
===========================
17307
 
17308
* Menu:
17309
 
17310
* VAX-Opts::                    VAX Command-Line Options
17311
* VAX-float::                   VAX Floating Point
17312
* VAX-directives::              Vax Machine Directives
17313
* VAX-opcodes::                 VAX Opcodes
17314
* VAX-branch::                  VAX Branch Improvement
17315
* VAX-operands::                VAX Operands
17316
* VAX-no::                      Not Supported on VAX
17317
 
17318

17319
File: as.info,  Node: VAX-Opts,  Next: VAX-float,  Up: Vax-Dependent
17320
 
17321
9.38.1 VAX Command-Line Options
17322
-------------------------------
17323
 
17324
The Vax version of `as' accepts any of the following options, gives a
17325
warning message that the option was ignored and proceeds.  These
17326
options are for compatibility with scripts designed for other people's
17327
assemblers.
17328
 
17329
``-D' (Debug)'
17330
``-S' (Symbol Table)'
17331
``-T' (Token Trace)'
17332
     These are obsolete options used to debug old assemblers.
17333
 
17334
``-d' (Displacement size for JUMPs)'
17335
     This option expects a number following the `-d'.  Like options
17336
     that expect filenames, the number may immediately follow the `-d'
17337
     (old standard) or constitute the whole of the command line
17338
     argument that follows `-d' (GNU standard).
17339
 
17340
``-V' (Virtualize Interpass Temporary File)'
17341
     Some other assemblers use a temporary file.  This option commanded
17342
     them to keep the information in active memory rather than in a
17343
     disk file.  `as' always does this, so this option is redundant.
17344
 
17345
``-J' (JUMPify Longer Branches)'
17346
     Many 32-bit computers permit a variety of branch instructions to
17347
     do the same job.  Some of these instructions are short (and fast)
17348
     but have a limited range; others are long (and slow) but can
17349
     branch anywhere in virtual memory.  Often there are 3 flavors of
17350
     branch: short, medium and long.  Some other assemblers would emit
17351
     short and medium branches, unless told by this option to emit
17352
     short and long branches.
17353
 
17354
``-t' (Temporary File Directory)'
17355
     Some other assemblers may use a temporary file, and this option
17356
     takes a filename being the directory to site the temporary file.
17357
     Since `as' does not use a temporary disk file, this option makes
17358
     no difference.  `-t' needs exactly one filename.
17359
 
17360
   The Vax version of the assembler accepts additional options when
17361
compiled for VMS:
17362
 
17363
`-h N'
17364
     External symbol or section (used for global variables) names are
17365
     not case sensitive on VAX/VMS and always mapped to upper case.
17366
     This is contrary to the C language definition which explicitly
17367
     distinguishes upper and lower case.  To implement a standard
17368
     conforming C compiler, names must be changed (mapped) to preserve
17369
     the case information.  The default mapping is to convert all lower
17370
     case characters to uppercase and adding an underscore followed by
17371
     a 6 digit hex value, representing a 24 digit binary value.  The
17372
     one digits in the binary value represent which characters are
17373
     uppercase in the original symbol name.
17374
 
17375
     The `-h N' option determines how we map names.  This takes several
17376
     values.  No `-h' switch at all allows case hacking as described
17377
     above.  A value of zero (`-h0') implies names should be upper
17378
     case, and inhibits the case hack.  A value of 2 (`-h2') implies
17379
     names should be all lower case, with no case hack.  A value of 3
17380
     (`-h3') implies that case should be preserved.  The value 1 is
17381
     unused.  The `-H' option directs `as' to display every mapped
17382
     symbol during assembly.
17383
 
17384
     Symbols whose names include a dollar sign `$' are exceptions to the
17385
     general name mapping.  These symbols are normally only used to
17386
     reference VMS library names.  Such symbols are always mapped to
17387
     upper case.
17388
 
17389
`-+'
17390
     The `-+' option causes `as' to truncate any symbol name larger
17391
     than 31 characters.  The `-+' option also prevents some code
17392
     following the `_main' symbol normally added to make the object
17393
     file compatible with Vax-11 "C".
17394
 
17395
`-1'
17396
     This option is ignored for backward compatibility with `as'
17397
     version 1.x.
17398
 
17399
`-H'
17400
     The `-H' option causes `as' to print every symbol which was
17401
     changed by case mapping.
17402
 
17403

17404
File: as.info,  Node: VAX-float,  Next: VAX-directives,  Prev: VAX-Opts,  Up: Vax-Dependent
17405
 
17406
9.38.2 VAX Floating Point
17407
-------------------------
17408
 
17409
Conversion of flonums to floating point is correct, and compatible with
17410
previous assemblers.  Rounding is towards zero if the remainder is
17411
exactly half the least significant bit.
17412
 
17413
   `D', `F', `G' and `H' floating point formats are understood.
17414
 
17415
   Immediate floating literals (_e.g._ `S`$6.9') are rendered
17416
correctly.  Again, rounding is towards zero in the boundary case.
17417
 
17418
   The `.float' directive produces `f' format numbers.  The `.double'
17419
directive produces `d' format numbers.
17420
 
17421

17422
File: as.info,  Node: VAX-directives,  Next: VAX-opcodes,  Prev: VAX-float,  Up: Vax-Dependent
17423
 
17424
9.38.3 Vax Machine Directives
17425
-----------------------------
17426
 
17427
The Vax version of the assembler supports four directives for
17428
generating Vax floating point constants.  They are described in the
17429
table below.
17430
 
17431
`.dfloat'
17432
     This expects zero or more flonums, separated by commas, and
17433
     assembles Vax `d' format 64-bit floating point constants.
17434
 
17435
`.ffloat'
17436
     This expects zero or more flonums, separated by commas, and
17437
     assembles Vax `f' format 32-bit floating point constants.
17438
 
17439
`.gfloat'
17440
     This expects zero or more flonums, separated by commas, and
17441
     assembles Vax `g' format 64-bit floating point constants.
17442
 
17443
`.hfloat'
17444
     This expects zero or more flonums, separated by commas, and
17445
     assembles Vax `h' format 128-bit floating point constants.
17446
 
17447
 
17448

17449
File: as.info,  Node: VAX-opcodes,  Next: VAX-branch,  Prev: VAX-directives,  Up: Vax-Dependent
17450
 
17451
9.38.4 VAX Opcodes
17452
------------------
17453
 
17454
All DEC mnemonics are supported.  Beware that `case...' instructions
17455
have exactly 3 operands.  The dispatch table that follows the `case...'
17456
instruction should be made with `.word' statements.  This is compatible
17457
with all unix assemblers we know of.
17458
 
17459

17460
File: as.info,  Node: VAX-branch,  Next: VAX-operands,  Prev: VAX-opcodes,  Up: Vax-Dependent
17461
 
17462
9.38.5 VAX Branch Improvement
17463
-----------------------------
17464
 
17465
Certain pseudo opcodes are permitted.  They are for branch
17466
instructions.  They expand to the shortest branch instruction that
17467
reaches the target.  Generally these mnemonics are made by substituting
17468
`j' for `b' at the start of a DEC mnemonic.  This feature is included
17469
both for compatibility and to help compilers.  If you do not need this
17470
feature, avoid these opcodes.  Here are the mnemonics, and the code
17471
they can expand into.
17472
 
17473
`jbsb'
17474
     `Jsb' is already an instruction mnemonic, so we chose `jbsb'.
17475
    (byte displacement)
17476
          `bsbb ...'
17477
 
17478
    (word displacement)
17479
          `bsbw ...'
17480
 
17481
    (long displacement)
17482
          `jsb ...'
17483
 
17484
`jbr'
17485
`jr'
17486
     Unconditional branch.
17487
    (byte displacement)
17488
          `brb ...'
17489
 
17490
    (word displacement)
17491
          `brw ...'
17492
 
17493
    (long displacement)
17494
          `jmp ...'
17495
 
17496
`jCOND'
17497
     COND may be any one of the conditional branches `neq', `nequ',
17498
     `eql', `eqlu', `gtr', `geq', `lss', `gtru', `lequ', `vc', `vs',
17499
     `gequ', `cc', `lssu', `cs'.  COND may also be one of the bit tests
17500
     `bs', `bc', `bss', `bcs', `bsc', `bcc', `bssi', `bcci', `lbs',
17501
     `lbc'.  NOTCOND is the opposite condition to COND.
17502
    (byte displacement)
17503
          `bCOND ...'
17504
 
17505
    (word displacement)
17506
          `bNOTCOND foo ; brw ... ; foo:'
17507
 
17508
    (long displacement)
17509
          `bNOTCOND foo ; jmp ... ; foo:'
17510
 
17511
`jacbX'
17512
     X may be one of `b d f g h l w'.
17513
    (word displacement)
17514
          `OPCODE ...'
17515
 
17516
    (long displacement)
17517
               OPCODE ..., foo ;
17518
               brb bar ;
17519
               foo: jmp ... ;
17520
               bar:
17521
 
17522
`jaobYYY'
17523
     YYY may be one of `lss leq'.
17524
 
17525
`jsobZZZ'
17526
     ZZZ may be one of `geq gtr'.
17527
    (byte displacement)
17528
          `OPCODE ...'
17529
 
17530
    (word displacement)
17531
               OPCODE ..., foo ;
17532
               brb bar ;
17533
               foo: brw DESTINATION ;
17534
               bar:
17535
 
17536
    (long displacement)
17537
               OPCODE ..., foo ;
17538
               brb bar ;
17539
               foo: jmp DESTINATION ;
17540
               bar:
17541
 
17542
`aobleq'
17543
`aoblss'
17544
`sobgeq'
17545
`sobgtr'
17546
 
17547
    (byte displacement)
17548
          `OPCODE ...'
17549
 
17550
    (word displacement)
17551
               OPCODE ..., foo ;
17552
               brb bar ;
17553
               foo: brw DESTINATION ;
17554
               bar:
17555
 
17556
    (long displacement)
17557
               OPCODE ..., foo ;
17558
               brb bar ;
17559
               foo: jmp DESTINATION ;
17560
               bar:
17561
 
17562

17563
File: as.info,  Node: VAX-operands,  Next: VAX-no,  Prev: VAX-branch,  Up: Vax-Dependent
17564
 
17565
9.38.6 VAX Operands
17566
-------------------
17567
 
17568
The immediate character is `$' for Unix compatibility, not `#' as DEC
17569
writes it.
17570
 
17571
   The indirect character is `*' for Unix compatibility, not `@' as DEC
17572
writes it.
17573
 
17574
   The displacement sizing character is ``' (an accent grave) for Unix
17575
compatibility, not `^' as DEC writes it.  The letter preceding ``' may
17576
have either case.  `G' is not understood, but all other letters (`b i l
17577
s w') are understood.
17578
 
17579
   Register names understood are `r0 r1 r2 ... r15 ap fp sp pc'.  Upper
17580
and lower case letters are equivalent.
17581
 
17582
   For instance
17583
     tstb *w`$4(r5)
17584
 
17585
   Any expression is permitted in an operand.  Operands are comma
17586
separated.
17587
 
17588

17589
File: as.info,  Node: VAX-no,  Prev: VAX-operands,  Up: Vax-Dependent
17590
 
17591
9.38.7 Not Supported on VAX
17592
---------------------------
17593
 
17594
Vax bit fields can not be assembled with `as'.  Someone can add the
17595
required code if they really need it.
17596
 
17597

17598
File: as.info,  Node: V850-Dependent,  Next: Xtensa-Dependent,  Prev: TIC54X-Dependent,  Up: Machine Dependencies
17599
 
17600
9.39 v850 Dependent Features
17601
============================
17602
 
17603
* Menu:
17604
 
17605
* V850 Options::              Options
17606
* V850 Syntax::               Syntax
17607
* V850 Floating Point::       Floating Point
17608
* V850 Directives::           V850 Machine Directives
17609
* V850 Opcodes::              Opcodes
17610
 
17611

17612
File: as.info,  Node: V850 Options,  Next: V850 Syntax,  Up: V850-Dependent
17613
 
17614
9.39.1 Options
17615
--------------
17616
 
17617
`as' supports the following additional command-line options for the
17618
V850 processor family:
17619
 
17620
`-wsigned_overflow'
17621
     Causes warnings to be produced when signed immediate values
17622
     overflow the space available for then within their opcodes.  By
17623
     default this option is disabled as it is possible to receive
17624
     spurious warnings due to using exact bit patterns as immediate
17625
     constants.
17626
 
17627
`-wunsigned_overflow'
17628
     Causes warnings to be produced when unsigned immediate values
17629
     overflow the space available for then within their opcodes.  By
17630
     default this option is disabled as it is possible to receive
17631
     spurious warnings due to using exact bit patterns as immediate
17632
     constants.
17633
 
17634
`-mv850'
17635
     Specifies that the assembled code should be marked as being
17636
     targeted at the V850 processor.  This allows the linker to detect
17637
     attempts to link such code with code assembled for other
17638
     processors.
17639
 
17640
`-mv850e'
17641
     Specifies that the assembled code should be marked as being
17642
     targeted at the V850E processor.  This allows the linker to detect
17643
     attempts to link such code with code assembled for other
17644
     processors.
17645
 
17646
`-mv850e1'
17647
     Specifies that the assembled code should be marked as being
17648
     targeted at the V850E1 processor.  This allows the linker to
17649
     detect attempts to link such code with code assembled for other
17650
     processors.
17651
 
17652
`-mv850any'
17653
     Specifies that the assembled code should be marked as being
17654
     targeted at the V850 processor but support instructions that are
17655
     specific to the extended variants of the process.  This allows the
17656
     production of binaries that contain target specific code, but
17657
     which are also intended to be used in a generic fashion.  For
17658
     example libgcc.a contains generic routines used by the code
17659
     produced by GCC for all versions of the v850 architecture,
17660
     together with support routines only used by the V850E architecture.
17661
 
17662
`-mrelax'
17663
     Enables relaxation.  This allows the .longcall and .longjump pseudo
17664
     ops to be used in the assembler source code.  These ops label
17665
     sections of code which are either a long function call or a long
17666
     branch.  The assembler will then flag these sections of code and
17667
     the linker will attempt to relax them.
17668
 
17669
 
17670

17671
File: as.info,  Node: V850 Syntax,  Next: V850 Floating Point,  Prev: V850 Options,  Up: V850-Dependent
17672
 
17673
9.39.2 Syntax
17674
-------------
17675
 
17676
* Menu:
17677
 
17678
* V850-Chars::                Special Characters
17679
* V850-Regs::                 Register Names
17680
 
17681

17682
File: as.info,  Node: V850-Chars,  Next: V850-Regs,  Up: V850 Syntax
17683
 
17684
9.39.2.1 Special Characters
17685
...........................
17686
 
17687
`#' is the line comment character.
17688
 
17689

17690
File: as.info,  Node: V850-Regs,  Prev: V850-Chars,  Up: V850 Syntax
17691
 
17692
9.39.2.2 Register Names
17693
.......................
17694
 
17695
`as' supports the following names for registers:
17696
`general register 0'
17697
     r0, zero
17698
 
17699
`general register 1'
17700
     r1
17701
 
17702
`general register 2'
17703
     r2, hp
17704
 
17705
`general register 3'
17706
     r3, sp
17707
 
17708
`general register 4'
17709
     r4, gp
17710
 
17711
`general register 5'
17712
     r5, tp
17713
 
17714
`general register 6'
17715
     r6
17716
 
17717
`general register 7'
17718
     r7
17719
 
17720
`general register 8'
17721
     r8
17722
 
17723
`general register 9'
17724
     r9
17725
 
17726
`general register 10'
17727
     r10
17728
 
17729
`general register 11'
17730
     r11
17731
 
17732
`general register 12'
17733
     r12
17734
 
17735
`general register 13'
17736
     r13
17737
 
17738
`general register 14'
17739
     r14
17740
 
17741
`general register 15'
17742
     r15
17743
 
17744
`general register 16'
17745
     r16
17746
 
17747
`general register 17'
17748
     r17
17749
 
17750
`general register 18'
17751
     r18
17752
 
17753
`general register 19'
17754
     r19
17755
 
17756
`general register 20'
17757
     r20
17758
 
17759
`general register 21'
17760
     r21
17761
 
17762
`general register 22'
17763
     r22
17764
 
17765
`general register 23'
17766
     r23
17767
 
17768
`general register 24'
17769
     r24
17770
 
17771
`general register 25'
17772
     r25
17773
 
17774
`general register 26'
17775
     r26
17776
 
17777
`general register 27'
17778
     r27
17779
 
17780
`general register 28'
17781
     r28
17782
 
17783
`general register 29'
17784
     r29
17785
 
17786
`general register 30'
17787
     r30, ep
17788
 
17789
`general register 31'
17790
     r31, lp
17791
 
17792
`system register 0'
17793
     eipc
17794
 
17795
`system register 1'
17796
     eipsw
17797
 
17798
`system register 2'
17799
     fepc
17800
 
17801
`system register 3'
17802
     fepsw
17803
 
17804
`system register 4'
17805
     ecr
17806
 
17807
`system register 5'
17808
     psw
17809
 
17810
`system register 16'
17811
     ctpc
17812
 
17813
`system register 17'
17814
     ctpsw
17815
 
17816
`system register 18'
17817
     dbpc
17818
 
17819
`system register 19'
17820
     dbpsw
17821
 
17822
`system register 20'
17823
     ctbp
17824
 
17825

17826
File: as.info,  Node: V850 Floating Point,  Next: V850 Directives,  Prev: V850 Syntax,  Up: V850-Dependent
17827
 
17828
9.39.3 Floating Point
17829
---------------------
17830
 
17831
The V850 family uses IEEE floating-point numbers.
17832
 
17833

17834
File: as.info,  Node: V850 Directives,  Next: V850 Opcodes,  Prev: V850 Floating Point,  Up: V850-Dependent
17835
 
17836
9.39.4 V850 Machine Directives
17837
------------------------------
17838
 
17839
`.offset '
17840
     Moves the offset into the current section to the specified amount.
17841
 
17842
`.section "name", '
17843
     This is an extension to the standard .section directive.  It sets
17844
     the current section to be  and creates an alias for this
17845
     section called "name".
17846
 
17847
`.v850'
17848
     Specifies that the assembled code should be marked as being
17849
     targeted at the V850 processor.  This allows the linker to detect
17850
     attempts to link such code with code assembled for other
17851
     processors.
17852
 
17853
`.v850e'
17854
     Specifies that the assembled code should be marked as being
17855
     targeted at the V850E processor.  This allows the linker to detect
17856
     attempts to link such code with code assembled for other
17857
     processors.
17858
 
17859
`.v850e1'
17860
     Specifies that the assembled code should be marked as being
17861
     targeted at the V850E1 processor.  This allows the linker to
17862
     detect attempts to link such code with code assembled for other
17863
     processors.
17864
 
17865
 
17866

17867
File: as.info,  Node: V850 Opcodes,  Prev: V850 Directives,  Up: V850-Dependent
17868
 
17869
9.39.5 Opcodes
17870
--------------
17871
 
17872
`as' implements all the standard V850 opcodes.
17873
 
17874
   `as' also implements the following pseudo ops:
17875
 
17876
`hi0()'
17877
     Computes the higher 16 bits of the given expression and stores it
17878
     into the immediate operand field of the given instruction.  For
17879
     example:
17880
 
17881
     `mulhi hi0(here - there), r5, r6'
17882
 
17883
     computes the difference between the address of labels 'here' and
17884
     'there', takes the upper 16 bits of this difference, shifts it
17885
     down 16 bits and then multiplies it by the lower 16 bits in
17886
     register 5, putting the result into register 6.
17887
 
17888
`lo()'
17889
     Computes the lower 16 bits of the given expression and stores it
17890
     into the immediate operand field of the given instruction.  For
17891
     example:
17892
 
17893
     `addi lo(here - there), r5, r6'
17894
 
17895
     computes the difference between the address of labels 'here' and
17896
     'there', takes the lower 16 bits of this difference and adds it to
17897
     register 5, putting the result into register 6.
17898
 
17899
`hi()'
17900
     Computes the higher 16 bits of the given expression and then adds
17901
     the value of the most significant bit of the lower 16 bits of the
17902
     expression and stores the result into the immediate operand field
17903
     of the given instruction.  For example the following code can be
17904
     used to compute the address of the label 'here' and store it into
17905
     register 6:
17906
 
17907
     `movhi hi(here), r0, r6'     `movea lo(here), r6, r6'
17908
 
17909
     The reason for this special behaviour is that movea performs a sign
17910
     extension on its immediate operand.  So for example if the address
17911
     of 'here' was 0xFFFFFFFF then without the special behaviour of the
17912
     hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6,
17913
     then the movea instruction would takes its immediate operand,
17914
     0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it
17915
     into r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E).
17916
     With the hi() pseudo op adding in the top bit of the lo() pseudo
17917
     op, the movhi instruction actually stores 0 into r6 (0xFFFF + 1 =
17918
     0x0000), so that the movea instruction stores 0xFFFFFFFF into r6 -
17919
     the right value.
17920
 
17921
`hilo()'
17922
     Computes the 32 bit value of the given expression and stores it
17923
     into the immediate operand field of the given instruction (which
17924
     must be a mov instruction).  For example:
17925
 
17926
     `mov hilo(here), r6'
17927
 
17928
     computes the absolute address of label 'here' and puts the result
17929
     into register 6.
17930
 
17931
`sdaoff()'
17932
     Computes the offset of the named variable from the start of the
17933
     Small Data Area (whoes address is held in register 4, the GP
17934
     register) and stores the result as a 16 bit signed value in the
17935
     immediate operand field of the given instruction.  For example:
17936
 
17937
     `ld.w sdaoff(_a_variable)[gp],r6'
17938
 
17939
     loads the contents of the location pointed to by the label
17940
     '_a_variable' into register 6, provided that the label is located
17941
     somewhere within +/- 32K of the address held in the GP register.
17942
     [Note the linker assumes that the GP register contains a fixed
17943
     address set to the address of the label called '__gp'.  This can
17944
     either be set up automatically by the linker, or specifically set
17945
     by using the `--defsym __gp=' command line option].
17946
 
17947
`tdaoff()'
17948
     Computes the offset of the named variable from the start of the
17949
     Tiny Data Area (whoes address is held in register 30, the EP
17950
     register) and stores the result as a 4,5, 7 or 8 bit unsigned
17951
     value in the immediate operand field of the given instruction.
17952
     For example:
17953
 
17954
     `sld.w tdaoff(_a_variable)[ep],r6'
17955
 
17956
     loads the contents of the location pointed to by the label
17957
     '_a_variable' into register 6, provided that the label is located
17958
     somewhere within +256 bytes of the address held in the EP
17959
     register.  [Note the linker assumes that the EP register contains
17960
     a fixed address set to the address of the label called '__ep'.
17961
     This can either be set up automatically by the linker, or
17962
     specifically set by using the `--defsym __ep=' command line
17963
     option].
17964
 
17965
`zdaoff()'
17966
     Computes the offset of the named variable from address 0 and
17967
     stores the result as a 16 bit signed value in the immediate
17968
     operand field of the given instruction.  For example:
17969
 
17970
     `movea zdaoff(_a_variable),zero,r6'
17971
 
17972
     puts the address of the label '_a_variable' into register 6,
17973
     assuming that the label is somewhere within the first 32K of
17974
     memory.  (Strictly speaking it also possible to access the last
17975
     32K of memory as well, as the offsets are signed).
17976
 
17977
`ctoff()'
17978
     Computes the offset of the named variable from the start of the
17979
     Call Table Area (whoes address is helg in system register 20, the
17980
     CTBP register) and stores the result a 6 or 16 bit unsigned value
17981
     in the immediate field of then given instruction or piece of data.
17982
     For example:
17983
 
17984
     `callt ctoff(table_func1)'
17985
 
17986
     will put the call the function whoes address is held in the call
17987
     table at the location labeled 'table_func1'.
17988
 
17989
`.longcall `name''
17990
     Indicates that the following sequence of instructions is a long
17991
     call to function `name'.  The linker will attempt to shorten this
17992
     call sequence if `name' is within a 22bit offset of the call.  Only
17993
     valid if the `-mrelax' command line switch has been enabled.
17994
 
17995
`.longjump `name''
17996
     Indicates that the following sequence of instructions is a long
17997
     jump to label `name'.  The linker will attempt to shorten this code
17998
     sequence if `name' is within a 22bit offset of the jump.  Only
17999
     valid if the `-mrelax' command line switch has been enabled.
18000
 
18001
 
18002
   For information on the V850 instruction set, see `V850 Family
18003
32-/16-Bit single-Chip Microcontroller Architecture Manual' from NEC.
18004
Ltd.
18005
 
18006

18007
File: as.info,  Node: Xtensa-Dependent,  Next: Z80-Dependent,  Prev: V850-Dependent,  Up: Machine Dependencies
18008
 
18009
9.40 Xtensa Dependent Features
18010
==============================
18011
 
18012
   This chapter covers features of the GNU assembler that are specific
18013
to the Xtensa architecture.  For details about the Xtensa instruction
18014
set, please consult the `Xtensa Instruction Set Architecture (ISA)
18015
Reference Manual'.
18016
 
18017
* Menu:
18018
 
18019
* Xtensa Options::              Command-line Options.
18020
* Xtensa Syntax::               Assembler Syntax for Xtensa Processors.
18021
* Xtensa Optimizations::        Assembler Optimizations.
18022
* Xtensa Relaxation::           Other Automatic Transformations.
18023
* Xtensa Directives::           Directives for Xtensa Processors.
18024
 
18025

18026
File: as.info,  Node: Xtensa Options,  Next: Xtensa Syntax,  Up: Xtensa-Dependent
18027
 
18028
9.40.1 Command Line Options
18029
---------------------------
18030
 
18031
The Xtensa version of the GNU assembler supports these special options:
18032
 
18033
`--text-section-literals | --no-text-section-literals'
18034
     Control the treatment of literal pools.  The default is
18035
     `--no-text-section-literals', which places literals in separate
18036
     sections in the output file.  This allows the literal pool to be
18037
     placed in a data RAM/ROM.  With `--text-section-literals', the
18038
     literals are interspersed in the text section in order to keep
18039
     them as close as possible to their references.  This may be
18040
     necessary for large assembly files, where the literals would
18041
     otherwise be out of range of the `L32R' instructions in the text
18042
     section.  These options only affect literals referenced via
18043
     PC-relative `L32R' instructions; literals for absolute mode `L32R'
18044
     instructions are handled separately.  *Note literal: Literal
18045
     Directive.
18046
 
18047
`--absolute-literals | --no-absolute-literals'
18048
     Indicate to the assembler whether `L32R' instructions use absolute
18049
     or PC-relative addressing.  If the processor includes the absolute
18050
     addressing option, the default is to use absolute `L32R'
18051
     relocations.  Otherwise, only the PC-relative `L32R' relocations
18052
     can be used.
18053
 
18054
`--target-align | --no-target-align'
18055
     Enable or disable automatic alignment to reduce branch penalties
18056
     at some expense in code size.  *Note Automatic Instruction
18057
     Alignment: Xtensa Automatic Alignment.  This optimization is
18058
     enabled by default.  Note that the assembler will always align
18059
     instructions like `LOOP' that have fixed alignment requirements.
18060
 
18061
`--longcalls | --no-longcalls'
18062
     Enable or disable transformation of call instructions to allow
18063
     calls across a greater range of addresses.  *Note Function Call
18064
     Relaxation: Xtensa Call Relaxation.  This option should be used
18065
     when call targets can potentially be out of range.  It may degrade
18066
     both code size and performance, but the linker can generally
18067
     optimize away the unnecessary overhead when a call ends up within
18068
     range.  The default is `--no-longcalls'.
18069
 
18070
`--transform | --no-transform'
18071
     Enable or disable all assembler transformations of Xtensa
18072
     instructions, including both relaxation and optimization.  The
18073
     default is `--transform'; `--no-transform' should only be used in
18074
     the rare cases when the instructions must be exactly as specified
18075
     in the assembly source.  Using `--no-transform' causes out of range
18076
     instruction operands to be errors.
18077
 
18078
`--rename-section OLDNAME=NEWNAME'
18079
     Rename the OLDNAME section to NEWNAME.  This option can be used
18080
     multiple times to rename multiple sections.
18081
 
18082

18083
File: as.info,  Node: Xtensa Syntax,  Next: Xtensa Optimizations,  Prev: Xtensa Options,  Up: Xtensa-Dependent
18084
 
18085
9.40.2 Assembler Syntax
18086
-----------------------
18087
 
18088
Block comments are delimited by `/*' and `*/'.  End of line comments
18089
may be introduced with either `#' or `//'.
18090
 
18091
   Instructions consist of a leading opcode or macro name followed by
18092
whitespace and an optional comma-separated list of operands:
18093
 
18094
     OPCODE [OPERAND, ...]
18095
 
18096
   Instructions must be separated by a newline or semicolon.
18097
 
18098
   FLIX instructions, which bundle multiple opcodes together in a single
18099
instruction, are specified by enclosing the bundled opcodes inside
18100
braces:
18101
 
18102
     {
18103
     [FORMAT]
18104
     OPCODE0 [OPERANDS]
18105
     OPCODE1 [OPERANDS]
18106
     OPCODE2 [OPERANDS]
18107
     ...
18108
     }
18109
 
18110
   The opcodes in a FLIX instruction are listed in the same order as the
18111
corresponding instruction slots in the TIE format declaration.
18112
Directives and labels are not allowed inside the braces of a FLIX
18113
instruction.  A particular TIE format name can optionally be specified
18114
immediately after the opening brace, but this is usually unnecessary.
18115
The assembler will automatically search for a format that can encode the
18116
specified opcodes, so the format name need only be specified in rare
18117
cases where there is more than one applicable format and where it
18118
matters which of those formats is used.  A FLIX instruction can also be
18119
specified on a single line by separating the opcodes with semicolons:
18120
 
18121
     { [FORMAT;] OPCODE0 [OPERANDS]; OPCODE1 [OPERANDS]; OPCODE2 [OPERANDS]; ... }
18122
 
18123
   If an opcode can only be encoded in a FLIX instruction but is not
18124
specified as part of a FLIX bundle, the assembler will choose the
18125
smallest format where the opcode can be encoded and will fill unused
18126
instruction slots with no-ops.
18127
 
18128
* Menu:
18129
 
18130
* Xtensa Opcodes::              Opcode Naming Conventions.
18131
* Xtensa Registers::            Register Naming.
18132
 
18133

18134
File: as.info,  Node: Xtensa Opcodes,  Next: Xtensa Registers,  Up: Xtensa Syntax
18135
 
18136
9.40.2.1 Opcode Names
18137
.....................
18138
 
18139
See the `Xtensa Instruction Set Architecture (ISA) Reference Manual'
18140
for a complete list of opcodes and descriptions of their semantics.
18141
 
18142
   If an opcode name is prefixed with an underscore character (`_'),
18143
`as' will not transform that instruction in any way.  The underscore
18144
prefix disables both optimization (*note Xtensa Optimizations: Xtensa
18145
Optimizations.) and relaxation (*note Xtensa Relaxation: Xtensa
18146
Relaxation.) for that particular instruction.  Only use the underscore
18147
prefix when it is essential to select the exact opcode produced by the
18148
assembler.  Using this feature unnecessarily makes the code less
18149
efficient by disabling assembler optimization and less flexible by
18150
disabling relaxation.
18151
 
18152
   Note that this special handling of underscore prefixes only applies
18153
to Xtensa opcodes, not to either built-in macros or user-defined macros.
18154
When an underscore prefix is used with a macro (e.g., `_MOV'), it
18155
refers to a different macro.  The assembler generally provides built-in
18156
macros both with and without the underscore prefix, where the underscore
18157
versions behave as if the underscore carries through to the instructions
18158
in the macros.  For example, `_MOV' may expand to `_MOV.N'.
18159
 
18160
   The underscore prefix only applies to individual instructions, not to
18161
series of instructions.  For example, if a series of instructions have
18162
underscore prefixes, the assembler will not transform the individual
18163
instructions, but it may insert other instructions between them (e.g.,
18164
to align a `LOOP' instruction).  To prevent the assembler from
18165
modifying a series of instructions as a whole, use the `no-transform'
18166
directive.  *Note transform: Transform Directive.
18167
 
18168

18169
File: as.info,  Node: Xtensa Registers,  Prev: Xtensa Opcodes,  Up: Xtensa Syntax
18170
 
18171
9.40.2.2 Register Names
18172
.......................
18173
 
18174
The assembly syntax for a register file entry is the "short" name for a
18175
TIE register file followed by the index into that register file.  For
18176
example, the general-purpose `AR' register file has a short name of
18177
`a', so these registers are named `a0'...`a15'.  As a special feature,
18178
`sp' is also supported as a synonym for `a1'.  Additional registers may
18179
be added by processor configuration options and by designer-defined TIE
18180
extensions.  An initial `$' character is optional in all register names.
18181
 
18182

18183
File: as.info,  Node: Xtensa Optimizations,  Next: Xtensa Relaxation,  Prev: Xtensa Syntax,  Up: Xtensa-Dependent
18184
 
18185
9.40.3 Xtensa Optimizations
18186
---------------------------
18187
 
18188
The optimizations currently supported by `as' are generation of density
18189
instructions where appropriate and automatic branch target alignment.
18190
 
18191
* Menu:
18192
 
18193
* Density Instructions::        Using Density Instructions.
18194
* Xtensa Automatic Alignment::  Automatic Instruction Alignment.
18195
 
18196

18197
File: as.info,  Node: Density Instructions,  Next: Xtensa Automatic Alignment,  Up: Xtensa Optimizations
18198
 
18199
9.40.3.1 Using Density Instructions
18200
...................................
18201
 
18202
The Xtensa instruction set has a code density option that provides
18203
16-bit versions of some of the most commonly used opcodes.  Use of these
18204
opcodes can significantly reduce code size.  When possible, the
18205
assembler automatically translates instructions from the core Xtensa
18206
instruction set into equivalent instructions from the Xtensa code
18207
density option.  This translation can be disabled by using underscore
18208
prefixes (*note Opcode Names: Xtensa Opcodes.), by using the
18209
`--no-transform' command-line option (*note Command Line Options:
18210
Xtensa Options.), or by using the `no-transform' directive (*note
18211
transform: Transform Directive.).
18212
 
18213
   It is a good idea _not_ to use the density instructions directly.
18214
The assembler will automatically select dense instructions where
18215
possible.  If you later need to use an Xtensa processor without the code
18216
density option, the same assembly code will then work without
18217
modification.
18218
 
18219

18220
File: as.info,  Node: Xtensa Automatic Alignment,  Prev: Density Instructions,  Up: Xtensa Optimizations
18221
 
18222
9.40.3.2 Automatic Instruction Alignment
18223
........................................
18224
 
18225
The Xtensa assembler will automatically align certain instructions, both
18226
to optimize performance and to satisfy architectural requirements.
18227
 
18228
   As an optimization to improve performance, the assembler attempts to
18229
align branch targets so they do not cross instruction fetch boundaries.
18230
(Xtensa processors can be configured with either 32-bit or 64-bit
18231
instruction fetch widths.)  An instruction immediately following a call
18232
is treated as a branch target in this context, because it will be the
18233
target of a return from the call.  This alignment has the potential to
18234
reduce branch penalties at some expense in code size.  This
18235
optimization is enabled by default.  You can disable it with the
18236
`--no-target-align' command-line option (*note Command Line Options:
18237
Xtensa Options.).
18238
 
18239
   The target alignment optimization is done without adding instructions
18240
that could increase the execution time of the program.  If there are
18241
density instructions in the code preceding a target, the assembler can
18242
change the target alignment by widening some of those instructions to
18243
the equivalent 24-bit instructions.  Extra bytes of padding can be
18244
inserted immediately following unconditional jump and return
18245
instructions.  This approach is usually successful in aligning many,
18246
but not all, branch targets.
18247
 
18248
   The `LOOP' family of instructions must be aligned such that the
18249
first instruction in the loop body does not cross an instruction fetch
18250
boundary (e.g., with a 32-bit fetch width, a `LOOP' instruction must be
18251
on either a 1 or 2 mod 4 byte boundary).  The assembler knows about
18252
this restriction and inserts the minimal number of 2 or 3 byte no-op
18253
instructions to satisfy it.  When no-op instructions are added, any
18254
label immediately preceding the original loop will be moved in order to
18255
refer to the loop instruction, not the newly generated no-op
18256
instruction.  To preserve binary compatibility across processors with
18257
different fetch widths, the assembler conservatively assumes a 32-bit
18258
fetch width when aligning `LOOP' instructions (except if the first
18259
instruction in the loop is a 64-bit instruction).
18260
 
18261
   Previous versions of the assembler automatically aligned `ENTRY'
18262
instructions to 4-byte boundaries, but that alignment is now the
18263
programmer's responsibility.
18264
 
18265

18266
File: as.info,  Node: Xtensa Relaxation,  Next: Xtensa Directives,  Prev: Xtensa Optimizations,  Up: Xtensa-Dependent
18267
 
18268
9.40.4 Xtensa Relaxation
18269
------------------------
18270
 
18271
When an instruction operand is outside the range allowed for that
18272
particular instruction field, `as' can transform the code to use a
18273
functionally-equivalent instruction or sequence of instructions.  This
18274
process is known as "relaxation".  This is typically done for branch
18275
instructions because the distance of the branch targets is not known
18276
until assembly-time.  The Xtensa assembler offers branch relaxation and
18277
also extends this concept to function calls, `MOVI' instructions and
18278
other instructions with immediate fields.
18279
 
18280
* Menu:
18281
 
18282
* Xtensa Branch Relaxation::        Relaxation of Branches.
18283
* Xtensa Call Relaxation::          Relaxation of Function Calls.
18284
* Xtensa Immediate Relaxation::     Relaxation of other Immediate Fields.
18285
 
18286

18287
File: as.info,  Node: Xtensa Branch Relaxation,  Next: Xtensa Call Relaxation,  Up: Xtensa Relaxation
18288
 
18289
9.40.4.1 Conditional Branch Relaxation
18290
......................................
18291
 
18292
When the target of a branch is too far away from the branch itself,
18293
i.e., when the offset from the branch to the target is too large to fit
18294
in the immediate field of the branch instruction, it may be necessary to
18295
replace the branch with a branch around a jump.  For example,
18296
 
18297
         beqz    a2, L
18298
 
18299
   may result in:
18300
 
18301
         bnez.n  a2, M
18302
         j L
18303
     M:
18304
 
18305
   (The `BNEZ.N' instruction would be used in this example only if the
18306
density option is available.  Otherwise, `BNEZ' would be used.)
18307
 
18308
   This relaxation works well because the unconditional jump instruction
18309
has a much larger offset range than the various conditional branches.
18310
However, an error will occur if a branch target is beyond the range of a
18311
jump instruction.  `as' cannot relax unconditional jumps.  Similarly,
18312
an error will occur if the original input contains an unconditional
18313
jump to a target that is out of range.
18314
 
18315
   Branch relaxation is enabled by default.  It can be disabled by using
18316
underscore prefixes (*note Opcode Names: Xtensa Opcodes.), the
18317
`--no-transform' command-line option (*note Command Line Options:
18318
Xtensa Options.), or the `no-transform' directive (*note transform:
18319
Transform Directive.).
18320
 
18321

18322
File: as.info,  Node: Xtensa Call Relaxation,  Next: Xtensa Immediate Relaxation,  Prev: Xtensa Branch Relaxation,  Up: Xtensa Relaxation
18323
 
18324
9.40.4.2 Function Call Relaxation
18325
.................................
18326
 
18327
Function calls may require relaxation because the Xtensa immediate call
18328
instructions (`CALL0', `CALL4', `CALL8' and `CALL12') provide a
18329
PC-relative offset of only 512 Kbytes in either direction.  For larger
18330
programs, it may be necessary to use indirect calls (`CALLX0',
18331
`CALLX4', `CALLX8' and `CALLX12') where the target address is specified
18332
in a register.  The Xtensa assembler can automatically relax immediate
18333
call instructions into indirect call instructions.  This relaxation is
18334
done by loading the address of the called function into the callee's
18335
return address register and then using a `CALLX' instruction.  So, for
18336
example:
18337
 
18338
         call8 func
18339
 
18340
   might be relaxed to:
18341
 
18342
         .literal .L1, func
18343
         l32r    a8, .L1
18344
         callx8  a8
18345
 
18346
   Because the addresses of targets of function calls are not generally
18347
known until link-time, the assembler must assume the worst and relax all
18348
the calls to functions in other source files, not just those that really
18349
will be out of range.  The linker can recognize calls that were
18350
unnecessarily relaxed, and it will remove the overhead introduced by the
18351
assembler for those cases where direct calls are sufficient.
18352
 
18353
   Call relaxation is disabled by default because it can have a negative
18354
effect on both code size and performance, although the linker can
18355
usually eliminate the unnecessary overhead.  If a program is too large
18356
and some of the calls are out of range, function call relaxation can be
18357
enabled using the `--longcalls' command-line option or the `longcalls'
18358
directive (*note longcalls: Longcalls Directive.).
18359
 
18360

18361
File: as.info,  Node: Xtensa Immediate Relaxation,  Prev: Xtensa Call Relaxation,  Up: Xtensa Relaxation
18362
 
18363
9.40.4.3 Other Immediate Field Relaxation
18364
.........................................
18365
 
18366
The assembler normally performs the following other relaxations.  They
18367
can be disabled by using underscore prefixes (*note Opcode Names:
18368
Xtensa Opcodes.), the `--no-transform' command-line option (*note
18369
Command Line Options: Xtensa Options.), or the `no-transform' directive
18370
(*note transform: Transform Directive.).
18371
 
18372
   The `MOVI' machine instruction can only materialize values in the
18373
range from -2048 to 2047.  Values outside this range are best
18374
materialized with `L32R' instructions.  Thus:
18375
 
18376
         movi a0, 100000
18377
 
18378
   is assembled into the following machine code:
18379
 
18380
         .literal .L1, 100000
18381
         l32r a0, .L1
18382
 
18383
   The `L8UI' machine instruction can only be used with immediate
18384
offsets in the range from 0 to 255. The `L16SI' and `L16UI' machine
18385
instructions can only be used with offsets from 0 to 510.  The `L32I'
18386
machine instruction can only be used with offsets from 0 to 1020.  A
18387
load offset outside these ranges can be materialized with an `L32R'
18388
instruction if the destination register of the load is different than
18389
the source address register.  For example:
18390
 
18391
         l32i a1, a0, 2040
18392
 
18393
   is translated to:
18394
 
18395
         .literal .L1, 2040
18396
         l32r a1, .L1
18397
         add a1, a0, a1
18398
         l32i a1, a1, 0
18399
 
18400
If the load destination and source address register are the same, an
18401
out-of-range offset causes an error.
18402
 
18403
   The Xtensa `ADDI' instruction only allows immediate operands in the
18404
range from -128 to 127.  There are a number of alternate instruction
18405
sequences for the `ADDI' operation.  First, if the immediate is 0, the
18406
`ADDI' will be turned into a `MOV.N' instruction (or the equivalent
18407
`OR' instruction if the code density option is not available).  If the
18408
`ADDI' immediate is outside of the range -128 to 127, but inside the
18409
range -32896 to 32639, an `ADDMI' instruction or `ADDMI'/`ADDI'
18410
sequence will be used.  Finally, if the immediate is outside of this
18411
range and a free register is available, an `L32R'/`ADD' sequence will
18412
be used with a literal allocated from the literal pool.
18413
 
18414
   For example:
18415
 
18416
         addi    a5, a6, 0
18417
         addi    a5, a6, 512
18418
         addi    a5, a6, 513
18419
         addi    a5, a6, 50000
18420
 
18421
   is assembled into the following:
18422
 
18423
         .literal .L1, 50000
18424
         mov.n   a5, a6
18425
         addmi   a5, a6, 0x200
18426
         addmi   a5, a6, 0x200
18427
         addi    a5, a5, 1
18428
         l32r    a5, .L1
18429
         add     a5, a6, a5
18430
 
18431

18432
File: as.info,  Node: Xtensa Directives,  Prev: Xtensa Relaxation,  Up: Xtensa-Dependent
18433
 
18434
9.40.5 Directives
18435
-----------------
18436
 
18437
The Xtensa assembler supports a region-based directive syntax:
18438
 
18439
         .begin DIRECTIVE [OPTIONS]
18440
         ...
18441
         .end DIRECTIVE
18442
 
18443
   All the Xtensa-specific directives that apply to a region of code use
18444
this syntax.
18445
 
18446
   The directive applies to code between the `.begin' and the `.end'.
18447
The state of the option after the `.end' reverts to what it was before
18448
the `.begin'.  A nested `.begin'/`.end' region can further change the
18449
state of the directive without having to be aware of its outer state.
18450
For example, consider:
18451
 
18452
         .begin no-transform
18453
     L:  add a0, a1, a2
18454
         .begin transform
18455
     M:  add a0, a1, a2
18456
         .end transform
18457
     N:  add a0, a1, a2
18458
         .end no-transform
18459
 
18460
   The `ADD' opcodes at `L' and `N' in the outer `no-transform' region
18461
both result in `ADD' machine instructions, but the assembler selects an
18462
`ADD.N' instruction for the `ADD' at `M' in the inner `transform'
18463
region.
18464
 
18465
   The advantage of this style is that it works well inside macros
18466
which can preserve the context of their callers.
18467
 
18468
   The following directives are available:
18469
 
18470
* Menu:
18471
 
18472
* Schedule Directive::         Enable instruction scheduling.
18473
* Longcalls Directive::        Use Indirect Calls for Greater Range.
18474
* Transform Directive::        Disable All Assembler Transformations.
18475
* Literal Directive::          Intermix Literals with Instructions.
18476
* Literal Position Directive:: Specify Inline Literal Pool Locations.
18477
* Literal Prefix Directive::   Specify Literal Section Name Prefix.
18478
* Absolute Literals Directive:: Control PC-Relative vs. Absolute Literals.
18479
 
18480

18481
File: as.info,  Node: Schedule Directive,  Next: Longcalls Directive,  Up: Xtensa Directives
18482
 
18483
9.40.5.1 schedule
18484
.................
18485
 
18486
The `schedule' directive is recognized only for compatibility with
18487
Tensilica's assembler.
18488
 
18489
         .begin [no-]schedule
18490
         .end [no-]schedule
18491
 
18492
   This directive is ignored and has no effect on `as'.
18493
 
18494

18495
File: as.info,  Node: Longcalls Directive,  Next: Transform Directive,  Prev: Schedule Directive,  Up: Xtensa Directives
18496
 
18497
9.40.5.2 longcalls
18498
..................
18499
 
18500
The `longcalls' directive enables or disables function call relaxation.
18501
*Note Function Call Relaxation: Xtensa Call Relaxation.
18502
 
18503
         .begin [no-]longcalls
18504
         .end [no-]longcalls
18505
 
18506
   Call relaxation is disabled by default unless the `--longcalls'
18507
command-line option is specified.  The `longcalls' directive overrides
18508
the default determined by the command-line options.
18509
 
18510

18511
File: as.info,  Node: Transform Directive,  Next: Literal Directive,  Prev: Longcalls Directive,  Up: Xtensa Directives
18512
 
18513
9.40.5.3 transform
18514
..................
18515
 
18516
This directive enables or disables all assembler transformation,
18517
including relaxation (*note Xtensa Relaxation: Xtensa Relaxation.) and
18518
optimization (*note Xtensa Optimizations: Xtensa Optimizations.).
18519
 
18520
         .begin [no-]transform
18521
         .end [no-]transform
18522
 
18523
   Transformations are enabled by default unless the `--no-transform'
18524
option is used.  The `transform' directive overrides the default
18525
determined by the command-line options.  An underscore opcode prefix,
18526
disabling transformation of that opcode, always takes precedence over
18527
both directives and command-line flags.
18528
 
18529

18530
File: as.info,  Node: Literal Directive,  Next: Literal Position Directive,  Prev: Transform Directive,  Up: Xtensa Directives
18531
 
18532
9.40.5.4 literal
18533
................
18534
 
18535
The `.literal' directive is used to define literal pool data, i.e.,
18536
read-only 32-bit data accessed via `L32R' instructions.
18537
 
18538
         .literal LABEL, VALUE[, VALUE...]
18539
 
18540
   This directive is similar to the standard `.word' directive, except
18541
that the actual location of the literal data is determined by the
18542
assembler and linker, not by the position of the `.literal' directive.
18543
Using this directive gives the assembler freedom to locate the literal
18544
data in the most appropriate place and possibly to combine identical
18545
literals.  For example, the code:
18546
 
18547
         entry sp, 40
18548
         .literal .L1, sym
18549
         l32r    a4, .L1
18550
 
18551
   can be used to load a pointer to the symbol `sym' into register
18552
`a4'.  The value of `sym' will not be placed between the `ENTRY' and
18553
`L32R' instructions; instead, the assembler puts the data in a literal
18554
pool.
18555
 
18556
   Literal pools are placed by default in separate literal sections;
18557
however, when using the `--text-section-literals' option (*note Command
18558
Line Options: Xtensa Options.), the literal pools for PC-relative mode
18559
`L32R' instructions are placed in the current section.(1) These text
18560
section literal pools are created automatically before `ENTRY'
18561
instructions and manually after `.literal_position' directives (*note
18562
literal_position: Literal Position Directive.).  If there are no
18563
preceding `ENTRY' instructions, explicit `.literal_position' directives
18564
must be used to place the text section literal pools; otherwise, `as'
18565
will report an error.
18566
 
18567
   When literals are placed in separate sections, the literal section
18568
names are derived from the names of the sections where the literals are
18569
defined.  The base literal section names are `.literal' for PC-relative
18570
mode `L32R' instructions and `.lit4' for absolute mode `L32R'
18571
instructions (*note absolute-literals: Absolute Literals Directive.).
18572
These base names are used for literals defined in the default `.text'
18573
section.  For literals defined in other sections or within the scope of
18574
a `literal_prefix' directive (*note literal_prefix: Literal Prefix
18575
Directive.), the following rules determine the literal section name:
18576
 
18577
  1. If the current section is a member of a section group, the literal
18578
     section name includes the group name as a suffix to the base
18579
     `.literal' or `.lit4' name, with a period to separate the base
18580
     name and group name.  The literal section is also made a member of
18581
     the group.
18582
 
18583
  2. If the current section name (or `literal_prefix' value) begins with
18584
     "`.gnu.linkonce.KIND.'", the literal section name is formed by
18585
     replacing "`.KIND'" with the base `.literal' or `.lit4' name.  For
18586
     example, for literals defined in a section named
18587
     `.gnu.linkonce.t.func', the literal section will be
18588
     `.gnu.linkonce.literal.func' or `.gnu.linkonce.lit4.func'.
18589
 
18590
  3. If the current section name (or `literal_prefix' value) ends with
18591
     `.text', the literal section name is formed by replacing that
18592
     suffix with the base `.literal' or `.lit4' name.  For example, for
18593
     literals defined in a section named `.iram0.text', the literal
18594
     section will be `.iram0.literal' or `.iram0.lit4'.
18595
 
18596
  4. If none of the preceding conditions apply, the literal section
18597
     name is formed by adding the base `.literal' or `.lit4' name as a
18598
     suffix to the current section name (or `literal_prefix' value).
18599
 
18600
   ---------- Footnotes ----------
18601
 
18602
   (1) Literals for the `.init' and `.fini' sections are always placed
18603
in separate sections, even when `--text-section-literals' is enabled.
18604
 
18605

18606
File: as.info,  Node: Literal Position Directive,  Next: Literal Prefix Directive,  Prev: Literal Directive,  Up: Xtensa Directives
18607
 
18608
9.40.5.5 literal_position
18609
.........................
18610
 
18611
When using `--text-section-literals' to place literals inline in the
18612
section being assembled, the `.literal_position' directive can be used
18613
to mark a potential location for a literal pool.
18614
 
18615
         .literal_position
18616
 
18617
   The `.literal_position' directive is ignored when the
18618
`--text-section-literals' option is not used or when `L32R'
18619
instructions use the absolute addressing mode.
18620
 
18621
   The assembler will automatically place text section literal pools
18622
before `ENTRY' instructions, so the `.literal_position' directive is
18623
only needed to specify some other location for a literal pool.  You may
18624
need to add an explicit jump instruction to skip over an inline literal
18625
pool.
18626
 
18627
   For example, an interrupt vector does not begin with an `ENTRY'
18628
instruction so the assembler will be unable to automatically find a good
18629
place to put a literal pool.  Moreover, the code for the interrupt
18630
vector must be at a specific starting address, so the literal pool
18631
cannot come before the start of the code.  The literal pool for the
18632
vector must be explicitly positioned in the middle of the vector (before
18633
any uses of the literals, due to the negative offsets used by
18634
PC-relative `L32R' instructions).  The `.literal_position' directive
18635
can be used to do this.  In the following code, the literal for `M'
18636
will automatically be aligned correctly and is placed after the
18637
unconditional jump.
18638
 
18639
         .global M
18640
     code_start:
18641
         j continue
18642
         .literal_position
18643
         .align 4
18644
     continue:
18645
         movi    a4, M
18646
 
18647

18648
File: as.info,  Node: Literal Prefix Directive,  Next: Absolute Literals Directive,  Prev: Literal Position Directive,  Up: Xtensa Directives
18649
 
18650
9.40.5.6 literal_prefix
18651
.......................
18652
 
18653
The `literal_prefix' directive allows you to override the default
18654
literal section names, which are derived from the names of the sections
18655
where the literals are defined.
18656
 
18657
         .begin literal_prefix [NAME]
18658
         .end literal_prefix
18659
 
18660
   For literals defined within the delimited region, the literal section
18661
names are derived from the NAME argument instead of the name of the
18662
current section.  The rules used to derive the literal section names do
18663
not change.  *Note literal: Literal Directive.  If the NAME argument is
18664
omitted, the literal sections revert to the defaults.  This directive
18665
has no effect when using the `--text-section-literals' option (*note
18666
Command Line Options: Xtensa Options.).
18667
 
18668

18669
File: as.info,  Node: Absolute Literals Directive,  Prev: Literal Prefix Directive,  Up: Xtensa Directives
18670
 
18671
9.40.5.7 absolute-literals
18672
..........................
18673
 
18674
The `absolute-literals' and `no-absolute-literals' directives control
18675
the absolute vs. PC-relative mode for `L32R' instructions.  These are
18676
relevant only for Xtensa configurations that include the absolute
18677
addressing option for `L32R' instructions.
18678
 
18679
         .begin [no-]absolute-literals
18680
         .end [no-]absolute-literals
18681
 
18682
   These directives do not change the `L32R' mode--they only cause the
18683
assembler to emit the appropriate kind of relocation for `L32R'
18684
instructions and to place the literal values in the appropriate section.
18685
To change the `L32R' mode, the program must write the `LITBASE' special
18686
register.  It is the programmer's responsibility to keep track of the
18687
mode and indicate to the assembler which mode is used in each region of
18688
code.
18689
 
18690
   If the Xtensa configuration includes the absolute `L32R' addressing
18691
option, the default is to assume absolute `L32R' addressing unless the
18692
`--no-absolute-literals' command-line option is specified.  Otherwise,
18693
the default is to assume PC-relative `L32R' addressing.  The
18694
`absolute-literals' directive can then be used to override the default
18695
determined by the command-line options.
18696
 
18697

18698
File: as.info,  Node: Reporting Bugs,  Next: Acknowledgements,  Prev: Machine Dependencies,  Up: Top
18699
 
18700
10 Reporting Bugs
18701
*****************
18702
 
18703
Your bug reports play an essential role in making `as' reliable.
18704
 
18705
   Reporting a bug may help you by bringing a solution to your problem,
18706
or it may not.  But in any case the principal function of a bug report
18707
is to help the entire community by making the next version of `as' work
18708
better.  Bug reports are your contribution to the maintenance of `as'.
18709
 
18710
   In order for a bug report to serve its purpose, you must include the
18711
information that enables us to fix the bug.
18712
 
18713
* Menu:
18714
 
18715
* Bug Criteria::                Have you found a bug?
18716
* Bug Reporting::               How to report bugs
18717
 
18718

18719
File: as.info,  Node: Bug Criteria,  Next: Bug Reporting,  Up: Reporting Bugs
18720
 
18721
10.1 Have You Found a Bug?
18722
==========================
18723
 
18724
If you are not sure whether you have found a bug, here are some
18725
guidelines:
18726
 
18727
   * If the assembler gets a fatal signal, for any input whatever, that
18728
     is a `as' bug.  Reliable assemblers never crash.
18729
 
18730
   * If `as' produces an error message for valid input, that is a bug.
18731
 
18732
   * If `as' does not produce an error message for invalid input, that
18733
     is a bug.  However, you should note that your idea of "invalid
18734
     input" might be our idea of "an extension" or "support for
18735
     traditional practice".
18736
 
18737
   * If you are an experienced user of assemblers, your suggestions for
18738
     improvement of `as' are welcome in any case.
18739
 
18740

18741
File: as.info,  Node: Bug Reporting,  Prev: Bug Criteria,  Up: Reporting Bugs
18742
 
18743
10.2 How to Report Bugs
18744
=======================
18745
 
18746
A number of companies and individuals offer support for GNU products.
18747
If you obtained `as' from a support organization, we recommend you
18748
contact that organization first.
18749
 
18750
   You can find contact information for many support companies and
18751
individuals in the file `etc/SERVICE' in the GNU Emacs distribution.
18752
 
18753
   In any event, we also recommend that you send bug reports for `as'
18754
to `http://www.sourceware.org/bugzilla/'.
18755
 
18756
   The fundamental principle of reporting bugs usefully is this:
18757
*report all the facts*.  If you are not sure whether to state a fact or
18758
leave it out, state it!
18759
 
18760
   Often people omit facts because they think they know what causes the
18761
problem and assume that some details do not matter.  Thus, you might
18762
assume that the name of a symbol you use in an example does not matter.
18763
Well, probably it does not, but one cannot be sure.  Perhaps the bug
18764
is a stray memory reference which happens to fetch from the location
18765
where that name is stored in memory; perhaps, if the name were
18766
different, the contents of that location would fool the assembler into
18767
doing the right thing despite the bug.  Play it safe and give a
18768
specific, complete example.  That is the easiest thing for you to do,
18769
and the most helpful.
18770
 
18771
   Keep in mind that the purpose of a bug report is to enable us to fix
18772
the bug if it is new to us.  Therefore, always write your bug reports
18773
on the assumption that the bug has not been reported previously.
18774
 
18775
   Sometimes people give a few sketchy facts and ask, "Does this ring a
18776
bell?"  This cannot help us fix a bug, so it is basically useless.  We
18777
respond by asking for enough details to enable us to investigate.  You
18778
might as well expedite matters by sending them to begin with.
18779
 
18780
   To enable us to fix the bug, you should include all these things:
18781
 
18782
   * The version of `as'.  `as' announces it if you start it with the
18783
     `--version' argument.
18784
 
18785
     Without this, we will not know whether there is any point in
18786
     looking for the bug in the current version of `as'.
18787
 
18788
   * Any patches you may have applied to the `as' source.
18789
 
18790
   * The type of machine you are using, and the operating system name
18791
     and version number.
18792
 
18793
   * What compiler (and its version) was used to compile `as'--e.g.
18794
     "`gcc-2.7'".
18795
 
18796
   * The command arguments you gave the assembler to assemble your
18797
     example and observe the bug.  To guarantee you will not omit
18798
     something important, list them all.  A copy of the Makefile (or
18799
     the output from make) is sufficient.
18800
 
18801
     If we were to try to guess the arguments, we would probably guess
18802
     wrong and then we might not encounter the bug.
18803
 
18804
   * A complete input file that will reproduce the bug.  If the bug is
18805
     observed when the assembler is invoked via a compiler, send the
18806
     assembler source, not the high level language source.  Most
18807
     compilers will produce the assembler source when run with the `-S'
18808
     option.  If you are using `gcc', use the options `-v
18809
     --save-temps'; this will save the assembler source in a file with
18810
     an extension of `.s', and also show you exactly how `as' is being
18811
     run.
18812
 
18813
   * A description of what behavior you observe that you believe is
18814
     incorrect.  For example, "It gets a fatal signal."
18815
 
18816
     Of course, if the bug is that `as' gets a fatal signal, then we
18817
     will certainly notice it.  But if the bug is incorrect output, we
18818
     might not notice unless it is glaringly wrong.  You might as well
18819
     not give us a chance to make a mistake.
18820
 
18821
     Even if the problem you experience is a fatal signal, you should
18822
     still say so explicitly.  Suppose something strange is going on,
18823
     such as, your copy of `as' is out of sync, or you have encountered
18824
     a bug in the C library on your system.  (This has happened!)  Your
18825
     copy might crash and ours would not.  If you told us to expect a
18826
     crash, then when ours fails to crash, we would know that the bug
18827
     was not happening for us.  If you had not told us to expect a
18828
     crash, then we would not be able to draw any conclusion from our
18829
     observations.
18830
 
18831
   * If you wish to suggest changes to the `as' source, send us context
18832
     diffs, as generated by `diff' with the `-u', `-c', or `-p' option.
18833
     Always send diffs from the old file to the new file.  If you even
18834
     discuss something in the `as' source, refer to it by context, not
18835
     by line number.
18836
 
18837
     The line numbers in our development sources will not match those
18838
     in your sources.  Your line numbers would convey no useful
18839
     information to us.
18840
 
18841
   Here are some things that are not necessary:
18842
 
18843
   * A description of the envelope of the bug.
18844
 
18845
     Often people who encounter a bug spend a lot of time investigating
18846
     which changes to the input file will make the bug go away and which
18847
     changes will not affect it.
18848
 
18849
     This is often time consuming and not very useful, because the way
18850
     we will find the bug is by running a single example under the
18851
     debugger with breakpoints, not by pure deduction from a series of
18852
     examples.  We recommend that you save your time for something else.
18853
 
18854
     Of course, if you can find a simpler example to report _instead_
18855
     of the original one, that is a convenience for us.  Errors in the
18856
     output will be easier to spot, running under the debugger will take
18857
     less time, and so on.
18858
 
18859
     However, simplification is not vital; if you do not want to do
18860
     this, report the bug anyway and send us the entire test case you
18861
     used.
18862
 
18863
   * A patch for the bug.
18864
 
18865
     A patch for the bug does help us if it is a good one.  But do not
18866
     omit the necessary information, such as the test case, on the
18867
     assumption that a patch is all we need.  We might see problems
18868
     with your patch and decide to fix the problem another way, or we
18869
     might not understand it at all.
18870
 
18871
     Sometimes with a program as complicated as `as' it is very hard to
18872
     construct an example that will make the program follow a certain
18873
     path through the code.  If you do not send us the example, we will
18874
     not be able to construct one, so we will not be able to verify
18875
     that the bug is fixed.
18876
 
18877
     And if we cannot understand what bug you are trying to fix, or why
18878
     your patch should be an improvement, we will not install it.  A
18879
     test case will help us to understand.
18880
 
18881
   * A guess about what the bug is or what it depends on.
18882
 
18883
     Such guesses are usually wrong.  Even we cannot guess right about
18884
     such things without first using the debugger to find the facts.
18885
 
18886

18887
File: as.info,  Node: Acknowledgements,  Next: GNU Free Documentation License,  Prev: Reporting Bugs,  Up: Top
18888
 
18889
11 Acknowledgements
18890
*******************
18891
 
18892
If you have contributed to GAS and your name isn't listed here, it is
18893
not meant as a slight.  We just don't know about it.  Send mail to the
18894
maintainer, and we'll correct the situation.  Currently the maintainer
18895
is Ken Raeburn (email address `raeburn@cygnus.com').
18896
 
18897
   Dean Elsner wrote the original GNU assembler for the VAX.(1)
18898
 
18899
   Jay Fenlason maintained GAS for a while, adding support for
18900
GDB-specific debug information and the 68k series machines, most of the
18901
preprocessing pass, and extensive changes in `messages.c',
18902
`input-file.c', `write.c'.
18903
 
18904
   K. Richard Pixley maintained GAS for a while, adding various
18905
enhancements and many bug fixes, including merging support for several
18906
processors, breaking GAS up to handle multiple object file format back
18907
ends (including heavy rewrite, testing, an integration of the coff and
18908
b.out back ends), adding configuration including heavy testing and
18909
verification of cross assemblers and file splits and renaming,
18910
converted GAS to strictly ANSI C including full prototypes, added
18911
support for m680[34]0 and cpu32, did considerable work on i960
18912
including a COFF port (including considerable amounts of reverse
18913
engineering), a SPARC opcode file rewrite, DECstation, rs6000, and
18914
hp300hpux host ports, updated "know" assertions and made them work,
18915
much other reorganization, cleanup, and lint.
18916
 
18917
   Ken Raeburn wrote the high-level BFD interface code to replace most
18918
of the code in format-specific I/O modules.
18919
 
18920
   The original VMS support was contributed by David L. Kashtan.  Eric
18921
Youngdale has done much work with it since.
18922
 
18923
   The Intel 80386 machine description was written by Eliot Dresselhaus.
18924
 
18925
   Minh Tran-Le at IntelliCorp contributed some AIX 386 support.
18926
 
18927
   The Motorola 88k machine description was contributed by Devon Bowen
18928
of Buffalo University and Torbjorn Granlund of the Swedish Institute of
18929
Computer Science.
18930
 
18931
   Keith Knowles at the Open Software Foundation wrote the original
18932
MIPS back end (`tc-mips.c', `tc-mips.h'), and contributed Rose format
18933
support (which hasn't been merged in yet).  Ralph Campbell worked with
18934
the MIPS code to support a.out format.
18935
 
18936
   Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k,
18937
tc-h8300), and IEEE 695 object file format (obj-ieee), was written by
18938
Steve Chamberlain of Cygnus Support.  Steve also modified the COFF back
18939
end to use BFD for some low-level operations, for use with the H8/300
18940
and AMD 29k targets.
18941
 
18942
   John Gilmore built the AMD 29000 support, added `.include' support,
18943
and simplified the configuration of which versions accept which
18944
directives.  He updated the 68k machine description so that Motorola's
18945
opcodes always produced fixed-size instructions (e.g., `jsr'), while
18946
synthetic instructions remained shrinkable (`jbsr').  John fixed many
18947
bugs, including true tested cross-compilation support, and one bug in
18948
relaxation that took a week and required the proverbial one-bit fix.
18949
 
18950
   Ian Lance Taylor of Cygnus Support merged the Motorola and MIT
18951
syntax for the 68k, completed support for some COFF targets (68k, i386
18952
SVR3, and SCO Unix), added support for MIPS ECOFF and ELF targets,
18953
wrote the initial RS/6000 and PowerPC assembler, and made a few other
18954
minor patches.
18955
 
18956
   Steve Chamberlain made GAS able to generate listings.
18957
 
18958
   Hewlett-Packard contributed support for the HP9000/300.
18959
 
18960
   Jeff Law wrote GAS and BFD support for the native HPPA object format
18961
(SOM) along with a fairly extensive HPPA testsuite (for both SOM and
18962
ELF object formats).  This work was supported by both the Center for
18963
Software Science at the University of Utah and Cygnus Support.
18964
 
18965
   Support for ELF format files has been worked on by Mark Eichin of
18966
Cygnus Support (original, incomplete implementation for SPARC), Pete
18967
Hoogenboom and Jeff Law at the University of Utah (HPPA mainly),
18968
Michael Meissner of the Open Software Foundation (i386 mainly), and Ken
18969
Raeburn of Cygnus Support (sparc, and some initial 64-bit support).
18970
 
18971
   Linas Vepstas added GAS support for the ESA/390 "IBM 370"
18972
architecture.
18973
 
18974
   Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote
18975
GAS and BFD support for openVMS/Alpha.
18976
 
18977
   Timothy Wall, Michael Hayes, and Greg Smart contributed to the
18978
various tic* flavors.
18979
 
18980
   David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from
18981
Tensilica, Inc. added support for Xtensa processors.
18982
 
18983
   Several engineers at Cygnus Support have also provided many small
18984
bug fixes and configuration enhancements.
18985
 
18986
   Jon Beniston added support for the Lattice Mico32 architecture.
18987
 
18988
   Many others have contributed large or small bugfixes and
18989
enhancements.  If you have contributed significant work and are not
18990
mentioned on this list, and want to be, let us know.  Some of the
18991
history has been lost; we are not intentionally leaving anyone out.
18992
 
18993
   ---------- Footnotes ----------
18994
 
18995
   (1) Any more details?
18996
 
18997

18998
File: as.info,  Node: GNU Free Documentation License,  Next: AS Index,  Prev: Acknowledgements,  Up: Top
18999
 
19000
Appendix A GNU Free Documentation License
19001
*****************************************
19002
 
19003
                     Version 1.3, 3 November 2008
19004
 
19005
     Copyright (C) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc.
19006
     `http://fsf.org/'
19007
 
19008
     Everyone is permitted to copy and distribute verbatim copies
19009
     of this license document, but changing it is not allowed.
19010
 
19011
  0. PREAMBLE
19012
 
19013
     The purpose of this License is to make a manual, textbook, or other
19014
     functional and useful document "free" in the sense of freedom: to
19015
     assure everyone the effective freedom to copy and redistribute it,
19016
     with or without modifying it, either commercially or
19017
     noncommercially.  Secondarily, this License preserves for the
19018
     author and publisher a way to get credit for their work, while not
19019
     being considered responsible for modifications made by others.
19020
 
19021
     This License is a kind of "copyleft", which means that derivative
19022
     works of the document must themselves be free in the same sense.
19023
     It complements the GNU General Public License, which is a copyleft
19024
     license designed for free software.
19025
 
19026
     We have designed this License in order to use it for manuals for
19027
     free software, because free software needs free documentation: a
19028
     free program should come with manuals providing the same freedoms
19029
     that the software does.  But this License is not limited to
19030
     software manuals; it can be used for any textual work, regardless
19031
     of subject matter or whether it is published as a printed book.
19032
     We recommend this License principally for works whose purpose is
19033
     instruction or reference.
19034
 
19035
  1. APPLICABILITY AND DEFINITIONS
19036
 
19037
     This License applies to any manual or other work, in any medium,
19038
     that contains a notice placed by the copyright holder saying it
19039
     can be distributed under the terms of this License.  Such a notice
19040
     grants a world-wide, royalty-free license, unlimited in duration,
19041
     to use that work under the conditions stated herein.  The
19042
     "Document", below, refers to any such manual or work.  Any member
19043
     of the public is a licensee, and is addressed as "you".  You
19044
     accept the license if you copy, modify or distribute the work in a
19045
     way requiring permission under copyright law.
19046
 
19047
     A "Modified Version" of the Document means any work containing the
19048
     Document or a portion of it, either copied verbatim, or with
19049
     modifications and/or translated into another language.
19050
 
19051
     A "Secondary Section" is a named appendix or a front-matter section
19052
     of the Document that deals exclusively with the relationship of the
19053
     publishers or authors of the Document to the Document's overall
19054
     subject (or to related matters) and contains nothing that could
19055
     fall directly within that overall subject.  (Thus, if the Document
19056
     is in part a textbook of mathematics, a Secondary Section may not
19057
     explain any mathematics.)  The relationship could be a matter of
19058
     historical connection with the subject or with related matters, or
19059
     of legal, commercial, philosophical, ethical or political position
19060
     regarding them.
19061
 
19062
     The "Invariant Sections" are certain Secondary Sections whose
19063
     titles are designated, as being those of Invariant Sections, in
19064
     the notice that says that the Document is released under this
19065
     License.  If a section does not fit the above definition of
19066
     Secondary then it is not allowed to be designated as Invariant.
19067
     The Document may contain zero Invariant Sections.  If the Document
19068
     does not identify any Invariant Sections then there are none.
19069
 
19070
     The "Cover Texts" are certain short passages of text that are
19071
     listed, as Front-Cover Texts or Back-Cover Texts, in the notice
19072
     that says that the Document is released under this License.  A
19073
     Front-Cover Text may be at most 5 words, and a Back-Cover Text may
19074
     be at most 25 words.
19075
 
19076
     A "Transparent" copy of the Document means a machine-readable copy,
19077
     represented in a format whose specification is available to the
19078
     general public, that is suitable for revising the document
19079
     straightforwardly with generic text editors or (for images
19080
     composed of pixels) generic paint programs or (for drawings) some
19081
     widely available drawing editor, and that is suitable for input to
19082
     text formatters or for automatic translation to a variety of
19083
     formats suitable for input to text formatters.  A copy made in an
19084
     otherwise Transparent file format whose markup, or absence of
19085
     markup, has been arranged to thwart or discourage subsequent
19086
     modification by readers is not Transparent.  An image format is
19087
     not Transparent if used for any substantial amount of text.  A
19088
     copy that is not "Transparent" is called "Opaque".
19089
 
19090
     Examples of suitable formats for Transparent copies include plain
19091
     ASCII without markup, Texinfo input format, LaTeX input format,
19092
     SGML or XML using a publicly available DTD, and
19093
     standard-conforming simple HTML, PostScript or PDF designed for
19094
     human modification.  Examples of transparent image formats include
19095
     PNG, XCF and JPG.  Opaque formats include proprietary formats that
19096
     can be read and edited only by proprietary word processors, SGML or
19097
     XML for which the DTD and/or processing tools are not generally
19098
     available, and the machine-generated HTML, PostScript or PDF
19099
     produced by some word processors for output purposes only.
19100
 
19101
     The "Title Page" means, for a printed book, the title page itself,
19102
     plus such following pages as are needed to hold, legibly, the
19103
     material this License requires to appear in the title page.  For
19104
     works in formats which do not have any title page as such, "Title
19105
     Page" means the text near the most prominent appearance of the
19106
     work's title, preceding the beginning of the body of the text.
19107
 
19108
     The "publisher" means any person or entity that distributes copies
19109
     of the Document to the public.
19110
 
19111
     A section "Entitled XYZ" means a named subunit of the Document
19112
     whose title either is precisely XYZ or contains XYZ in parentheses
19113
     following text that translates XYZ in another language.  (Here XYZ
19114
     stands for a specific section name mentioned below, such as
19115
     "Acknowledgements", "Dedications", "Endorsements", or "History".)
19116
     To "Preserve the Title" of such a section when you modify the
19117
     Document means that it remains a section "Entitled XYZ" according
19118
     to this definition.
19119
 
19120
     The Document may include Warranty Disclaimers next to the notice
19121
     which states that this License applies to the Document.  These
19122
     Warranty Disclaimers are considered to be included by reference in
19123
     this License, but only as regards disclaiming warranties: any other
19124
     implication that these Warranty Disclaimers may have is void and
19125
     has no effect on the meaning of this License.
19126
 
19127
  2. VERBATIM COPYING
19128
 
19129
     You may copy and distribute the Document in any medium, either
19130
     commercially or noncommercially, provided that this License, the
19131
     copyright notices, and the license notice saying this License
19132
     applies to the Document are reproduced in all copies, and that you
19133
     add no other conditions whatsoever to those of this License.  You
19134
     may not use technical measures to obstruct or control the reading
19135
     or further copying of the copies you make or distribute.  However,
19136
     you may accept compensation in exchange for copies.  If you
19137
     distribute a large enough number of copies you must also follow
19138
     the conditions in section 3.
19139
 
19140
     You may also lend copies, under the same conditions stated above,
19141
     and you may publicly display copies.
19142
 
19143
  3. COPYING IN QUANTITY
19144
 
19145
     If you publish printed copies (or copies in media that commonly
19146
     have printed covers) of the Document, numbering more than 100, and
19147
     the Document's license notice requires Cover Texts, you must
19148
     enclose the copies in covers that carry, clearly and legibly, all
19149
     these Cover Texts: Front-Cover Texts on the front cover, and
19150
     Back-Cover Texts on the back cover.  Both covers must also clearly
19151
     and legibly identify you as the publisher of these copies.  The
19152
     front cover must present the full title with all words of the
19153
     title equally prominent and visible.  You may add other material
19154
     on the covers in addition.  Copying with changes limited to the
19155
     covers, as long as they preserve the title of the Document and
19156
     satisfy these conditions, can be treated as verbatim copying in
19157
     other respects.
19158
 
19159
     If the required texts for either cover are too voluminous to fit
19160
     legibly, you should put the first ones listed (as many as fit
19161
     reasonably) on the actual cover, and continue the rest onto
19162
     adjacent pages.
19163
 
19164
     If you publish or distribute Opaque copies of the Document
19165
     numbering more than 100, you must either include a
19166
     machine-readable Transparent copy along with each Opaque copy, or
19167
     state in or with each Opaque copy a computer-network location from
19168
     which the general network-using public has access to download
19169
     using public-standard network protocols a complete Transparent
19170
     copy of the Document, free of added material.  If you use the
19171
     latter option, you must take reasonably prudent steps, when you
19172
     begin distribution of Opaque copies in quantity, to ensure that
19173
     this Transparent copy will remain thus accessible at the stated
19174
     location until at least one year after the last time you
19175
     distribute an Opaque copy (directly or through your agents or
19176
     retailers) of that edition to the public.
19177
 
19178
     It is requested, but not required, that you contact the authors of
19179
     the Document well before redistributing any large number of
19180
     copies, to give them a chance to provide you with an updated
19181
     version of the Document.
19182
 
19183
  4. MODIFICATIONS
19184
 
19185
     You may copy and distribute a Modified Version of the Document
19186
     under the conditions of sections 2 and 3 above, provided that you
19187
     release the Modified Version under precisely this License, with
19188
     the Modified Version filling the role of the Document, thus
19189
     licensing distribution and modification of the Modified Version to
19190
     whoever possesses a copy of it.  In addition, you must do these
19191
     things in the Modified Version:
19192
 
19193
       A. Use in the Title Page (and on the covers, if any) a title
19194
          distinct from that of the Document, and from those of
19195
          previous versions (which should, if there were any, be listed
19196
          in the History section of the Document).  You may use the
19197
          same title as a previous version if the original publisher of
19198
          that version gives permission.
19199
 
19200
       B. List on the Title Page, as authors, one or more persons or
19201
          entities responsible for authorship of the modifications in
19202
          the Modified Version, together with at least five of the
19203
          principal authors of the Document (all of its principal
19204
          authors, if it has fewer than five), unless they release you
19205
          from this requirement.
19206
 
19207
       C. State on the Title page the name of the publisher of the
19208
          Modified Version, as the publisher.
19209
 
19210
       D. Preserve all the copyright notices of the Document.
19211
 
19212
       E. Add an appropriate copyright notice for your modifications
19213
          adjacent to the other copyright notices.
19214
 
19215
       F. Include, immediately after the copyright notices, a license
19216
          notice giving the public permission to use the Modified
19217
          Version under the terms of this License, in the form shown in
19218
          the Addendum below.
19219
 
19220
       G. Preserve in that license notice the full lists of Invariant
19221
          Sections and required Cover Texts given in the Document's
19222
          license notice.
19223
 
19224
       H. Include an unaltered copy of this License.
19225
 
19226
       I. Preserve the section Entitled "History", Preserve its Title,
19227
          and add to it an item stating at least the title, year, new
19228
          authors, and publisher of the Modified Version as given on
19229
          the Title Page.  If there is no section Entitled "History" in
19230
          the Document, create one stating the title, year, authors,
19231
          and publisher of the Document as given on its Title Page,
19232
          then add an item describing the Modified Version as stated in
19233
          the previous sentence.
19234
 
19235
       J. Preserve the network location, if any, given in the Document
19236
          for public access to a Transparent copy of the Document, and
19237
          likewise the network locations given in the Document for
19238
          previous versions it was based on.  These may be placed in
19239
          the "History" section.  You may omit a network location for a
19240
          work that was published at least four years before the
19241
          Document itself, or if the original publisher of the version
19242
          it refers to gives permission.
19243
 
19244
       K. For any section Entitled "Acknowledgements" or "Dedications",
19245
          Preserve the Title of the section, and preserve in the
19246
          section all the substance and tone of each of the contributor
19247
          acknowledgements and/or dedications given therein.
19248
 
19249
       L. Preserve all the Invariant Sections of the Document,
19250
          unaltered in their text and in their titles.  Section numbers
19251
          or the equivalent are not considered part of the section
19252
          titles.
19253
 
19254
       M. Delete any section Entitled "Endorsements".  Such a section
19255
          may not be included in the Modified Version.
19256
 
19257
       N. Do not retitle any existing section to be Entitled
19258
          "Endorsements" or to conflict in title with any Invariant
19259
          Section.
19260
 
19261
       O. Preserve any Warranty Disclaimers.
19262
 
19263
     If the Modified Version includes new front-matter sections or
19264
     appendices that qualify as Secondary Sections and contain no
19265
     material copied from the Document, you may at your option
19266
     designate some or all of these sections as invariant.  To do this,
19267
     add their titles to the list of Invariant Sections in the Modified
19268
     Version's license notice.  These titles must be distinct from any
19269
     other section titles.
19270
 
19271
     You may add a section Entitled "Endorsements", provided it contains
19272
     nothing but endorsements of your Modified Version by various
19273
     parties--for example, statements of peer review or that the text
19274
     has been approved by an organization as the authoritative
19275
     definition of a standard.
19276
 
19277
     You may add a passage of up to five words as a Front-Cover Text,
19278
     and a passage of up to 25 words as a Back-Cover Text, to the end
19279
     of the list of Cover Texts in the Modified Version.  Only one
19280
     passage of Front-Cover Text and one of Back-Cover Text may be
19281
     added by (or through arrangements made by) any one entity.  If the
19282
     Document already includes a cover text for the same cover,
19283
     previously added by you or by arrangement made by the same entity
19284
     you are acting on behalf of, you may not add another; but you may
19285
     replace the old one, on explicit permission from the previous
19286
     publisher that added the old one.
19287
 
19288
     The author(s) and publisher(s) of the Document do not by this
19289
     License give permission to use their names for publicity for or to
19290
     assert or imply endorsement of any Modified Version.
19291
 
19292
  5. COMBINING DOCUMENTS
19293
 
19294
     You may combine the Document with other documents released under
19295
     this License, under the terms defined in section 4 above for
19296
     modified versions, provided that you include in the combination
19297
     all of the Invariant Sections of all of the original documents,
19298
     unmodified, and list them all as Invariant Sections of your
19299
     combined work in its license notice, and that you preserve all
19300
     their Warranty Disclaimers.
19301
 
19302
     The combined work need only contain one copy of this License, and
19303
     multiple identical Invariant Sections may be replaced with a single
19304
     copy.  If there are multiple Invariant Sections with the same name
19305
     but different contents, make the title of each such section unique
19306
     by adding at the end of it, in parentheses, the name of the
19307
     original author or publisher of that section if known, or else a
19308
     unique number.  Make the same adjustment to the section titles in
19309
     the list of Invariant Sections in the license notice of the
19310
     combined work.
19311
 
19312
     In the combination, you must combine any sections Entitled
19313
     "History" in the various original documents, forming one section
19314
     Entitled "History"; likewise combine any sections Entitled
19315
     "Acknowledgements", and any sections Entitled "Dedications".  You
19316
     must delete all sections Entitled "Endorsements."
19317
 
19318
  6. COLLECTIONS OF DOCUMENTS
19319
 
19320
     You may make a collection consisting of the Document and other
19321
     documents released under this License, and replace the individual
19322
     copies of this License in the various documents with a single copy
19323
     that is included in the collection, provided that you follow the
19324
     rules of this License for verbatim copying of each of the
19325
     documents in all other respects.
19326
 
19327
     You may extract a single document from such a collection, and
19328
     distribute it individually under this License, provided you insert
19329
     a copy of this License into the extracted document, and follow
19330
     this License in all other respects regarding verbatim copying of
19331
     that document.
19332
 
19333
  7. AGGREGATION WITH INDEPENDENT WORKS
19334
 
19335
     A compilation of the Document or its derivatives with other
19336
     separate and independent documents or works, in or on a volume of
19337
     a storage or distribution medium, is called an "aggregate" if the
19338
     copyright resulting from the compilation is not used to limit the
19339
     legal rights of the compilation's users beyond what the individual
19340
     works permit.  When the Document is included in an aggregate, this
19341
     License does not apply to the other works in the aggregate which
19342
     are not themselves derivative works of the Document.
19343
 
19344
     If the Cover Text requirement of section 3 is applicable to these
19345
     copies of the Document, then if the Document is less than one half
19346
     of the entire aggregate, the Document's Cover Texts may be placed
19347
     on covers that bracket the Document within the aggregate, or the
19348
     electronic equivalent of covers if the Document is in electronic
19349
     form.  Otherwise they must appear on printed covers that bracket
19350
     the whole aggregate.
19351
 
19352
  8. TRANSLATION
19353
 
19354
     Translation is considered a kind of modification, so you may
19355
     distribute translations of the Document under the terms of section
19356
     4.  Replacing Invariant Sections with translations requires special
19357
     permission from their copyright holders, but you may include
19358
     translations of some or all Invariant Sections in addition to the
19359
     original versions of these Invariant Sections.  You may include a
19360
     translation of this License, and all the license notices in the
19361
     Document, and any Warranty Disclaimers, provided that you also
19362
     include the original English version of this License and the
19363
     original versions of those notices and disclaimers.  In case of a
19364
     disagreement between the translation and the original version of
19365
     this License or a notice or disclaimer, the original version will
19366
     prevail.
19367
 
19368
     If a section in the Document is Entitled "Acknowledgements",
19369
     "Dedications", or "History", the requirement (section 4) to
19370
     Preserve its Title (section 1) will typically require changing the
19371
     actual title.
19372
 
19373
  9. TERMINATION
19374
 
19375
     You may not copy, modify, sublicense, or distribute the Document
19376
     except as expressly provided under this License.  Any attempt
19377
     otherwise to copy, modify, sublicense, or distribute it is void,
19378
     and will automatically terminate your rights under this License.
19379
 
19380
     However, if you cease all violation of this License, then your
19381
     license from a particular copyright holder is reinstated (a)
19382
     provisionally, unless and until the copyright holder explicitly
19383
     and finally terminates your license, and (b) permanently, if the
19384
     copyright holder fails to notify you of the violation by some
19385
     reasonable means prior to 60 days after the cessation.
19386
 
19387
     Moreover, your license from a particular copyright holder is
19388
     reinstated permanently if the copyright holder notifies you of the
19389
     violation by some reasonable means, this is the first time you have
19390
     received notice of violation of this License (for any work) from
19391
     that copyright holder, and you cure the violation prior to 30 days
19392
     after your receipt of the notice.
19393
 
19394
     Termination of your rights under this section does not terminate
19395
     the licenses of parties who have received copies or rights from
19396
     you under this License.  If your rights have been terminated and
19397
     not permanently reinstated, receipt of a copy of some or all of
19398
     the same material does not give you any rights to use it.
19399
 
19400
 10. FUTURE REVISIONS OF THIS LICENSE
19401
 
19402
     The Free Software Foundation may publish new, revised versions of
19403
     the GNU Free Documentation License from time to time.  Such new
19404
     versions will be similar in spirit to the present version, but may
19405
     differ in detail to address new problems or concerns.  See
19406
     `http://www.gnu.org/copyleft/'.
19407
 
19408
     Each version of the License is given a distinguishing version
19409
     number.  If the Document specifies that a particular numbered
19410
     version of this License "or any later version" applies to it, you
19411
     have the option of following the terms and conditions either of
19412
     that specified version or of any later version that has been
19413
     published (not as a draft) by the Free Software Foundation.  If
19414
     the Document does not specify a version number of this License,
19415
     you may choose any version ever published (not as a draft) by the
19416
     Free Software Foundation.  If the Document specifies that a proxy
19417
     can decide which future versions of this License can be used, that
19418
     proxy's public statement of acceptance of a version permanently
19419
     authorizes you to choose that version for the Document.
19420
 
19421
 11. RELICENSING
19422
 
19423
     "Massive Multiauthor Collaboration Site" (or "MMC Site") means any
19424
     World Wide Web server that publishes copyrightable works and also
19425
     provides prominent facilities for anybody to edit those works.  A
19426
     public wiki that anybody can edit is an example of such a server.
19427
     A "Massive Multiauthor Collaboration" (or "MMC") contained in the
19428
     site means any set of copyrightable works thus published on the MMC
19429
     site.
19430
 
19431
     "CC-BY-SA" means the Creative Commons Attribution-Share Alike 3.0
19432
     license published by Creative Commons Corporation, a not-for-profit
19433
     corporation with a principal place of business in San Francisco,
19434
     California, as well as future copyleft versions of that license
19435
     published by that same organization.
19436
 
19437
     "Incorporate" means to publish or republish a Document, in whole or
19438
     in part, as part of another Document.
19439
 
19440
     An MMC is "eligible for relicensing" if it is licensed under this
19441
     License, and if all works that were first published under this
19442
     License somewhere other than this MMC, and subsequently
19443
     incorporated in whole or in part into the MMC, (1) had no cover
19444
     texts or invariant sections, and (2) were thus incorporated prior
19445
     to November 1, 2008.
19446
 
19447
     The operator of an MMC Site may republish an MMC contained in the
19448
     site under CC-BY-SA on the same site at any time before August 1,
19449
     2009, provided the MMC is eligible for relicensing.
19450
 
19451
 
19452
ADDENDUM: How to use this License for your documents
19453
====================================================
19454
 
19455
To use this License in a document you have written, include a copy of
19456
the License in the document and put the following copyright and license
19457
notices just after the title page:
19458
 
19459
       Copyright (C)  YEAR  YOUR NAME.
19460
       Permission is granted to copy, distribute and/or modify this document
19461
       under the terms of the GNU Free Documentation License, Version 1.3
19462
       or any later version published by the Free Software Foundation;
19463
       with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
19464
       Texts.  A copy of the license is included in the section entitled ``GNU
19465
       Free Documentation License''.
19466
 
19467
   If you have Invariant Sections, Front-Cover Texts and Back-Cover
19468
Texts, replace the "with...Texts." line with this:
19469
 
19470
         with the Invariant Sections being LIST THEIR TITLES, with
19471
         the Front-Cover Texts being LIST, and with the Back-Cover Texts
19472
         being LIST.
19473
 
19474
   If you have Invariant Sections without Cover Texts, or some other
19475
combination of the three, merge those two alternatives to suit the
19476
situation.
19477
 
19478
   If your document contains nontrivial examples of program code, we
19479
recommend releasing these examples in parallel under your choice of
19480
free software license, such as the GNU General Public License, to
19481
permit their use in free software.
19482
 
19483

19484
File: as.info,  Node: AS Index,  Prev: GNU Free Documentation License,  Up: Top
19485
 
19486
AS Index
19487
********
19488
 
19489
 
19490
* Menu:
19491
19492
* #:                                     Comments.            (line  39)
19493
* #APP:                                  Preprocessing.       (line  27)
19494
* #NO_APP:                               Preprocessing.       (line  27)
19495
* $ in symbol names <1>:                 D30V-Chars.          (line  63)
19496
* $ in symbol names <2>:                 SH64-Chars.          (line  10)
19497
* $ in symbol names <3>:                 D10V-Chars.          (line  46)
19498
* $ in symbol names:                     SH-Chars.            (line  10)
19499
* $a:                                    ARM Mapping Symbols. (line   9)
19500
* $acos math builtin, TIC54X:            TIC54X-Builtins.     (line  10)
19501
* $asin math builtin, TIC54X:            TIC54X-Builtins.     (line  13)
19502
* $atan math builtin, TIC54X:            TIC54X-Builtins.     (line  16)
19503
* $atan2 math builtin, TIC54X:           TIC54X-Builtins.     (line  19)
19504
* $ceil math builtin, TIC54X:            TIC54X-Builtins.     (line  22)
19505
* $cos math builtin, TIC54X:             TIC54X-Builtins.     (line  28)
19506
* $cosh math builtin, TIC54X:            TIC54X-Builtins.     (line  25)
19507
* $cvf math builtin, TIC54X:             TIC54X-Builtins.     (line  31)
19508
* $cvi math builtin, TIC54X:             TIC54X-Builtins.     (line  34)
19509
* $d:                                    ARM Mapping Symbols. (line  15)
19510
* $exp math builtin, TIC54X:             TIC54X-Builtins.     (line  37)
19511
* $fabs math builtin, TIC54X:            TIC54X-Builtins.     (line  40)
19512
* $firstch subsym builtin, TIC54X:       TIC54X-Macros.       (line  26)
19513
* $floor math builtin, TIC54X:           TIC54X-Builtins.     (line  43)
19514
* $fmod math builtin, TIC54X:            TIC54X-Builtins.     (line  47)
19515
* $int math builtin, TIC54X:             TIC54X-Builtins.     (line  50)
19516
* $iscons subsym builtin, TIC54X:        TIC54X-Macros.       (line  43)
19517
* $isdefed subsym builtin, TIC54X:       TIC54X-Macros.       (line  34)
19518
* $ismember subsym builtin, TIC54X:      TIC54X-Macros.       (line  38)
19519
* $isname subsym builtin, TIC54X:        TIC54X-Macros.       (line  47)
19520
* $isreg subsym builtin, TIC54X:         TIC54X-Macros.       (line  50)
19521
* $lastch subsym builtin, TIC54X:        TIC54X-Macros.       (line  30)
19522
* $ldexp math builtin, TIC54X:           TIC54X-Builtins.     (line  53)
19523
* $log math builtin, TIC54X:             TIC54X-Builtins.     (line  59)
19524
* $log10 math builtin, TIC54X:           TIC54X-Builtins.     (line  56)
19525
* $max math builtin, TIC54X:             TIC54X-Builtins.     (line  62)
19526
* $min math builtin, TIC54X:             TIC54X-Builtins.     (line  65)
19527
* $pow math builtin, TIC54X:             TIC54X-Builtins.     (line  68)
19528
* $round math builtin, TIC54X:           TIC54X-Builtins.     (line  71)
19529
* $sgn math builtin, TIC54X:             TIC54X-Builtins.     (line  74)
19530
* $sin math builtin, TIC54X:             TIC54X-Builtins.     (line  77)
19531
* $sinh math builtin, TIC54X:            TIC54X-Builtins.     (line  80)
19532
* $sqrt math builtin, TIC54X:            TIC54X-Builtins.     (line  83)
19533
* $structacc subsym builtin, TIC54X:     TIC54X-Macros.       (line  57)
19534
* $structsz subsym builtin, TIC54X:      TIC54X-Macros.       (line  54)
19535
* $symcmp subsym builtin, TIC54X:        TIC54X-Macros.       (line  23)
19536
* $symlen subsym builtin, TIC54X:        TIC54X-Macros.       (line  20)
19537
* $t:                                    ARM Mapping Symbols. (line  12)
19538
* $tan math builtin, TIC54X:             TIC54X-Builtins.     (line  86)
19539
* $tanh math builtin, TIC54X:            TIC54X-Builtins.     (line  89)
19540
* $trunc math builtin, TIC54X:           TIC54X-Builtins.     (line  92)
19541
* -+ option, VAX/VMS:                    VAX-Opts.            (line  71)
19542
* --:                                    Command Line.        (line  10)
19543
* --32 option, i386:                     i386-Options.        (line   8)
19544
* --32 option, x86-64:                   i386-Options.        (line   8)
19545
* --64 option, i386:                     i386-Options.        (line   8)
19546
* --64 option, x86-64:                   i386-Options.        (line   8)
19547
* --absolute-literals:                   Xtensa Options.      (line  23)
19548
* --allow-reg-prefix:                    SH Options.          (line   9)
19549
* --alternate:                           alternate.           (line   6)
19550
* --base-size-default-16:                M68K-Opts.           (line  71)
19551
* --base-size-default-32:                M68K-Opts.           (line  71)
19552
* --big:                                 SH Options.          (line   9)
19553
* --bitwise-or option, M680x0:           M68K-Opts.           (line  64)
19554
* --disp-size-default-16:                M68K-Opts.           (line  80)
19555
* --disp-size-default-32:                M68K-Opts.           (line  80)
19556
* --divide option, i386:                 i386-Options.        (line  24)
19557
* --dsp:                                 SH Options.          (line   9)
19558
* --emulation=crisaout command line option, CRIS: CRIS-Opts.  (line   9)
19559
* --emulation=criself command line option, CRIS: CRIS-Opts.   (line   9)
19560
* --enforce-aligned-data:                Sparc-Aligned-Data.  (line  11)
19561
* --fatal-warnings:                      W.                   (line  16)
19562
* --fix-v4bx command line option, ARM:   ARM Options.         (line 143)
19563
* --fixed-special-register-names command line option, MMIX: MMIX-Opts.
19564
                                                              (line   8)
19565
* --force-long-branches:                 M68HC11-Opts.        (line  69)
19566
* --generate-example:                    M68HC11-Opts.        (line  86)
19567
* --globalize-symbols command line option, MMIX: MMIX-Opts.   (line  12)
19568
* --gnu-syntax command line option, MMIX: MMIX-Opts.          (line  16)
19569
* --hash-size=NUMBER:                    Overview.            (line 326)
19570
* --linker-allocated-gregs command line option, MMIX: MMIX-Opts.
19571
                                                              (line  67)
19572
* --listing-cont-lines:                  listing.             (line  34)
19573
* --listing-lhs-width:                   listing.             (line  16)
19574
* --listing-lhs-width2:                  listing.             (line  21)
19575
* --listing-rhs-width:                   listing.             (line  28)
19576
* --little:                              SH Options.          (line   9)
19577
* --longcalls:                           Xtensa Options.      (line  37)
19578
* --march=ARCHITECTURE command line option, CRIS: CRIS-Opts.  (line  33)
19579
* --MD:                                  MD.                  (line   6)
19580
* --mul-bug-abort command line option, CRIS: CRIS-Opts.       (line  61)
19581
* --no-absolute-literals:                Xtensa Options.      (line  23)
19582
* --no-expand command line option, MMIX: MMIX-Opts.           (line  31)
19583
* --no-longcalls:                        Xtensa Options.      (line  37)
19584
* --no-merge-gregs command line option, MMIX: MMIX-Opts.      (line  36)
19585
* --no-mul-bug-abort command line option, CRIS: CRIS-Opts.    (line  61)
19586
* --no-predefined-syms command line option, MMIX: MMIX-Opts.  (line  22)
19587
* --no-pushj-stubs command line option, MMIX: MMIX-Opts.      (line  54)
19588
* --no-stubs command line option, MMIX:  MMIX-Opts.           (line  54)
19589
* --no-target-align:                     Xtensa Options.      (line  30)
19590
* --no-text-section-literals:            Xtensa Options.      (line   9)
19591
* --no-transform:                        Xtensa Options.      (line  46)
19592
* --no-underscore command line option, CRIS: CRIS-Opts.       (line  15)
19593
* --no-warn:                             W.                   (line  11)
19594
* --pcrel:                               M68K-Opts.           (line  92)
19595
* --pic command line option, CRIS:       CRIS-Opts.           (line  27)
19596
* --print-insn-syntax:                   M68HC11-Opts.        (line  75)
19597
* --print-opcodes:                       M68HC11-Opts.        (line  79)
19598
* --register-prefix-optional option, M680x0: M68K-Opts.       (line  51)
19599
* --relax:                               SH Options.          (line   9)
19600
* --relax command line option, MMIX:     MMIX-Opts.           (line  19)
19601
* --rename-section:                      Xtensa Options.      (line  54)
19602
* --renesas:                             SH Options.          (line   9)
19603
* --short-branches:                      M68HC11-Opts.        (line  54)
19604
* --small:                               SH Options.          (line   9)
19605
* --statistics:                          statistics.          (line   6)
19606
* --strict-direct-mode:                  M68HC11-Opts.        (line  44)
19607
* --target-align:                        Xtensa Options.      (line  30)
19608
* --text-section-literals:               Xtensa Options.      (line   9)
19609
* --traditional-format:                  traditional-format.  (line   6)
19610
* --transform:                           Xtensa Options.      (line  46)
19611
* --underscore command line option, CRIS: CRIS-Opts.          (line  15)
19612
* --warn:                                W.                   (line  19)
19613
* -1 option, VAX/VMS:                    VAX-Opts.            (line  77)
19614
* -32addr command line option, Alpha:    Alpha Options.       (line  58)
19615
* -a:                                    a.                   (line   6)
19616
* -A options, i960:                      Options-i960.        (line   6)
19617
* -ac:                                   a.                   (line   6)
19618
* -ad:                                   a.                   (line   6)
19619
* -ag:                                   a.                   (line   6)
19620
* -ah:                                   a.                   (line   6)
19621
* -al:                                   a.                   (line   6)
19622
* -an:                                   a.                   (line   6)
19623
* -as:                                   a.                   (line   6)
19624
* -Asparclet:                            Sparc-Opts.          (line  25)
19625
* -Asparclite:                           Sparc-Opts.          (line  25)
19626
* -Av6:                                  Sparc-Opts.          (line  25)
19627
* -Av8:                                  Sparc-Opts.          (line  25)
19628
* -Av9:                                  Sparc-Opts.          (line  25)
19629
* -Av9a:                                 Sparc-Opts.          (line  25)
19630
* -b option, i960:                       Options-i960.        (line  22)
19631
* -big option, M32R:                     M32R-Opts.           (line  35)
19632
* -D:                                    D.                   (line   6)
19633
* -D, ignored on VAX:                    VAX-Opts.            (line  11)
19634
* -d, VAX option:                        VAX-Opts.            (line  16)
19635
* -eabi= command line option, ARM:       ARM Options.         (line 126)
19636
* -EB command line option, ARC:          ARC Options.         (line  31)
19637
* -EB command line option, ARM:          ARM Options.         (line 131)
19638
* -EB option (MIPS):                     MIPS Opts.           (line  13)
19639
* -EB option, M32R:                      M32R-Opts.           (line  39)
19640
* -EL command line option, ARC:          ARC Options.         (line  35)
19641
* -EL command line option, ARM:          ARM Options.         (line 135)
19642
* -EL option (MIPS):                     MIPS Opts.           (line  13)
19643
* -EL option, M32R:                      M32R-Opts.           (line  32)
19644
* -f:                                    f.                   (line   6)
19645
* -F command line option, Alpha:         Alpha Options.       (line  58)
19646
* -G command line option, Alpha:         Alpha Options.       (line  54)
19647
* -g command line option, Alpha:         Alpha Options.       (line  48)
19648
* -G option (MIPS):                      MIPS Opts.           (line   8)
19649
* -H option, VAX/VMS:                    VAX-Opts.            (line  81)
19650
* -h option, VAX/VMS:                    VAX-Opts.            (line  45)
19651
* -I PATH:                               I.                   (line   6)
19652
* -ignore-parallel-conflicts option, M32RX: M32R-Opts.        (line  87)
19653
* -Ip option, M32RX:                     M32R-Opts.           (line  97)
19654
* -J, ignored on VAX:                    VAX-Opts.            (line  27)
19655
* -K:                                    K.                   (line   6)
19656
* -k command line option, ARM:           ARM Options.         (line 139)
19657
* -KPIC option, M32R:                    M32R-Opts.           (line  42)
19658
* -KPIC option, MIPS:                    MIPS Opts.           (line  21)
19659
* -L:                                    L.                   (line   6)
19660
* -l option, M680x0:                     M68K-Opts.           (line  39)
19661
* -little option, M32R:                  M32R-Opts.           (line  27)
19662
* -M:                                    M.                   (line   6)
19663
* -m11/03:                               PDP-11-Options.      (line 140)
19664
* -m11/04:                               PDP-11-Options.      (line 143)
19665
* -m11/05:                               PDP-11-Options.      (line 146)
19666
* -m11/10:                               PDP-11-Options.      (line 146)
19667
* -m11/15:                               PDP-11-Options.      (line 149)
19668
* -m11/20:                               PDP-11-Options.      (line 149)
19669
* -m11/21:                               PDP-11-Options.      (line 152)
19670
* -m11/23:                               PDP-11-Options.      (line 155)
19671
* -m11/24:                               PDP-11-Options.      (line 155)
19672
* -m11/34:                               PDP-11-Options.      (line 158)
19673
* -m11/34a:                              PDP-11-Options.      (line 161)
19674
* -m11/35:                               PDP-11-Options.      (line 164)
19675
* -m11/40:                               PDP-11-Options.      (line 164)
19676
* -m11/44:                               PDP-11-Options.      (line 167)
19677
* -m11/45:                               PDP-11-Options.      (line 170)
19678
* -m11/50:                               PDP-11-Options.      (line 170)
19679
* -m11/53:                               PDP-11-Options.      (line 173)
19680
* -m11/55:                               PDP-11-Options.      (line 170)
19681
* -m11/60:                               PDP-11-Options.      (line 176)
19682
* -m11/70:                               PDP-11-Options.      (line 170)
19683
* -m11/73:                               PDP-11-Options.      (line 173)
19684
* -m11/83:                               PDP-11-Options.      (line 173)
19685
* -m11/84:                               PDP-11-Options.      (line 173)
19686
* -m11/93:                               PDP-11-Options.      (line 173)
19687
* -m11/94:                               PDP-11-Options.      (line 173)
19688
* -m16c option, M16C:                    M32C-Opts.           (line  12)
19689
* -m31 option, s390:                     s390 Options.        (line   8)
19690
* -m32c option, M32C:                    M32C-Opts.           (line   9)
19691
* -m32r option, M32R:                    M32R-Opts.           (line  21)
19692
* -m32rx option, M32R2:                  M32R-Opts.           (line  17)
19693
* -m32rx option, M32RX:                  M32R-Opts.           (line   9)
19694
* -m64 option, s390:                     s390 Options.        (line   8)
19695
* -m68000 and related options:           M68K-Opts.           (line 104)
19696
* -m68hc11:                              M68HC11-Opts.        (line   9)
19697
* -m68hc12:                              M68HC11-Opts.        (line  14)
19698
* -m68hcs12:                             M68HC11-Opts.        (line  21)
19699
* -m[no-]68851 command line option, M680x0: M68K-Opts.        (line  21)
19700
* -m[no-]68881 command line option, M680x0: M68K-Opts.        (line  21)
19701
* -m[no-]div command line option, M680x0: M68K-Opts.          (line  21)
19702
* -m[no-]emac command line option, M680x0: M68K-Opts.         (line  21)
19703
* -m[no-]float command line option, M680x0: M68K-Opts.        (line  21)
19704
* -m[no-]mac command line option, M680x0: M68K-Opts.          (line  21)
19705
* -m[no-]usp command line option, M680x0: M68K-Opts.          (line  21)
19706
* -mall:                                 PDP-11-Options.      (line  26)
19707
* -mall-enabled command line option, LM32: LM32 Options.      (line  30)
19708
* -mall-extensions:                      PDP-11-Options.      (line  26)
19709
* -mall-opcodes command line option, AVR: AVR Options.        (line  62)
19710
* -mapcs command line option, ARM:       ARM Options.         (line  99)
19711
* -mapcs-float command line option, ARM: ARM Options.         (line 112)
19712
* -mapcs-reentrant command line option, ARM: ARM Options.     (line 117)
19713
* -marc[5|6|7|8] command line option, ARC: ARC Options.       (line   6)
19714
* -march= command line option, ARM:      ARM Options.         (line  40)
19715
* -march= command line option, M680x0:   M68K-Opts.           (line   8)
19716
* -march= option, i386:                  i386-Options.        (line  31)
19717
* -march= option, s390:                  s390 Options.        (line  25)
19718
* -march= option, x86-64:                i386-Options.        (line  31)
19719
* -matpcs command line option, ARM:      ARM Options.         (line 104)
19720
* -mbarrel-shift-enabled command line option, LM32: LM32 Options.
19721
                                                              (line  12)
19722
* -mbreak-enabled command line option, LM32: LM32 Options.    (line  27)
19723
* -mcis:                                 PDP-11-Options.      (line  32)
19724
* -mconstant-gp command line option, IA-64: IA-64 Options.    (line   6)
19725
* -mCPU command line option, Alpha:      Alpha Options.       (line   6)
19726
* -mcpu option, cpu:                     TIC54X-Opts.         (line  15)
19727
* -mcpu= command line option, ARM:       ARM Options.         (line   6)
19728
* -mcpu= command line option, Blackfin:  Blackfin Options.    (line   6)
19729
* -mcpu= command line option, M680x0:    M68K-Opts.           (line  14)
19730
* -mcsm:                                 PDP-11-Options.      (line  43)
19731
* -mdcache-enabled command line option, LM32: LM32 Options.   (line  24)
19732
* -mdebug command line option, Alpha:    Alpha Options.       (line  25)
19733
* -mdivide-enabled command line option, LM32: LM32 Options.   (line   9)
19734
* -me option, stderr redirect:           TIC54X-Opts.         (line  20)
19735
* -meis:                                 PDP-11-Options.      (line  46)
19736
* -merrors-to-file option, stderr redirect: TIC54X-Opts.      (line  20)
19737
* -mesa option, s390:                    s390 Options.        (line  17)
19738
* -mf option, far-mode:                  TIC54X-Opts.         (line   8)
19739
* -mf11:                                 PDP-11-Options.      (line 122)
19740
* -mfar-mode option, far-mode:           TIC54X-Opts.         (line   8)
19741
* -mfis:                                 PDP-11-Options.      (line  51)
19742
* -mfloat-abi= command line option, ARM: ARM Options.         (line 121)
19743
* -mfp-11:                               PDP-11-Options.      (line  56)
19744
* -mfpp:                                 PDP-11-Options.      (line  56)
19745
* -mfpu:                                 PDP-11-Options.      (line  56)
19746
* -mfpu= command line option, ARM:       ARM Options.         (line  55)
19747
* -micache-enabled command line option, LM32: LM32 Options.   (line  21)
19748
* -mimplicit-it command line option, ARM: ARM Options.        (line  83)
19749
* -mip2022 option, IP2K:                 IP2K-Opts.           (line  14)
19750
* -mip2022ext option, IP2022:            IP2K-Opts.           (line   9)
19751
* -mj11:                                 PDP-11-Options.      (line 126)
19752
* -mka11:                                PDP-11-Options.      (line  92)
19753
* -mkb11:                                PDP-11-Options.      (line  95)
19754
* -mkd11a:                               PDP-11-Options.      (line  98)
19755
* -mkd11b:                               PDP-11-Options.      (line 101)
19756
* -mkd11d:                               PDP-11-Options.      (line 104)
19757
* -mkd11e:                               PDP-11-Options.      (line 107)
19758
* -mkd11f:                               PDP-11-Options.      (line 110)
19759
* -mkd11h:                               PDP-11-Options.      (line 110)
19760
* -mkd11k:                               PDP-11-Options.      (line 114)
19761
* -mkd11q:                               PDP-11-Options.      (line 110)
19762
* -mkd11z:                               PDP-11-Options.      (line 118)
19763
* -mkev11:                               PDP-11-Options.      (line  51)
19764
* -mlimited-eis:                         PDP-11-Options.      (line  64)
19765
* -mlong:                                M68HC11-Opts.        (line  32)
19766
* -mlong-double:                         M68HC11-Opts.        (line  40)
19767
* -mmcu= command line option, AVR:       AVR Options.         (line   6)
19768
* -mmfpt:                                PDP-11-Options.      (line  70)
19769
* -mmicrocode:                           PDP-11-Options.      (line  83)
19770
* -mmnemonic= option, i386:              i386-Options.        (line  80)
19771
* -mmnemonic= option, x86-64:            i386-Options.        (line  80)
19772
* -mmultiply-enabled command line option, LM32: LM32 Options. (line   6)
19773
* -mmutiproc:                            PDP-11-Options.      (line  73)
19774
* -mmxps:                                PDP-11-Options.      (line  77)
19775
* -mnaked-reg option, i386:              i386-Options.        (line  94)
19776
* -mnaked-reg option, x86-64:            i386-Options.        (line  94)
19777
* -mno-cis:                              PDP-11-Options.      (line  32)
19778
* -mno-csm:                              PDP-11-Options.      (line  43)
19779
* -mno-eis:                              PDP-11-Options.      (line  46)
19780
* -mno-extensions:                       PDP-11-Options.      (line  29)
19781
* -mno-fis:                              PDP-11-Options.      (line  51)
19782
* -mno-fp-11:                            PDP-11-Options.      (line  56)
19783
* -mno-fpp:                              PDP-11-Options.      (line  56)
19784
* -mno-fpu:                              PDP-11-Options.      (line  56)
19785
* -mno-kev11:                            PDP-11-Options.      (line  51)
19786
* -mno-limited-eis:                      PDP-11-Options.      (line  64)
19787
* -mno-mfpt:                             PDP-11-Options.      (line  70)
19788
* -mno-microcode:                        PDP-11-Options.      (line  83)
19789
* -mno-mutiproc:                         PDP-11-Options.      (line  73)
19790
* -mno-mxps:                             PDP-11-Options.      (line  77)
19791
* -mno-pic:                              PDP-11-Options.      (line  11)
19792
* -mno-regnames option, s390:            s390 Options.        (line  35)
19793
* -mno-skip-bug command line option, AVR: AVR Options.        (line  65)
19794
* -mno-spl:                              PDP-11-Options.      (line  80)
19795
* -mno-sym32:                            MIPS Opts.           (line 189)
19796
* -mno-wrap command line option, AVR:    AVR Options.         (line  68)
19797
* -mpic:                                 PDP-11-Options.      (line  11)
19798
* -mregnames option, s390:               s390 Options.        (line  32)
19799
* -mrelax command line option, V850:     V850 Options.        (line  51)
19800
* -mshort:                               M68HC11-Opts.        (line  27)
19801
* -mshort-double:                        M68HC11-Opts.        (line  36)
19802
* -msign-extend-enabled command line option, LM32: LM32 Options.
19803
                                                              (line  15)
19804
* -mspl:                                 PDP-11-Options.      (line  80)
19805
* -msse-check= option, i386:             i386-Options.        (line  68)
19806
* -msse-check= option, x86-64:           i386-Options.        (line  68)
19807
* -msse2avx option, i386:                i386-Options.        (line  64)
19808
* -msse2avx option, x86-64:              i386-Options.        (line  64)
19809
* -msym32:                               MIPS Opts.           (line 189)
19810
* -msyntax= option, i386:                i386-Options.        (line  87)
19811
* -msyntax= option, x86-64:              i386-Options.        (line  87)
19812
* -mt11:                                 PDP-11-Options.      (line 130)
19813
* -mthumb command line option, ARM:      ARM Options.         (line  74)
19814
* -mthumb-interwork command line option, ARM: ARM Options.    (line  79)
19815
* -mtune= option, i386:                  i386-Options.        (line  56)
19816
* -mtune= option, x86-64:                i386-Options.        (line  56)
19817
* -muser-enabled command line option, LM32: LM32 Options.     (line  18)
19818
* -mv850 command line option, V850:      V850 Options.        (line  23)
19819
* -mv850any command line option, V850:   V850 Options.        (line  41)
19820
* -mv850e command line option, V850:     V850 Options.        (line  29)
19821
* -mv850e1 command line option, V850:    V850 Options.        (line  35)
19822
* -mvxworks-pic option, MIPS:            MIPS Opts.           (line  26)
19823
* -mwarn-areg-zero option, s390:         s390 Options.        (line  38)
19824
* -mwarn-deprecated command line option, ARM: ARM Options.    (line 147)
19825
* -mzarch option, s390:                  s390 Options.        (line  17)
19826
* -N command line option, CRIS:          CRIS-Opts.           (line  57)
19827
* -nIp option, M32RX:                    M32R-Opts.           (line 101)
19828
* -no-bitinst, M32R2:                    M32R-Opts.           (line  54)
19829
* -no-ignore-parallel-conflicts option, M32RX: M32R-Opts.     (line  93)
19830
* -no-mdebug command line option, Alpha: Alpha Options.       (line  25)
19831
* -no-parallel option, M32RX:            M32R-Opts.           (line  51)
19832
* -no-relax option, i960:                Options-i960.        (line  66)
19833
* -no-warn-explicit-parallel-conflicts option, M32RX: M32R-Opts.
19834
                                                              (line  79)
19835
* -no-warn-unmatched-high option, M32R:  M32R-Opts.           (line 111)
19836
* -nocpp ignored (MIPS):                 MIPS Opts.           (line 192)
19837
* -noreplace command line option, Alpha: Alpha Options.       (line  40)
19838
* -o:                                    o.                   (line   6)
19839
* -O option, M32RX:                      M32R-Opts.           (line  59)
19840
* -parallel option, M32RX:               M32R-Opts.           (line  46)
19841
* -R:                                    R.                   (line   6)
19842
* -r800 command line option, Z80:        Z80 Options.         (line  41)
19843
* -relax command line option, Alpha:     Alpha Options.       (line  32)
19844
* -replace command line option, Alpha:   Alpha Options.       (line  40)
19845
* -S, ignored on VAX:                    VAX-Opts.            (line  11)
19846
* -t, ignored on VAX:                    VAX-Opts.            (line  36)
19847
* -T, ignored on VAX:                    VAX-Opts.            (line  11)
19848
* -v:                                    v.                   (line   6)
19849
* -V, redundant on VAX:                  VAX-Opts.            (line  22)
19850
* -version:                              v.                   (line   6)
19851
* -W:                                    W.                   (line  11)
19852
* -warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. (line  65)
19853
* -warn-unmatched-high option, M32R:     M32R-Opts.           (line 105)
19854
* -Wnp option, M32RX:                    M32R-Opts.           (line  83)
19855
* -Wnuh option, M32RX:                   M32R-Opts.           (line 117)
19856
* -Wp option, M32RX:                     M32R-Opts.           (line  75)
19857
* -wsigned_overflow command line option, V850: V850 Options.  (line   9)
19858
* -Wuh option, M32RX:                    M32R-Opts.           (line 114)
19859
* -wunsigned_overflow command line option, V850: V850 Options.
19860
                                                              (line  16)
19861
* -x command line option, MMIX:          MMIX-Opts.           (line  44)
19862
* -z80 command line option, Z80:         Z80 Options.         (line   8)
19863
* -z8001 command line option, Z8000:     Z8000 Options.       (line   6)
19864
* -z8002 command line option, Z8000:     Z8000 Options.       (line   9)
19865
* . (symbol):                            Dot.                 (line   6)
19866
* .2byte directive, ARM:                 ARM Directives.      (line   6)
19867
* .4byte directive, ARM:                 ARM Directives.      (line   6)
19868
* .8byte directive, ARM:                 ARM Directives.      (line   6)
19869
* .align directive, ARM:                 ARM Directives.      (line  11)
19870
* .arch directive, ARM:                  ARM Directives.      (line  18)
19871
* .arm directive, ARM:                   ARM Directives.      (line  22)
19872
* .big directive, M32RX:                 M32R-Directives.     (line  88)
19873
* .bss directive, ARM:                   ARM Directives.      (line  30)
19874
* .cantunwind directive, ARM:            ARM Directives.      (line  33)
19875
* .code directive, ARM:                  ARM Directives.      (line  37)
19876
* .cpu directive, ARM:                   ARM Directives.      (line  41)
19877
* .dn and .qn directives, ARM:           ARM Directives.      (line  45)
19878
* .eabi_attribute directive, ARM:        ARM Directives.      (line  69)
19879
* .even directive, ARM:                  ARM Directives.      (line  93)
19880
* .extend directive, ARM:                ARM Directives.      (line  96)
19881
* .fnend directive, ARM:                 ARM Directives.      (line 102)
19882
* .fnstart directive, ARM:               ARM Directives.      (line 111)
19883
* .force_thumb directive, ARM:           ARM Directives.      (line 114)
19884
* .fpu directive, ARM:                   ARM Directives.      (line 118)
19885
* .global:                               MIPS insn.           (line  12)
19886
* .handlerdata directive, ARM:           ARM Directives.      (line 122)
19887
* .insn:                                 MIPS insn.           (line   6)
19888
* .insn directive, s390:                 s390 Directives.     (line  11)
19889
* .inst directive, ARM:                  ARM Directives.      (line 131)
19890
* .ldouble directive, ARM:               ARM Directives.      (line  96)
19891
* .little directive, M32RX:              M32R-Directives.     (line  82)
19892
* .long directive, s390:                 s390 Directives.     (line  16)
19893
* .ltorg directive, ARM:                 ARM Directives.      (line 143)
19894
* .ltorg directive, s390:                s390 Directives.     (line  88)
19895
* .m32r directive, M32R:                 M32R-Directives.     (line  66)
19896
* .m32r2 directive, M32R2:               M32R-Directives.     (line  77)
19897
* .m32rx directive, M32RX:               M32R-Directives.     (line  72)
19898
* .movsp directive, ARM:                 ARM Directives.      (line 157)
19899
* .o:                                    Object.              (line   6)
19900
* .object_arch directive, ARM:           ARM Directives.      (line 162)
19901
* .packed directive, ARM:                ARM Directives.      (line 168)
19902
* .pad directive, ARM:                   ARM Directives.      (line  25)
19903
* .param on HPPA:                        HPPA Directives.     (line  19)
19904
* .personality directive, ARM:           ARM Directives.      (line 178)
19905
* .personalityindex directive, ARM:      ARM Directives.      (line 181)
19906
* .pool directive, ARM:                  ARM Directives.      (line 185)
19907
* .quad directive, s390:                 s390 Directives.     (line  16)
19908
* .req directive, ARM:                   ARM Directives.      (line 188)
19909
* .save directive, ARM:                  ARM Directives.      (line 193)
19910
* .secrel32 directive, ARM:              ARM Directives.      (line 231)
19911
* .set arch=CPU:                         MIPS ISA.            (line  18)
19912
* .set autoextend:                       MIPS autoextend.     (line   6)
19913
* .set doublefloat:                      MIPS floating-point. (line  12)
19914
* .set dsp:                              MIPS ASE instruction generation overrides.
19915
                                                              (line  21)
19916
* .set dspr2:                            MIPS ASE instruction generation overrides.
19917
                                                              (line  26)
19918
* .set hardfloat:                        MIPS floating-point. (line   6)
19919
* .set mdmx:                             MIPS ASE instruction generation overrides.
19920
                                                              (line  16)
19921
* .set mips3d:                           MIPS ASE instruction generation overrides.
19922
                                                              (line   6)
19923
* .set mipsN:                            MIPS ISA.            (line   6)
19924
* .set mt:                               MIPS ASE instruction generation overrides.
19925
                                                              (line  32)
19926
* .set noautoextend:                     MIPS autoextend.     (line   6)
19927
* .set nodsp:                            MIPS ASE instruction generation overrides.
19928
                                                              (line  21)
19929
* .set nodspr2:                          MIPS ASE instruction generation overrides.
19930
                                                              (line  26)
19931
* .set nomdmx:                           MIPS ASE instruction generation overrides.
19932
                                                              (line  16)
19933
* .set nomips3d:                         MIPS ASE instruction generation overrides.
19934
                                                              (line   6)
19935
* .set nomt:                             MIPS ASE instruction generation overrides.
19936
                                                              (line  32)
19937
* .set nosmartmips:                      MIPS ASE instruction generation overrides.
19938
                                                              (line  11)
19939
* .set nosym32:                          MIPS symbol sizes.   (line   6)
19940
* .set pop:                              MIPS option stack.   (line   6)
19941
* .set push:                             MIPS option stack.   (line   6)
19942
* .set singlefloat:                      MIPS floating-point. (line  12)
19943
* .set smartmips:                        MIPS ASE instruction generation overrides.
19944
                                                              (line  11)
19945
* .set softfloat:                        MIPS floating-point. (line   6)
19946
* .set sym32:                            MIPS symbol sizes.   (line   6)
19947
* .setfp directive, ARM:                 ARM Directives.      (line 217)
19948
* .short directive, s390:                s390 Directives.     (line  16)
19949
* .syntax directive, ARM:                ARM Directives.      (line 236)
19950
* .thumb directive, ARM:                 ARM Directives.      (line 240)
19951
* .thumb_func directive, ARM:            ARM Directives.      (line 243)
19952
* .thumb_set directive, ARM:             ARM Directives.      (line 254)
19953
* .unreq directive, ARM:                 ARM Directives.      (line 261)
19954
* .unwind_raw directive, ARM:            ARM Directives.      (line 272)
19955
* .v850 directive, V850:                 V850 Directives.     (line  14)
19956
* .v850e directive, V850:                V850 Directives.     (line  20)
19957
* .v850e1 directive, V850:               V850 Directives.     (line  26)
19958
* .vsave directive, ARM:                 ARM Directives.      (line 279)
19959
* .z8001:                                Z8000 Directives.    (line  11)
19960
* .z8002:                                Z8000 Directives.    (line  15)
19961
* 16-bit code, i386:                     i386-16bit.          (line   6)
19962
* 2byte directive, ARC:                  ARC Directives.      (line   9)
19963
* 3byte directive, ARC:                  ARC Directives.      (line  12)
19964
* 3DNow!, i386:                          i386-SIMD.           (line   6)
19965
* 3DNow!, x86-64:                        i386-SIMD.           (line   6)
19966
* 430 support:                           MSP430-Dependent.    (line   6)
19967
* 4byte directive, ARC:                  ARC Directives.      (line  15)
19968
* : (label):                             Statements.          (line  30)
19969
* @word modifier, D10V:                  D10V-Word.           (line   6)
19970
* \" (doublequote character):            Strings.             (line  43)
19971
* \\ (\ character):                      Strings.             (line  40)
19972
* \b (backspace character):              Strings.             (line  15)
19973
* \DDD (octal character code):           Strings.             (line  30)
19974
* \f (formfeed character):               Strings.             (line  18)
19975
* \n (newline character):                Strings.             (line  21)
19976
* \r (carriage return character):        Strings.             (line  24)
19977
* \t (tab):                              Strings.             (line  27)
19978
* \XD... (hex character code):           Strings.             (line  36)
19979
* _ opcode prefix:                       Xtensa Opcodes.      (line   9)
19980
* a.out:                                 Object.              (line   6)
19981
* a.out symbol attributes:               a.out Symbols.       (line   6)
19982
* A_DIR environment variable, TIC54X:    TIC54X-Env.          (line   6)
19983
* ABI options, SH64:                     SH64 Options.        (line  29)
19984
* abort directive:                       Abort.               (line   6)
19985
* ABORT directive:                       ABORT (COFF).        (line   6)
19986
* absolute section:                      Ld Sections.         (line  29)
19987
* absolute-literals directive:           Absolute Literals Directive.
19988
                                                              (line   6)
19989
* ADDI instructions, relaxation:         Xtensa Immediate Relaxation.
19990
                                                              (line  43)
19991
* addition, permitted arguments:         Infix Ops.           (line  44)
19992
* addresses:                             Expressions.         (line   6)
19993
* addresses, format of:                  Secs Background.     (line  68)
19994
* addressing modes, D10V:                D10V-Addressing.     (line   6)
19995
* addressing modes, D30V:                D30V-Addressing.     (line   6)
19996
* addressing modes, H8/300:              H8/300-Addressing.   (line   6)
19997
* addressing modes, M680x0:              M68K-Syntax.         (line  21)
19998
* addressing modes, M68HC11:             M68HC11-Syntax.      (line  17)
19999
* addressing modes, SH:                  SH-Addressing.       (line   6)
20000
* addressing modes, SH64:                SH64-Addressing.     (line   6)
20001
* addressing modes, Z8000:               Z8000-Addressing.    (line   6)
20002
* ADR reg,
20003
* ADRL reg,
20004
* advancing location counter:            Org.                 (line   6)
20005
* align directive:                       Align.               (line   6)
20006
* align directive, SPARC:                Sparc-Directives.    (line   9)
20007
* align directive, TIC54X:               TIC54X-Directives.   (line   6)
20008
* alignment of branch targets:           Xtensa Automatic Alignment.
20009
                                                              (line   6)
20010
* alignment of LOOP instructions:        Xtensa Automatic Alignment.
20011
                                                              (line   6)
20012
* Alpha floating point (IEEE):           Alpha Floating Point.
20013
                                                              (line   6)
20014
* Alpha line comment character:          Alpha-Chars.         (line   6)
20015
* Alpha line separator:                  Alpha-Chars.         (line   8)
20016
* Alpha notes:                           Alpha Notes.         (line   6)
20017
* Alpha options:                         Alpha Options.       (line   6)
20018
* Alpha registers:                       Alpha-Regs.          (line   6)
20019
* Alpha relocations:                     Alpha-Relocs.        (line   6)
20020
* Alpha support:                         Alpha-Dependent.     (line   6)
20021
* Alpha Syntax:                          Alpha Options.       (line  62)
20022
* Alpha-only directives:                 Alpha Directives.    (line  10)
20023
* altered difference tables:             Word.                (line  12)
20024
* alternate syntax for the 680x0:        M68K-Moto-Syntax.    (line   6)
20025
* ARC floating point (IEEE):             ARC Floating Point.  (line   6)
20026
* ARC machine directives:                ARC Directives.      (line   6)
20027
* ARC opcodes:                           ARC Opcodes.         (line   6)
20028
* ARC options (none):                    ARC Options.         (line   6)
20029
* ARC register names:                    ARC-Regs.            (line   6)
20030
* ARC special characters:                ARC-Chars.           (line   6)
20031
* ARC support:                           ARC-Dependent.       (line   6)
20032
* arc5 arc5, ARC:                        ARC Options.         (line  10)
20033
* arc6 arc6, ARC:                        ARC Options.         (line  13)
20034
* arc7 arc7, ARC:                        ARC Options.         (line  21)
20035
* arc8 arc8, ARC:                        ARC Options.         (line  24)
20036
* arch directive, i386:                  i386-Arch.           (line   6)
20037
* arch directive, M680x0:                M68K-Directives.     (line  22)
20038
* arch directive, x86-64:                i386-Arch.           (line   6)
20039
* architecture options, i960:            Options-i960.        (line   6)
20040
* architecture options, IP2022:          IP2K-Opts.           (line   9)
20041
* architecture options, IP2K:            IP2K-Opts.           (line  14)
20042
* architecture options, M16C:            M32C-Opts.           (line  12)
20043
* architecture options, M32C:            M32C-Opts.           (line   9)
20044
* architecture options, M32R:            M32R-Opts.           (line  21)
20045
* architecture options, M32R2:           M32R-Opts.           (line  17)
20046
* architecture options, M32RX:           M32R-Opts.           (line   9)
20047
* architecture options, M680x0:          M68K-Opts.           (line 104)
20048
* Architecture variant option, CRIS:     CRIS-Opts.           (line  33)
20049
* architectures, PowerPC:                PowerPC-Opts.        (line   6)
20050
* architectures, SCORE:                  SCORE-Opts.          (line   6)
20051
* architectures, SPARC:                  Sparc-Opts.          (line   6)
20052
* arguments for addition:                Infix Ops.           (line  44)
20053
* arguments for subtraction:             Infix Ops.           (line  49)
20054
* arguments in expressions:              Arguments.           (line   6)
20055
* arithmetic functions:                  Operators.           (line   6)
20056
* arithmetic operands:                   Arguments.           (line   6)
20057
* ARM data relocations:                  ARM-Relocations.     (line   6)
20058
* ARM floating point (IEEE):             ARM Floating Point.  (line   6)
20059
* ARM identifiers:                       ARM-Chars.           (line  15)
20060
* ARM immediate character:               ARM-Chars.           (line  13)
20061
* ARM line comment character:            ARM-Chars.           (line   6)
20062
* ARM line separator:                    ARM-Chars.           (line  10)
20063
* ARM machine directives:                ARM Directives.      (line   6)
20064
* ARM opcodes:                           ARM Opcodes.         (line   6)
20065
* ARM options (none):                    ARM Options.         (line   6)
20066
* ARM register names:                    ARM-Regs.            (line   6)
20067
* ARM support:                           ARM-Dependent.       (line   6)
20068
* ascii directive:                       Ascii.               (line   6)
20069
* asciz directive:                       Asciz.               (line   6)
20070
* asg directive, TIC54X:                 TIC54X-Directives.   (line  20)
20071
* assembler bugs, reporting:             Bug Reporting.       (line   6)
20072
* assembler crash:                       Bug Criteria.        (line   9)
20073
* assembler directive .arch, CRIS:       CRIS-Pseudos.        (line  45)
20074
* assembler directive .dword, CRIS:      CRIS-Pseudos.        (line  12)
20075
* assembler directive .far, M68HC11:     M68HC11-Directives.  (line  20)
20076
* assembler directive .interrupt, M68HC11: M68HC11-Directives.
20077
                                                              (line  26)
20078
* assembler directive .mode, M68HC11:    M68HC11-Directives.  (line  16)
20079
* assembler directive .relax, M68HC11:   M68HC11-Directives.  (line  10)
20080
* assembler directive .syntax, CRIS:     CRIS-Pseudos.        (line  17)
20081
* assembler directive .xrefb, M68HC11:   M68HC11-Directives.  (line  31)
20082
* assembler directive BSPEC, MMIX:       MMIX-Pseudos.        (line 131)
20083
* assembler directive BYTE, MMIX:        MMIX-Pseudos.        (line  97)
20084
* assembler directive ESPEC, MMIX:       MMIX-Pseudos.        (line 131)
20085
* assembler directive GREG, MMIX:        MMIX-Pseudos.        (line  50)
20086
* assembler directive IS, MMIX:          MMIX-Pseudos.        (line  42)
20087
* assembler directive LOC, MMIX:         MMIX-Pseudos.        (line   7)
20088
* assembler directive LOCAL, MMIX:       MMIX-Pseudos.        (line  28)
20089
* assembler directive OCTA, MMIX:        MMIX-Pseudos.        (line 108)
20090
* assembler directive PREFIX, MMIX:      MMIX-Pseudos.        (line 120)
20091
* assembler directive TETRA, MMIX:       MMIX-Pseudos.        (line 108)
20092
* assembler directive WYDE, MMIX:        MMIX-Pseudos.        (line 108)
20093
* assembler directives, CRIS:            CRIS-Pseudos.        (line   6)
20094
* assembler directives, M68HC11:         M68HC11-Directives.  (line   6)
20095
* assembler directives, M68HC12:         M68HC11-Directives.  (line   6)
20096
* assembler directives, MMIX:            MMIX-Pseudos.        (line   6)
20097
* assembler internal logic error:        As Sections.         (line  13)
20098
* assembler version:                     v.                   (line   6)
20099
* assembler, and linker:                 Secs Background.     (line  10)
20100
* assembly listings, enabling:           a.                   (line   6)
20101
* assigning values to symbols <1>:       Setting Symbols.     (line   6)
20102
* assigning values to symbols:           Equ.                 (line   6)
20103
* atmp directive, i860:                  Directives-i860.     (line  16)
20104
* att_syntax pseudo op, i386:            i386-Syntax.         (line   6)
20105
* att_syntax pseudo op, x86-64:          i386-Syntax.         (line   6)
20106
* attributes, symbol:                    Symbol Attributes.   (line   6)
20107
* auxiliary attributes, COFF symbols:    COFF Symbols.        (line  19)
20108
* auxiliary symbol information, COFF:    Dim.                 (line   6)
20109
* Av7:                                   Sparc-Opts.          (line  25)
20110
* AVR line comment character:            AVR-Chars.           (line   6)
20111
* AVR line separator:                    AVR-Chars.           (line  10)
20112
* AVR modifiers:                         AVR-Modifiers.       (line   6)
20113
* AVR opcode summary:                    AVR Opcodes.         (line   6)
20114
* AVR options (none):                    AVR Options.         (line   6)
20115
* AVR register names:                    AVR-Regs.            (line   6)
20116
* AVR support:                           AVR-Dependent.       (line   6)
20117
* backslash (\\):                        Strings.             (line  40)
20118
* backspace (\b):                        Strings.             (line  15)
20119
* balign directive:                      Balign.              (line   6)
20120
* balignl directive:                     Balign.              (line  27)
20121
* balignw directive:                     Balign.              (line  27)
20122
* bes directive, TIC54X:                 TIC54X-Directives.   (line 197)
20123
* big endian output, MIPS:               Overview.            (line 641)
20124
* big endian output, PJ:                 Overview.            (line 548)
20125
* big-endian output, MIPS:               MIPS Opts.           (line  13)
20126
* bignums:                               Bignums.             (line   6)
20127
* binary constants, TIC54X:              TIC54X-Constants.    (line   8)
20128
* binary files, including:               Incbin.              (line   6)
20129
* binary integers:                       Integers.            (line   6)
20130
* bit names, IA-64:                      IA-64-Bits.          (line   6)
20131
* bitfields, not supported on VAX:       VAX-no.              (line   6)
20132
* Blackfin directives:                   Blackfin Directives. (line   6)
20133
* Blackfin options (none):               Blackfin Options.    (line   6)
20134
* Blackfin support:                      Blackfin-Dependent.  (line   6)
20135
* Blackfin syntax:                       Blackfin Syntax.     (line   6)
20136
* block:                                 Z8000 Directives.    (line  55)
20137
* branch improvement, M680x0:            M68K-Branch.         (line   6)
20138
* branch improvement, M68HC11:           M68HC11-Branch.      (line   6)
20139
* branch improvement, VAX:               VAX-branch.          (line   6)
20140
* branch instructions, relaxation:       Xtensa Branch Relaxation.
20141
                                                              (line   6)
20142
* branch recording, i960:                Options-i960.        (line  22)
20143
* branch statistics table, i960:         Options-i960.        (line  40)
20144
* branch target alignment:               Xtensa Automatic Alignment.
20145
                                                              (line   6)
20146
* break directive, TIC54X:               TIC54X-Directives.   (line 143)
20147
* BSD syntax:                            PDP-11-Syntax.       (line   6)
20148
* bss directive, i960:                   Directives-i960.     (line   6)
20149
* bss directive, TIC54X:                 TIC54X-Directives.   (line  29)
20150
* bss section <1>:                       bss.                 (line   6)
20151
* bss section:                           Ld Sections.         (line  20)
20152
* bug criteria:                          Bug Criteria.        (line   6)
20153
* bug reports:                           Bug Reporting.       (line   6)
20154
* bugs in assembler:                     Reporting Bugs.      (line   6)
20155
* Built-in symbols, CRIS:                CRIS-Symbols.        (line   6)
20156
* builtin math functions, TIC54X:        TIC54X-Builtins.     (line   6)
20157
* builtin subsym functions, TIC54X:      TIC54X-Macros.       (line  16)
20158
* bus lock prefixes, i386:               i386-Prefixes.       (line  36)
20159
* bval:                                  Z8000 Directives.    (line  30)
20160
* byte directive:                        Byte.                (line   6)
20161
* byte directive, TIC54X:                TIC54X-Directives.   (line  36)
20162
* C54XDSP_DIR environment variable, TIC54X: TIC54X-Env.       (line   6)
20163
* c_mode directive, TIC54X:              TIC54X-Directives.   (line  51)
20164
* call instructions, i386:               i386-Mnemonics.      (line  55)
20165
* call instructions, relaxation:         Xtensa Call Relaxation.
20166
                                                              (line   6)
20167
* call instructions, x86-64:             i386-Mnemonics.      (line  55)
20168
* callj, i960 pseudo-opcode:             callj-i960.          (line   6)
20169
* carriage return (\r):                  Strings.             (line  24)
20170
* case sensitivity, Z80:                 Z80-Case.            (line   6)
20171
* cfi_endproc directive:                 CFI directives.      (line  26)
20172
* cfi_sections directive:                CFI directives.      (line  13)
20173
* cfi_startproc directive:               CFI directives.      (line   6)
20174
* char directive, TIC54X:                TIC54X-Directives.   (line  36)
20175
* character constant, Z80:               Z80-Chars.           (line  13)
20176
* character constants:                   Characters.          (line   6)
20177
* character escape codes:                Strings.             (line  15)
20178
* character escapes, Z80:                Z80-Chars.           (line  11)
20179
* character, single:                     Chars.               (line   6)
20180
* characters used in symbols:            Symbol Intro.        (line   6)
20181
* clink directive, TIC54X:               TIC54X-Directives.   (line  45)
20182
* code16 directive, i386:                i386-16bit.          (line   6)
20183
* code16gcc directive, i386:             i386-16bit.          (line   6)
20184
* code32 directive, i386:                i386-16bit.          (line   6)
20185
* code64 directive, i386:                i386-16bit.          (line   6)
20186
* code64 directive, x86-64:              i386-16bit.          (line   6)
20187
* COFF auxiliary symbol information:     Dim.                 (line   6)
20188
* COFF structure debugging:              Tag.                 (line   6)
20189
* COFF symbol attributes:                COFF Symbols.        (line   6)
20190
* COFF symbol descriptor:                Desc.                (line   6)
20191
* COFF symbol storage class:             Scl.                 (line   6)
20192
* COFF symbol type:                      Type.                (line  11)
20193
* COFF symbols, debugging:               Def.                 (line   6)
20194
* COFF value attribute:                  Val.                 (line   6)
20195
* COMDAT:                                Linkonce.            (line   6)
20196
* comm directive:                        Comm.                (line   6)
20197
* command line conventions:              Command Line.        (line   6)
20198
* command line options, V850:            V850 Options.        (line   9)
20199
* command-line options ignored, VAX:     VAX-Opts.            (line   6)
20200
* comments:                              Comments.            (line   6)
20201
* comments, M680x0:                      M68K-Chars.          (line   6)
20202
* comments, removed by preprocessor:     Preprocessing.       (line  11)
20203
* common directive, SPARC:               Sparc-Directives.    (line  12)
20204
* common sections:                       Linkonce.            (line   6)
20205
* common variable storage:               bss.                 (line   6)
20206
* compare and jump expansions, i960:     Compare-and-branch-i960.
20207
                                                              (line  13)
20208
* compare/branch instructions, i960:     Compare-and-branch-i960.
20209
                                                              (line   6)
20210
* comparison expressions:                Infix Ops.           (line  55)
20211
* conditional assembly:                  If.                  (line   6)
20212
* constant, single character:            Chars.               (line   6)
20213
* constants:                             Constants.           (line   6)
20214
* constants, bignum:                     Bignums.             (line   6)
20215
* constants, character:                  Characters.          (line   6)
20216
* constants, converted by preprocessor:  Preprocessing.       (line  14)
20217
* constants, floating point:             Flonums.             (line   6)
20218
* constants, integer:                    Integers.            (line   6)
20219
* constants, number:                     Numbers.             (line   6)
20220
* constants, Sparc:                      Sparc-Constants.     (line   6)
20221
* constants, string:                     Strings.             (line   6)
20222
* constants, TIC54X:                     TIC54X-Constants.    (line   6)
20223
* conversion instructions, i386:         i386-Mnemonics.      (line  36)
20224
* conversion instructions, x86-64:       i386-Mnemonics.      (line  36)
20225
* coprocessor wait, i386:                i386-Prefixes.       (line  40)
20226
* copy directive, TIC54X:                TIC54X-Directives.   (line  54)
20227
* cpu directive, M680x0:                 M68K-Directives.     (line  30)
20228
* CR16 Operand Qualifiers:               CR16 Operand Qualifiers.
20229
                                                              (line   6)
20230
* CR16 support:                          CR16-Dependent.      (line   6)
20231
* crash of assembler:                    Bug Criteria.        (line   9)
20232
* CRIS --emulation=crisaout command line option: CRIS-Opts.   (line   9)
20233
* CRIS --emulation=criself command line option: CRIS-Opts.    (line   9)
20234
* CRIS --march=ARCHITECTURE command line option: CRIS-Opts.   (line  33)
20235
* CRIS --mul-bug-abort command line option: CRIS-Opts.        (line  61)
20236
* CRIS --no-mul-bug-abort command line option: CRIS-Opts.     (line  61)
20237
* CRIS --no-underscore command line option: CRIS-Opts.        (line  15)
20238
* CRIS --pic command line option:        CRIS-Opts.           (line  27)
20239
* CRIS --underscore command line option: CRIS-Opts.           (line  15)
20240
* CRIS -N command line option:           CRIS-Opts.           (line  57)
20241
* CRIS architecture variant option:      CRIS-Opts.           (line  33)
20242
* CRIS assembler directive .arch:        CRIS-Pseudos.        (line  45)
20243
* CRIS assembler directive .dword:       CRIS-Pseudos.        (line  12)
20244
* CRIS assembler directive .syntax:      CRIS-Pseudos.        (line  17)
20245
* CRIS assembler directives:             CRIS-Pseudos.        (line   6)
20246
* CRIS built-in symbols:                 CRIS-Symbols.        (line   6)
20247
* CRIS instruction expansion:            CRIS-Expand.         (line   6)
20248
* CRIS line comment characters:          CRIS-Chars.          (line   6)
20249
* CRIS options:                          CRIS-Opts.           (line   6)
20250
* CRIS position-independent code:        CRIS-Opts.           (line  27)
20251
* CRIS pseudo-op .arch:                  CRIS-Pseudos.        (line  45)
20252
* CRIS pseudo-op .dword:                 CRIS-Pseudos.        (line  12)
20253
* CRIS pseudo-op .syntax:                CRIS-Pseudos.        (line  17)
20254
* CRIS pseudo-ops:                       CRIS-Pseudos.        (line   6)
20255
* CRIS register names:                   CRIS-Regs.           (line   6)
20256
* CRIS support:                          CRIS-Dependent.      (line   6)
20257
* CRIS symbols in position-independent code: CRIS-Pic.        (line   6)
20258
* ctbp register, V850:                   V850-Regs.           (line 131)
20259
* ctoff pseudo-op, V850:                 V850 Opcodes.        (line 111)
20260
* ctpc register, V850:                   V850-Regs.           (line 119)
20261
* ctpsw register, V850:                  V850-Regs.           (line 122)
20262
* current address:                       Dot.                 (line   6)
20263
* current address, advancing:            Org.                 (line   6)
20264
* D10V @word modifier:                   D10V-Word.           (line   6)
20265
* D10V addressing modes:                 D10V-Addressing.     (line   6)
20266
* D10V floating point:                   D10V-Float.          (line   6)
20267
* D10V line comment character:           D10V-Chars.          (line   6)
20268
* D10V opcode summary:                   D10V-Opcodes.        (line   6)
20269
* D10V optimization:                     Overview.            (line 420)
20270
* D10V options:                          D10V-Opts.           (line   6)
20271
* D10V registers:                        D10V-Regs.           (line   6)
20272
* D10V size modifiers:                   D10V-Size.           (line   6)
20273
* D10V sub-instruction ordering:         D10V-Chars.          (line   6)
20274
* D10V sub-instructions:                 D10V-Subs.           (line   6)
20275
* D10V support:                          D10V-Dependent.      (line   6)
20276
* D10V syntax:                           D10V-Syntax.         (line   6)
20277
* D30V addressing modes:                 D30V-Addressing.     (line   6)
20278
* D30V floating point:                   D30V-Float.          (line   6)
20279
* D30V Guarded Execution:                D30V-Guarded.        (line   6)
20280
* D30V line comment character:           D30V-Chars.          (line   6)
20281
* D30V nops:                             Overview.            (line 428)
20282
* D30V nops after 32-bit multiply:       Overview.            (line 431)
20283
* D30V opcode summary:                   D30V-Opcodes.        (line   6)
20284
* D30V optimization:                     Overview.            (line 425)
20285
* D30V options:                          D30V-Opts.           (line   6)
20286
* D30V registers:                        D30V-Regs.           (line   6)
20287
* D30V size modifiers:                   D30V-Size.           (line   6)
20288
* D30V sub-instruction ordering:         D30V-Chars.          (line   6)
20289
* D30V sub-instructions:                 D30V-Subs.           (line   6)
20290
* D30V support:                          D30V-Dependent.      (line   6)
20291
* D30V syntax:                           D30V-Syntax.         (line   6)
20292
* data alignment on SPARC:               Sparc-Aligned-Data.  (line   6)
20293
* data and text sections, joining:       R.                   (line   6)
20294
* data directive:                        Data.                (line   6)
20295
* data directive, TIC54X:                TIC54X-Directives.   (line  61)
20296
* data relocations, ARM:                 ARM-Relocations.     (line   6)
20297
* data section:                          Ld Sections.         (line   9)
20298
* data1 directive, M680x0:               M68K-Directives.     (line   9)
20299
* data2 directive, M680x0:               M68K-Directives.     (line  12)
20300
* datalabel, SH64:                       SH64-Addressing.     (line  16)
20301
* dbpc register, V850:                   V850-Regs.           (line 125)
20302
* dbpsw register, V850:                  V850-Regs.           (line 128)
20303
* debuggers, and symbol order:           Symbols.             (line  10)
20304
* debugging COFF symbols:                Def.                 (line   6)
20305
* DEC syntax:                            PDP-11-Syntax.       (line   6)
20306
* decimal integers:                      Integers.            (line  12)
20307
* def directive:                         Def.                 (line   6)
20308
* def directive, TIC54X:                 TIC54X-Directives.   (line 103)
20309
* density instructions:                  Density Instructions.
20310
                                                              (line   6)
20311
* dependency tracking:                   MD.                  (line   6)
20312
* deprecated directives:                 Deprecated.          (line   6)
20313
* desc directive:                        Desc.                (line   6)
20314
* descriptor, of a.out symbol:           Symbol Desc.         (line   6)
20315
* dfloat directive, VAX:                 VAX-directives.      (line  10)
20316
* difference tables altered:             Word.                (line  12)
20317
* difference tables, warning:            K.                   (line   6)
20318
* differences, mmixal:                   MMIX-mmixal.         (line   6)
20319
* dim directive:                         Dim.                 (line   6)
20320
* directives and instructions:           Statements.          (line  19)
20321
* directives for PowerPC:                PowerPC-Pseudo.      (line   6)
20322
* directives for SCORE:                  SCORE-Pseudo.        (line   6)
20323
* directives, Blackfin:                  Blackfin Directives. (line   6)
20324
* directives, M32R:                      M32R-Directives.     (line   6)
20325
* directives, M680x0:                    M68K-Directives.     (line   6)
20326
* directives, machine independent:       Pseudo Ops.          (line   6)
20327
* directives, Xtensa:                    Xtensa Directives.   (line   6)
20328
* directives, Z8000:                     Z8000 Directives.    (line   6)
20329
* Disable floating-point instructions:   MIPS floating-point. (line   6)
20330
* Disable single-precision floating-point operations: MIPS floating-point.
20331
                                                              (line  12)
20332
* displacement sizing character, VAX:    VAX-operands.        (line  12)
20333
* dollar local symbols:                  Symbol Names.        (line 105)
20334
* dot (symbol):                          Dot.                 (line   6)
20335
* double directive:                      Double.              (line   6)
20336
* double directive, i386:                i386-Float.          (line  14)
20337
* double directive, M680x0:              M68K-Float.          (line  14)
20338
* double directive, M68HC11:             M68HC11-Float.       (line  14)
20339
* double directive, TIC54X:              TIC54X-Directives.   (line  64)
20340
* double directive, VAX:                 VAX-float.           (line  15)
20341
* double directive, x86-64:              i386-Float.          (line  14)
20342
* doublequote (\"):                      Strings.             (line  43)
20343
* drlist directive, TIC54X:              TIC54X-Directives.   (line  73)
20344
* drnolist directive, TIC54X:            TIC54X-Directives.   (line  73)
20345
* dual directive, i860:                  Directives-i860.     (line   6)
20346
* ECOFF sections:                        MIPS Object.         (line   6)
20347
* ecr register, V850:                    V850-Regs.           (line 113)
20348
* eight-byte integer:                    Quad.                (line   9)
20349
* eipc register, V850:                   V850-Regs.           (line 101)
20350
* eipsw register, V850:                  V850-Regs.           (line 104)
20351
* eject directive:                       Eject.               (line   6)
20352
* ELF symbol type:                       Type.                (line  22)
20353
* else directive:                        Else.                (line   6)
20354
* elseif directive:                      Elseif.              (line   6)
20355
* empty expressions:                     Empty Exprs.         (line   6)
20356
* emsg directive, TIC54X:                TIC54X-Directives.   (line  77)
20357
* emulation:                             Overview.            (line 744)
20358
* encoding options, i386:                i386-Mnemonics.      (line  32)
20359
* encoding options, x86-64:              i386-Mnemonics.      (line  32)
20360
* end directive:                         End.                 (line   6)
20361
* enddual directive, i860:               Directives-i860.     (line  11)
20362
* endef directive:                       Endef.               (line   6)
20363
* endfunc directive:                     Endfunc.             (line   6)
20364
* endianness, MIPS:                      Overview.            (line 641)
20365
* endianness, PJ:                        Overview.            (line 548)
20366
* endif directive:                       Endif.               (line   6)
20367
* endloop directive, TIC54X:             TIC54X-Directives.   (line 143)
20368
* endm directive:                        Macro.               (line 138)
20369
* endm directive, TIC54X:                TIC54X-Directives.   (line 153)
20370
* endstruct directive, TIC54X:           TIC54X-Directives.   (line 217)
20371
* endunion directive, TIC54X:            TIC54X-Directives.   (line 251)
20372
* environment settings, TIC54X:          TIC54X-Env.          (line   6)
20373
* EOF, newline must precede:             Statements.          (line  13)
20374
* ep register, V850:                     V850-Regs.           (line  95)
20375
* equ directive:                         Equ.                 (line   6)
20376
* equ directive, TIC54X:                 TIC54X-Directives.   (line 192)
20377
* equiv directive:                       Equiv.               (line   6)
20378
* eqv directive:                         Eqv.                 (line   6)
20379
* err directive:                         Err.                 (line   6)
20380
* error directive:                       Error.               (line   6)
20381
* error messages:                        Errors.              (line   6)
20382
* error on valid input:                  Bug Criteria.        (line  12)
20383
* errors, caused by warnings:            W.                   (line  16)
20384
* errors, continuing after:              Z.                   (line   6)
20385
* ESA/390 floating point (IEEE):         ESA/390 Floating Point.
20386
                                                              (line   6)
20387
* ESA/390 support:                       ESA/390-Dependent.   (line   6)
20388
* ESA/390 Syntax:                        ESA/390 Options.     (line   8)
20389
* ESA/390-only directives:               ESA/390 Directives.  (line  12)
20390
* escape codes, character:               Strings.             (line  15)
20391
* eval directive, TIC54X:                TIC54X-Directives.   (line  24)
20392
* even:                                  Z8000 Directives.    (line  58)
20393
* even directive, M680x0:                M68K-Directives.     (line  15)
20394
* even directive, TIC54X:                TIC54X-Directives.   (line   6)
20395
* exitm directive:                       Macro.               (line 141)
20396
* expr (internal section):               As Sections.         (line  17)
20397
* expression arguments:                  Arguments.           (line   6)
20398
* expressions:                           Expressions.         (line   6)
20399
* expressions, comparison:               Infix Ops.           (line  55)
20400
* expressions, empty:                    Empty Exprs.         (line   6)
20401
* expressions, integer:                  Integer Exprs.       (line   6)
20402
* extAuxRegister directive, ARC:         ARC Directives.      (line  18)
20403
* extCondCode directive, ARC:            ARC Directives.      (line  41)
20404
* extCoreRegister directive, ARC:        ARC Directives.      (line  53)
20405
* extend directive M680x0:               M68K-Float.          (line  17)
20406
* extend directive M68HC11:              M68HC11-Float.       (line  17)
20407
* extended directive, i960:              Directives-i960.     (line  13)
20408
* extern directive:                      Extern.              (line   6)
20409
* extInstruction directive, ARC:         ARC Directives.      (line  78)
20410
* fail directive:                        Fail.                (line   6)
20411
* far_mode directive, TIC54X:            TIC54X-Directives.   (line  82)
20412
* faster processing (-f):                f.                   (line   6)
20413
* fatal signal:                          Bug Criteria.        (line   9)
20414
* fclist directive, TIC54X:              TIC54X-Directives.   (line  87)
20415
* fcnolist directive, TIC54X:            TIC54X-Directives.   (line  87)
20416
* fepc register, V850:                   V850-Regs.           (line 107)
20417
* fepsw register, V850:                  V850-Regs.           (line 110)
20418
* ffloat directive, VAX:                 VAX-directives.      (line  14)
20419
* field directive, TIC54X:               TIC54X-Directives.   (line  91)
20420
* file directive:                        File.                (line   6)
20421
* file directive, MSP 430:               MSP430 Directives.   (line   6)
20422
* file name, logical:                    File.                (line  13)
20423
* files, including:                      Include.             (line   6)
20424
* files, input:                          Input Files.         (line   6)
20425
* fill directive:                        Fill.                (line   6)
20426
* filling memory <1>:                    Skip.                (line   6)
20427
* filling memory:                        Space.               (line   6)
20428
* FLIX syntax:                           Xtensa Syntax.       (line   6)
20429
* float directive:                       Float.               (line   6)
20430
* float directive, i386:                 i386-Float.          (line  14)
20431
* float directive, M680x0:               M68K-Float.          (line  11)
20432
* float directive, M68HC11:              M68HC11-Float.       (line  11)
20433
* float directive, TIC54X:               TIC54X-Directives.   (line  64)
20434
* float directive, VAX:                  VAX-float.           (line  15)
20435
* float directive, x86-64:               i386-Float.          (line  14)
20436
* floating point numbers:                Flonums.             (line   6)
20437
* floating point numbers (double):       Double.              (line   6)
20438
* floating point numbers (single) <1>:   Float.               (line   6)
20439
* floating point numbers (single):       Single.              (line   6)
20440
* floating point, Alpha (IEEE):          Alpha Floating Point.
20441
                                                              (line   6)
20442
* floating point, ARC (IEEE):            ARC Floating Point.  (line   6)
20443
* floating point, ARM (IEEE):            ARM Floating Point.  (line   6)
20444
* floating point, D10V:                  D10V-Float.          (line   6)
20445
* floating point, D30V:                  D30V-Float.          (line   6)
20446
* floating point, ESA/390 (IEEE):        ESA/390 Floating Point.
20447
                                                              (line   6)
20448
* floating point, H8/300 (IEEE):         H8/300 Floating Point.
20449
                                                              (line   6)
20450
* floating point, HPPA (IEEE):           HPPA Floating Point. (line   6)
20451
* floating point, i386:                  i386-Float.          (line   6)
20452
* floating point, i960 (IEEE):           Floating Point-i960. (line   6)
20453
* floating point, M680x0:                M68K-Float.          (line   6)
20454
* floating point, M68HC11:               M68HC11-Float.       (line   6)
20455
* floating point, MSP 430 (IEEE):        MSP430 Floating Point.
20456
                                                              (line   6)
20457
* floating point, s390:                  s390 Floating Point. (line   6)
20458
* floating point, SH (IEEE):             SH Floating Point.   (line   6)
20459
* floating point, SPARC (IEEE):          Sparc-Float.         (line   6)
20460
* floating point, V850 (IEEE):           V850 Floating Point. (line   6)
20461
* floating point, VAX:                   VAX-float.           (line   6)
20462
* floating point, x86-64:                i386-Float.          (line   6)
20463
* floating point, Z80:                   Z80 Floating Point.  (line   6)
20464
* flonums:                               Flonums.             (line   6)
20465
* format of error messages:              Errors.              (line  24)
20466
* format of warning messages:            Errors.              (line  12)
20467
* formfeed (\f):                         Strings.             (line  18)
20468
* func directive:                        Func.                (line   6)
20469
* functions, in expressions:             Operators.           (line   6)
20470
* gbr960, i960 postprocessor:            Options-i960.        (line  40)
20471
* gfloat directive, VAX:                 VAX-directives.      (line  18)
20472
* global:                                Z8000 Directives.    (line  21)
20473
* global directive:                      Global.              (line   6)
20474
* global directive, TIC54X:              TIC54X-Directives.   (line 103)
20475
* gp register, MIPS:                     MIPS Object.         (line  11)
20476
* gp register, V850:                     V850-Regs.           (line  17)
20477
* grouping data:                         Sub-Sections.        (line   6)
20478
* H8/300 addressing modes:               H8/300-Addressing.   (line   6)
20479
* H8/300 floating point (IEEE):          H8/300 Floating Point.
20480
                                                              (line   6)
20481
* H8/300 line comment character:         H8/300-Chars.        (line   6)
20482
* H8/300 line separator:                 H8/300-Chars.        (line   8)
20483
* H8/300 machine directives (none):      H8/300 Directives.   (line   6)
20484
* H8/300 opcode summary:                 H8/300 Opcodes.      (line   6)
20485
* H8/300 options:                        H8/300 Options.      (line   6)
20486
* H8/300 registers:                      H8/300-Regs.         (line   6)
20487
* H8/300 size suffixes:                  H8/300 Opcodes.      (line 163)
20488
* H8/300 support:                        H8/300-Dependent.    (line   6)
20489
* H8/300H, assembling for:               H8/300 Directives.   (line   8)
20490
* half directive, ARC:                   ARC Directives.      (line 156)
20491
* half directive, SPARC:                 Sparc-Directives.    (line  17)
20492
* half directive, TIC54X:                TIC54X-Directives.   (line 111)
20493
* hex character code (\XD...):           Strings.             (line  36)
20494
* hexadecimal integers:                  Integers.            (line  15)
20495
* hexadecimal prefix, Z80:               Z80-Chars.           (line   8)
20496
* hfloat directive, VAX:                 VAX-directives.      (line  22)
20497
* hi pseudo-op, V850:                    V850 Opcodes.        (line  33)
20498
* hi0 pseudo-op, V850:                   V850 Opcodes.        (line  10)
20499
* hidden directive:                      Hidden.              (line   6)
20500
* high directive, M32R:                  M32R-Directives.     (line  18)
20501
* hilo pseudo-op, V850:                  V850 Opcodes.        (line  55)
20502
* HPPA directives not supported:         HPPA Directives.     (line  11)
20503
* HPPA floating point (IEEE):            HPPA Floating Point. (line   6)
20504
* HPPA Syntax:                           HPPA Options.        (line   8)
20505
* HPPA-only directives:                  HPPA Directives.     (line  24)
20506
* hword directive:                       hword.               (line   6)
20507
* i370 support:                          ESA/390-Dependent.   (line   6)
20508
* i386 16-bit code:                      i386-16bit.          (line   6)
20509
* i386 arch directive:                   i386-Arch.           (line   6)
20510
* i386 att_syntax pseudo op:             i386-Syntax.         (line   6)
20511
* i386 conversion instructions:          i386-Mnemonics.      (line  36)
20512
* i386 floating point:                   i386-Float.          (line   6)
20513
* i386 immediate operands:               i386-Syntax.         (line  15)
20514
* i386 instruction naming:               i386-Mnemonics.      (line   6)
20515
* i386 instruction prefixes:             i386-Prefixes.       (line   6)
20516
* i386 intel_syntax pseudo op:           i386-Syntax.         (line   6)
20517
* i386 jump optimization:                i386-Jumps.          (line   6)
20518
* i386 jump, call, return:               i386-Syntax.         (line  38)
20519
* i386 jump/call operands:               i386-Syntax.         (line  15)
20520
* i386 memory references:                i386-Memory.         (line   6)
20521
* i386 mnemonic compatibility:           i386-Mnemonics.      (line  61)
20522
* i386 mul, imul instructions:           i386-Notes.          (line   6)
20523
* i386 options:                          i386-Options.        (line   6)
20524
* i386 register operands:                i386-Syntax.         (line  15)
20525
* i386 registers:                        i386-Regs.           (line   6)
20526
* i386 sections:                         i386-Syntax.         (line  44)
20527
* i386 size suffixes:                    i386-Syntax.         (line  29)
20528
* i386 source, destination operands:     i386-Syntax.         (line  22)
20529
* i386 support:                          i386-Dependent.      (line   6)
20530
* i386 syntax compatibility:             i386-Syntax.         (line   6)
20531
* i80386 support:                        i386-Dependent.      (line   6)
20532
* i860 machine directives:               Directives-i860.     (line   6)
20533
* i860 opcodes:                          Opcodes for i860.    (line   6)
20534
* i860 support:                          i860-Dependent.      (line   6)
20535
* i960 architecture options:             Options-i960.        (line   6)
20536
* i960 branch recording:                 Options-i960.        (line  22)
20537
* i960 callj pseudo-opcode:              callj-i960.          (line   6)
20538
* i960 compare and jump expansions:      Compare-and-branch-i960.
20539
                                                              (line  13)
20540
* i960 compare/branch instructions:      Compare-and-branch-i960.
20541
                                                              (line   6)
20542
* i960 floating point (IEEE):            Floating Point-i960. (line   6)
20543
* i960 machine directives:               Directives-i960.     (line   6)
20544
* i960 opcodes:                          Opcodes for i960.    (line   6)
20545
* i960 options:                          Options-i960.        (line   6)
20546
* i960 support:                          i960-Dependent.      (line   6)
20547
* IA-64 line comment character:          IA-64-Chars.         (line   6)
20548
* IA-64 line separator:                  IA-64-Chars.         (line   8)
20549
* IA-64 options:                         IA-64 Options.       (line   6)
20550
* IA-64 Processor-status-Register bit names: IA-64-Bits.      (line   6)
20551
* IA-64 registers:                       IA-64-Regs.          (line   6)
20552
* IA-64 support:                         IA-64-Dependent.     (line   6)
20553
* IA-64 Syntax:                          IA-64 Options.       (line  96)
20554
* ident directive:                       Ident.               (line   6)
20555
* identifiers, ARM:                      ARM-Chars.           (line  15)
20556
* identifiers, MSP 430:                  MSP430-Chars.        (line   8)
20557
* if directive:                          If.                  (line   6)
20558
* ifb directive:                         If.                  (line  21)
20559
* ifc directive:                         If.                  (line  25)
20560
* ifdef directive:                       If.                  (line  16)
20561
* ifeq directive:                        If.                  (line  33)
20562
* ifeqs directive:                       If.                  (line  36)
20563
* ifge directive:                        If.                  (line  40)
20564
* ifgt directive:                        If.                  (line  44)
20565
* ifle directive:                        If.                  (line  48)
20566
* iflt directive:                        If.                  (line  52)
20567
* ifnb directive:                        If.                  (line  56)
20568
* ifnc directive:                        If.                  (line  61)
20569
* ifndef directive:                      If.                  (line  65)
20570
* ifne directive:                        If.                  (line  72)
20571
* ifnes directive:                       If.                  (line  76)
20572
* ifnotdef directive:                    If.                  (line  65)
20573
* immediate character, ARM:              ARM-Chars.           (line  13)
20574
* immediate character, M680x0:           M68K-Chars.          (line   6)
20575
* immediate character, VAX:              VAX-operands.        (line   6)
20576
* immediate fields, relaxation:          Xtensa Immediate Relaxation.
20577
                                                              (line   6)
20578
* immediate operands, i386:              i386-Syntax.         (line  15)
20579
* immediate operands, x86-64:            i386-Syntax.         (line  15)
20580
* imul instruction, i386:                i386-Notes.          (line   6)
20581
* imul instruction, x86-64:              i386-Notes.          (line   6)
20582
* incbin directive:                      Incbin.              (line   6)
20583
* include directive:                     Include.             (line   6)
20584
* include directive search path:         I.                   (line   6)
20585
* indirect character, VAX:               VAX-operands.        (line   9)
20586
* infix operators:                       Infix Ops.           (line   6)
20587
* inhibiting interrupts, i386:           i386-Prefixes.       (line  36)
20588
* input:                                 Input Files.         (line   6)
20589
* input file linenumbers:                Input Files.         (line  35)
20590
* instruction aliases, s390:             s390 Aliases.        (line   6)
20591
* instruction expansion, CRIS:           CRIS-Expand.         (line   6)
20592
* instruction expansion, MMIX:           MMIX-Expand.         (line   6)
20593
* instruction formats, s390:             s390 Formats.        (line   6)
20594
* instruction marker, s390:              s390 Instruction Marker.
20595
                                                              (line   6)
20596
* instruction mnemonics, s390:           s390 Mnemonics.      (line   6)
20597
* instruction naming, i386:              i386-Mnemonics.      (line   6)
20598
* instruction naming, x86-64:            i386-Mnemonics.      (line   6)
20599
* instruction operand modifier, s390:    s390 Operand Modifier.
20600
                                                              (line   6)
20601
* instruction operands, s390:            s390 Operands.       (line   6)
20602
* instruction prefixes, i386:            i386-Prefixes.       (line   6)
20603
* instruction set, M680x0:               M68K-opcodes.        (line   6)
20604
* instruction set, M68HC11:              M68HC11-opcodes.     (line   6)
20605
* instruction summary, AVR:              AVR Opcodes.         (line   6)
20606
* instruction summary, D10V:             D10V-Opcodes.        (line   6)
20607
* instruction summary, D30V:             D30V-Opcodes.        (line   6)
20608
* instruction summary, H8/300:           H8/300 Opcodes.      (line   6)
20609
* instruction summary, LM32:             LM32 Opcodes.        (line   6)
20610
* instruction summary, SH:               SH Opcodes.          (line   6)
20611
* instruction summary, SH64:             SH64 Opcodes.        (line   6)
20612
* instruction summary, Z8000:            Z8000 Opcodes.       (line   6)
20613
* instruction syntax, s390:              s390 Syntax.         (line   6)
20614
* instructions and directives:           Statements.          (line  19)
20615
* int directive:                         Int.                 (line   6)
20616
* int directive, H8/300:                 H8/300 Directives.   (line   6)
20617
* int directive, i386:                   i386-Float.          (line  21)
20618
* int directive, TIC54X:                 TIC54X-Directives.   (line 111)
20619
* int directive, x86-64:                 i386-Float.          (line  21)
20620
* integer expressions:                   Integer Exprs.       (line   6)
20621
* integer, 16-byte:                      Octa.                (line   6)
20622
* integer, 8-byte:                       Quad.                (line   9)
20623
* integers:                              Integers.            (line   6)
20624
* integers, 16-bit:                      hword.               (line   6)
20625
* integers, 32-bit:                      Int.                 (line   6)
20626
* integers, binary:                      Integers.            (line   6)
20627
* integers, decimal:                     Integers.            (line  12)
20628
* integers, hexadecimal:                 Integers.            (line  15)
20629
* integers, octal:                       Integers.            (line   9)
20630
* integers, one byte:                    Byte.                (line   6)
20631
* intel_syntax pseudo op, i386:          i386-Syntax.         (line   6)
20632
* intel_syntax pseudo op, x86-64:        i386-Syntax.         (line   6)
20633
* internal assembler sections:           As Sections.         (line   6)
20634
* internal directive:                    Internal.            (line   6)
20635
* invalid input:                         Bug Criteria.        (line  14)
20636
* invocation summary:                    Overview.            (line   6)
20637
* IP2K architecture options:             IP2K-Opts.           (line  14)
20638
* IP2K options:                          IP2K-Opts.           (line   6)
20639
* IP2K support:                          IP2K-Dependent.      (line   6)
20640
* irp directive:                         Irp.                 (line   6)
20641
* irpc directive:                        Irpc.                (line   6)
20642
* ISA options, SH64:                     SH64 Options.        (line   6)
20643
* joining text and data sections:        R.                   (line   6)
20644
* jump instructions, i386:               i386-Mnemonics.      (line  55)
20645
* jump instructions, x86-64:             i386-Mnemonics.      (line  55)
20646
* jump optimization, i386:               i386-Jumps.          (line   6)
20647
* jump optimization, x86-64:             i386-Jumps.          (line   6)
20648
* jump/call operands, i386:              i386-Syntax.         (line  15)
20649
* jump/call operands, x86-64:            i386-Syntax.         (line  15)
20650
* L16SI instructions, relaxation:        Xtensa Immediate Relaxation.
20651
                                                              (line  23)
20652
* L16UI instructions, relaxation:        Xtensa Immediate Relaxation.
20653
                                                              (line  23)
20654
* L32I instructions, relaxation:         Xtensa Immediate Relaxation.
20655
                                                              (line  23)
20656
* L8UI instructions, relaxation:         Xtensa Immediate Relaxation.
20657
                                                              (line  23)
20658
* label (:):                             Statements.          (line  30)
20659
* label directive, TIC54X:               TIC54X-Directives.   (line 123)
20660
* labels:                                Labels.              (line   6)
20661
* lcomm directive:                       Lcomm.               (line   6)
20662
* lcomm directive, COFF:                 i386-Directives.     (line   6)
20663
* ld:                                    Object.              (line  15)
20664
* ldouble directive M680x0:              M68K-Float.          (line  17)
20665
* ldouble directive M68HC11:             M68HC11-Float.       (line  17)
20666
* ldouble directive, TIC54X:             TIC54X-Directives.   (line  64)
20667
* LDR reg,=
20668
* leafproc directive, i960:              Directives-i960.     (line  18)
20669
* length directive, TIC54X:              TIC54X-Directives.   (line 127)
20670
* length of symbols:                     Symbol Intro.        (line  14)
20671
* lflags directive (ignored):            Lflags.              (line   6)
20672
* line comment character:                Comments.            (line  19)
20673
* line comment character, Alpha:         Alpha-Chars.         (line   6)
20674
* line comment character, ARM:           ARM-Chars.           (line   6)
20675
* line comment character, AVR:           AVR-Chars.           (line   6)
20676
* line comment character, D10V:          D10V-Chars.          (line   6)
20677
* line comment character, D30V:          D30V-Chars.          (line   6)
20678
* line comment character, H8/300:        H8/300-Chars.        (line   6)
20679
* line comment character, IA-64:         IA-64-Chars.         (line   6)
20680
* line comment character, M680x0:        M68K-Chars.          (line   6)
20681
* line comment character, MSP 430:       MSP430-Chars.        (line   6)
20682
* line comment character, s390:          s390 Characters.     (line   6)
20683
* line comment character, SH:            SH-Chars.            (line   6)
20684
* line comment character, SH64:          SH64-Chars.          (line   6)
20685
* line comment character, Sparc:         Sparc-Chars.         (line   6)
20686
* line comment character, V850:          V850-Chars.          (line   6)
20687
* line comment character, Z80:           Z80-Chars.           (line   6)
20688
* line comment character, Z8000:         Z8000-Chars.         (line   6)
20689
* line comment characters, CRIS:         CRIS-Chars.          (line   6)
20690
* line comment characters, MMIX:         MMIX-Chars.          (line   6)
20691
* line directive:                        Line.                (line   6)
20692
* line directive, MSP 430:               MSP430 Directives.   (line  14)
20693
* line numbers, in input files:          Input Files.         (line  35)
20694
* line numbers, in warnings/errors:      Errors.              (line  16)
20695
* line separator character:              Statements.          (line   6)
20696
* line separator, Alpha:                 Alpha-Chars.         (line   8)
20697
* line separator, ARM:                   ARM-Chars.           (line  10)
20698
* line separator, AVR:                   AVR-Chars.           (line  10)
20699
* line separator, H8/300:                H8/300-Chars.        (line   8)
20700
* line separator, IA-64:                 IA-64-Chars.         (line   8)
20701
* line separator, SH:                    SH-Chars.            (line   8)
20702
* line separator, SH64:                  SH64-Chars.          (line   8)
20703
* line separator, Sparc:                 Sparc-Chars.         (line   8)
20704
* line separator, Z8000:                 Z8000-Chars.         (line   8)
20705
* lines starting with #:                 Comments.            (line  39)
20706
* linker:                                Object.              (line  15)
20707
* linker, and assembler:                 Secs Background.     (line  10)
20708
* linkonce directive:                    Linkonce.            (line   6)
20709
* list directive:                        List.                (line   6)
20710
* list directive, TIC54X:                TIC54X-Directives.   (line 131)
20711
* listing control, turning off:          Nolist.              (line   6)
20712
* listing control, turning on:           List.                (line   6)
20713
* listing control: new page:             Eject.               (line   6)
20714
* listing control: paper size:           Psize.               (line   6)
20715
* listing control: subtitle:             Sbttl.               (line   6)
20716
* listing control: title line:           Title.               (line   6)
20717
* listings, enabling:                    a.                   (line   6)
20718
* literal directive:                     Literal Directive.   (line   6)
20719
* literal pool entries, s390:            s390 Literal Pool Entries.
20720
                                                              (line   6)
20721
* literal_position directive:            Literal Position Directive.
20722
                                                              (line   6)
20723
* literal_prefix directive:              Literal Prefix Directive.
20724
                                                              (line   6)
20725
* little endian output, MIPS:            Overview.            (line 644)
20726
* little endian output, PJ:              Overview.            (line 551)
20727
* little-endian output, MIPS:            MIPS Opts.           (line  13)
20728
* LM32 modifiers:                        LM32-Modifiers.      (line   6)
20729
* LM32 opcode summary:                   LM32 Opcodes.        (line   6)
20730
* LM32 options (none):                   LM32 Options.        (line   6)
20731
* LM32 register names:                   LM32-Regs.           (line   6)
20732
* LM32 support:                          LM32-Dependent.      (line   6)
20733
* ln directive:                          Ln.                  (line   6)
20734
* lo pseudo-op, V850:                    V850 Opcodes.        (line  22)
20735
* loc directive:                         Loc.                 (line   6)
20736
* loc_mark_labels directive:             Loc_mark_labels.     (line   6)
20737
* local common symbols:                  Lcomm.               (line   6)
20738
* local directive:                       Local.               (line   6)
20739
* local labels:                          Symbol Names.        (line  35)
20740
* local symbol names:                    Symbol Names.        (line  22)
20741
* local symbols, retaining in output:    L.                   (line   6)
20742
* location counter:                      Dot.                 (line   6)
20743
* location counter, advancing:           Org.                 (line   6)
20744
* location counter, Z80:                 Z80-Chars.           (line   8)
20745
* logical file name:                     File.                (line  13)
20746
* logical line number:                   Line.                (line   6)
20747
* logical line numbers:                  Comments.            (line  39)
20748
* long directive:                        Long.                (line   6)
20749
* long directive, ARC:                   ARC Directives.      (line 159)
20750
* long directive, i386:                  i386-Float.          (line  21)
20751
* long directive, TIC54X:                TIC54X-Directives.   (line 135)
20752
* long directive, x86-64:                i386-Float.          (line  21)
20753
* longcall pseudo-op, V850:              V850 Opcodes.        (line 123)
20754
* longcalls directive:                   Longcalls Directive. (line   6)
20755
* longjump pseudo-op, V850:              V850 Opcodes.        (line 129)
20756
* loop directive, TIC54X:                TIC54X-Directives.   (line 143)
20757
* LOOP instructions, alignment:          Xtensa Automatic Alignment.
20758
                                                              (line   6)
20759
* low directive, M32R:                   M32R-Directives.     (line   9)
20760
* lp register, V850:                     V850-Regs.           (line  98)
20761
* lval:                                  Z8000 Directives.    (line  27)
20762
* M16C architecture option:              M32C-Opts.           (line  12)
20763
* M32C architecture option:              M32C-Opts.           (line   9)
20764
* M32C modifiers:                        M32C-Modifiers.      (line   6)
20765
* M32C options:                          M32C-Opts.           (line   6)
20766
* M32C support:                          M32C-Dependent.      (line   6)
20767
* M32R architecture options:             M32R-Opts.           (line   9)
20768
* M32R directives:                       M32R-Directives.     (line   6)
20769
* M32R options:                          M32R-Opts.           (line   6)
20770
* M32R support:                          M32R-Dependent.      (line   6)
20771
* M32R warnings:                         M32R-Warnings.       (line   6)
20772
* M680x0 addressing modes:               M68K-Syntax.         (line  21)
20773
* M680x0 architecture options:           M68K-Opts.           (line 104)
20774
* M680x0 branch improvement:             M68K-Branch.         (line   6)
20775
* M680x0 directives:                     M68K-Directives.     (line   6)
20776
* M680x0 floating point:                 M68K-Float.          (line   6)
20777
* M680x0 immediate character:            M68K-Chars.          (line   6)
20778
* M680x0 line comment character:         M68K-Chars.          (line   6)
20779
* M680x0 opcodes:                        M68K-opcodes.        (line   6)
20780
* M680x0 options:                        M68K-Opts.           (line   6)
20781
* M680x0 pseudo-opcodes:                 M68K-Branch.         (line   6)
20782
* M680x0 size modifiers:                 M68K-Syntax.         (line   8)
20783
* M680x0 support:                        M68K-Dependent.      (line   6)
20784
* M680x0 syntax:                         M68K-Syntax.         (line   8)
20785
* M68HC11 addressing modes:              M68HC11-Syntax.      (line  17)
20786
* M68HC11 and M68HC12 support:           M68HC11-Dependent.   (line   6)
20787
* M68HC11 assembler directive .far:      M68HC11-Directives.  (line  20)
20788
* M68HC11 assembler directive .interrupt: M68HC11-Directives. (line  26)
20789
* M68HC11 assembler directive .mode:     M68HC11-Directives.  (line  16)
20790
* M68HC11 assembler directive .relax:    M68HC11-Directives.  (line  10)
20791
* M68HC11 assembler directive .xrefb:    M68HC11-Directives.  (line  31)
20792
* M68HC11 assembler directives:          M68HC11-Directives.  (line   6)
20793
* M68HC11 branch improvement:            M68HC11-Branch.      (line   6)
20794
* M68HC11 floating point:                M68HC11-Float.       (line   6)
20795
* M68HC11 modifiers:                     M68HC11-Modifiers.   (line   6)
20796
* M68HC11 opcodes:                       M68HC11-opcodes.     (line   6)
20797
* M68HC11 options:                       M68HC11-Opts.        (line   6)
20798
* M68HC11 pseudo-opcodes:                M68HC11-Branch.      (line   6)
20799
* M68HC11 syntax:                        M68HC11-Syntax.      (line   6)
20800
* M68HC12 assembler directives:          M68HC11-Directives.  (line   6)
20801
* machine dependencies:                  Machine Dependencies.
20802
                                                              (line   6)
20803
* machine directives, ARC:               ARC Directives.      (line   6)
20804
* machine directives, ARM:               ARM Directives.      (line   6)
20805
* machine directives, H8/300 (none):     H8/300 Directives.   (line   6)
20806
* machine directives, i860:              Directives-i860.     (line   6)
20807
* machine directives, i960:              Directives-i960.     (line   6)
20808
* machine directives, MSP 430:           MSP430 Directives.   (line   6)
20809
* machine directives, SH:                SH Directives.       (line   6)
20810
* machine directives, SH64:              SH64 Directives.     (line   9)
20811
* machine directives, SPARC:             Sparc-Directives.    (line   6)
20812
* machine directives, TIC54X:            TIC54X-Directives.   (line   6)
20813
* machine directives, V850:              V850 Directives.     (line   6)
20814
* machine directives, VAX:               VAX-directives.      (line   6)
20815
* machine directives, x86:               i386-Directives.     (line   6)
20816
* machine independent directives:        Pseudo Ops.          (line   6)
20817
* machine instructions (not covered):    Manual.              (line  14)
20818
* machine-independent syntax:            Syntax.              (line   6)
20819
* macro directive:                       Macro.               (line  28)
20820
* macro directive, TIC54X:               TIC54X-Directives.   (line 153)
20821
* macros:                                Macro.               (line   6)
20822
* macros, count executed:                Macro.               (line 143)
20823
* Macros, MSP 430:                       MSP430-Macros.       (line   6)
20824
* macros, TIC54X:                        TIC54X-Macros.       (line   6)
20825
* make rules:                            MD.                  (line   6)
20826
* manual, structure and purpose:         Manual.              (line   6)
20827
* math builtins, TIC54X:                 TIC54X-Builtins.     (line   6)
20828
* Maximum number of continuation lines:  listing.             (line  34)
20829
* memory references, i386:               i386-Memory.         (line   6)
20830
* memory references, x86-64:             i386-Memory.         (line   6)
20831
* memory-mapped registers, TIC54X:       TIC54X-MMRegs.       (line   6)
20832
* merging text and data sections:        R.                   (line   6)
20833
* messages from assembler:               Errors.              (line   6)
20834
* MicroBlaze architectures:              MicroBlaze-Dependent.
20835
                                                              (line   6)
20836
* MicroBlaze directives:                 MicroBlaze Directives.
20837
                                                              (line   6)
20838
* MicroBlaze support:                    MicroBlaze-Dependent.
20839
                                                              (line  13)
20840
* minus, permitted arguments:            Infix Ops.           (line  49)
20841
* MIPS architecture options:             MIPS Opts.           (line  29)
20842
* MIPS big-endian output:                MIPS Opts.           (line  13)
20843
* MIPS CPU override:                     MIPS ISA.            (line  18)
20844
* MIPS debugging directives:             MIPS Stabs.          (line   6)
20845
* MIPS DSP Release 1 instruction generation override: MIPS ASE instruction generation overrides.
20846
                                                              (line  21)
20847
* MIPS DSP Release 2 instruction generation override: MIPS ASE instruction generation overrides.
20848
                                                              (line  26)
20849
* MIPS ECOFF sections:                   MIPS Object.         (line   6)
20850
* MIPS endianness:                       Overview.            (line 641)
20851
* MIPS ISA:                              Overview.            (line 647)
20852
* MIPS ISA override:                     MIPS ISA.            (line   6)
20853
* MIPS little-endian output:             MIPS Opts.           (line  13)
20854
* MIPS MDMX instruction generation override: MIPS ASE instruction generation overrides.
20855
                                                              (line  16)
20856
* MIPS MIPS-3D instruction generation override: MIPS ASE instruction generation overrides.
20857
                                                              (line   6)
20858
* MIPS MT instruction generation override: MIPS ASE instruction generation overrides.
20859
                                                              (line  32)
20860
* MIPS option stack:                     MIPS option stack.   (line   6)
20861
* MIPS processor:                        MIPS-Dependent.      (line   6)
20862
* MIT:                                   M68K-Syntax.         (line   6)
20863
* mlib directive, TIC54X:                TIC54X-Directives.   (line 159)
20864
* mlist directive, TIC54X:               TIC54X-Directives.   (line 164)
20865
* MMIX assembler directive BSPEC:        MMIX-Pseudos.        (line 131)
20866
* MMIX assembler directive BYTE:         MMIX-Pseudos.        (line  97)
20867
* MMIX assembler directive ESPEC:        MMIX-Pseudos.        (line 131)
20868
* MMIX assembler directive GREG:         MMIX-Pseudos.        (line  50)
20869
* MMIX assembler directive IS:           MMIX-Pseudos.        (line  42)
20870
* MMIX assembler directive LOC:          MMIX-Pseudos.        (line   7)
20871
* MMIX assembler directive LOCAL:        MMIX-Pseudos.        (line  28)
20872
* MMIX assembler directive OCTA:         MMIX-Pseudos.        (line 108)
20873
* MMIX assembler directive PREFIX:       MMIX-Pseudos.        (line 120)
20874
* MMIX assembler directive TETRA:        MMIX-Pseudos.        (line 108)
20875
* MMIX assembler directive WYDE:         MMIX-Pseudos.        (line 108)
20876
* MMIX assembler directives:             MMIX-Pseudos.        (line   6)
20877
* MMIX line comment characters:          MMIX-Chars.          (line   6)
20878
* MMIX options:                          MMIX-Opts.           (line   6)
20879
* MMIX pseudo-op BSPEC:                  MMIX-Pseudos.        (line 131)
20880
* MMIX pseudo-op BYTE:                   MMIX-Pseudos.        (line  97)
20881
* MMIX pseudo-op ESPEC:                  MMIX-Pseudos.        (line 131)
20882
* MMIX pseudo-op GREG:                   MMIX-Pseudos.        (line  50)
20883
* MMIX pseudo-op IS:                     MMIX-Pseudos.        (line  42)
20884
* MMIX pseudo-op LOC:                    MMIX-Pseudos.        (line   7)
20885
* MMIX pseudo-op LOCAL:                  MMIX-Pseudos.        (line  28)
20886
* MMIX pseudo-op OCTA:                   MMIX-Pseudos.        (line 108)
20887
* MMIX pseudo-op PREFIX:                 MMIX-Pseudos.        (line 120)
20888
* MMIX pseudo-op TETRA:                  MMIX-Pseudos.        (line 108)
20889
* MMIX pseudo-op WYDE:                   MMIX-Pseudos.        (line 108)
20890
* MMIX pseudo-ops:                       MMIX-Pseudos.        (line   6)
20891
* MMIX register names:                   MMIX-Regs.           (line   6)
20892
* MMIX support:                          MMIX-Dependent.      (line   6)
20893
* mmixal differences:                    MMIX-mmixal.         (line   6)
20894
* mmregs directive, TIC54X:              TIC54X-Directives.   (line 170)
20895
* mmsg directive, TIC54X:                TIC54X-Directives.   (line  77)
20896
* MMX, i386:                             i386-SIMD.           (line   6)
20897
* MMX, x86-64:                           i386-SIMD.           (line   6)
20898
* mnemonic compatibility, i386:          i386-Mnemonics.      (line  61)
20899
* mnemonic suffixes, i386:               i386-Syntax.         (line  29)
20900
* mnemonic suffixes, x86-64:             i386-Syntax.         (line  29)
20901
* mnemonics for opcodes, VAX:            VAX-opcodes.         (line   6)
20902
* mnemonics, AVR:                        AVR Opcodes.         (line   6)
20903
* mnemonics, D10V:                       D10V-Opcodes.        (line   6)
20904
* mnemonics, D30V:                       D30V-Opcodes.        (line   6)
20905
* mnemonics, H8/300:                     H8/300 Opcodes.      (line   6)
20906
* mnemonics, LM32:                       LM32 Opcodes.        (line   6)
20907
* mnemonics, SH:                         SH Opcodes.          (line   6)
20908
* mnemonics, SH64:                       SH64 Opcodes.        (line   6)
20909
* mnemonics, Z8000:                      Z8000 Opcodes.       (line   6)
20910
* mnolist directive, TIC54X:             TIC54X-Directives.   (line 164)
20911
* Motorola syntax for the 680x0:         M68K-Moto-Syntax.    (line   6)
20912
* MOVI instructions, relaxation:         Xtensa Immediate Relaxation.
20913
                                                              (line  12)
20914
* MOVW and MOVT relocations, ARM:        ARM-Relocations.     (line  20)
20915
* MRI compatibility mode:                M.                   (line   6)
20916
* mri directive:                         MRI.                 (line   6)
20917
* MRI mode, temporarily:                 MRI.                 (line   6)
20918
* MSP 430 floating point (IEEE):         MSP430 Floating Point.
20919
                                                              (line   6)
20920
* MSP 430 identifiers:                   MSP430-Chars.        (line   8)
20921
* MSP 430 line comment character:        MSP430-Chars.        (line   6)
20922
* MSP 430 machine directives:            MSP430 Directives.   (line   6)
20923
* MSP 430 macros:                        MSP430-Macros.       (line   6)
20924
* MSP 430 opcodes:                       MSP430 Opcodes.      (line   6)
20925
* MSP 430 options (none):                MSP430 Options.      (line   6)
20926
* MSP 430 profiling capability:          MSP430 Profiling Capability.
20927
                                                              (line   6)
20928
* MSP 430 register names:                MSP430-Regs.         (line   6)
20929
* MSP 430 support:                       MSP430-Dependent.    (line   6)
20930
* MSP430 Assembler Extensions:           MSP430-Ext.          (line   6)
20931
* mul instruction, i386:                 i386-Notes.          (line   6)
20932
* mul instruction, x86-64:               i386-Notes.          (line   6)
20933
* name:                                  Z8000 Directives.    (line  18)
20934
* named section:                         Section.             (line   6)
20935
* named sections:                        Ld Sections.         (line   8)
20936
* names, symbol:                         Symbol Names.        (line   6)
20937
* naming object file:                    o.                   (line   6)
20938
* new page, in listings:                 Eject.               (line   6)
20939
* newblock directive, TIC54X:            TIC54X-Directives.   (line 176)
20940
* newline (\n):                          Strings.             (line  21)
20941
* newline, required at file end:         Statements.          (line  13)
20942
* no-absolute-literals directive:        Absolute Literals Directive.
20943
                                                              (line   6)
20944
* no-longcalls directive:                Longcalls Directive. (line   6)
20945
* no-schedule directive:                 Schedule Directive.  (line   6)
20946
* no-transform directive:                Transform Directive. (line   6)
20947
* nolist directive:                      Nolist.              (line   6)
20948
* nolist directive, TIC54X:              TIC54X-Directives.   (line 131)
20949
* NOP pseudo op, ARM:                    ARM Opcodes.         (line   9)
20950
* notes for Alpha:                       Alpha Notes.         (line   6)
20951
* null-terminated strings:               Asciz.               (line   6)
20952
* number constants:                      Numbers.             (line   6)
20953
* number of macros executed:             Macro.               (line 143)
20954
* numbered subsections:                  Sub-Sections.        (line   6)
20955
* numbers, 16-bit:                       hword.               (line   6)
20956
* numeric values:                        Expressions.         (line   6)
20957
* nword directive, SPARC:                Sparc-Directives.    (line  20)
20958
* object attributes:                     Object Attributes.   (line   6)
20959
* object file:                           Object.              (line   6)
20960
* object file format:                    Object Formats.      (line   6)
20961
* object file name:                      o.                   (line   6)
20962
* object file, after errors:             Z.                   (line   6)
20963
* obsolescent directives:                Deprecated.          (line   6)
20964
* octa directive:                        Octa.                (line   6)
20965
* octal character code (\DDD):           Strings.             (line  30)
20966
* octal integers:                        Integers.            (line   9)
20967
* offset directive, V850:                V850 Directives.     (line   6)
20968
* opcode mnemonics, VAX:                 VAX-opcodes.         (line   6)
20969
* opcode names, Xtensa:                  Xtensa Opcodes.      (line   6)
20970
* opcode summary, AVR:                   AVR Opcodes.         (line   6)
20971
* opcode summary, D10V:                  D10V-Opcodes.        (line   6)
20972
* opcode summary, D30V:                  D30V-Opcodes.        (line   6)
20973
* opcode summary, H8/300:                H8/300 Opcodes.      (line   6)
20974
* opcode summary, LM32:                  LM32 Opcodes.        (line   6)
20975
* opcode summary, SH:                    SH Opcodes.          (line   6)
20976
* opcode summary, SH64:                  SH64 Opcodes.        (line   6)
20977
* opcode summary, Z8000:                 Z8000 Opcodes.       (line   6)
20978
* opcodes for ARC:                       ARC Opcodes.         (line   6)
20979
* opcodes for ARM:                       ARM Opcodes.         (line   6)
20980
* opcodes for MSP 430:                   MSP430 Opcodes.      (line   6)
20981
* opcodes for V850:                      V850 Opcodes.        (line   6)
20982
* opcodes, i860:                         Opcodes for i860.    (line   6)
20983
* opcodes, i960:                         Opcodes for i960.    (line   6)
20984
* opcodes, M680x0:                       M68K-opcodes.        (line   6)
20985
* opcodes, M68HC11:                      M68HC11-opcodes.     (line   6)
20986
* operand delimiters, i386:              i386-Syntax.         (line  15)
20987
* operand delimiters, x86-64:            i386-Syntax.         (line  15)
20988
* operand notation, VAX:                 VAX-operands.        (line   6)
20989
* operands in expressions:               Arguments.           (line   6)
20990
* operator precedence:                   Infix Ops.           (line  11)
20991
* operators, in expressions:             Operators.           (line   6)
20992
* operators, permitted arguments:        Infix Ops.           (line   6)
20993
* optimization, D10V:                    Overview.            (line 420)
20994
* optimization, D30V:                    Overview.            (line 425)
20995
* optimizations:                         Xtensa Optimizations.
20996
                                                              (line   6)
20997
* option directive, ARC:                 ARC Directives.      (line 162)
20998
* option directive, TIC54X:              TIC54X-Directives.   (line 180)
20999
* option summary:                        Overview.            (line   6)
21000
* options for Alpha:                     Alpha Options.       (line   6)
21001
* options for ARC (none):                ARC Options.         (line   6)
21002
* options for ARM (none):                ARM Options.         (line   6)
21003
* options for AVR (none):                AVR Options.         (line   6)
21004
* options for Blackfin (none):           Blackfin Options.    (line   6)
21005
* options for i386:                      i386-Options.        (line   6)
21006
* options for IA-64:                     IA-64 Options.       (line   6)
21007
* options for LM32 (none):               LM32 Options.        (line   6)
21008
* options for MSP430 (none):             MSP430 Options.      (line   6)
21009
* options for PDP-11:                    PDP-11-Options.      (line   6)
21010
* options for PowerPC:                   PowerPC-Opts.        (line   6)
21011
* options for s390:                      s390 Options.        (line   6)
21012
* options for SCORE:                     SCORE-Opts.          (line   6)
21013
* options for SPARC:                     Sparc-Opts.          (line   6)
21014
* options for V850 (none):               V850 Options.        (line   6)
21015
* options for VAX/VMS:                   VAX-Opts.            (line  42)
21016
* options for x86-64:                    i386-Options.        (line   6)
21017
* options for Z80:                       Z80 Options.         (line   6)
21018
* options, all versions of assembler:    Invoking.            (line   6)
21019
* options, command line:                 Command Line.        (line  13)
21020
* options, CRIS:                         CRIS-Opts.           (line   6)
21021
* options, D10V:                         D10V-Opts.           (line   6)
21022
* options, D30V:                         D30V-Opts.           (line   6)
21023
* options, H8/300:                       H8/300 Options.      (line   6)
21024
* options, i960:                         Options-i960.        (line   6)
21025
* options, IP2K:                         IP2K-Opts.           (line   6)
21026
* options, M32C:                         M32C-Opts.           (line   6)
21027
* options, M32R:                         M32R-Opts.           (line   6)
21028
* options, M680x0:                       M68K-Opts.           (line   6)
21029
* options, M68HC11:                      M68HC11-Opts.        (line   6)
21030
* options, MMIX:                         MMIX-Opts.           (line   6)
21031
* options, PJ:                           PJ Options.          (line   6)
21032
* options, SH:                           SH Options.          (line   6)
21033
* options, SH64:                         SH64 Options.        (line   6)
21034
* options, TIC54X:                       TIC54X-Opts.         (line   6)
21035
* options, Z8000:                        Z8000 Options.       (line   6)
21036
* org directive:                         Org.                 (line   6)
21037
* other attribute, of a.out symbol:      Symbol Other.        (line   6)
21038
* output file:                           Object.              (line   6)
21039
* p2align directive:                     P2align.             (line   6)
21040
* p2alignl directive:                    P2align.             (line  28)
21041
* p2alignw directive:                    P2align.             (line  28)
21042
* padding the location counter:          Align.               (line   6)
21043
* padding the location counter given a power of two: P2align. (line   6)
21044
* padding the location counter given number of bytes: Balign. (line   6)
21045
* page, in listings:                     Eject.               (line   6)
21046
* paper size, for listings:              Psize.               (line   6)
21047
* paths for .include:                    I.                   (line   6)
21048
* patterns, writing in memory:           Fill.                (line   6)
21049
* PDP-11 comments:                       PDP-11-Syntax.       (line  16)
21050
* PDP-11 floating-point register syntax: PDP-11-Syntax.       (line  13)
21051
* PDP-11 general-purpose register syntax: PDP-11-Syntax.      (line  10)
21052
* PDP-11 instruction naming:             PDP-11-Mnemonics.    (line   6)
21053
* PDP-11 support:                        PDP-11-Dependent.    (line   6)
21054
* PDP-11 syntax:                         PDP-11-Syntax.       (line   6)
21055
* PIC code generation for ARM:           ARM Options.         (line 139)
21056
* PIC code generation for M32R:          M32R-Opts.           (line  42)
21057
* PIC selection, MIPS:                   MIPS Opts.           (line  21)
21058
* PJ endianness:                         Overview.            (line 548)
21059
* PJ options:                            PJ Options.          (line   6)
21060
* PJ support:                            PJ-Dependent.        (line   6)
21061
* plus, permitted arguments:             Infix Ops.           (line  44)
21062
* popsection directive:                  PopSection.          (line   6)
21063
* Position-independent code, CRIS:       CRIS-Opts.           (line  27)
21064
* Position-independent code, symbols in, CRIS: CRIS-Pic.      (line   6)
21065
* PowerPC architectures:                 PowerPC-Opts.        (line   6)
21066
* PowerPC directives:                    PowerPC-Pseudo.      (line   6)
21067
* PowerPC options:                       PowerPC-Opts.        (line   6)
21068
* PowerPC support:                       PPC-Dependent.       (line   6)
21069
* precedence of operators:               Infix Ops.           (line  11)
21070
* precision, floating point:             Flonums.             (line   6)
21071
* prefix operators:                      Prefix Ops.          (line   6)
21072
* prefixes, i386:                        i386-Prefixes.       (line   6)
21073
* preprocessing:                         Preprocessing.       (line   6)
21074
* preprocessing, turning on and off:     Preprocessing.       (line  27)
21075
* previous directive:                    Previous.            (line   6)
21076
* primary attributes, COFF symbols:      COFF Symbols.        (line  13)
21077
* print directive:                       Print.               (line   6)
21078
* proc directive, SPARC:                 Sparc-Directives.    (line  25)
21079
* profiler directive, MSP 430:           MSP430 Directives.   (line  22)
21080
* profiling capability for MSP 430:      MSP430 Profiling Capability.
21081
                                                              (line   6)
21082
* protected directive:                   Protected.           (line   6)
21083
* pseudo-op .arch, CRIS:                 CRIS-Pseudos.        (line  45)
21084
* pseudo-op .dword, CRIS:                CRIS-Pseudos.        (line  12)
21085
* pseudo-op .syntax, CRIS:               CRIS-Pseudos.        (line  17)
21086
* pseudo-op BSPEC, MMIX:                 MMIX-Pseudos.        (line 131)
21087
* pseudo-op BYTE, MMIX:                  MMIX-Pseudos.        (line  97)
21088
* pseudo-op ESPEC, MMIX:                 MMIX-Pseudos.        (line 131)
21089
* pseudo-op GREG, MMIX:                  MMIX-Pseudos.        (line  50)
21090
* pseudo-op IS, MMIX:                    MMIX-Pseudos.        (line  42)
21091
* pseudo-op LOC, MMIX:                   MMIX-Pseudos.        (line   7)
21092
* pseudo-op LOCAL, MMIX:                 MMIX-Pseudos.        (line  28)
21093
* pseudo-op OCTA, MMIX:                  MMIX-Pseudos.        (line 108)
21094
* pseudo-op PREFIX, MMIX:                MMIX-Pseudos.        (line 120)
21095
* pseudo-op TETRA, MMIX:                 MMIX-Pseudos.        (line 108)
21096
* pseudo-op WYDE, MMIX:                  MMIX-Pseudos.        (line 108)
21097
* pseudo-opcodes, M680x0:                M68K-Branch.         (line   6)
21098
* pseudo-opcodes, M68HC11:               M68HC11-Branch.      (line   6)
21099
* pseudo-ops for branch, VAX:            VAX-branch.          (line   6)
21100
* pseudo-ops, CRIS:                      CRIS-Pseudos.        (line   6)
21101
* pseudo-ops, machine independent:       Pseudo Ops.          (line   6)
21102
* pseudo-ops, MMIX:                      MMIX-Pseudos.        (line   6)
21103
* psize directive:                       Psize.               (line   6)
21104
* PSR bits:                              IA-64-Bits.          (line   6)
21105
* pstring directive, TIC54X:             TIC54X-Directives.   (line 209)
21106
* psw register, V850:                    V850-Regs.           (line 116)
21107
* purgem directive:                      Purgem.              (line   6)
21108
* purpose of GNU assembler:              GNU Assembler.       (line  12)
21109
* pushsection directive:                 PushSection.         (line   6)
21110
* quad directive:                        Quad.                (line   6)
21111
* quad directive, i386:                  i386-Float.          (line  21)
21112
* quad directive, x86-64:                i386-Float.          (line  21)
21113
* real-mode code, i386:                  i386-16bit.          (line   6)
21114
* ref directive, TIC54X:                 TIC54X-Directives.   (line 103)
21115
* register directive, SPARC:             Sparc-Directives.    (line  29)
21116
* register names, Alpha:                 Alpha-Regs.          (line   6)
21117
* register names, ARC:                   ARC-Regs.            (line   6)
21118
* register names, ARM:                   ARM-Regs.            (line   6)
21119
* register names, AVR:                   AVR-Regs.            (line   6)
21120
* register names, CRIS:                  CRIS-Regs.           (line   6)
21121
* register names, H8/300:                H8/300-Regs.         (line   6)
21122
* register names, IA-64:                 IA-64-Regs.          (line   6)
21123
* register names, LM32:                  LM32-Regs.           (line   6)
21124
* register names, MMIX:                  MMIX-Regs.           (line   6)
21125
* register names, MSP 430:               MSP430-Regs.         (line   6)
21126
* register names, Sparc:                 Sparc-Regs.          (line   6)
21127
* register names, V850:                  V850-Regs.           (line   6)
21128
* register names, VAX:                   VAX-operands.        (line  17)
21129
* register names, Xtensa:                Xtensa Registers.    (line   6)
21130
* register names, Z80:                   Z80-Regs.            (line   6)
21131
* register naming, s390:                 s390 Register.       (line   6)
21132
* register operands, i386:               i386-Syntax.         (line  15)
21133
* register operands, x86-64:             i386-Syntax.         (line  15)
21134
* registers, D10V:                       D10V-Regs.           (line   6)
21135
* registers, D30V:                       D30V-Regs.           (line   6)
21136
* registers, i386:                       i386-Regs.           (line   6)
21137
* registers, SH:                         SH-Regs.             (line   6)
21138
* registers, SH64:                       SH64-Regs.           (line   6)
21139
* registers, TIC54X memory-mapped:       TIC54X-MMRegs.       (line   6)
21140
* registers, x86-64:                     i386-Regs.           (line   6)
21141
* registers, Z8000:                      Z8000-Regs.          (line   6)
21142
* relaxation:                            Xtensa Relaxation.   (line   6)
21143
* relaxation of ADDI instructions:       Xtensa Immediate Relaxation.
21144
                                                              (line  43)
21145
* relaxation of branch instructions:     Xtensa Branch Relaxation.
21146
                                                              (line   6)
21147
* relaxation of call instructions:       Xtensa Call Relaxation.
21148
                                                              (line   6)
21149
* relaxation of immediate fields:        Xtensa Immediate Relaxation.
21150
                                                              (line   6)
21151
* relaxation of L16SI instructions:      Xtensa Immediate Relaxation.
21152
                                                              (line  23)
21153
* relaxation of L16UI instructions:      Xtensa Immediate Relaxation.
21154
                                                              (line  23)
21155
* relaxation of L32I instructions:       Xtensa Immediate Relaxation.
21156
                                                              (line  23)
21157
* relaxation of L8UI instructions:       Xtensa Immediate Relaxation.
21158
                                                              (line  23)
21159
* relaxation of MOVI instructions:       Xtensa Immediate Relaxation.
21160
                                                              (line  12)
21161
* reloc directive:                       Reloc.               (line   6)
21162
* relocation:                            Sections.            (line   6)
21163
* relocation example:                    Ld Sections.         (line  40)
21164
* relocations, Alpha:                    Alpha-Relocs.        (line   6)
21165
* relocations, Sparc:                    Sparc-Relocs.        (line   6)
21166
* repeat prefixes, i386:                 i386-Prefixes.       (line  44)
21167
* reporting bugs in assembler:           Reporting Bugs.      (line   6)
21168
* rept directive:                        Rept.                (line   6)
21169
* reserve directive, SPARC:              Sparc-Directives.    (line  39)
21170
* return instructions, i386:             i386-Syntax.         (line  38)
21171
* return instructions, x86-64:           i386-Syntax.         (line  38)
21172
* REX prefixes, i386:                    i386-Prefixes.       (line  46)
21173
* rsect:                                 Z8000 Directives.    (line  52)
21174
* s390 floating point:                   s390 Floating Point. (line   6)
21175
* s390 instruction aliases:              s390 Aliases.        (line   6)
21176
* s390 instruction formats:              s390 Formats.        (line   6)
21177
* s390 instruction marker:               s390 Instruction Marker.
21178
                                                              (line   6)
21179
* s390 instruction mnemonics:            s390 Mnemonics.      (line   6)
21180
* s390 instruction operand modifier:     s390 Operand Modifier.
21181
                                                              (line   6)
21182
* s390 instruction operands:             s390 Operands.       (line   6)
21183
* s390 instruction syntax:               s390 Syntax.         (line   6)
21184
* s390 line comment character:           s390 Characters.     (line   6)
21185
* s390 literal pool entries:             s390 Literal Pool Entries.
21186
                                                              (line   6)
21187
* s390 options:                          s390 Options.        (line   6)
21188
* s390 register naming:                  s390 Register.       (line   6)
21189
* s390 support:                          S/390-Dependent.     (line   6)
21190
* sblock directive, TIC54X:              TIC54X-Directives.   (line 183)
21191
* sbttl directive:                       Sbttl.               (line   6)
21192
* schedule directive:                    Schedule Directive.  (line   6)
21193
* scl directive:                         Scl.                 (line   6)
21194
* SCORE architectures:                   SCORE-Opts.          (line   6)
21195
* SCORE directives:                      SCORE-Pseudo.        (line   6)
21196
* SCORE options:                         SCORE-Opts.          (line   6)
21197
* SCORE processor:                       SCORE-Dependent.     (line   6)
21198
* sdaoff pseudo-op, V850:                V850 Opcodes.        (line  65)
21199
* search path for .include:              I.                   (line   6)
21200
* sect directive, MSP 430:               MSP430 Directives.   (line  18)
21201
* sect directive, TIC54X:                TIC54X-Directives.   (line 189)
21202
* section directive (COFF version):      Section.             (line  16)
21203
* section directive (ELF version):       Section.             (line  73)
21204
* section directive, V850:               V850 Directives.     (line   9)
21205
* section override prefixes, i386:       i386-Prefixes.       (line  23)
21206
* Section Stack <1>:                     Section.             (line  68)
21207
* Section Stack <2>:                     SubSection.          (line   6)
21208
* Section Stack <3>:                     PopSection.          (line   6)
21209
* Section Stack <4>:                     PushSection.         (line   6)
21210
* Section Stack:                         Previous.            (line   6)
21211
* section-relative addressing:           Secs Background.     (line  68)
21212
* sections:                              Sections.            (line   6)
21213
* sections in messages, internal:        As Sections.         (line   6)
21214
* sections, i386:                        i386-Syntax.         (line  44)
21215
* sections, named:                       Ld Sections.         (line   8)
21216
* sections, x86-64:                      i386-Syntax.         (line  44)
21217
* seg directive, SPARC:                  Sparc-Directives.    (line  44)
21218
* segm:                                  Z8000 Directives.    (line  10)
21219
* set directive:                         Set.                 (line   6)
21220
* set directive, TIC54X:                 TIC54X-Directives.   (line 192)
21221
* SH addressing modes:                   SH-Addressing.       (line   6)
21222
* SH floating point (IEEE):              SH Floating Point.   (line   6)
21223
* SH line comment character:             SH-Chars.            (line   6)
21224
* SH line separator:                     SH-Chars.            (line   8)
21225
* SH machine directives:                 SH Directives.       (line   6)
21226
* SH opcode summary:                     SH Opcodes.          (line   6)
21227
* SH options:                            SH Options.          (line   6)
21228
* SH registers:                          SH-Regs.             (line   6)
21229
* SH support:                            SH-Dependent.        (line   6)
21230
* SH64 ABI options:                      SH64 Options.        (line  29)
21231
* SH64 addressing modes:                 SH64-Addressing.     (line   6)
21232
* SH64 ISA options:                      SH64 Options.        (line   6)
21233
* SH64 line comment character:           SH64-Chars.          (line   6)
21234
* SH64 line separator:                   SH64-Chars.          (line   8)
21235
* SH64 machine directives:               SH64 Directives.     (line   9)
21236
* SH64 opcode summary:                   SH64 Opcodes.        (line   6)
21237
* SH64 options:                          SH64 Options.        (line   6)
21238
* SH64 registers:                        SH64-Regs.           (line   6)
21239
* SH64 support:                          SH64-Dependent.      (line   6)
21240
* shigh directive, M32R:                 M32R-Directives.     (line  26)
21241
* short directive:                       Short.               (line   6)
21242
* short directive, ARC:                  ARC Directives.      (line 171)
21243
* short directive, TIC54X:               TIC54X-Directives.   (line 111)
21244
* SIMD, i386:                            i386-SIMD.           (line   6)
21245
* SIMD, x86-64:                          i386-SIMD.           (line   6)
21246
* single character constant:             Chars.               (line   6)
21247
* single directive:                      Single.              (line   6)
21248
* single directive, i386:                i386-Float.          (line  14)
21249
* single directive, x86-64:              i386-Float.          (line  14)
21250
* single quote, Z80:                     Z80-Chars.           (line  13)
21251
* sixteen bit integers:                  hword.               (line   6)
21252
* sixteen byte integer:                  Octa.                (line   6)
21253
* size directive (COFF version):         Size.                (line  11)
21254
* size directive (ELF version):          Size.                (line  19)
21255
* size modifiers, D10V:                  D10V-Size.           (line   6)
21256
* size modifiers, D30V:                  D30V-Size.           (line   6)
21257
* size modifiers, M680x0:                M68K-Syntax.         (line   8)
21258
* size prefixes, i386:                   i386-Prefixes.       (line  27)
21259
* size suffixes, H8/300:                 H8/300 Opcodes.      (line 163)
21260
* size, translations, Sparc:             Sparc-Size-Translations.
21261
                                                              (line   6)
21262
* sizes operands, i386:                  i386-Syntax.         (line  29)
21263
* sizes operands, x86-64:                i386-Syntax.         (line  29)
21264
* skip directive:                        Skip.                (line   6)
21265
* skip directive, M680x0:                M68K-Directives.     (line  19)
21266
* skip directive, SPARC:                 Sparc-Directives.    (line  48)
21267
* sleb128 directive:                     Sleb128.             (line   6)
21268
* small objects, MIPS ECOFF:             MIPS Object.         (line  11)
21269
* SmartMIPS instruction generation override: MIPS ASE instruction generation overrides.
21270
                                                              (line  11)
21271
* SOM symbol attributes:                 SOM Symbols.         (line   6)
21272
* source program:                        Input Files.         (line   6)
21273
* source, destination operands; i386:    i386-Syntax.         (line  22)
21274
* source, destination operands; x86-64:  i386-Syntax.         (line  22)
21275
* sp register:                           Xtensa Registers.    (line   6)
21276
* sp register, V850:                     V850-Regs.           (line  14)
21277
* space directive:                       Space.               (line   6)
21278
* space directive, TIC54X:               TIC54X-Directives.   (line 197)
21279
* space used, maximum for assembly:      statistics.          (line   6)
21280
* SPARC architectures:                   Sparc-Opts.          (line   6)
21281
* Sparc constants:                       Sparc-Constants.     (line   6)
21282
* SPARC data alignment:                  Sparc-Aligned-Data.  (line   6)
21283
* SPARC floating point (IEEE):           Sparc-Float.         (line   6)
21284
* Sparc line comment character:          Sparc-Chars.         (line   6)
21285
* Sparc line separator:                  Sparc-Chars.         (line   8)
21286
* SPARC machine directives:              Sparc-Directives.    (line   6)
21287
* SPARC options:                         Sparc-Opts.          (line   6)
21288
* Sparc registers:                       Sparc-Regs.          (line   6)
21289
* Sparc relocations:                     Sparc-Relocs.        (line   6)
21290
* Sparc size translations:               Sparc-Size-Translations.
21291
                                                              (line   6)
21292
* SPARC support:                         Sparc-Dependent.     (line   6)
21293
* SPARC syntax:                          Sparc-Aligned-Data.  (line  21)
21294
* special characters, ARC:               ARC-Chars.           (line   6)
21295
* special characters, M680x0:            M68K-Chars.          (line   6)
21296
* special purpose registers, MSP 430:    MSP430-Regs.         (line  11)
21297
* sslist directive, TIC54X:              TIC54X-Directives.   (line 204)
21298
* ssnolist directive, TIC54X:            TIC54X-Directives.   (line 204)
21299
* stabd directive:                       Stab.                (line  38)
21300
* stabn directive:                       Stab.                (line  48)
21301
* stabs directive:                       Stab.                (line  51)
21302
* stabX directives:                      Stab.                (line   6)
21303
* standard assembler sections:           Secs Background.     (line  27)
21304
* standard input, as input file:         Command Line.        (line  10)
21305
* statement separator character:         Statements.          (line   6)
21306
* statement separator, Alpha:            Alpha-Chars.         (line   8)
21307
* statement separator, ARM:              ARM-Chars.           (line  10)
21308
* statement separator, AVR:              AVR-Chars.           (line  10)
21309
* statement separator, H8/300:           H8/300-Chars.        (line   8)
21310
* statement separator, IA-64:            IA-64-Chars.         (line   8)
21311
* statement separator, SH:               SH-Chars.            (line   8)
21312
* statement separator, SH64:             SH64-Chars.          (line   8)
21313
* statement separator, Sparc:            Sparc-Chars.         (line   8)
21314
* statement separator, Z8000:            Z8000-Chars.         (line   8)
21315
* statements, structure of:              Statements.          (line   6)
21316
* statistics, about assembly:            statistics.          (line   6)
21317
* stopping the assembly:                 Abort.               (line   6)
21318
* string constants:                      Strings.             (line   6)
21319
* string directive:                      String.              (line   8)
21320
* string directive on HPPA:              HPPA Directives.     (line 137)
21321
* string directive, TIC54X:              TIC54X-Directives.   (line 209)
21322
* string literals:                       Ascii.               (line   6)
21323
* string, copying to object file:        String.              (line   8)
21324
* string16 directive:                    String.              (line   8)
21325
* string16, copying to object file:      String.              (line   8)
21326
* string32 directive:                    String.              (line   8)
21327
* string32, copying to object file:      String.              (line   8)
21328
* string64 directive:                    String.              (line   8)
21329
* string64, copying to object file:      String.              (line   8)
21330
* string8 directive:                     String.              (line   8)
21331
* string8, copying to object file:       String.              (line   8)
21332
* struct directive:                      Struct.              (line   6)
21333
* struct directive, TIC54X:              TIC54X-Directives.   (line 217)
21334
* structure debugging, COFF:             Tag.                 (line   6)
21335
* sub-instruction ordering, D10V:        D10V-Chars.          (line   6)
21336
* sub-instruction ordering, D30V:        D30V-Chars.          (line   6)
21337
* sub-instructions, D10V:                D10V-Subs.           (line   6)
21338
* sub-instructions, D30V:                D30V-Subs.           (line   6)
21339
* subexpressions:                        Arguments.           (line  24)
21340
* subsection directive:                  SubSection.          (line   6)
21341
* subsym builtins, TIC54X:               TIC54X-Macros.       (line  16)
21342
* subtitles for listings:                Sbttl.               (line   6)
21343
* subtraction, permitted arguments:      Infix Ops.           (line  49)
21344
* summary of options:                    Overview.            (line   6)
21345
* support:                               HPPA-Dependent.      (line   6)
21346
* supporting files, including:           Include.             (line   6)
21347
* suppressing warnings:                  W.                   (line  11)
21348
* sval:                                  Z8000 Directives.    (line  33)
21349
* symbol attributes:                     Symbol Attributes.   (line   6)
21350
* symbol attributes, a.out:              a.out Symbols.       (line   6)
21351
* symbol attributes, COFF:               COFF Symbols.        (line   6)
21352
* symbol attributes, SOM:                SOM Symbols.         (line   6)
21353
* symbol descriptor, COFF:               Desc.                (line   6)
21354
* symbol modifiers <1>:                  AVR-Modifiers.       (line  12)
21355
* symbol modifiers <2>:                  LM32-Modifiers.      (line  12)
21356
* symbol modifiers <3>:                  M32C-Modifiers.      (line  11)
21357
* symbol modifiers:                      M68HC11-Modifiers.   (line  12)
21358
* symbol names:                          Symbol Names.        (line   6)
21359
* symbol names, $ in <1>:                SH-Chars.            (line  10)
21360
* symbol names, $ in <2>:                SH64-Chars.          (line  10)
21361
* symbol names, $ in <3>:                D30V-Chars.          (line  63)
21362
* symbol names, $ in:                    D10V-Chars.          (line  46)
21363
* symbol names, local:                   Symbol Names.        (line  22)
21364
* symbol names, temporary:               Symbol Names.        (line  35)
21365
* symbol storage class (COFF):           Scl.                 (line   6)
21366
* symbol type:                           Symbol Type.         (line   6)
21367
* symbol type, COFF:                     Type.                (line  11)
21368
* symbol type, ELF:                      Type.                (line  22)
21369
* symbol value:                          Symbol Value.        (line   6)
21370
* symbol value, setting:                 Set.                 (line   6)
21371
* symbol values, assigning:              Setting Symbols.     (line   6)
21372
* symbol versioning:                     Symver.              (line   6)
21373
* symbol, common:                        Comm.                (line   6)
21374
* symbol, making visible to linker:      Global.              (line   6)
21375
* symbolic debuggers, information for:   Stab.                (line   6)
21376
* symbols:                               Symbols.             (line   6)
21377
* Symbols in position-independent code, CRIS: CRIS-Pic.       (line   6)
21378
* symbols with uppercase, VAX/VMS:       VAX-Opts.            (line  42)
21379
* symbols, assigning values to:          Equ.                 (line   6)
21380
* Symbols, built-in, CRIS:               CRIS-Symbols.        (line   6)
21381
* Symbols, CRIS, built-in:               CRIS-Symbols.        (line   6)
21382
* symbols, local common:                 Lcomm.               (line   6)
21383
* symver directive:                      Symver.              (line   6)
21384
* syntax compatibility, i386:            i386-Syntax.         (line   6)
21385
* syntax compatibility, x86-64:          i386-Syntax.         (line   6)
21386
* syntax, AVR:                           AVR-Modifiers.       (line   6)
21387
* syntax, Blackfin:                      Blackfin Syntax.     (line   6)
21388
* syntax, D10V:                          D10V-Syntax.         (line   6)
21389
* syntax, D30V:                          D30V-Syntax.         (line   6)
21390
* syntax, LM32:                          LM32-Modifiers.      (line   6)
21391
* syntax, M32C:                          M32C-Modifiers.      (line   6)
21392
* syntax, M680x0:                        M68K-Syntax.         (line   8)
21393
* syntax, M68HC11 <1>:                   M68HC11-Modifiers.   (line   6)
21394
* syntax, M68HC11:                       M68HC11-Syntax.      (line   6)
21395
* syntax, machine-independent:           Syntax.              (line   6)
21396
* syntax, SPARC:                         Sparc-Aligned-Data.  (line  21)
21397
* syntax, Xtensa assembler:              Xtensa Syntax.       (line   6)
21398
* sysproc directive, i960:               Directives-i960.     (line  37)
21399
* tab (\t):                              Strings.             (line  27)
21400
* tab directive, TIC54X:                 TIC54X-Directives.   (line 248)
21401
* tag directive:                         Tag.                 (line   6)
21402
* tag directive, TIC54X:                 TIC54X-Directives.   (line 251)
21403
* tdaoff pseudo-op, V850:                V850 Opcodes.        (line  81)
21404
* temporary symbol names:                Symbol Names.        (line  35)
21405
* text and data sections, joining:       R.                   (line   6)
21406
* text directive:                        Text.                (line   6)
21407
* text section:                          Ld Sections.         (line   9)
21408
* tfloat directive, i386:                i386-Float.          (line  14)
21409
* tfloat directive, x86-64:              i386-Float.          (line  14)
21410
* Thumb support:                         ARM-Dependent.       (line   6)
21411
* TIC54X builtin math functions:         TIC54X-Builtins.     (line   6)
21412
* TIC54X machine directives:             TIC54X-Directives.   (line   6)
21413
* TIC54X memory-mapped registers:        TIC54X-MMRegs.       (line   6)
21414
* TIC54X options:                        TIC54X-Opts.         (line   6)
21415
* TIC54X subsym builtins:                TIC54X-Macros.       (line  16)
21416
* TIC54X support:                        TIC54X-Dependent.    (line   6)
21417
* TIC54X-specific macros:                TIC54X-Macros.       (line   6)
21418
* time, total for assembly:              statistics.          (line   6)
21419
* title directive:                       Title.               (line   6)
21420
* tp register, V850:                     V850-Regs.           (line  20)
21421
* transform directive:                   Transform Directive. (line   6)
21422
* trusted compiler:                      f.                   (line   6)
21423
* turning preprocessing on and off:      Preprocessing.       (line  27)
21424
* type directive (COFF version):         Type.                (line  11)
21425
* type directive (ELF version):          Type.                (line  22)
21426
* type of a symbol:                      Symbol Type.         (line   6)
21427
* ualong directive, SH:                  SH Directives.       (line   6)
21428
* uaword directive, SH:                  SH Directives.       (line   6)
21429
* ubyte directive, TIC54X:               TIC54X-Directives.   (line  36)
21430
* uchar directive, TIC54X:               TIC54X-Directives.   (line  36)
21431
* uhalf directive, TIC54X:               TIC54X-Directives.   (line 111)
21432
* uint directive, TIC54X:                TIC54X-Directives.   (line 111)
21433
* uleb128 directive:                     Uleb128.             (line   6)
21434
* ulong directive, TIC54X:               TIC54X-Directives.   (line 135)
21435
* undefined section:                     Ld Sections.         (line  36)
21436
* union directive, TIC54X:               TIC54X-Directives.   (line 251)
21437
* unsegm:                                Z8000 Directives.    (line  14)
21438
* usect directive, TIC54X:               TIC54X-Directives.   (line 263)
21439
* ushort directive, TIC54X:              TIC54X-Directives.   (line 111)
21440
* uword directive, TIC54X:               TIC54X-Directives.   (line 111)
21441
* V850 command line options:             V850 Options.        (line   9)
21442
* V850 floating point (IEEE):            V850 Floating Point. (line   6)
21443
* V850 line comment character:           V850-Chars.          (line   6)
21444
* V850 machine directives:               V850 Directives.     (line   6)
21445
* V850 opcodes:                          V850 Opcodes.        (line   6)
21446
* V850 options (none):                   V850 Options.        (line   6)
21447
* V850 register names:                   V850-Regs.           (line   6)
21448
* V850 support:                          V850-Dependent.      (line   6)
21449
* val directive:                         Val.                 (line   6)
21450
* value attribute, COFF:                 Val.                 (line   6)
21451
* value of a symbol:                     Symbol Value.        (line   6)
21452
* var directive, TIC54X:                 TIC54X-Directives.   (line 273)
21453
* VAX bitfields not supported:           VAX-no.              (line   6)
21454
* VAX branch improvement:                VAX-branch.          (line   6)
21455
* VAX command-line options ignored:      VAX-Opts.            (line   6)
21456
* VAX displacement sizing character:     VAX-operands.        (line  12)
21457
* VAX floating point:                    VAX-float.           (line   6)
21458
* VAX immediate character:               VAX-operands.        (line   6)
21459
* VAX indirect character:                VAX-operands.        (line   9)
21460
* VAX machine directives:                VAX-directives.      (line   6)
21461
* VAX opcode mnemonics:                  VAX-opcodes.         (line   6)
21462
* VAX operand notation:                  VAX-operands.        (line   6)
21463
* VAX register names:                    VAX-operands.        (line  17)
21464
* VAX support:                           Vax-Dependent.       (line   6)
21465
* Vax-11 C compatibility:                VAX-Opts.            (line  42)
21466
* VAX/VMS options:                       VAX-Opts.            (line  42)
21467
* version directive:                     Version.             (line   6)
21468
* version directive, TIC54X:             TIC54X-Directives.   (line 277)
21469
* version of assembler:                  v.                   (line   6)
21470
* versions of symbols:                   Symver.              (line   6)
21471
* visibility <1>:                        Internal.            (line   6)
21472
* visibility <2>:                        Protected.           (line   6)
21473
* visibility:                            Hidden.              (line   6)
21474
* VMS (VAX) options:                     VAX-Opts.            (line  42)
21475
* vtable_entry directive:                VTableEntry.         (line   6)
21476
* vtable_inherit directive:              VTableInherit.       (line   6)
21477
* warning directive:                     Warning.             (line   6)
21478
* warning for altered difference tables: K.                   (line   6)
21479
* warning messages:                      Errors.              (line   6)
21480
* warnings, causing error:               W.                   (line  16)
21481
* warnings, M32R:                        M32R-Warnings.       (line   6)
21482
* warnings, suppressing:                 W.                   (line  11)
21483
* warnings, switching on:                W.                   (line  19)
21484
* weak directive:                        Weak.                (line   6)
21485
* weakref directive:                     Weakref.             (line   6)
21486
* whitespace:                            Whitespace.          (line   6)
21487
* whitespace, removed by preprocessor:   Preprocessing.       (line   7)
21488
* wide floating point directives, VAX:   VAX-directives.      (line  10)
21489
* width directive, TIC54X:               TIC54X-Directives.   (line 127)
21490
* Width of continuation lines of disassembly output: listing. (line  21)
21491
* Width of first line disassembly output: listing.            (line  16)
21492
* Width of source line output:           listing.             (line  28)
21493
* wmsg directive, TIC54X:                TIC54X-Directives.   (line  77)
21494
* word directive:                        Word.                (line   6)
21495
* word directive, ARC:                   ARC Directives.      (line 174)
21496
* word directive, H8/300:                H8/300 Directives.   (line   6)
21497
* word directive, i386:                  i386-Float.          (line  21)
21498
* word directive, SPARC:                 Sparc-Directives.    (line  51)
21499
* word directive, TIC54X:                TIC54X-Directives.   (line 111)
21500
* word directive, x86-64:                i386-Float.          (line  21)
21501
* writing patterns in memory:            Fill.                (line   6)
21502
* wval:                                  Z8000 Directives.    (line  24)
21503
* x86 machine directives:                i386-Directives.     (line   6)
21504
* x86-64 arch directive:                 i386-Arch.           (line   6)
21505
* x86-64 att_syntax pseudo op:           i386-Syntax.         (line   6)
21506
* x86-64 conversion instructions:        i386-Mnemonics.      (line  36)
21507
* x86-64 floating point:                 i386-Float.          (line   6)
21508
* x86-64 immediate operands:             i386-Syntax.         (line  15)
21509
* x86-64 instruction naming:             i386-Mnemonics.      (line   6)
21510
* x86-64 intel_syntax pseudo op:         i386-Syntax.         (line   6)
21511
* x86-64 jump optimization:              i386-Jumps.          (line   6)
21512
* x86-64 jump, call, return:             i386-Syntax.         (line  38)
21513
* x86-64 jump/call operands:             i386-Syntax.         (line  15)
21514
* x86-64 memory references:              i386-Memory.         (line   6)
21515
* x86-64 options:                        i386-Options.        (line   6)
21516
* x86-64 register operands:              i386-Syntax.         (line  15)
21517
* x86-64 registers:                      i386-Regs.           (line   6)
21518
* x86-64 sections:                       i386-Syntax.         (line  44)
21519
* x86-64 size suffixes:                  i386-Syntax.         (line  29)
21520
* x86-64 source, destination operands:   i386-Syntax.         (line  22)
21521
* x86-64 support:                        i386-Dependent.      (line   6)
21522
* x86-64 syntax compatibility:           i386-Syntax.         (line   6)
21523
* xfloat directive, TIC54X:              TIC54X-Directives.   (line  64)
21524
* xlong directive, TIC54X:               TIC54X-Directives.   (line 135)
21525
* Xtensa architecture:                   Xtensa-Dependent.    (line   6)
21526
* Xtensa assembler syntax:               Xtensa Syntax.       (line   6)
21527
* Xtensa directives:                     Xtensa Directives.   (line   6)
21528
* Xtensa opcode names:                   Xtensa Opcodes.      (line   6)
21529
* Xtensa register names:                 Xtensa Registers.    (line   6)
21530
* xword directive, SPARC:                Sparc-Directives.    (line  55)
21531
* Z80 $:                                 Z80-Chars.           (line   8)
21532
* Z80 ':                                 Z80-Chars.           (line  13)
21533
* Z80 floating point:                    Z80 Floating Point.  (line   6)
21534
* Z80 line comment character:            Z80-Chars.           (line   6)
21535
* Z80 options:                           Z80 Options.         (line   6)
21536
* Z80 registers:                         Z80-Regs.            (line   6)
21537
* Z80 support:                           Z80-Dependent.       (line   6)
21538
* Z80 Syntax:                            Z80 Options.         (line  47)
21539
* Z80, \:                                Z80-Chars.           (line  11)
21540
* Z80, case sensitivity:                 Z80-Case.            (line   6)
21541
* Z80-only directives:                   Z80 Directives.      (line   9)
21542
* Z800 addressing modes:                 Z8000-Addressing.    (line   6)
21543
* Z8000 directives:                      Z8000 Directives.    (line   6)
21544
* Z8000 line comment character:          Z8000-Chars.         (line   6)
21545
* Z8000 line separator:                  Z8000-Chars.         (line   8)
21546
* Z8000 opcode summary:                  Z8000 Opcodes.       (line   6)
21547
* Z8000 options:                         Z8000 Options.       (line   6)
21548
* Z8000 registers:                       Z8000-Regs.          (line   6)
21549
* Z8000 support:                         Z8000-Dependent.     (line   6)
21550
 
21551
 
21552
* zero-terminated strings:               Asciz.               (line   6)
21553
21554
21555

21556
Tag Table:
21557
Node: Top770
21558
Node: Overview1758
21559
Node: Manual30675
21560
Node: GNU Assembler31619
21561
Node: Object Formats32790
21562
Node: Command Line33242
21563
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21730
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21731
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21732
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21733
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21734
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21735
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21736
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21737
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21738
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21739
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21740
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21741
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21744
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21745
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21749
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21750
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21751
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21752
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21753
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21754
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21755
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21756
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21757
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21758
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21759
Ref: arm_pad232219
21760
Ref: arm_fnend235291
21761
Ref: arm_fnstart235615
21762
Ref: arm_save238627
21763
Ref: arm_setfp239328
21764
Node: ARM Opcodes242409
21765
Node: ARM Mapping Symbols244497
21766
Node: ARM Unwinding Tutorial245307
21767
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21768
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21769
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21770
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21771
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21772
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21773
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21775
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21776
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21777
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21779
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21788
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21789
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21817
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21825
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21826
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21827
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21828
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21829
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21830
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21831
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21832
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21833
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21834
Node: ESA/390 Floating Point332942
21835
Node: ESA/390 Directives333221
21836
Node: ESA/390 Opcodes336510
21837
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21838
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22064
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22065
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22070
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22071
Node: Acknowledgements679258
22072
Ref: Acknowledgements-Footnote-1684224
22073
Node: GNU Free Documentation License684250

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