OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [gas/] [itbl-ops.h] - Blame information for rev 304

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 205 julius
/* itbl-ops.h
2
   Copyright 1997, 1999, 2000, 2003, 2005, 2006, 2007
3
   Free Software Foundation, Inc.
4
 
5
   This file is part of GAS, the GNU Assembler.
6
 
7
   GAS is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
 
12
   GAS is distributed in the hope that it will be useful,
13
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
   GNU General Public License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with GAS; see the file COPYING.  If not, write to the Free
19
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20
   02110-1301, USA.  */
21
 
22
/* External functions, constants and defines for itbl support */
23
 
24
#ifdef HAVE_ITBL_CPU
25
#include "itbl-cpu.h"
26
#endif
27
 
28
/* Defaults for definitions required by generic code */
29
#ifndef ITBL_NUMBER_OF_PROCESSORS
30
#define ITBL_NUMBER_OF_PROCESSORS 1
31
#endif
32
 
33
#ifndef ITBL_MAX_BITPOS
34
#define ITBL_MAX_BITPOS 31
35
#endif
36
 
37
#ifndef ITBL_TYPE
38
#define ITBL_TYPE unsigned long
39
#endif
40
 
41
#ifndef ITBL_IS_INSN
42
#define ITBL_IS_INSN(insn) 1
43
#endif
44
 
45
#ifndef ITBL_DECODE_PNUM
46
#define ITBL_DECODE_PNUM(insn) 0
47
#endif
48
 
49
#ifndef ITBL_ENCODE_PNUM
50
#define ITBL_ENCODE_PNUM(pnum) 0
51
#endif
52
 
53
typedef ITBL_TYPE t_insn;
54
 
55
/* types of entries */
56
typedef enum
57
  {
58
    e_insn,
59
    e_dreg,
60
    e_regtype0 = e_dreg,
61
    e_creg,
62
    e_greg,
63
    e_addr,
64
    e_nregtypes = e_greg + 1,
65
    e_immed,
66
    e_ntypes,
67
    e_invtype                   /* invalid type */
68
  } e_type;
69
 
70
typedef enum
71
  {
72
    e_p0,
73
    e_nprocs = ITBL_NUMBER_OF_PROCESSORS,
74
    e_invproc                   /* invalid processor */
75
  } e_processor;
76
 
77
/* 0 means an instruction table was not specified.  */
78
extern int itbl_have_entries;
79
 
80
/* These routines are visible to the main part of the assembler */
81
 
82
int itbl_parse (char *insntbl);
83
void itbl_init (void);
84
char *itbl_get_field (char **s);
85
unsigned long itbl_assemble (char *name, char *operands);
86
int itbl_disassemble (char *str, unsigned long insn);
87
int itbl_parse (char *tbl);     /* parses insn tbl */
88
int itbl_get_reg_val (char *name, unsigned long *pval);
89
int itbl_get_val (e_processor processor, e_type type, char *name,
90
                  unsigned long *pval);
91
char *itbl_get_name (e_processor processor, e_type type, unsigned long val);
92
 
93
/* These routines are called by the table parser used to build the
94
   dynamic list of new processor instructions and registers.  */
95
 
96
struct itbl_entry *itbl_add_reg (int yyproc, int yytype,
97
                                 char *regname, int regnum);
98
struct itbl_entry *itbl_add_insn (int yyproc, char *name,
99
             unsigned long value, int sbit, int ebit, unsigned long flags);
100
struct itbl_field *itbl_add_operand (struct itbl_entry * e, int yytype,
101
                                  int sbit, int ebit, unsigned long flags);

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.