OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [arc/] [st.d] - Blame information for rev 277

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 205 julius
#as: -EL
2
#objdump: -dr -EL
3
 
4
.*: +file format elf32-.*arc
5
 
6
Disassembly of section .text:
7
 
8
00000000 <.text>:
9
   0:   00 02 01 10     10010200     st         r1,\[r2\]
10
   4:   0e 02 01 10     1001020e     st         r1,\[r2,14\]
11
   8:   00 02 41 10     10410200     stb        r1,\[r2\]
12
   c:   0e 82 01 11     1101820e     st.a       r1,\[r3,14\]
13
  10:   02 02 81 11     11810202     stw.a      r1,\[r2,2\]
14
  14:   00 02 1f 10     101f0200     st         r1,\[0x384\]
15
  18:   84 03 00 00
16
  1c:   00 7e 41 10     10417e00     stb        0,\[r2\]
17
  20:   f8 7f 01 10     10017ff8     st         -8,\[r2,-8\]
18
  24:   50 7e 1f 10     101f7e50     st         80,\[0x2ee\]
19
  28:   9e 02 00 00
20
  2c:   00 04 1f 10     101f0400     st         r2,\[0\]
21
  30:   00 00 00 00
22
                        30: R_ARC_32    foo
23
  34:   02 02 01 14     14010202     st.di      r1,\[r2,2\]
24
  38:   03 02 01 15     15010203     st.a.di    r1,\[r2,3\]
25
  3c:   04 02 81 15     15810204     stw.a.di   r1,\[r2,4\]
26
  40:   04 7c 06 10     10067c04     st         80,\[r12,4\]
27
  44:   50 00 00 00
28
                        44: R_ARC_32    .text
29
  48:   04 7c 06 10     10067c04     st         20,\[r12,4\]
30
  4c:   14 00 00 00
31
                        4c: R_ARC_B26   .text
32
  50:   00 02 01 12     12010200     sr         r1,\[r2\]
33
  54:   0e 82 1f 12     121f820e     sr         r1,\[0xe\]
34
  58:   00 fc 00 12     1200fc00     sr         0x3e8,\[r1\]
35
  5c:   e8 03 00 00
36
  60:   64 7e 01 12     12017e64     sr         100,\[r2\]
37
  64:   00 02 1f 12     121f0200     sr         r1,\[0x2710\]
38
  68:   10 27 00 00
39
  6c:   64 7e 1f 12     121f7e64     sr         100,\[0x2710\]
40
  70:   10 27 00 00
41
  74:   64 fc 1f 12     121ffc64     sr         0x2710,\[0x64\]
42
  78:   10 27 00 00

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.