OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [arm/] [branch-reloc.d] - Blame information for rev 205

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 205 julius
#name: Inter-section branch relocations
2
#This test is only valid on ELF based ports.
3
#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
4
#as: -march=armv5t
5
#objdump: -rd
6
#stderr: branch-reloc.l
7
 
8
# Test the generation of relocation for inter-section branches
9
 
10
.*: +file format.*arm.*
11
 
12
 
13
Disassembly of section .text:
14
 
15
00000000 :
16
   0:   e1a00000        nop                     ; \(mov r0, r0\)
17
 
18
00000004 :
19
   4:   ebfffffe        bl      46 
20
                        4: R_ARM_CALL   thumb_glob_sym1
21
   8:   ebfffffe        bl      100 
22
                        8: R_ARM_CALL   thumb_glob_sym2
23
   c:   fa00000c        blx     44 
24
  10:   ebfffffe        bl      4 
25
                        10: R_ARM_CALL  arm_glob_sym1
26
  14:   ebfffffe        bl      13c 
27
                        14: R_ARM_CALL  arm_glob_sym2
28
  18:   eb000007        bl      3c 
29
  1c:   fafffffe        blx     46 
30
                        1c: R_ARM_CALL  thumb_glob_sym1
31
  20:   fafffffe        blx     100 
32
                        20: R_ARM_CALL  thumb_glob_sym2
33
  24:   fa000006        blx     44 
34
  28:   fafffffe        blx     4 
35
                        28: R_ARM_CALL  arm_glob_sym1
36
  2c:   fafffffe        blx     13c 
37
                        2c: R_ARM_CALL  arm_glob_sym2
38
  30:   eb000001        bl      3c 
39
  34:   e1a00000        nop                     ; \(mov r0, r0\)
40
  38:   e12fff1e        bx      lr
41
 
42
0000003c :
43
  3c:   e1a00000        nop                     ; \(mov r0, r0\)
44
  40:   e12fff1e        bx      lr
45
 
46
00000044 :
47
  44:   4770            bx      lr
48
 
49
00000046 :
50
  46:   4770            bx      lr
51
 
52
Disassembly of section foo:
53
 
54
00000000 :
55
        ...
56
 
57
00000100 :
58
 100:   f7ff fffe       bl      4 
59
                        100: R_ARM_THM_CALL     arm_glob_sym1
60
 104:   f7ff fffe       bl      13c 
61
                        104: R_ARM_THM_CALL     arm_glob_sym2
62
 108:   f000 e816       blx     138 
63
 10c:   f7ff fffe       bl      46 
64
                        10c: R_ARM_THM_CALL     thumb_glob_sym1
65
 110:   f7ff fffe       bl      100 
66
                        110: R_ARM_THM_CALL     thumb_glob_sym2
67
 114:   f000 f80e       bl      134 
68
 118:   f7ff effe       blx     4 
69
                        118: R_ARM_THM_CALL     arm_glob_sym1
70
 11c:   f7ff effe       blx     13c 
71
                        11c: R_ARM_THM_CALL     arm_glob_sym2
72
 120:   f000 e80a       blx     138 
73
 124:   f7ff effe       blx     46 
74
                        124: R_ARM_THM_CALL     thumb_glob_sym1
75
 128:   f7ff effe       blx     100 
76
                        128: R_ARM_THM_CALL     thumb_glob_sym2
77
 12c:   f000 f802       bl      134 
78
 130:   46c0            nop                     ; \(mov r8, r8\)
79
 132:   4770            bx      lr
80
 
81
00000134 :
82
 134:   46c0            nop                     ; \(mov r8, r8\)
83
 136:   4770            bx      lr
84
 
85
00000138 :
86
 138:   e12fff1e        bx      lr
87
 
88
0000013c :
89
 13c:   e12fff1e        bx      lr

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.