URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [arm/] [thumb2_ldmstm.d] - Blame information for rev 205

Line No.	Rev	Author	Line
1	205	julius	`# name: Thumb-2 LDM/STM single reg`
2			`# as: -march=armv6t2`
3			`# objdump: -dr --prefix-addresses --show-raw-insn`
4
5			`.: +file format .arm.*`
6
7			`Disassembly of section .text:`
8			`0[0-9a-f]+ <[^>]+> bc01 pop {r0}`
9			`0[0-9a-f]+ <[^>]+> f85d 8b04 ldr.w r8, \[sp\], #4`
10			`0[0-9a-f]+ <[^>]+> f8d1 9000 ldr.w r9, \[r1\]`
11			`0[0-9a-f]+ <[^>]+> f852 cb04 ldr.w ip, \[r2\], #4`
12			`0[0-9a-f]+ <[^>]+> f85d 2d04 ldr.w r2, \[sp, #-4\]!`
13			`0[0-9a-f]+ <[^>]+> f85d 8d04 ldr.w r8, \[sp, #-4\]!`
14			`0[0-9a-f]+ <[^>]+> f856 4c04 ldr.w r4, \[r6, #-4\]`
15			`0[0-9a-f]+ <[^>]+> f856 8c04 ldr.w r8, \[r6, #-4\]`
16			`0[0-9a-f]+ <[^>]+> f852 4d04 ldr.w r4, \[r2, #-4\]!`
17			`0[0-9a-f]+ <[^>]+> f852 cd04 ldr.w ip, \[r2, #-4\]!`
18			`0[0-9a-f]+ <[^>]+> b408 push {r3}`
19			`0[0-9a-f]+ <[^>]+> f84d 9b04 str.w r9, \[sp\], #4`
20			`0[0-9a-f]+ <[^>]+> f8c3 c000 str.w ip, \[r3\]`
21			`0[0-9a-f]+ <[^>]+> f844 cb04 str.w ip, \[r4\], #4`
22			`0[0-9a-f]+ <[^>]+> f84d 3d04 str.w r3, \[sp, #-4\]!`
23			`0[0-9a-f]+ <[^>]+> f84d 9d04 str.w r9, \[sp, #-4\]!`
24			`0[0-9a-f]+ <[^>]+> f847 5c04 str.w r5, \[r7, #-4\]`
25			`0[0-9a-f]+ <[^>]+> f846 cc04 str.w ip, \[r6, #-4\]`
26			`0[0-9a-f]+ <[^>]+> f846 bd04 str.w fp, \[r6, #-4\]!`
27			`0[0-9a-f]+ <[^>]+> f845 8d04 str.w r8, \[r5, #-4\]!`