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[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [arm/] [vfp1.s] - Blame information for rev 205

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1 205 julius
@ VFP Instructions for D variants (Double precision)
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        .text
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        .global F
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F:
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        @ First we test the basic syntax and bit patterns of the opcodes.
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        @ Most of these tests deliberatly use d0/r0 to avoid setting
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        @ any more bits than necessary.
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        @ Comparison operations
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        fcmped  d0, d0
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        fcmpezd d0
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        fcmpd   d0, d0
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        fcmpzd  d0
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        @ Monadic data operations
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        fabsd   d0, d0
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        fcpyd   d0, d0
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        fnegd   d0, d0
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        fsqrtd  d0, d0
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        @ Dyadic data operations
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        faddd   d0, d0, d0
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        fdivd   d0, d0, d0
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        fmacd   d0, d0, d0
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        fmscd   d0, d0, d0
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        fmuld   d0, d0, d0
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        fnmacd  d0, d0, d0
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        fnmscd  d0, d0, d0
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        fnmuld  d0, d0, d0
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        fsubd   d0, d0, d0
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        @ Load/store operations
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        fldd    d0, [r0]
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        fstd    d0, [r0]
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        @ Load/store multiple operations
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        fldmiad r0, {d0}
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        fldmfdd r0, {d0}
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        fldmiad r0!, {d0}
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        fldmfdd r0!, {d0}
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        fldmdbd r0!, {d0}
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        fldmead r0!, {d0}
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        fstmiad r0, {d0}
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        fstmead r0, {d0}
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        fstmiad r0!, {d0}
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        fstmead r0!, {d0}
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        fstmdbd r0!, {d0}
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        fstmfdd r0!, {d0}
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        @ Conversion operations
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        fsitod  d0, s0
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        fuitod  d0, s0
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        ftosid  s0, d0
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        ftosizd s0, d0
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        ftouid  s0, d0
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        ftouizd s0, d0
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        fcvtds  d0, s0
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        fcvtsd  s0, d0
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        @ ARM from VFP operations
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        fmrdh   r0, d0
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        fmrdl   r0, d0
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        @ VFP From ARM operations
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        fmdhr   d0, r0
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        fmdlr   d0, r0
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        @ Now we test that the register fields are updated correctly for
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        @ each class of instruction.
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        @ Single register operations (compare-zero):
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        fcmpzd  d1
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        fcmpzd  d2
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        fcmpzd  d15
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        @ Two register comparison operations:
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        fcmpd   d0, d1
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        fcmpd   d0, d2
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        fcmpd   d0, d15
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        fcmpd   d1, d0
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        fcmpd   d2, d0
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        fcmpd   d15, d0
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        fcmpd   d5, d12
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        @ Two register data operations (monadic)
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        fnegd   d0, d1
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        fnegd   d0, d2
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        fnegd   d0, d15
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        fnegd   d1, d0
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        fnegd   d2, d0
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        fnegd   d15, d0
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        fnegd   d12, d5
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        @ Three register data operations (dyadic)
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        faddd   d0, d0, d1
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        faddd   d0, d0, d2
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        faddd   d0, d0, d15
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        faddd   d0, d1, d0
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        faddd   d0, d2, d0
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        faddd   d0, d15, d0
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        faddd   d1, d0, d0
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        faddd   d2, d0, d0
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        faddd   d15, d0, d0
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        faddd   d12, d9, d5
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        @ Conversion operations
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        fcvtds  d0, s1
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        fcvtds  d0, s2
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        fcvtds  d0, s31
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        fcvtds  d1, s0
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        fcvtds  d2, s0
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        fcvtds  d15, s0
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        fcvtsd  s1, d0
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        fcvtsd  s2, d0
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        fcvtsd  s31, d0
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        fcvtsd  s0, d1
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        fcvtsd  s0, d2
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        fcvtsd  s0, d15
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        @ Move to VFP from ARM
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        fmrdh   r1, d0
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        fmrdh   r14, d0
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        fmrdh   r0, d1
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        fmrdh   r0, d2
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        fmrdh   r0, d15
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        fmrdl   r1, d0
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        fmrdl   r14, d0
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        fmrdl   r0, d1
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        fmrdl   r0, d2
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        fmrdl   r0, d15
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        @ Move to ARM from VFP
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        fmdhr   d0, r1
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        fmdhr   d0, r14
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        fmdhr   d1, r0
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        fmdhr   d2, r0
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        fmdhr   d15, r0
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        fmdlr   d0, r1
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        fmdlr   d0, r14
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        fmdlr   d1, r0
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        fmdlr   d2, r0
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        fmdlr   d15, r0
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        @ Load/store operations
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        fldd    d0, [r1]
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        fldd    d0, [r14]
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        fldd    d0, [r0, #0]
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        fldd    d0, [r0, #1020]
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        fldd    d0, [r0, #-1020]
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        fldd    d1, [r0]
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        fldd    d2, [r0]
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        fldd    d15, [r0]
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        fstd    d12, [r12, #804]
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        @ Load/store multiple operations
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        fldmiad r0, {d1}
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        fldmiad r0, {d2}
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        fldmiad r0, {d15}
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        fldmiad r0, {d0-d1}
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        fldmiad r0, {d0-d2}
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        fldmiad r0, {d0-d15}
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        fldmiad r0, {d1-d15}
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        fldmiad r0, {d2-d15}
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        fldmiad r0, {d14-d15}
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        fldmiad r1, {d0}
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        fldmiad r14, {d0}
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        @ Check that we assemble all the register names correctly
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        fcmpzd  d0
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        fcmpzd  d1
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        fcmpzd  d2
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        fcmpzd  d3
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        fcmpzd  d4
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        fcmpzd  d5
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        fcmpzd  d6
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        fcmpzd  d7
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        fcmpzd  d8
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        fcmpzd  d9
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        fcmpzd  d10
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        fcmpzd  d11
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        fcmpzd  d12
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        fcmpzd  d13
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        fcmpzd  d14
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        fcmpzd  d15
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        @ Now we check the placement of the conditional execution substring.
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        @ On VFP this is always at the end of the instruction.
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        @ Comparison operations
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        fcmpedeq        d1, d15
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        fcmpezdeq       d2
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        fcmpdeq d3, d14
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        fcmpzdeq        d4
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        @ Monadic data operations
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        fabsdeq d5, d13
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        fcpydeq d6, d12
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        fnegdeq d7, d11
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        fsqrtdeq        d8, d10
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        @ Dyadic data operations
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        fadddeq d9, d1, d15
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        fdivdeq d2, d3, d14
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        fmacdeq d4, d13, d12
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        fmscdeq d5, d6, d11
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        fmuldeq d7, d10, d9
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        fnmacdeq        d8, d9, d10
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        fnmscdeq        d7, d6, d11
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        fnmuldeq        d5, d4, d12
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        fsubdeq d3, d13, d14
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        @ Load/store operations
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        flddeq  d2, [r5]
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        fstdeq  d1, [r12]
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        @ Load/store multiple operations
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        fldmiadeq       r1, {d1}
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        fldmfddeq       r2, {d2}
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        fldmiadeq       r3!, {d3}
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        fldmfddeq       r4!, {d4}
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        fldmdbdeq       r5!, {d5}
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        fldmeadeq       r6!, {d6}
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        fstmiadeq       r7, {d15}
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        fstmeadeq       r8, {d14}
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        fstmiadeq       r9!, {d13}
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        fstmeadeq       r10!, {d12}
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        fstmdbdeq       r11!, {d11}
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        fstmfddeq       r12!, {d10}
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        @ Conversion operations
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        fsitodeq        d15, s1
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        fuitodeq        d1, s31
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        ftosideq        s1, d15
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        ftosizdeq       s31, d2
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        ftouideq        s15, d2
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        ftouizdeq       s11, d3
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        fcvtdseq        d1, s10
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        fcvtsdeq        s11, d1
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        @ ARM from VFP operations
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        fmrdheq r8, d1
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        fmrdleq r7, d15
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        @ VFP From ARM operations
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        fmdhreq d1, r15
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        fmdlreq d15, r1
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        # Add three nop instructions to ensure that the
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        # output is 32-byte aligned as required for arm-aout.
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        nop
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        nop
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        nop

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