OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [bfin/] [shift2.s] - Blame information for rev 205

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 205 julius
 
2
.EXTERN MY_LABEL2;
3
.section .text;
4
 
5
//
6
//9 SHIFT/ROTATE OPERATIONS
7
//
8
 
9
//Preg = ( Preg + Preg ) << 1 ; /* dest_reg = (dest_reg + src_reg) x 2 (a) */
10
P0 = (P0+P0)<<1;
11
P0 = (P0+P1)<<1;
12
P2 = (P2+P0)<<1;
13
P1 = (P1+P2)<<1;
14
 
15
//P0 = (P2+P0)<<1;
16
 
17
//Preg = ( Preg + Preg ) << 2 ; /* dest_reg = (dest_reg + src_reg) x 4 (a) */
18
P0 = (P0+P0)<<2;
19
P0 = (P0+P1)<<2;
20
P2 = (P2+P0)<<2;
21
P1 = (P1+P2)<<2;
22
 
23
//P0 = (P2+P0)<<2;
24
 
25
//Dreg = (Dreg + Dreg) << 1 ; /* dest_reg = (dest_reg + src_reg) x 2 (a) */
26
R0 = (R0+R0)<<1;
27
R0 = (R0+R1)<<1;
28
R2 = (R2+R0)<<1;
29
R1 = (R1+R2)<<1;
30
 
31
//R0 = (R2+R0)<<1;
32
 
33
 
34
//Dreg = (Dreg + Dreg) << 2 ; /* dest_reg = (dest_reg + src_reg) x 4 (a) */
35
R0 = (R0+R0)<<2;
36
R0 = (R0+R1)<<2;
37
R2 = (R2+R0)<<2;
38
R1 = (R1+R2)<<2;
39
 
40
//R0 = (R2+R0)<<2;
41
 
42
//Preg = Preg + ( Preg << 1 ) ; /* adder_pntr + (src_pntr x 2) (a) */
43
P0 = P0 + (P0 << 1);
44
P0 = P0 + (P1 << 1);
45
P0 = P0 + (P2 << 1);
46
P0 = P1 + (P2 << 1);
47
P0 = P2 + (P3 << 1);
48
P1 = P0 + (P0 << 1);
49
P1 = P0 + (P1 << 1);
50
P1 = P0 + (P2 << 1);
51
P1 = P1 + (P2 << 1);
52
P1 = P2 + (P3 << 1);
53
 
54
//Preg = Preg + ( Preg << 2 ) ; /* adder_pntr + (src_pntr x 4) (a) */
55
P0 = P0 + (P0 << 2);
56
P0 = P0 + (P1 << 2);
57
P0 = P0 + (P2 << 2);
58
P0 = P1 + (P2 << 2);
59
P0 = P2 + (P3 << 2);
60
P1 = P0 + (P0 << 2);
61
P1 = P0 + (P1 << 2);
62
P1 = P0 + (P2 << 2);
63
P1 = P1 + (P2 << 2);
64
P1 = P2 + (P3 << 2);
65
 
66
//Dreg >>>= uimm5 ; /* arithmetic right shift (a) */
67
R0 >>>= 0;
68
R0 >>>= 31;
69
R0 >>>= 5;
70
R5 >>>= 0;
71
R5 >>>= 31;
72
R5 >>>= 5;
73
 
74
//Dreg <<= uimm5 ; /* logical left shift (a) */
75
R0 <<= 0;
76
R0 <<= 31;
77
R0 <<= 5;
78
R5 <<= 0;
79
R5 <<= 31;
80
R5 <<= 5;
81
//Dreg_lo_hi = Dreg_lo_hi >>> uimm4 ; /* arithmetic right shift (b) */
82
R0.L = R0.L >>> 0;
83
R0.L = R0.L >>> 15;
84
R0.L = R0.H >>> 0;
85
R0.L = R0.H >>> 15;
86
R0.H = R0.L >>> 0;
87
R0.H = R0.L >>> 15;
88
R0.H = R0.H >>> 0;
89
R0.H = R0.H >>> 15;
90
 
91
R0.L = R1.L >>> 0;
92
R0.L = R1.L >>> 15;
93
R0.L = R1.H >>> 0;
94
R0.L = R1.H >>> 15;
95
R0.H = R1.L >>> 0;
96
R0.H = R1.L >>> 15;
97
R0.H = R1.H >>> 0;
98
R0.H = R1.H >>> 15;
99
 
100
R0.L = R7.L >>> 0;
101
R1.L = R6.L >>> 15;
102
R2.L = R5.H >>> 0;
103
R3.L = R4.H >>> 15;
104
R4.H = R3.L >>> 0;
105
R5.H = R2.L >>> 15;
106
R6.H = R1.H >>> 0;
107
R7.H = R0.H >>> 15;
108
 
109
//Dreg_lo_hi = Dreg_lo_hi << uimm4 (S) ; /* arithmetic left shift (b) */
110
R0.L = R0.L << 0(S);
111
R0.L = R0.L << 15(S);
112
R0.L = R0.H << 0(S);
113
R0.L = R0.H << 15(S);
114
R0.H = R0.L << 0(S);
115
R0.H = R0.L << 15(S);
116
R0.H = R0.H << 0(S);
117
R0.H = R0.H << 15(S);
118
 
119
R0.L = R1.L << 0(S);
120
R0.L = R1.L << 15(S);
121
R0.L = R1.H << 0(S);
122
R0.L = R1.H << 15(S);
123
R0.H = R1.L << 0(S);
124
R0.H = R1.L << 15(S);
125
R0.H = R1.H << 0(S);
126
R0.H = R1.H << 15(S);
127
 
128
R0.L = R7.L << 0(S);
129
R1.L = R6.L << 15(S);
130
R2.L = R5.H << 0(S);
131
R3.L = R4.H << 15(S);
132
R4.H = R3.L << 0(S);
133
R5.H = R2.L << 15(S);
134
R6.H = R1.H << 0(S);
135
R7.H = R0.H << 15(S);
136
//Dreg = Dreg >>> uimm5 ; /* arithmetic right shift (b) */
137
R0 = R0 >>> 0;
138
R0 = R0 >>> 31;
139
R0 = R1 >>> 0;
140
R0 = R1 >>> 31;
141
R7 = R0 >>> 0;
142
R6 = R1 >>> 31;
143
R5 = R2 >>> 0;
144
R4 = R3 >>> 31;
145
R3 = R4 >>> 0;
146
R2 = R5 >>> 31;
147
R1 = R6 >>> 0;
148
R0 = R7 >>> 31;
149
 
150
//Dreg = Dreg << uimm5 (S) ; /* arithmetic left shift (b) */
151
R0 = R0 << 0(S);
152
R0 = R0 << 31(S);
153
R0 = R1 << 0(S);
154
R0 = R1 << 31(S);
155
R7 = R0 << 0(S);
156
R6 = R1 << 31(S);
157
R5 = R2 << 0(S);
158
R4 = R3 << 31(S);
159
R3 = R4 << 0(S);
160
R2 = R5 << 31(S);
161
R1 = R6 << 0(S);
162
R0 = R7 << 31(S);
163
//A0 = A0 >>> uimm5 ; /* arithmetic right shift (b) */
164
A0 = A0 >>> 0;
165
A0 = A0 >>> 15;
166
A0 = A0 >>> 31;
167
 
168
//A0 = A0 << uimm5 ; /* logical left shift (b) */
169
A0 = A0 << 0;
170
A0 = A0 << 15;
171
A0 = A0 << 31;
172
 
173
//A1 = A1 >>> uimm5 ; /* arithmetic right shift (b) */
174
A1 = A1 >>> 0;
175
A1 = A1 >>> 15;
176
A1 = A1 >>> 31;
177
 
178
//A1 = A1 << uimm5 ; /* logical left shift (b) */
179
A1 = A1 << 0;
180
A1 = A1 << 15;
181
A1 = A1 << 31;
182
 
183
//Dreg >>>= Dreg ; /* arithmetic right shift (a) */
184
R0 >>>= R0;
185
R0 >>>= R1;
186
R1 >>>= R0;
187
R1 >>>= R7;
188
 
189
//Dreg <<= Dreg ; /* logical left shift (a) */
190
R0 <<= R0;
191
R0 <<= R1;
192
R1 <<= R0;
193
R1 <<= R7;
194
 
195
//Dreg_lo_hi = ASHIFT Dreg_lo_hi BY Dreg_lo (opt_sat) ; /* arithmetic right shift (b) */
196
r3.l = ashift r0.h by r7.l ; /* shift, half-word */
197
r3.h = ashift r0.l by r7.l ;
198
r3.h = ashift r0.h by r7.l ;
199
r3.l = ashift r0.l by r7.l ;
200
r3.l = ashift r0.h by r7.l(s) ; /* shift, half-word, saturated */
201
r3.h = ashift r0.l by r7.l(s) ; /* shift, half-word, saturated */
202
r3.h = ashift r0.h by r7.l(s) ;
203
r3.l = ashift r0.l by r7.l (s) ;
204
 
205
//Dreg = ASHIFT Dreg BY Dreg_lo (opt_sat) ; /* arithmetic right shift (b) */
206
r4 = ashift r2 by r7.l ; /* shift, word */
207
r4 = ashift r2 by r7.l (s) ; /* shift, word, saturated */
208
 
209
//A0 = ASHIFT A0 BY Dreg_lo ; /* arithmetic right shift (b)*/
210
A0 = ashift A0 by r7.l ; /* shift, Accumulator */
211
 
212
//A1 = ASHIFT A1 BY Dreg_lo ; /* arithmetic right shift (b)*/
213
A1 = ashift A1 by r7.l ; /* shift, Accumulator */
214
 
215
p3 = p2 >> 1 ; /* pointer right shift by 1 */
216
p3 = p3 >> 2 ; /* pointer right shift by 2 */
217
p4 = p5 << 1 ; /* pointer left shift by 1 */
218
p0 = p1 << 2 ; /* pointer left shift by 2 */
219
r3 >>= 17 ; /* data right shift */
220
r3 <<= 17 ; /* data left shift */
221
r3.l = r0.l >> 4 ; /* data right shift, half-word register */
222
r3.l = r0.h >> 4 ; /* same as above; half-word register combinations are arbitrary */
223
r3.h = r0.l << 12 ; /* data left shift, half-word register */
224
r3.h = r0.h << 14 ; /* same as above; half-word register combinations are arbitrary */
225
 
226
r3 = r6 >> 4 ; /* right shift, 32-bit word */
227
r3 = r6 << 4 ; /* left shift, 32-bit word */
228
 
229
a0 = a0 >> 7 ; /* Accumulator right shift */
230
a1 = a1 >> 25 ; /* Accumulator right shift */
231
a0 = a0 << 7 ; /* Accumulator left shift */
232
a1 = a1 << 14 ; /* Accumulator left shift */
233
 
234
r3 >>= r0 ; /* data right shift */
235
r3 <<= r1 ; /* data left shift */
236
 
237
r3.l = lshift r0.l by r2.l ; /* shift direction controlled by sign of R2.L */
238
r3.h = lshift r0.l by r2.l ;
239
 
240
a0 = lshift a0 by r7.l ;
241
a1 = lshift a1 by r7.l ;
242
 
243
r4 = rot r1 by 31 ; /* rotate left */
244
r4 = rot r1 by -32 ; /* rotate right */
245
r4 = rot r1 by 5 ; /* rotate right */
246
 
247
a0 = rot a0 by 22 ; /* rotate Accumulator left */
248
a0 = rot a0 by -32 ; /* rotate Accumulator left */
249
a0 = rot a0 by 31 ; /* rotate Accumulator left */
250
 
251
a1 = rot a1 by -32 ; /* rotate Accumulator right */
252
a1 = rot a1 by 31 ; /* rotate Accumulator right */
253
a1 = rot a1 by 22 ; /* rotate Accumulator right */
254
 
255
r4 = rot r1 by r2.l ;
256
a0 = rot a0 by r3.l ;
257
a1 = rot a1 by r7.l ;
258
 
259
r0.l = r1.l << 0;
260
r0.l = r1.l << 1;
261
r0.l = r1.l << 2;
262
r0.l = r1.l << 4;
263
r0.l = r1.l >> 0;
264
r0.l = r1.l >> 1;
265
r0.l = r1.l >> 2;
266
r0.l = r1.l >> 4;
267
r0.l = r1.l >>> 1;
268
r0.l = r1.l >>> 2;
269
r0.l = r1.l >>> 4;
270
 
271
r0.l = r1.h << 0;
272
r0.l = r1.h << 1;
273
r0.l = r1.h << 2;
274
r0.l = r1.h << 4;
275
r0.l = r1.h >> 0;
276
r0.l = r1.h >> 1;
277
r0.l = r1.h >> 2;
278
r0.l = r1.h >> 4;
279
r0.l = r1.h >>> 1;
280
r0.l = r1.h >>> 2;
281
r0.l = r1.h >>> 4;
282
 
283
r0.l = r1.h << 0 (S);
284
r0.l = r1.h << 1 (S);
285
r0.l = r1.h << 2 (S);
286
r0.l = r1.h << 4 (S);
287
r0.l = r1.h >>> 1 (S);
288
r0.l = r1.h >>> 2 (S);
289
r0.l = r1.h >>> 4 (S);
290
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.