OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [mips/] [fpr-names-numeric.d] - Blame information for rev 205

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 205 julius
#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,fpr-names=numeric
2
#name: MIPS FPR disassembly (numeric)
3
#source: fpr-names.s
4
 
5
# Check objdump's handling of -M fpr-names=foo options.
6
 
7
.*: +file format .*mips.*
8
 
9
Disassembly of section .text:
10
0+0000 <[^>]*> 44800000     mtc1    \$0,\$f0
11
0+0004 <[^>]*> 44800800     mtc1    \$0,\$f1
12
0+0008 <[^>]*> 44801000     mtc1    \$0,\$f2
13
0+000c <[^>]*> 44801800     mtc1    \$0,\$f3
14
0+0010 <[^>]*> 44802000     mtc1    \$0,\$f4
15
0+0014 <[^>]*> 44802800     mtc1    \$0,\$f5
16
0+0018 <[^>]*> 44803000     mtc1    \$0,\$f6
17
0+001c <[^>]*> 44803800     mtc1    \$0,\$f7
18
0+0020 <[^>]*> 44804000     mtc1    \$0,\$f8
19
0+0024 <[^>]*> 44804800     mtc1    \$0,\$f9
20
0+0028 <[^>]*> 44805000     mtc1    \$0,\$f10
21
0+002c <[^>]*> 44805800     mtc1    \$0,\$f11
22
0+0030 <[^>]*> 44806000     mtc1    \$0,\$f12
23
0+0034 <[^>]*> 44806800     mtc1    \$0,\$f13
24
0+0038 <[^>]*> 44807000     mtc1    \$0,\$f14
25
0+003c <[^>]*> 44807800     mtc1    \$0,\$f15
26
0+0040 <[^>]*> 44808000     mtc1    \$0,\$f16
27
0+0044 <[^>]*> 44808800     mtc1    \$0,\$f17
28
0+0048 <[^>]*> 44809000     mtc1    \$0,\$f18
29
0+004c <[^>]*> 44809800     mtc1    \$0,\$f19
30
0+0050 <[^>]*> 4480a000     mtc1    \$0,\$f20
31
0+0054 <[^>]*> 4480a800     mtc1    \$0,\$f21
32
0+0058 <[^>]*> 4480b000     mtc1    \$0,\$f22
33
0+005c <[^>]*> 4480b800     mtc1    \$0,\$f23
34
0+0060 <[^>]*> 4480c000     mtc1    \$0,\$f24
35
0+0064 <[^>]*> 4480c800     mtc1    \$0,\$f25
36
0+0068 <[^>]*> 4480d000     mtc1    \$0,\$f26
37
0+006c <[^>]*> 4480d800     mtc1    \$0,\$f27
38
0+0070 <[^>]*> 4480e000     mtc1    \$0,\$f28
39
0+0074 <[^>]*> 4480e800     mtc1    \$0,\$f29
40
0+0078 <[^>]*> 4480f000     mtc1    \$0,\$f30
41
0+007c <[^>]*> 4480f800     mtc1    \$0,\$f31
42
        \.\.\.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.