OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [mips/] [lb-svr4pic-ilocks.d] - Blame information for rev 205

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 205 julius
#objdump: -dr --prefix-addresses
2
#name: MIPS lb-svr4pic-ilocks
3
#as: -32 -KPIC
4
#source: lb-pic.s
5
 
6
# Test the lb macro with -KPIC.
7
 
8
.*: +file format .*mips.*
9
 
10
Disassembly of section .text:
11
0+0000 <[^>]*> lb   a0,0\(zero\)
12
0+0004 <[^>]*> lb   a0,1\(zero\)
13
0+0008 <[^>]*> lui  a0,0x1
14
0+000c <[^>]*> lb   a0,-32768\(a0\)
15
0+0010 <[^>]*> lb   a0,-32768\(zero\)
16
0+0014 <[^>]*> lui  a0,0x1
17
0+0018 <[^>]*> lb   a0,0\(a0\)
18
0+001c <[^>]*> lui  a0,0x2
19
0+0020 <[^>]*> lb   a0,-23131\(a0\)
20
0+0024 <[^>]*> lb   a0,0\(a1\)
21
0+0028 <[^>]*> lb   a0,1\(a1\)
22
0+002c <[^>]*> lui  a0,0x1
23
0+0030 <[^>]*> addu a0,a0,a1
24
0+0034 <[^>]*> lb   a0,-32768\(a0\)
25
0+0038 <[^>]*> lb   a0,-32768\(a1\)
26
0+003c <[^>]*> lui  a0,0x1
27
0+0040 <[^>]*> addu a0,a0,a1
28
0+0044 <[^>]*> lb   a0,0\(a0\)
29
0+0048 <[^>]*> lui  a0,0x2
30
0+004c <[^>]*> addu a0,a0,a1
31
0+0050 <[^>]*> lb   a0,-23131\(a0\)
32
0+0054 <[^>]*> lw   a0,0\(gp\)
33
[       ]*54: R_MIPS_GOT16      .data
34
0+0058 <[^>]*> addiu        a0,a0,0
35
[       ]*58: R_MIPS_LO16       .data
36
0+005c <[^>]*> lb   a0,0\(a0\)
37
0+0060 <[^>]*> lw   a0,0\(gp\)
38
[       ]*60: R_MIPS_GOT16      big_external_data_label
39
0+0064 <[^>]*> lb   a0,0\(a0\)
40
0+0068 <[^>]*> lw   a0,0\(gp\)
41
[       ]*68: R_MIPS_GOT16      small_external_data_label
42
0+006c <[^>]*> lb   a0,0\(a0\)
43
0+0070 <[^>]*> lw   a0,0\(gp\)
44
[       ]*70: R_MIPS_GOT16      big_external_common
45
0+0074 <[^>]*> lb   a0,0\(a0\)
46
0+0078 <[^>]*> lw   a0,0\(gp\)
47
[       ]*78: R_MIPS_GOT16      small_external_common
48
0+007c <[^>]*> lb   a0,0\(a0\)
49
0+0080 <[^>]*> lw   a0,0\(gp\)
50
[       ]*80: R_MIPS_GOT16      .bss
51
0+0084 <[^>]*> addiu        a0,a0,0
52
[       ]*84: R_MIPS_LO16       .bss
53
0+0088 <[^>]*> lb   a0,0\(a0\)
54
0+008c <[^>]*> lw   a0,0\(gp\)
55
[       ]*8c: R_MIPS_GOT16      .bss
56
0+0090 <[^>]*> addiu        a0,a0,1000
57
[       ]*90: R_MIPS_LO16       .bss
58
0+0094 <[^>]*> lb   a0,0\(a0\)
59
0+0098 <[^>]*> lw   a0,0\(gp\)
60
[       ]*98: R_MIPS_GOT16      .data
61
0+009c <[^>]*> addiu        a0,a0,0
62
[       ]*9c: R_MIPS_LO16       .data
63
0+00a0 <[^>]*> lb   a0,1\(a0\)
64
0+00a4 <[^>]*> lw   a0,0\(gp\)
65
[       ]*a4: R_MIPS_GOT16      big_external_data_label
66
0+00a8 <[^>]*> lb   a0,1\(a0\)
67
0+00ac <[^>]*> lw   a0,0\(gp\)
68
[       ]*ac: R_MIPS_GOT16      small_external_data_label
69
0+00b0 <[^>]*> lb   a0,1\(a0\)
70
0+00b4 <[^>]*> lw   a0,0\(gp\)
71
[       ]*b4: R_MIPS_GOT16      big_external_common
72
0+00b8 <[^>]*> lb   a0,1\(a0\)
73
0+00bc <[^>]*> lw   a0,0\(gp\)
74
[       ]*bc: R_MIPS_GOT16      small_external_common
75
0+00c0 <[^>]*> lb   a0,1\(a0\)
76
0+00c4 <[^>]*> lw   a0,0\(gp\)
77
[       ]*c4: R_MIPS_GOT16      .bss
78
0+00c8 <[^>]*> addiu        a0,a0,0
79
[       ]*c8: R_MIPS_LO16       .bss
80
0+00cc <[^>]*> lb   a0,1\(a0\)
81
0+00d0 <[^>]*> lw   a0,0\(gp\)
82
[       ]*d0: R_MIPS_GOT16      .bss
83
0+00d4 <[^>]*> addiu        a0,a0,1000
84
[       ]*d4: R_MIPS_LO16       .bss
85
0+00d8 <[^>]*> lb   a0,1\(a0\)
86
0+00dc <[^>]*> lw   a0,0\(gp\)
87
[       ]*dc: R_MIPS_GOT16      .data
88
0+00e0 <[^>]*> addiu        a0,a0,0
89
[       ]*e0: R_MIPS_LO16       .data
90
0+00e4 <[^>]*> addu a0,a0,a1
91
0+00e8 <[^>]*> lb   a0,0\(a0\)
92
0+00ec <[^>]*> lw   a0,0\(gp\)
93
[       ]*ec: R_MIPS_GOT16      big_external_data_label
94
0+00f0 <[^>]*> addu a0,a0,a1
95
0+00f4 <[^>]*> lb   a0,0\(a0\)
96
0+00f8 <[^>]*> lw   a0,0\(gp\)
97
[       ]*f8: R_MIPS_GOT16      small_external_data_label
98
0+00fc <[^>]*> addu a0,a0,a1
99
0+0100 <[^>]*> lb   a0,0\(a0\)
100
0+0104 <[^>]*> lw   a0,0\(gp\)
101
[       ]*104: R_MIPS_GOT16     big_external_common
102
0+0108 <[^>]*> addu a0,a0,a1
103
0+010c <[^>]*> lb   a0,0\(a0\)
104
0+0110 <[^>]*> lw   a0,0\(gp\)
105
[       ]*110: R_MIPS_GOT16     small_external_common
106
0+0114 <[^>]*> addu a0,a0,a1
107
0+0118 <[^>]*> lb   a0,0\(a0\)
108
0+011c <[^>]*> lw   a0,0\(gp\)
109
[       ]*11c: R_MIPS_GOT16     .bss
110
0+0120 <[^>]*> addiu        a0,a0,0
111
[       ]*120: R_MIPS_LO16      .bss
112
0+0124 <[^>]*> addu a0,a0,a1
113
0+0128 <[^>]*> lb   a0,0\(a0\)
114
0+012c <[^>]*> lw   a0,0\(gp\)
115
[       ]*12c: R_MIPS_GOT16     .bss
116
0+0130 <[^>]*> addiu        a0,a0,1000
117
[       ]*130: R_MIPS_LO16      .bss
118
0+0134 <[^>]*> addu a0,a0,a1
119
0+0138 <[^>]*> lb   a0,0\(a0\)
120
0+013c <[^>]*> lw   a0,0\(gp\)
121
[       ]*13c: R_MIPS_GOT16     .data
122
0+0140 <[^>]*> addiu        a0,a0,0
123
[       ]*140: R_MIPS_LO16      .data
124
0+0144 <[^>]*> addu a0,a0,a1
125
0+0148 <[^>]*> lb   a0,1\(a0\)
126
0+014c <[^>]*> lw   a0,0\(gp\)
127
[       ]*14c: R_MIPS_GOT16     big_external_data_label
128
0+0150 <[^>]*> addu a0,a0,a1
129
0+0154 <[^>]*> lb   a0,1\(a0\)
130
0+0158 <[^>]*> lw   a0,0\(gp\)
131
[       ]*158: R_MIPS_GOT16     small_external_data_label
132
0+015c <[^>]*> addu a0,a0,a1
133
0+0160 <[^>]*> lb   a0,1\(a0\)
134
0+0164 <[^>]*> lw   a0,0\(gp\)
135
[       ]*164: R_MIPS_GOT16     big_external_common
136
0+0168 <[^>]*> addu a0,a0,a1
137
0+016c <[^>]*> lb   a0,1\(a0\)
138
0+0170 <[^>]*> lw   a0,0\(gp\)
139
[       ]*170: R_MIPS_GOT16     small_external_common
140
0+0174 <[^>]*> addu a0,a0,a1
141
0+0178 <[^>]*> lb   a0,1\(a0\)
142
0+017c <[^>]*> lw   a0,0\(gp\)
143
[       ]*17c: R_MIPS_GOT16     .bss
144
0+0180 <[^>]*> addiu        a0,a0,0
145
[       ]*180: R_MIPS_LO16      .bss
146
0+0184 <[^>]*> addu a0,a0,a1
147
0+0188 <[^>]*> lb   a0,1\(a0\)
148
0+018c <[^>]*> lw   a0,0\(gp\)
149
[       ]*18c: R_MIPS_GOT16     .bss
150
0+0190 <[^>]*> addiu        a0,a0,1000
151
[       ]*190: R_MIPS_LO16      .bss
152
0+0194 <[^>]*> addu a0,a0,a1
153
0+0198 <[^>]*> lb   a0,1\(a0\)
154
0+019c <[^>]*> nop

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.