OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [mips/] [ulh-svr4pic.d] - Blame information for rev 205

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 205 julius
#objdump: -dr --prefix-addresses -mmips:3000
2
#name: MIPS ulh-svr4pic
3
#as: -32 -mips1 -KPIC -EB
4
#source: ulh-pic.s
5
 
6
# Test the unaligned load and store macros with -KPIC.
7
 
8
.*: +file format .*mips.*
9
 
10
Disassembly of section .text:
11
0+0000 <[^>]*> lw   at,0\(gp\)
12
[       ]*0: R_MIPS_GOT16       .data
13
0+0004 <[^>]*> nop
14
0+0008 <[^>]*> addiu        at,at,0
15
[       ]*8: R_MIPS_LO16        .data
16
0+000c <[^>]*> lb   a0,0\(at\)
17
0+0010 <[^>]*> lbu  at,1\(at\)
18
0+0014 <[^>]*> sll  a0,a0,0x8
19
0+0018 <[^>]*> or   a0,a0,at
20
0+001c <[^>]*> lw   at,0\(gp\)
21
[       ]*1c: R_MIPS_GOT16      big_external_data_label
22
0+0020 <[^>]*> nop
23
0+0024 <[^>]*> lbu  a0,0\(at\)
24
0+0028 <[^>]*> lbu  at,1\(at\)
25
0+002c <[^>]*> sll  a0,a0,0x8
26
0+0030 <[^>]*> or   a0,a0,at
27
0+0034 <[^>]*> lw   at,0\(gp\)
28
[       ]*34: R_MIPS_GOT16      small_external_data_label
29
0+0038 <[^>]*> nop
30
0+003c <[^>]*> lwl  a0,0\(at\)
31
0+0040 <[^>]*> lwr  a0,3\(at\)
32
0+0044 <[^>]*> lw   at,0\(gp\)
33
[       ]*44: R_MIPS_GOT16      big_external_common
34
0+0048 <[^>]*> nop
35
0+004c <[^>]*> sb   a0,1\(at\)
36
0+0050 <[^>]*> srl  a0,a0,0x8
37
0+0054 <[^>]*> sb   a0,0\(at\)
38
0+0058 <[^>]*> lbu  at,1\(at\)
39
0+005c <[^>]*> sll  a0,a0,0x8
40
0+0060 <[^>]*> or   a0,a0,at
41
0+0064 <[^>]*> lw   at,0\(gp\)
42
[       ]*64: R_MIPS_GOT16      small_external_common
43
0+0068 <[^>]*> nop
44
0+006c <[^>]*> swl  a0,0\(at\)
45
0+0070 <[^>]*> swr  a0,3\(at\)
46
0+0074 <[^>]*> lw   at,0\(gp\)
47
[       ]*74: R_MIPS_GOT16      .bss
48
0+0078 <[^>]*> nop
49
0+007c <[^>]*> addiu        at,at,0
50
[       ]*7c: R_MIPS_LO16       .bss
51
0+0080 <[^>]*> lb   a0,0\(at\)
52
0+0084 <[^>]*> lbu  at,1\(at\)
53
0+0088 <[^>]*> sll  a0,a0,0x8
54
0+008c <[^>]*> or   a0,a0,at
55
0+0090 <[^>]*> lw   at,0\(gp\)
56
[       ]*90: R_MIPS_GOT16      .bss
57
0+0094 <[^>]*> nop
58
0+0098 <[^>]*> addiu        at,at,1000
59
[       ]*98: R_MIPS_LO16       .bss
60
0+009c <[^>]*> lbu  a0,0\(at\)
61
0+00a0 <[^>]*> lbu  at,1\(at\)
62
0+00a4 <[^>]*> sll  a0,a0,0x8
63
0+00a8 <[^>]*> or   a0,a0,at
64
0+00ac <[^>]*> lw   at,0\(gp\)
65
[       ]*ac: R_MIPS_GOT16      .data
66
0+00b0 <[^>]*> nop
67
0+00b4 <[^>]*> addiu        at,at,0
68
[       ]*b4: R_MIPS_LO16       .data
69
0+00b8 <[^>]*> addiu        at,at,1
70
0+00bc <[^>]*> lwl  a0,0\(at\)
71
0+00c0 <[^>]*> lwr  a0,3\(at\)
72
0+00c4 <[^>]*> lw   at,0\(gp\)
73
[       ]*c4: R_MIPS_GOT16      big_external_data_label
74
0+00c8 <[^>]*> nop
75
0+00cc <[^>]*> addiu        at,at,1
76
0+00d0 <[^>]*> sb   a0,1\(at\)
77
0+00d4 <[^>]*> srl  a0,a0,0x8
78
0+00d8 <[^>]*> sb   a0,0\(at\)
79
0+00dc <[^>]*> lbu  at,1\(at\)
80
0+00e0 <[^>]*> sll  a0,a0,0x8
81
0+00e4 <[^>]*> or   a0,a0,at
82
0+00e8 <[^>]*> lw   at,0\(gp\)
83
[       ]*e8: R_MIPS_GOT16      small_external_data_label
84
0+00ec <[^>]*> nop
85
0+00f0 <[^>]*> addiu        at,at,1
86
0+00f4 <[^>]*> swl  a0,0\(at\)
87
0+00f8 <[^>]*> swr  a0,3\(at\)
88
0+00fc <[^>]*> lw   at,0\(gp\)
89
[       ]*fc: R_MIPS_GOT16      big_external_common
90
0+0100 <[^>]*> nop
91
0+0104 <[^>]*> addiu        at,at,1
92
0+0108 <[^>]*> lb   a0,0\(at\)
93
0+010c <[^>]*> lbu  at,1\(at\)
94
0+0110 <[^>]*> sll  a0,a0,0x8
95
0+0114 <[^>]*> or   a0,a0,at
96
0+0118 <[^>]*> lw   at,0\(gp\)
97
[       ]*118: R_MIPS_GOT16     small_external_common
98
0+011c <[^>]*> nop
99
0+0120 <[^>]*> addiu        at,at,1
100
0+0124 <[^>]*> lbu  a0,0\(at\)
101
0+0128 <[^>]*> lbu  at,1\(at\)
102
0+012c <[^>]*> sll  a0,a0,0x8
103
0+0130 <[^>]*> or   a0,a0,at
104
0+0134 <[^>]*> lw   at,0\(gp\)
105
[       ]*134: R_MIPS_GOT16     .bss
106
0+0138 <[^>]*> nop
107
0+013c <[^>]*> addiu        at,at,0
108
[       ]*13c: R_MIPS_LO16      .bss
109
0+0140 <[^>]*> addiu        at,at,1
110
0+0144 <[^>]*> lwl  a0,0\(at\)
111
0+0148 <[^>]*> lwr  a0,3\(at\)
112
0+014c <[^>]*> lw   at,0\(gp\)
113
[       ]*14c: R_MIPS_GOT16     .bss
114
0+0150 <[^>]*> nop
115
0+0154 <[^>]*> addiu        at,at,1000
116
[       ]*154: R_MIPS_LO16      .bss
117
0+0158 <[^>]*> addiu        at,at,1
118
0+015c <[^>]*> sb   a0,1\(at\)
119
0+0160 <[^>]*> srl  a0,a0,0x8
120
0+0164 <[^>]*> sb   a0,0\(at\)
121
0+0168 <[^>]*> lbu  at,1\(at\)
122
0+016c <[^>]*> sll  a0,a0,0x8
123
0+0170 <[^>]*> or   a0,a0,at
124
        ...

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.