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[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [mips/] [vr4120-2.d] - Blame information for rev 205

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1 205 julius 
#objdump: -dz --prefix-addresses -m mips:4120
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#as: -32 -march=vr4120 -mfix-vr4120
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#name: MIPS vr4120 workarounds
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.*: +file format .*mips.*
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Disassembly of section .text:
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.* <[^>]*> macc     a0,a1,a2
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.* <[^>]*> nop
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.* <[^>]*> div      zero,a3,t0
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.* <[^>]*> or       a0,a0,a1
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.* <[^>]*> dmacc    a0,a1,a2
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.* <[^>]*> nop
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.* <[^>]*> div      zero,a3,t0
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.* <[^>]*> or       a0,a0,a1
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.* <[^>]*> macc     a0,a1,a2
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.* <[^>]*> nop
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.* <[^>]*> divu     zero,a3,t0
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.* <[^>]*> or       a0,a0,a1
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.* <[^>]*> dmacc    a0,a1,a2
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.* <[^>]*> nop
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.* <[^>]*> divu     zero,a3,t0
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.* <[^>]*> or       a0,a0,a1
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.* <[^>]*> macc     a0,a1,a2
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.* <[^>]*> nop
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.* <[^>]*> ddiv     zero,a3,t0
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.* <[^>]*> or       a0,a0,a1
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.* <[^>]*> dmacc    a0,a1,a2
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.* <[^>]*> nop
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.* <[^>]*> ddiv     zero,a3,t0
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.* <[^>]*> or       a0,a0,a1
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.* <[^>]*> macc     a0,a1,a2
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.* <[^>]*> nop
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.* <[^>]*> ddivu    zero,a3,t0
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.* <[^>]*> or       a0,a0,a1
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.* <[^>]*> dmacc    a0,a1,a2
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.* <[^>]*> nop
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.* <[^>]*> ddivu    zero,a3,t0
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.* <[^>]*> or       a0,a0,a1
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.* <[^>]*> dmult    a0,a1
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.* <[^>]*> nop
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.* <[^>]*> dmult    a2,a3
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.* <[^>]*> or       a0,a0,a1
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.* <[^>]*> dmultu   a0,a1
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.* <[^>]*> nop
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.* <[^>]*> dmultu   a2,a3
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.* <[^>]*> or       a0,a0,a1
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.* <[^>]*> dmacc    a0,a1,a2
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.* <[^>]*> nop
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.* <[^>]*> dmacc    a2,a3,t0
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.* <[^>]*> or       a0,a0,a1
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.* <[^>]*> dmult    a0,a1
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.* <[^>]*> nop
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.* <[^>]*> dmacc    a2,a3,t0
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.* <[^>]*> or       a0,a0,a1
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.* <[^>]*> macc     a0,a1,a2
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.* <[^>]*> nop
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.* <[^>]*> mtlo     a3
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.* <[^>]*> dmacc    a0,a1,a2
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.* <[^>]*> nop
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.* <[^>]*> mtlo     a3
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.* <[^>]*> macc     a0,a1,a2
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.* <[^>]*> nop
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.* <[^>]*> mthi     a3
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.* <[^>]*> dmacc    a0,a1,a2
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.* <[^>]*> nop
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.* <[^>]*> mthi     a3
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#
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# vr4181a_md1:
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#
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.* <[^>]*> macc     a0,a1,a2
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.* <[^>]*> nop
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.* <[^>]*> mult     a0,a1
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.* <[^>]*> or       a0,a0,a1
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#
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.* <[^>]*> macc     a0,a1,a2
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.* <[^>]*> nop
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.* <[^>]*> multu    a0,a1
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.* <[^>]*> or       a0,a0,a1
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#
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.* <[^>]*> macc     a0,a1,a2
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.* <[^>]*> nop
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.* <[^>]*> dmult    a0,a1
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.* <[^>]*> or       a0,a0,a1
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#
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.* <[^>]*> macc     a0,a1,a2
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.* <[^>]*> nop
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.* <[^>]*> dmultu   a0,a1
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.* <[^>]*> or       a0,a0,a1
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#
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.* <[^>]*> dmacc    a0,a1,a2
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.* <[^>]*> nop
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.* <[^>]*> mult     a0,a1
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.* <[^>]*> or       a0,a0,a1
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#
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.* <[^>]*> dmacc    a0,a1,a2
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.* <[^>]*> nop
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.* <[^>]*> multu    a0,a1
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.* <[^>]*> or       a0,a0,a1
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#
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.* <[^>]*> dmacc    a0,a1,a2
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.* <[^>]*> nop
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.* <[^>]*> dmult    a0,a1
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.* <[^>]*> or       a0,a0,a1
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#
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.* <[^>]*> dmacc    a0,a1,a2
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.* <[^>]*> nop
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.* <[^>]*> dmultu   a0,a1
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.* <[^>]*> or       a0,a0,a1
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#
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# vr4181a_md4:
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#
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.* <[^>]*> dmult    a0,a1
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.* <[^>]*> nop
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.* <[^>]*> macc     a0,a1,a2
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.* <[^>]*> or       a0,a0,a1
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#
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.* <[^>]*> dmultu   a0,a1
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.* <[^>]*> nop
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.* <[^>]*> macc     a0,a1,a2
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.* <[^>]*> or       a0,a0,a1
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#
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.* <[^>]*> div      zero,a0,a1
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.* <[^>]*> nop
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.* <[^>]*> macc     a0,a1,a2
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.* <[^>]*> or       a0,a0,a1
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#
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.* <[^>]*> divu     zero,a0,a1
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.* <[^>]*> nop
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.* <[^>]*> macc     a0,a1,a2
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.* <[^>]*> or       a0,a0,a1
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#
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.* <[^>]*> ddiv     zero,a0,a1
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.* <[^>]*> nop
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.* <[^>]*> macc     a0,a1,a2
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.* <[^>]*> or       a0,a0,a1
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#
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.* <[^>]*> ddivu    zero,a0,a1
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.* <[^>]*> nop
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.* <[^>]*> macc     a0,a1,a2
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.* <[^>]*> or       a0,a0,a1
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#
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.* <[^>]*> dmult    a0,a1
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.* <[^>]*> nop
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.* <[^>]*> dmacc    a0,a1,a2
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.* <[^>]*> or       a0,a0,a1
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#
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.* <[^>]*> dmultu   a0,a1
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.* <[^>]*> nop
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.* <[^>]*> dmacc    a0,a1,a2
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.* <[^>]*> or       a0,a0,a1
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#
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.* <[^>]*> div      zero,a0,a1
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.* <[^>]*> nop
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.* <[^>]*> dmacc    a0,a1,a2
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.* <[^>]*> or       a0,a0,a1
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#
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.* <[^>]*> divu     zero,a0,a1
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.* <[^>]*> nop
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.* <[^>]*> dmacc    a0,a1,a2
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.* <[^>]*> or       a0,a0,a1
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#
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.* <[^>]*> ddiv     zero,a0,a1
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.* <[^>]*> nop
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.* <[^>]*> dmacc    a0,a1,a2
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.* <[^>]*> or       a0,a0,a1
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#
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.* <[^>]*> ddivu    zero,a0,a1
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.* <[^>]*> nop
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.* <[^>]*> dmacc    a0,a1,a2
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.* <[^>]*> or       a0,a0,a1
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#...

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