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[/] [openrisc/] [trunk/] [gnu-src/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [mips/] [vr5400.d] - Blame information for rev 205

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Line No. Rev Author Line
1 205 julius
#objdump: -dr --prefix-addresses
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#name: MIPS VR5400
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#as: -march=vr5400
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.*: +file format .*mips.*
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Disassembly of section \.text:
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0+0000  mul     a0,a1,a2
9
0+0004  mulu    a0,a1,a2
10
0+0008  mulhi   a0,a1,a2
11
0+000c  mulhiu  a0,a1,a2
12
0+0010  muls    a0,a1,a2
13
0+0014  mulsu   a0,a1,a2
14
0+0018  mulshi  a0,a1,a2
15
0+001c  mulshiu a0,a1,a2
16
0+0020  macc    a0,a1,a2
17
0+0024  maccu   a0,a1,a2
18
0+0028  macchi  a0,a1,a2
19
0+002c  macchiu a0,a1,a2
20
0+0030  msac    a0,a1,a2
21
0+0034  msacu   a0,a1,a2
22
0+0038  msachi  a0,a1,a2
23
0+003c  msachiu a0,a1,a2
24
0+0040  ror     a0,a1,0x19
25
0+0044  rorv    a0,a1,a2
26
0+0048  dror    a0,a1,0x19
27
0+004c  dror32  a0,a1,0x19
28
0+0050  dror32  a0,a1,0x19
29
0+0054  drorv   a0,a1,a2
30
0+0058  dbreak
31
0+005c  dret
32
0+0060  mfdr    v1,\$3
33
0+0064  mtdr    v1,\$3
34
0+0068  mfpc    a0,1
35
0+006c  mfps    a0,1
36
0+0070  mtpc    a0,1
37
0+0074  mtps    a0,1
38
0+0078  add\.ob \$f0,\$f2,\$f4
39
0+007c  add\.ob \$f2,\$f4,\$f6\[2\]
40
0+0080  add\.ob \$f6,\$f4,0xf
41
0+0084  add\.ob \$f4,\$f6,0x1f
42
0+0088  and\.ob \$f0,\$f2,\$f4
43
0+008c  and\.ob \$f2,\$f4,\$f6\[2\]
44
0+0090  and\.ob \$f6,\$f4,0xf
45
0+0094  and\.ob \$f4,\$f6,0x1f
46
0+0098  c\.eq\.ob       \$f0,\$f2
47
0+009c  c\.eq\.ob       \$f4,\$f6\[2\]
48
0+00a0  c\.eq\.ob       \$f6,0xf
49
0+00a4  c\.eq\.ob       \$f4,0x1f
50
0+00a8  c\.le\.ob       \$f0,\$f2
51
0+00ac  c\.le\.ob       \$f4,\$f6\[2\]
52
0+00b0  c\.le\.ob       \$f6,0xf
53
0+00b4  c\.le\.ob       \$f4,0x1f
54
0+00b8  c\.lt\.ob       \$f0,\$f2
55
0+00bc  c\.lt\.ob       \$f4,\$f6\[2\]
56
0+00c0  c\.lt\.ob       \$f6,0xf
57
0+00c4  c\.lt\.ob       \$f4,0x1f
58
0+00c8  max\.ob \$f0,\$f2,\$f4
59
0+00cc  max\.ob \$f2,\$f4,\$f6\[2\]
60
0+00d0  max\.ob \$f6,\$f4,0xf
61
0+00d4  max\.ob \$f4,\$f6,0x1f
62
0+00d8  min\.ob \$f0,\$f2,\$f4
63
0+00dc  min\.ob \$f2,\$f4,\$f6\[2\]
64
0+00e0  min\.ob \$f6,\$f4,0xf
65
0+00e4  min\.ob \$f4,\$f6,0x1f
66
0+00e8  mul\.ob \$f0,\$f2,\$f4
67
0+00ec  mul\.ob \$f2,\$f4,\$f6\[2\]
68
0+00f0  mul\.ob \$f6,\$f4,0xf
69
0+00f4  mul\.ob \$f4,\$f6,0x1f
70
0+00f8  mula\.ob        \$f0,\$f2
71
0+00fc  mula\.ob        \$f4,\$f6\[2\]
72
0+0100  mula\.ob        \$f6,0xf
73
0+0104  mula\.ob        \$f4,0x1f
74
0+0108  mull\.ob        \$f0,\$f2
75
0+010c  mull\.ob        \$f4,\$f6\[2\]
76
0+0110  mull\.ob        \$f6,0xf
77
0+0114  mull\.ob        \$f4,0x1f
78
0+0118  muls\.ob        \$f0,\$f2
79
0+011c  muls\.ob        \$f4,\$f6\[2\]
80
0+0120  muls\.ob        \$f6,0xf
81
0+0124  muls\.ob        \$f4,0x1f
82
0+0128  mulsl\.ob       \$f0,\$f2
83
0+012c  mulsl\.ob       \$f4,\$f6\[2\]
84
0+0130  mulsl\.ob       \$f6,0xf
85
0+0134  mulsl\.ob       \$f4,0x1f
86
0+0138  nor\.ob \$f0,\$f2,\$f4
87
0+013c  nor\.ob \$f2,\$f4,\$f6\[2\]
88
0+0140  nor\.ob \$f6,\$f4,0xf
89
0+0144  nor\.ob \$f4,\$f6,0x1f
90
0+0148  or\.ob  \$f0,\$f2,\$f4
91
0+014c  or\.ob  \$f2,\$f4,\$f6\[2\]
92
0+0150  or\.ob  \$f6,\$f4,0xf
93
0+0154  or\.ob  \$f4,\$f6,0x1f
94
0+0158  pickf\.ob       \$f0,\$f2,\$f4
95
0+015c  pickf\.ob       \$f2,\$f4,\$f6\[2\]
96
0+0160  pickf\.ob       \$f6,\$f4,0xf
97
0+0164  pickf\.ob       \$f4,\$f6,0x1f
98
0+0168  pickt\.ob       \$f0,\$f2,\$f4
99
0+016c  pickt\.ob       \$f2,\$f4,\$f6\[2\]
100
0+0170  pickt\.ob       \$f6,\$f4,0xf
101
0+0174  pickt\.ob       \$f4,\$f6,0x1f
102
0+0178  sub\.ob \$f0,\$f2,\$f4
103
0+017c  sub\.ob \$f2,\$f4,\$f6\[2\]
104
0+0180  sub\.ob \$f6,\$f4,0xf
105
0+0184  sub\.ob \$f4,\$f6,0x1f
106
0+0188  xor\.ob \$f0,\$f2,\$f4
107
0+018c  xor\.ob \$f2,\$f4,\$f6\[2\]
108
0+0190  xor\.ob \$f6,\$f4,0xf
109
0+0194  xor\.ob \$f4,\$f6,0x1f
110
0+0198  alni\.ob        \$f0,\$f2,\$f4,5
111
0+019c  shfl\.mixh\.ob  \$f0,\$f2,\$f4
112
0+01a0  shfl\.mixl\.ob  \$f0,\$f2,\$f4
113
0+01a4  shfl\.pach\.ob  \$f0,\$f2,\$f4
114
0+01a8  shfl\.pacl\.ob  \$f0,\$f2,\$f4
115
0+01ac  sll\.ob \$f2,\$f4,\$f6\[3\]
116
0+01b0  sll\.ob \$f4,\$f6,0xe
117
0+01b4  srl\.ob \$f2,\$f4,\$f6\[3\]
118
0+01b8  srl\.ob \$f4,\$f6,0xe
119
0+01bc  rzu\.ob \$f2,0xd
120
0+01c0  rach\.ob        \$f2
121
0+01c4  racl\.ob        \$f2
122
0+01c8  racm\.ob        \$f2
123
0+01cc  wach\.ob        \$f2
124
0+01d0  wacl\.ob        \$f2,\$f4
125
0+01d4  rorv    a0,a1,a2
126
0+01d8  ror     a0,a1,0x11
127
0+01dc  drorv   a0,a1,a2
128
0+01e0  dror32  a0,a1,0x1
129
0+01e4  dror    a0,a1,0x2
130
        \.\.\.

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