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julius |
#objdump: -dr --prefix-addresses
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#name: MIPS VR5400
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#as: -march=vr5400
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.*: +file format .*mips.*
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Disassembly of section \.text:
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0+0000 mul a0,a1,a2
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0+0004 mulu a0,a1,a2
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0+0008 mulhi a0,a1,a2
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0+000c mulhiu a0,a1,a2
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0+0010 muls a0,a1,a2
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0+0014 mulsu a0,a1,a2
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0+0018 mulshi a0,a1,a2
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0+001c mulshiu a0,a1,a2
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0+0020 macc a0,a1,a2
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0+0024 maccu a0,a1,a2
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0+0028 macchi a0,a1,a2
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0+002c macchiu a0,a1,a2
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0+0030 msac a0,a1,a2
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0+0034 msacu a0,a1,a2
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0+0038 msachi a0,a1,a2
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0+003c msachiu a0,a1,a2
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0+0040 ror a0,a1,0x19
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0+0044 rorv a0,a1,a2
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0+0048 dror a0,a1,0x19
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0+004c dror32 a0,a1,0x19
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0+0050 dror32 a0,a1,0x19
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0+0054 drorv a0,a1,a2
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0+0058 dbreak
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0+005c dret
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0+0060 mfdr v1,\$3
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0+0064 mtdr v1,\$3
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0+0068 mfpc a0,1
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0+006c mfps a0,1
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0+0070 mtpc a0,1
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0+0074 mtps a0,1
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0+0078 add\.ob \$f0,\$f2,\$f4
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0+007c add\.ob \$f2,\$f4,\$f6\[2\]
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0+0080 add\.ob \$f6,\$f4,0xf
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0+0084 add\.ob \$f4,\$f6,0x1f
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0+0088 and\.ob \$f0,\$f2,\$f4
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0+008c and\.ob \$f2,\$f4,\$f6\[2\]
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0+0090 and\.ob \$f6,\$f4,0xf
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0+0094 and\.ob \$f4,\$f6,0x1f
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0+0098 c\.eq\.ob \$f0,\$f2
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0+009c c\.eq\.ob \$f4,\$f6\[2\]
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0+00a0 c\.eq\.ob \$f6,0xf
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0+00a4 c\.eq\.ob \$f4,0x1f
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0+00a8 c\.le\.ob \$f0,\$f2
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0+00ac c\.le\.ob \$f4,\$f6\[2\]
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0+00b0 c\.le\.ob \$f6,0xf
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0+00b4 c\.le\.ob \$f4,0x1f
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0+00b8 c\.lt\.ob \$f0,\$f2
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0+00bc c\.lt\.ob \$f4,\$f6\[2\]
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0+00c0 c\.lt\.ob \$f6,0xf
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0+00c4 c\.lt\.ob \$f4,0x1f
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0+00c8 max\.ob \$f0,\$f2,\$f4
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0+00cc max\.ob \$f2,\$f4,\$f6\[2\]
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0+00d0 max\.ob \$f6,\$f4,0xf
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0+00d4 max\.ob \$f4,\$f6,0x1f
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0+00d8 min\.ob \$f0,\$f2,\$f4
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0+00dc min\.ob \$f2,\$f4,\$f6\[2\]
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0+00e0 min\.ob \$f6,\$f4,0xf
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0+00e4 min\.ob \$f4,\$f6,0x1f
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0+00e8 mul\.ob \$f0,\$f2,\$f4
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0+00ec mul\.ob \$f2,\$f4,\$f6\[2\]
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0+00f0 mul\.ob \$f6,\$f4,0xf
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0+00f4 mul\.ob \$f4,\$f6,0x1f
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0+00f8 mula\.ob \$f0,\$f2
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0+00fc mula\.ob \$f4,\$f6\[2\]
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0+0100 mula\.ob \$f6,0xf
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0+0104 mula\.ob \$f4,0x1f
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0+0108 mull\.ob \$f0,\$f2
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0+010c mull\.ob \$f4,\$f6\[2\]
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0+0110 mull\.ob \$f6,0xf
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0+0114 mull\.ob \$f4,0x1f
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0+0118 muls\.ob \$f0,\$f2
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0+011c muls\.ob \$f4,\$f6\[2\]
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0+0120 muls\.ob \$f6,0xf
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0+0124 muls\.ob \$f4,0x1f
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0+0128 mulsl\.ob \$f0,\$f2
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0+012c mulsl\.ob \$f4,\$f6\[2\]
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0+0130 mulsl\.ob \$f6,0xf
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0+0134 mulsl\.ob \$f4,0x1f
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0+0138 nor\.ob \$f0,\$f2,\$f4
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0+013c nor\.ob \$f2,\$f4,\$f6\[2\]
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0+0140 nor\.ob \$f6,\$f4,0xf
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0+0144 nor\.ob \$f4,\$f6,0x1f
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0+0148 or\.ob \$f0,\$f2,\$f4
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0+014c or\.ob \$f2,\$f4,\$f6\[2\]
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0+0150 or\.ob \$f6,\$f4,0xf
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0+0154 or\.ob \$f4,\$f6,0x1f
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0+0158 pickf\.ob \$f0,\$f2,\$f4
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0+015c pickf\.ob \$f2,\$f4,\$f6\[2\]
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0+0160 pickf\.ob \$f6,\$f4,0xf
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0+0164 pickf\.ob \$f4,\$f6,0x1f
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0+0168 pickt\.ob \$f0,\$f2,\$f4
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0+016c pickt\.ob \$f2,\$f4,\$f6\[2\]
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0+0170 pickt\.ob \$f6,\$f4,0xf
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0+0174 pickt\.ob \$f4,\$f6,0x1f
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0+0178 sub\.ob \$f0,\$f2,\$f4
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0+017c sub\.ob \$f2,\$f4,\$f6\[2\]
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0+0180 sub\.ob \$f6,\$f4,0xf
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0+0184 sub\.ob \$f4,\$f6,0x1f
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0+0188 xor\.ob \$f0,\$f2,\$f4
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0+018c xor\.ob \$f2,\$f4,\$f6\[2\]
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0+0190 xor\.ob \$f6,\$f4,0xf
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| 109 |
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0+0194 xor\.ob \$f4,\$f6,0x1f
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| 110 |
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0+0198 alni\.ob \$f0,\$f2,\$f4,5
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0+019c shfl\.mixh\.ob \$f0,\$f2,\$f4
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0+01a0 shfl\.mixl\.ob \$f0,\$f2,\$f4
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0+01a4 shfl\.pach\.ob \$f0,\$f2,\$f4
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0+01a8 shfl\.pacl\.ob \$f0,\$f2,\$f4
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0+01ac sll\.ob \$f2,\$f4,\$f6\[3\]
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0+01b0 sll\.ob \$f4,\$f6,0xe
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0+01b4 srl\.ob \$f2,\$f4,\$f6\[3\]
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0+01b8 srl\.ob \$f4,\$f6,0xe
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0+01bc rzu\.ob \$f2,0xd
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0+01c0 rach\.ob \$f2
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0+01c4 racl\.ob \$f2
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0+01c8 racm\.ob \$f2
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0+01cc wach\.ob \$f2
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0+01d0 wacl\.ob \$f2,\$f4
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0+01d4 rorv a0,a1,a2
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0+01d8 ror a0,a1,0x11
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0+01dc drorv a0,a1,a2
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0+01e0 dror32 a0,a1,0x1
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0+01e4 dror a0,a1,0x2
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\.\.\.
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